This patch should be applied to an un-modified XFree86 version 4.7.0 source tree. It is patch 1 of 4 patches that will will convert the source tree to XFree86 version 4.8.0. To apply this patch, run the following from the directory containing your 'xc' directory: patch -p0 -E < XFree86-4.7.0-4.8.0.diff1 patch -p0 -E < XFree86-4.7.0-4.8.0.diff2 patch -p0 -E < XFree86-4.7.0-4.8.0.diff3 patch -p0 -E < XFree86-4.7.0-4.8.0.diff4 sh XFree86-4.7.0-4.8.0-cleanup.sh gzip -d < XFree86-4.7.0-4.8.0-diff0.tgz | tar vxf - ------------------------------------------------------------------------------- Prereq: 4.7.0 Index: xc/programs/Xserver/hw/xfree86/CHANGELOG diff -u xc/programs/Xserver/hw/xfree86/CHANGELOG:3.3905 xc/programs/Xserver/hw/xfree86/CHANGELOG:3.3988 --- xc/programs/Xserver/hw/xfree86/CHANGELOG:3.3905 Sun Aug 12 17:57:46 2007 +++ xc/programs/Xserver/hw/xfree86/CHANGELOG Sun Dec 14 09:32:59 2008 @@ -1,3 +1,244 @@ +XFree86 4.8.0 (15 December 2008) + 70. 4.8.0 release. + +XFree86 4.7.99.31 (9 December 2008) + 69. Fix error path in -configure processing. (Matthieu Herrb) + +XFree86 4.7.99.30 (23 November 2008) + +XFree86 4.7.99.29 (9 November 2008) + 68. Move CloseWellKnownConnections() calls into OsCleanup(TRUE) calls. + Catches yet another server exit case where sockets were not being closed + (Marc La France). + +XFree86 4.7.99.28 (23 October 2008) + 67. When using BSD authentication in xdm, wipe out the password as soon as + possible to prevent it from showing up in the address space of + subsequently forked child processes (Matthieu Herrb). + 66. Ensure XVidModeGetMonitor() always returns dynamically allocated data, as + documented in its man page (Marc La France). + 65. Fix potential crash in DBE (Dave Arlie). + 64. Import X.Org fixes for CVE-2008-1377, CVE-2008-1379, CVE-2008-2360 and + CVE-2008-2361 security advisories. + 63. Various x86emu changes: + - Fix various halfword overflow issues (Scitech). + - Add RDTSC emulation (Aaron Plattner). + - Fix JNL emulation (David Wong). + - Add emulation of CPUID, levels 0 & 1. If the host architecture + supports CPUID, pass that implementation's results to the emulation. + If running on a 386 or 486 that does not support CPUID, provide a + reasonable simulation (instead of SIGILL'ing). On all other host + architectures, the emulator will report itself as a 486DX4 + (Marc La France). + - Add BTS emulation (Felix Kuehling). + - Fix BSF & BSR emulations (Aaron Plattner). + - Fix MUL and IMUL emulations in the 64-bit case (Matthias Hopf). + 62. xf86sym.c build fix when RandR is disabled (Pat Kane, Bugzilla #1693). + 61. Spruce up implementation of pthread_key_create(), pthread_key_delete() + pthread_getspecific() and pthread_setspecific() stubs in libXThrStub + library. Inspired by a change found in OpenBSD repository + (Marc La France). + 60. When opening display, if LOCALCONN fails, fall back to UNIXCOMM, then + TCPCONN (Alex Chen). + 59. Improve uniqueness of XDM-AUTHORIZATION-1 cookies. (Egbert Eich). + 58. Fix possible segfault when using XDM-AUTHORIZATION-1 keys for remote + clients over IPv6. (Christian Weisgerber) + +XFree86 4.7.99.27 (9 October 2008) + +XFree86 4.7.99.26 (23 September 2008) + +XFree86 4.7.99.25 (9 September 2008) + +XFree86 4.7.99.24 (23 August 2008) + +XFree86 4.7.99.23 (9 August 2008) + +XFree86 4.7.99.22 (23 July 2008) + 57. Immunise VBESetGetPalletteData() against attempts to set null pallette + data. (Dick Wesseling, Bugzilla #1691). + +XFree86 4.7.99.21 (9 July 2008) + 56. Allow 32-bit PCI I/O addresses on Linux/PowerPC (Marc La France). + 55. A less kludgy implementation of the Simba hack introduced in CHANGELOG + #39 (Marc La France). + +XFree86 4.7.99.20 (23 June 2008) + 54. Fix possible reference to freed memory in HP ZX1 PCI chipset scan and + emulate configuration space more closely for its fake bridges + (Marc La France). + 53. Fix bug that caused the PCI scan to ignore bus segments that are known to + exist before the scan starts (Marc La France). + +XFree86 4.7.99.19 (9 June 2008) + +XFree86 4.7.99.18 (23 May 2008) + 52. Fix radeon driver to not relocate the framebuffer within its aperture on + non-DRI platforms. Fixes a SunOS/sparc panic upon /dev/console (or + /dev/wscons) output while the server is running. (Marc La France). + 51. Change atimisc to not disable the MMIO area at the tail end of the linear + aperture if it is found to be enabled on entry. Fixes a hang on + Solaris/sparc upon /dev/console or /dev/wscons output while the server is + running (Marc La France). + 50. Change the aperture driver for Solaris to mark its mappings as non- + cacheable and as having sideeffects (Marc La France). + 49. Avoid unpredictable behaviour on PCI-X and/or PCI Express capable ix86, + x86_64 and PowerPC systems (Marc La France). + +XFree86 4.7.99.17 (9 May 2008) + 48. Fix ATIPreInit() glitch that caused it to ignore the possibility that the + common layer had relocated a Mach64's PCI block I/O base + (Marc La France). + 47. Disable Mach64 hardware cursors when the unaccelerated VGA CRTC is used + to produce server-generated video modes (Marc La France). + 46. Fix Mach64 video memory burst transfers on x86_64 (Marc La France). + 45. Remove two unused functions from xf4bpp (Miod Vallat, Marc La France). + 44. Fix additional incorrect assumptions regarding unassigned PCI resources + (Marc La France). + 43. Mitigate brokenness in /dev/console redirection on Solaris. Should this + redirection fail, redirect the server's stderr to the log to avoid screen + corruption due to the server's own console output. (Marc La France). + 42. Add a few more Radeon PCI IDs (prompted by Loic Mahe). Also, remove the + tracking of these from the "ati" module. (Marc La France) + 41. On SunOS, add a command line flag to disable the server's /dev/console + redirection (Marc La France). + 40. Rework the handling of unassigned PCI resources in the server to ensure + they are reassigned while the server is running and restore them to their + unassigned state on server exit (Marc La France). + 39. Change the scanpci and pcitweak utilities to simulate a completed master + abort instead of reading PCI register 0xb8 of Sun's Simba PCI-to-PCI + bridges, as reads of this register cause a PCI interrupt acknowledge + cycle on the secondary bus for an interrupt that did not actually occur. + Note that no other code touches this register. (Marc La France). + 38. Avoid screen corruption that occurs upon /dev/console output while the + X server is running on SunOS, by redirecting this output into a file. + The file is copied back to /dev/console on server exit. Note that screen + corruption still occurs on output to /dev/wscons because wscons cannot be + redirected in this fashion. (Marc La France). + +XFree86 4.7.99.16 (23 April 2008) + +XFree86 4.7.99.15 (9 April 2008) + 37. Radeon driver changes: + - Merge in various changes from X.Org, via OpenBSD's xenocara repository. + Among other things, this adds support for newer Radeon's. + - Don't use vgaHW if the video mode on server entry is found to be an + accelerator (i.e. non-VGA) video mode (Marc La France). + - Avoid hard-failed master aborts while attempting to read video BIOS + (Marc La France). + 36. Rage 128 driver changes: + - Add support for dual head on Rage 128 Mobility's (X.Org, via OpenBSD's + xenocara repository). + - Don't use vgaHW if the video mode on server entry is found to be an + accelerator (i.e. non-VGA) video mode (Marc La France). + - Avoid hard-failed master aborts while attempting to read video BIOS + (Marc La France). + 35. Fix PCI resource relocation to avoid nullifying resources + (Marc La France). + 34. In int10, do not attempt to populate shadow system BIOS segments if + there's a risk of hard-failed master aborts (Marc La France). + 33. Zero out all SPARC SunOS framebuffers on server exit (Marc La France). + 32. Temporarily ignore 64-bit PCI memory address spaces on SPARC + (Marc La France). + 31. For fault isolation purposes, on SPARC, bracket all PCI configuration + space accesses with MEMBAR's (Marc La France). + 30.5. Change PCI scan to mitigate the effects of PCI Express Unsupported + requests (its idea of PCI's master aborts). On Solaris/SPARC at least, + this tones down a system freeze to a SIGKILL of the PCI scan. + (Marc La France). + 30. Add PCI-X and PCI Express to the mix of PCI variants that are supported + in a single system. Includes, but is not limited to, support for Sun's + Ultra 25 and Ultra 45 systems. (Marc La France). + 29. Remove assumption that all PCI entities have a function 0 + (Marc La France). + 28. Update to 2008-03-26 pci.ids snapshot. Also add some more recent PCI + Radeon IDs. (Marc La France) + 27. Fix integer wrap-arounds in XAA's wide line code path (Paul Mackerras). + 26. Fix XAA segfault when dealing with certain TE fonts with null glyphs + (Soran Sandmann Pedersen). + 25. Make some of ATIProbe()'s verbose messages less misleading + (Marc La France). + 24. Fix reversed memset() arguments in atimisc LUT handling (David Krause). + 23. In favour of the majority case, assume x86 and x86_64 systems cannot + hard-fail master aborts. On an experimental basis, also assume the same + of alpha systems. This adds support for such systems that don't include + a PCI-to-ISA bridge. (Marc La France) + +XFree86 4.7.99.14 (23 March 2008) + 22. Fix null pointer defereference in XKB when LEDs don't exist + (Peter Hutterer, via X.Org bug #13961). + 21. Adapt from X.Org fixes for the CVE-2007-5760, CVE-2007-5958, + CVE-2007-6427, CVE-2007-6428, CVE-2007-6429 and CVE-2008-0006 security + advisories. + 20. Remove unnecessary #include of from our Linux DRM + source (Bugzilla #1689, Marc La France). + 19. When building an XFree86 loader server with stack backtrace support, use + GCC's -fno-omit-frame-pointer flag to improve the accuracy of stack + traces (Marc La France). + 18. Fix (portably this time) X server links to ensure dependant subdirs are + tranversed before the server linked (Marc La France). + +XFree86 4.7.99.13 (9 March 2008) + +XFree86 4.7.99.12 (23 February 2008) + +XFree86 4.7.99.11 (9 February 2008) + +XFree86 4.7.99.10 (23 January 2008) + +XFree86 4.7.99.9 (9 January 2008) + 17. Update SHAPE extension to Keith Packard's 1.1 version. Adds input + regions to windows that scope the area within which pointer movements are + reported to the client. Fixes build issue in certain sawfish window + manager versions. Also bump libXext shared library minor version. + Problem reported by John Lumby. + 16. Fix file descriptor leaks in Xprt, and various attempts to close streams + that were not opened successfully (Marc La France). + +XFree86 4.7.99.8 (23 December 2007) + +XFree86 4.7.99.7 (9 December 2007) + +XFree86 4.7.99.6 (23 November 2007) + +XFree86 4.7.99.5 (9 November 2007) + 15. Do not free all Mesa buffers upon GLX extension closedown. Instead these + will be freed later, when FreeAllResources() is called to also free the + drawable privates that reference these buffers. Fixes Bugzilla #1685 + (Marc La France). + 14. Fix Mesa to complain (on stderr), rather than segfault, when an attempt + is made to free an unknown buffer (Marc La France). + 13. Fix initialisation of __GLXscreenInfo structures (Marc La France). + 12. Fix memory leak and code formatting in RADEONProbe() function + (Marc La France). + +XFree86 4.7.99.4 (23 October 2007) + +XFree86 4.7.99.3 (9 October 2007) + 11. Fix i830 driver bug that occurs when the amount of video memory + initially reported by the BIOS is zero (Marc La France). + 10. Fix byte-swapping issues in libXft's handling of XImages (Alan Brown, + Bugzilla #1687). + 9. Fix the SDK's header directory structure (Marc La France). + +XFree86 4.7.99.2 (23 September 2007) + 8. 64-bit fix in XAAValidateGC() (Marc La France). + 7. Speed up Mach64 block transfers on AMD64s (Marc La France). + 6. Fix stipples in Xigs and Xsis530 servers (Marc La France). + 5. Fix bug in Xdmx's handling of USB devices (Marc La France). + 4. Darwin build fix, for the case where an X11 implementation has yet to be + installed (Marc La France, problem reported by Yves de Champlain). + 3. Change `lndir` utility to trim off trailing self-references (i.e. "/" and + "/." from its "from" argument (Marc La France). + 2. On SVR4 variants (including SunOS & Solaris), use the `make` + implementation found in $PATH, instead of a hard-wired one + (Marc La France). + 1. Remove (what's left of) the build's dependencies on the Glide2 and Glide3 + libraries. What remains are run-time only dependencies in the 2D glide + driver (Glide2) and the tdfx DRI driver (Glide3) (Marc La France). + +XFree86 4.7.99.1 (9 August 2007) + XFree86 4.7.0 (12 August 2007) 167. 4.7.0 release. @@ -20590,4 +20831,4 @@ XFree86 3.0 (26 April 1994) -$XFree86: xc/programs/Xserver/hw/xfree86/CHANGELOG,v 3.3905 2007/08/13 00:57:46 dawes Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/CHANGELOG,v 3.3988 2008/12/14 17:32:59 tsi Exp $ Index: xc/BUILD.txt diff -u xc/BUILD.txt:1.4 xc/BUILD.txt:1.5 --- xc/BUILD.txt:1.4 Fri Aug 3 19:16:06 2007 +++ xc/BUILD.txt Sat Nov 22 14:57:24 2008 @@ -17,69 +17,69 @@ We recommend using gcc to build XFree86, but XFree86 generally builds with the native compiler for each OS platform. -1. How to get the XFree86 4.7.0 source +1. How to get the XFree86 4.8.0 source -The recommended way of getting the XFree86 4.7.0 source is to obtain it +The recommended way of getting the XFree86 4.8.0 source is to obtain it directly from the XFree86 CVS repository. There are several ways of doing that, and they are described at our CVS web page . -The CVS tag for this release is "xf-4_7_0". The tag for the maintenance -branch for this release is "xf-4_7-branch". +The CVS tag for this release is "xf-4_8_0". The tag for the maintenance +branch for this release is "xf-4_8-branch". -Another method of getting the XFree86 4.7.0 source is to either download the -4.7.0 source tarballs from the XFree86 ftp site. The procedure for this is +Another method of getting the XFree86 4.8.0 source is to either download the +4.8.0 source tarballs from the XFree86 ftp site. The procedure for this is as follows: - o The XFree86 4.7.0 source is contained in the files: + o The XFree86 4.8.0 source is contained in the files: - XFree86-4.7.0-src-1.tgz + XFree86-4.8.0-src-1.tgz - XFree86-4.7.0-src-2.tgz + XFree86-4.8.0-src-2.tgz - XFree86-4.7.0-src-3.tgz + XFree86-4.8.0-src-3.tgz - XFree86-4.7.0-src-4.tgz + XFree86-4.8.0-src-4.tgz - XFree86-4.7.0-src-5.tgz + XFree86-4.8.0-src-5.tgz - XFree86-4.7.0-src-6.tgz + XFree86-4.8.0-src-6.tgz - XFree86-4.7.0-src-7.tgz + XFree86-4.8.0-src-7.tgz - These can be found at ftp://ftp.xfree86.org/pub/XFree86/4.7.0/source/. - XFree86-4.7.0-src-4.tgz and XFree86-4.7.0-src-5.tgz contains the fonts. - XFree86-4.7.0-src-6.tgz contains the documentation source. - XFree86-4.7.0-src-7.tgz contains the hardcopy documentation. - XFree86-4.7.0-src-1.tgz, XFree86-4.7.0-src-2.tgz and - XFree86-4.7.0-src-3.tgz contains everything else. + These can be found at ftp://ftp.xfree86.org/pub/XFree86/4.8.0/source/. + XFree86-4.8.0-src-4.tgz and XFree86-4.8.0-src-5.tgz contains the fonts. + XFree86-4.8.0-src-6.tgz contains the documentation source. + XFree86-4.8.0-src-7.tgz contains the hardcopy documentation. + XFree86-4.8.0-src-1.tgz, XFree86-4.8.0-src-2.tgz and + XFree86-4.8.0-src-3.tgz contains everything else. If you do not need either the documentation or the fonts, then you need - only XFree86-4.7.0-src-1.tgz, XFree86-4.7.0-src-2.tgz and - XFree86-4.7.0-src-3.tgz. + only XFree86-4.8.0-src-1.tgz, XFree86-4.8.0-src-2.tgz and + XFree86-4.8.0-src-3.tgz. o Extract each of these files by running the following from a directory on a filesystem containing enough space (the full source requires around 270MB, with a similar amount being required for the compiled binaries): - gzip -d < XFree86-4.7.0-src-1.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-1.tgz | tar vxf - - gzip -d < XFree86-4.7.0-src-2.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-2.tgz | tar vxf - - gzip -d < XFree86-4.7.0-src-3.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-3.tgz | tar vxf - - gzip -d < XFree86-4.7.0-src-4.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-4.tgz | tar vxf - - gzip -d < XFree86-4.7.0-src-5.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-5.tgz | tar vxf - - gzip -d < XFree86-4.7.0-src-6.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-6.tgz | tar vxf - - gzip -d < XFree86-4.7.0-src-7.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-7.tgz | tar vxf - -Alternatively, if you already have a pristine copy of the XFree86 4.6.0 +Alternatively, if you already have a pristine copy of the XFree86 4.7.0 source, you can download patches from -ftp://ftp.xfree86.org/pub/XFree86/4.7.0/patches/ that will allow you to con- -vert it to 4.7.0. Information about which patch files to download and how to +ftp://ftp.xfree86.org/pub/XFree86/4.8.0/patches/ that will allow you to con- +vert it to 4.8.0. Information about which patch files to download and how to apply them can be found in the "How to get XFree86" section of the README for this release. @@ -102,8 +102,8 @@ sarily. Before making too many modifications, check the configuration param- eters specified in the xc/config/cf/README file. -If you are using just the XFree86-4.7.0-src-1.tgz, XFree86-4.7.0-src-2.tgz -and XFree86-4.7.0-src-3.tgz parts of the source dist, you will need to define +If you are using just the XFree86-4.8.0-src-1.tgz, XFree86-4.8.0-src-2.tgz +and XFree86-4.8.0-src-3.tgz parts of the source dist, you will need to define BuildFonts to NO. 3. Using a shadow directory of symbolic links for the build @@ -284,4 +284,4 @@ Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/BUILD.sgml,v 3.20 dawes Exp $ -$XFree86: xc/BUILD.txt,v 1.4 2007/08/04 02:16:06 tsi Exp $ +$XFree86: xc/BUILD.txt,v 1.5 2008/11/22 22:57:24 tsi Exp $ Index: xc/Install.txt diff -u xc/Install.txt:1.4 xc/Install.txt:1.6 --- xc/Install.txt:1.4 Fri Aug 3 19:16:06 2007 +++ xc/Install.txt Sat Nov 22 14:57:24 2008 @@ -1,8 +1,8 @@ - Installation Details for XFree86® 4.7.0 + Installation Details for XFree86® 4.8.0 The XFree86 Project, Inc - 2 February 2005 + 12 August 2007 Abstract @@ -22,11 +22,11 @@ XFree86 CVS repository's "utils" module, and from our ftp site .) -2. Downloading the XFree86 4.7.0 binaries +2. Downloading the XFree86 4.8.0 binaries -We provide XFree86 4.7.0 binaries for a range of operating systems at our ftp -site and our web site -. Often during +We provide XFree86 4.8.0 binaries for a range of operating systems at our ftp +site and our web site +. Often during releases our site is heavily loaded. Instead of downloading directly from us we recommend that instead you use one of our mirror sites. @@ -71,9 +71,9 @@ that your target will not be be available for this release. This is likeliest possibility if you are looking more than about two weeks after the release date. Check here - for information about + for information about updates to our binary distributions, and here - for errata related to + for errata related to this release. Assuming that you have run the Xinstall.sh script and found the binary dis- @@ -138,9 +138,9 @@ If you miss some and want to install them later, go to the Manual Installa- tion (section 4., page 1) section. -3. Installing XFree86 4.7.0 using the Xinstall.sh script +3. Installing XFree86 4.8.0 using the Xinstall.sh script -We strongly recommend that our XFree86 4.7.0 binaries be installed using the +We strongly recommend that our XFree86 4.8.0 binaries be installed using the Xinstall.sh script we provide. There are a lot of steps in the manual installation process, and those steps can vary according to the platform and hardware setup. There is a description of the manual installation process @@ -284,9 +284,9 @@ After the X server configuration is done, it may be advisable to reboot, especially if you run xdm (or equivalent) or the font server (xfs). -4. Installing XFree86 4.7.0 manually +4. Installing XFree86 4.8.0 manually -This section contains information about manually installing the XFree86 4.7.0 +This section contains information about manually installing the XFree86 4.8.0 binary distributions. You should only use this method if you know what you're doing. The information here covers some common cases, but not every possible case. It also may not be complete or up to date. Use at your own @@ -393,7 +393,7 @@ /sbin/ldconfig -m /usr/X11R6/lib # For FreeBSD, NetBSD, OpenBSD /usr/X11R6/bin/mkfontdir /usr/X11R6/lib/X11/fonts/misc - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Install.sgml,v 1.22 dawes Exp $ + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Install.sgml,v 1.23 tsi Exp $ -$XFree86: xc/Install.txt,v 1.4 2007/08/04 02:16:06 tsi Exp $ +$XFree86: xc/Install.txt,v 1.6 2008/11/22 22:57:24 tsi Exp $ Index: xc/LICENSE.txt diff -u xc/LICENSE.txt:1.9 xc/LICENSE.txt:1.11 --- xc/LICENSE.txt:1.9 Fri Aug 3 19:16:06 2007 +++ xc/LICENSE.txt Sat Nov 22 14:57:24 2008 @@ -49,14 +49,14 @@ 3.1 Open Source -We believe that all of the code in this release (4.7.0) of XFree86 meet the +We believe that all of the code in this release (4.8.0) of XFree86 meet the requirements of the Open Source Definition , as maintained by the Open Source Initiative (OSI) . 3.2 Free Software -We believe that most of the code in this release (4.7.0) of XFree86 meets the +We believe that most of the code in this release (4.8.0) of XFree86 meets the requirements of the Free Software definition as defined by the Free Software Foundation (FSF) . @@ -188,7 +188,7 @@ Copyright (C) 1999-2003 by Peter Kunzmann, Citron GmbH, Germany. -Copyright (C) 1994 through 2007 by Marc Aurele La France (TSI @ UQV), +Copyright (C) 1994 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org Copyright (C) 1996 by Steven Lang @@ -1631,7 +1631,7 @@ authorization from the Gnome Foundation or Bitstream Inc., respectively. For further information, contact: fonts at gnome dot org. - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LICENSE.sgml,v 1.45 tsi Exp $ + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LICENSE.sgml,v 1.46 tsi Exp $ -$XFree86: xc/LICENSE.txt,v 1.9 2007/08/04 02:16:06 tsi Exp $ +$XFree86: xc/LICENSE.txt,v 1.11 2008/11/22 22:57:24 tsi Exp $ Index: xc/README.txt diff -u xc/README.txt:1.6 xc/README.txt:1.8 --- xc/README.txt:1.6 Fri Aug 3 19:16:06 2007 +++ xc/README.txt Sat Nov 22 14:57:24 2008 @@ -1,8 +1,8 @@ - README for XFree86® 4.7.0 + README for XFree86® 4.8.0 The XFree86 Project, Inc - April 2006 + August 2007 Abstract @@ -11,20 +11,20 @@ Linux, FreeBSD, NetBSD, OpenBSD and Solaris) on Intel and other platforms. This version is compatible with X11R6.6. -1. What is XFree86 4.7.0? +1. What is XFree86 4.8.0? -XFree86 4.7.0 is the tenth full release in the XFree86 4.x series. +XFree86 4.8.0 is the eleventh full release in the XFree86 4.x series. XFree86 4.x is the current XFree86 release series. The first release in this series was in early 2000. The core of XFree86 4.x is a modular X server. -The 4.7.0 version is a new release that includes additional hardware support, +The 4.8.0 version is a new release that includes additional hardware support, functional enhancements and bug fixes. Specific release enhancements can be viewed in the Release Notes. -Most modern PC video hardware is supported in XFree86 4.7.0, and most PC +Most modern PC video hardware is supported in XFree86 4.8.0, and most PC video hardware that isn't supported explicitly can be used with the "vesa" driver. The Release Notes has a table showing the drivers provided with -XFree86 4.7.0, and links to related documentation. +XFree86 4.8.0, and links to related documentation. XFree86® is produced by The XFree86 Project, Inc through the work of a group of volunteer independent developers. The XFree86 Project is a non-commercial @@ -61,7 +61,7 @@ 3. Pointers to additional information The documentation for this release can be found online at the XFree86 web -site . Documentation for the latest +site . Documentation for the latest release version can always be found here , and documentation for the latest pre-release snapshot can be found here . @@ -116,23 +116,23 @@ Current information about the XFree86 development process can be found at our web site . -6. How to get XFree86 4.7.0 +6. How to get XFree86 4.8.0 -XFree86 4.7.0 can be found at the XFree86 ftp server -. Information about obtaining +XFree86 4.8.0 can be found at the XFree86 ftp server +. Information about obtaining and installing binary distributions of this release can be found in the Installation Document. Information about obtaining the release in source form is given below. -The source for version 4.7.0 is split into seven tarballs: +The source for version 4.8.0 is split into seven tarballs: - XFree86-4.7.0-src-1.tgz - XFree86-4.7.0-src-2.tgz - XFree86-4.7.0-src-3.tgz - XFree86-4.7.0-src-4.tgz - XFree86-4.7.0-src-5.tgz - XFree86-4.7.0-src-6.tgz - XFree86-4.7.0-src-7.tgz + XFree86-4.8.0-src-1.tgz + XFree86-4.8.0-src-2.tgz + XFree86-4.8.0-src-3.tgz + XFree86-4.8.0-src-4.tgz + XFree86-4.8.0-src-5.tgz + XFree86-4.8.0-src-6.tgz + XFree86-4.8.0-src-7.tgz The first three contain everything except the fonts and general X11 documen- tation. Those three are sufficient for building XFree86 if you already have @@ -140,36 +140,36 @@ the source for the general X11 documentation. The seventh contains the gen- eral X11 documentation in hardcopy format. -A source patch relative to version 4.6.0 is also available. Because of its +A source patch relative to version 4.7.0 is also available. Because of its size, it is split into four parts. The patch files are: - XFree86-4.6.0-4.7.0.diff1.gz - XFree86-4.6.0-4.7.0.diff2.gz - XFree86-4.6.0-4.7.0.diff3.gz - XFree86-4.6.0-4.7.0.diff4.gz + XFree86-4.7.0-4.8.0.diff1.gz + XFree86-4.7.0-4.8.0.diff2.gz + XFree86-4.7.0-4.8.0.diff3.gz + XFree86-4.7.0-4.8.0.diff4.gz There is also a tarball and a cleanup script that handle files that have com- ponents that can't be included in a diff. These are: - XFree86-4.6.0-4.7.0-diff0.tgz - XFree86-4.6.0-4.7.0-cleanup.sh + XFree86-4.7.0-4.8.0-diff0.tgz + XFree86-4.7.0-4.8.0-cleanup.sh -These patches should be applied to a clean 4.6.0 source tree, working from +These patches should be applied to a clean 4.7.0 source tree, working from the directory containing the xc/ directory. The patches should be applied by running: - gzip -d < XFree86-4.6.0-4.7.0.diff1.gz | patch -p0 -E - gzip -d < XFree86-4.6.0-4.7.0.diff2.gz | patch -p0 -E - gzip -d < XFree86-4.6.0-4.7.0.diff3.gz | patch -p0 -E - gzip -d < XFree86-4.6.0-4.7.0.diff4.gz | patch -p0 -E + gzip -d < XFree86-4.7.0-4.8.0.diff1.gz | patch -p0 -E + gzip -d < XFree86-4.7.0-4.8.0.diff2.gz | patch -p0 -E + gzip -d < XFree86-4.7.0-4.8.0.diff3.gz | patch -p0 -E + gzip -d < XFree86-4.7.0-4.8.0.diff4.gz | patch -p0 -E - sh XFree86-4.6.0-4.7.0-cleanup.sh - gzip -d < XFree86-4.6.0-4.7.0-diff0.tgz | tar vxf - + sh XFree86-4.7.0-4.8.0-cleanup.sh + gzip -d < XFree86-4.7.0-4.8.0-diff0.tgz | tar vxf - To format the XFree86 documentation use the latest version of our doctools package available from the XFree86 CVS repository's "doctools" module, and from our ftp site . +tools-1.3.5.tgz>. The XFree86 source code for this and all releases/snapshots as well as devel- opment versions can also be accessed via the XFree86 CVS repository. Infor- @@ -177,8 +177,8 @@ on our web site. It's also possible to browse the XFree86 CVS repository at our CVSWeb server . The CVS tag for this version is -"xf-4_7_0". The CVS tag for the stable branch for this release is -"xf-4_7-branch". To check out the latest development version, don't specify +"xf-4_8_0". The CVS tag for the stable branch for this release is +"xf-4_8-branch". To check out the latest development version, don't specify any tag. 7. Reporting Bugs @@ -203,4 +203,4 @@ Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml,v 3.149 dawes Exp $ -$XFree86: xc/README.txt,v 1.6 2007/08/04 02:16:06 tsi Exp $ +$XFree86: xc/README.txt,v 1.8 2008/11/22 22:57:24 tsi Exp $ Index: xc/RELNOTES.txt diff -u xc/RELNOTES.txt:1.10 xc/RELNOTES.txt:1.11 --- xc/RELNOTES.txt:1.10 Sun Aug 12 17:57:46 2007 +++ xc/RELNOTES.txt Sat Nov 22 14:57:24 2008 @@ -1,18 +1,18 @@ - Release Notes for XFree86® 4.7.0 + Release Notes for XFree86® 4.8.0 The XFree86 Project, Inc - August 2007 + December 2008 Abstract This document contains information about the various features and - their current status in the XFree86 4.7.0 release. + their current status in the XFree86 4.8.0 release. 1. Introduction to the 4.x Release Series XFree86 4.0 was the first official release of the XFree86 4 series. The cur- -rent release (4.7.0) is the latest in that series. The XFree86 4.x series +rent release (4.8.0) is the latest in that series. The XFree86 4.x series represents a significant redesign of the XFree86 X server, with a strong focus on modularity and configurability. @@ -72,13 +72,12 @@ through the Installation Document as it can point out which particular binary you should download. -The next section describes what is new in the latest version (4.7.0) compared -with the previous full release (4.6.0). There are many new features in this -release and we unfortunately do not have enough space to cover them all here. +The next section describes what is new in the latest version (4.8.0) compared +with the previous full release (4.7.0). -3. Summary of new features in 4.7.0. +3. Summary of new features in 4.8.0. -This is a sampling of the new features in XFree86 4.7.0. A more complete +This is a sampling of the new features in XFree86 4.8.0. A more complete list of changes can be found in the CHANGELOG that is part of the XFree86 source tree. It can also be viewed online at our CVSweb server , or the 'cvs log' information for individual @@ -834,42 +689,23 @@ New Features, Enhancements and Updates: Security Updates: - Josh Bressens, Chris Evans, Matthieu Herrb, Marc La - France, Sean Larsson, Victor Stinner, iDefense. + X.Org, Matthieu Herrb. - NVIDIA driver updates and new hardware support: - Mark Vojkovich - - Improved SPARC support: + Improved SPARC, PCI-X and PCI Express support: Marc La France. - Xterm enhancements and updates: - Thomas Dickey. - - DragonFly support: - David H. Dawes. - Integration: General Integration of Submissions: Marc La France, David H. Dawes. - Release Engineering: - David H. Dawes. - Patches and other submissions (in alphabetical order): - Andrew Aitchison, Marc Balmer, Etienne Bersac, Martin Bochnig, - Peter Breitenlohner, Josh Bressers, James Chacon, Yves de Cham- - plain, Alan Coopersmith, David Dawes, Eike Dehling, Thomas - Dickey, Matthias Drochner, Jay Estabrook, Chris Evans, Will L G, - Andriy Gapon, Charles M. Hannum, Frank J. R. Hanstick, Ben Har- - ris, Matthieu Herrb, Iain Hibbert, Martin Husemann, iDefense, - Milos Komarcevic, Marc La France, Sean Larrson, Michael Lorenz, - Jie Luo, Loic Mahe, Minoura Makoto, Martin Mares, Luke Mewburn, - NetBSD, Dmitry Pervushin, Alexander Pohoyda, Ty Sarna, SciFi, - Christopher Sekiya, Jamey Sharp, Victor Stinner, Frank van der - Linden, Shin Takemura, Mark Vojkovich, Nathan J. Williams, X.Org, - Christos Zoulos. + David Arlie, Alan Brown, Alex Chen, Yves de Champlain, Egbert + Eich, Matthieu Herrb, Matthias Hopf, Peter Hutterer, Pat Kane, + David Krause, Felix Kuehling, Marc La France, John Lumby, Paul + Mackerras, Keith Packard, Soran Sandmann Pedersen, Aaron Plat- + tner, Scitech, Miod Vallat, Christian Weisgerber, Dick Wesseling, + David Wong, X.Org. Webmaster: Georgina O. Economou @@ -896,7 +732,7 @@ This product includes software developed by X-Oz Technologies (http://www.x- oz.com/). - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTES.sgml,v 1.143 tsi Exp $ + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTES.sgml,v 1.144 tsi Exp $ -$XFree86: xc/RELNOTES.txt,v 1.10 2007/08/13 00:57:46 dawes Exp $ +$XFree86: xc/RELNOTES.txt,v 1.11 2008/11/22 22:57:24 tsi Exp $ Index: xc/config/cf/Imake.rules diff -u xc/config/cf/Imake.rules:3.154 xc/config/cf/Imake.rules:3.155 --- xc/config/cf/Imake.rules:3.154 Mon Apr 9 08:19:10 2007 +++ xc/config/cf/Imake.rules Tue Mar 18 12:36:52 2008 @@ -1,6 +1,6 @@ XCOMM --------------------------------------------------------------------- XCOMM Imake rules for building libraries, programs, scripts, and data files -XCOMM rules: $XFree86: xc/config/cf/Imake.rules,v 3.154 2007/04/09 15:19:10 tsi Exp $ +XCOMM rules: $XFree86: xc/config/cf/Imake.rules,v 3.155 2008/03/18 19:36:52 tsi Exp $ /* * Copyright (c) 1994-2006 by The XFree86 Project, Inc. * All rights reserved. @@ -1139,7 +1139,12 @@ #ifndef ServerTargetWithFlags #define ServerTargetWithFlags(server,subdirs,objects,libs,syslibs,flags) @@\ AllTarget(ProgramTargetName(server)) @@\ -ProgramTargetName(server): subdirs /* objects libs */ @@\ +Concat(server,DEPS) = objects libs @@\ + @@\ +$(Concat(server,DEPS)):: subdirs @@\ + $(_NULLCMD_) @@\ + @@\ +ProgramTargetName(server): objects libs @@\ MoveToBakFile($@) @@\ LinkRule($@,$(LDOPTIONS),objects,libs $(LDLIBS) syslibs) @@\ @@\ Index: xc/config/cf/Imake.tmpl diff -u xc/config/cf/Imake.tmpl:3.180 xc/config/cf/Imake.tmpl:3.183 --- xc/config/cf/Imake.tmpl:3.180 Sat Apr 21 17:37:18 2007 +++ xc/config/cf/Imake.tmpl Mon Dec 8 08:56:07 2008 @@ -1,6 +1,6 @@ XCOMM ---------------------------------------------------------------------- XCOMM Makefile generated from IMAKE_TEMPLATE and INCLUDE_IMAKEFILE -XCOMM $XFree86: xc/config/cf/Imake.tmpl,v 3.180 2007/04/22 00:37:18 tsi Exp $ +XCOMM $XFree86: xc/config/cf/Imake.tmpl,v 3.183 2008/12/08 16:56:07 tsi Exp $ XCOMM ---------------------------------------------------------------------- /* * Copyright (c) 1994-2005 by The XFree86 Project, Inc. @@ -722,36 +722,6 @@ #ifdef NCursesIncDir NCURSESINCDIR = NCursesIncDir #endif -#ifndef HasGlide2 -#define HasGlide2 NO -#endif -#ifndef Glide2IncDir -#if HasGlide2 -#define Glide2IncDir /usr/include/glide -#else -#define Glide2IncDir -#endif -#endif -GLIDE2INCDIR = Glide2IncDir -#ifndef HasGlide3 -#define HasGlide3 NO -#endif -#ifndef Glide3IncDir -#if HasGlide3 -#define Glide3IncDir /usr/include/glide3 -#else -#define Glide3IncDir -#endif -#endif -GLIDE3INCDIR = Glide3IncDir -#ifndef Glide3LibName -#if HasGlide3 -#define Glide3LibName glide3 -#else -#define Glide3LibName -#endif -#endif -GLIDE3LIBNAME = Glide3LibName #ifndef HasTk #define HasTk NO #endif @@ -1567,7 +1537,7 @@ #endif #ifdef HTMLroffCmd #ifndef DocFilesToClean -#define DocFilesToClean grohtml*.png *-auto-*.png +#define DocFilesToClean groff-html-*.png grohtml*.png *-auto-*.png #endif #endif #ifndef MsMacros @@ -1714,7 +1684,7 @@ #define DocFilesToClean /**/ #endif #ifndef FilesToClean -#define FilesToClean *.CKP *.ln *.BAK *.bak *.Osuf core errs ,* *~ *.a .emacs_* tags TAGS make.log MakeOut +#define FilesToClean *.CKP *.ln *.BAK *.bak *.Osuf *.i *.ii core errs ,* *~ *.a .emacs_* tags TAGS make.log MakeOut #endif #ifdef CrossCompileDir Index: xc/config/cf/OpenBSDLib.tmpl diff -u xc/config/cf/OpenBSDLib.tmpl:1.14 xc/config/cf/OpenBSDLib.tmpl:1.15 --- xc/config/cf/OpenBSDLib.tmpl:1.14 Sun Jul 23 13:51:48 2006 +++ xc/config/cf/OpenBSDLib.tmpl Fri Jan 4 09:50:10 2008 @@ -1,4 +1,4 @@ -XCOMM platform: $XFree86: xc/config/cf/OpenBSDLib.tmpl,v 1.14 2006/07/23 20:51:48 tsi Exp $ +XCOMM platform: $XFree86: xc/config/cf/OpenBSDLib.tmpl,v 1.15 2008/01/04 17:50:10 tsi Exp $ XCOMM /* Shared libraries dependencies */ @@ -18,7 +18,7 @@ # define SharedXThrStubRev 7.0 # endif # ifndef SharedXextRev -# define SharedXextRev 7.0 +# define SharedXextRev 7.1 # endif # ifndef SharedXssRev # define SharedXssRev 2.0 Index: xc/config/cf/Win32.rules diff -u xc/config/cf/Win32.rules:1.8 xc/config/cf/Win32.rules:1.9 --- xc/config/cf/Win32.rules:1.8 Tue May 16 09:01:50 2006 +++ xc/config/cf/Win32.rules Tue Mar 18 12:36:52 2008 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/config/cf/Win32.rules,v 1.8 2006/05/16 16:01:50 tsi Exp $ +XCOMM $XFree86: xc/config/cf/Win32.rules,v 1.9 2008/03/18 19:36:52 tsi Exp $ #define HasSharedLibraries YES #define NeedLibInsideFlag YES @@ -506,7 +506,11 @@ XVARdef0 = objects @@\ @@\ AllTarget(ProgramTargetName(server)) @@\ -ProgramTargetName(server): subdirs $(XVARuse0:.o=.obj) libs @@\ + @@\ +$(XVARuse0:.o=.obj) libs:: subdirs @@\ + $(_NULLCMD_) @@\ + @@\ +ProgramTargetName(server): $(XVARuse0:.o=.obj) libs @@\ MoveToBakFile($@) @@\ LinkRule($@,$(LDOPTIONS),$(XVARuse0:.o=.obj),libs $(LDLIBS) syslibs) @@\ @@\ Index: xc/config/cf/X11.tmpl diff -u xc/config/cf/X11.tmpl:1.298 xc/config/cf/X11.tmpl:1.300 --- xc/config/cf/X11.tmpl:1.298 Sat Apr 28 11:35:30 2007 +++ xc/config/cf/X11.tmpl Sat Dec 6 09:00:39 2008 @@ -1,6 +1,6 @@ XCOMM ---------------------------------------------------------------------- XCOMM X Window System Build Parameters and Rules -XCOMM $XFree86: xc/config/cf/X11.tmpl,v 1.298 2007/04/28 18:35:30 tsi Exp $ +XCOMM $XFree86: xc/config/cf/X11.tmpl,v 1.300 2008/12/06 17:00:39 tsi Exp $ /* * Copyright (c) 1994-2005 by The XFree86 Project, Inc. * All rights reserved. @@ -2128,7 +2128,7 @@ XEXTLIBSRC = $(LIBSRC)/Xext #if SharedLibXext #ifndef SharedXextRev -#define SharedXextRev 6.4 +#define SharedXextRev 6.5 #endif SharedLibReferences(EXTENSION,Xext,$(XEXTLIBSRC),SOXEXTREV,SharedXextRev) #else @@ -4958,7 +4958,7 @@ #ifdef HTMLroffCmd #define MakeDepSimpleHtmlDoc(file,deps,srcs) @@\ HtmlTarget(file): deps @@\ - $(HTMLROFF) $(MSMACROS) $(XDOCMACROS) Concat(-P-I,file) srcs \ @@\ + $(HTMLROFF) $(MSMACROS) Concat(-P-I,file) $(XDOCMACROS) srcs \ @@\ 2> index.raw > file.nhtml \ @@\ && PostProcessTroffHTML(file.nhtml,$@) #else Index: xc/config/cf/bsdi.cf diff -u xc/config/cf/bsdi.cf:3.42 xc/config/cf/bsdi.cf:3.43 --- xc/config/cf/bsdi.cf:3.42 Sun Jul 23 13:51:48 2006 +++ xc/config/cf/bsdi.cf Sat Sep 15 17:24:57 2007 @@ -1,4 +1,4 @@ -XCOMM platform: $XFree86: xc/config/cf/bsdi.cf,v 3.42 2006/07/23 20:51:48 tsi Exp $ +XCOMM platform: $XFree86: xc/config/cf/bsdi.cf,v 3.43 2007/09/16 00:24:57 tsi Exp $ /* * Copyright (c) 1994-2004 by The XFree86 Project, Inc. @@ -220,7 +220,7 @@ /* * Heck, build a server that can load modules too... */ -#define DoLoadableServer Yes +#define DoLoadableServer YES #endif XCOMM math.h uses _REENTRANT in FreeBSD, so we define it here too Index: xc/config/cf/linux.cf diff -u xc/config/cf/linux.cf:3.245 xc/config/cf/linux.cf:3.246 --- xc/config/cf/linux.cf:3.245 Wed Jan 3 19:33:41 2007 +++ xc/config/cf/linux.cf Sat Sep 15 18:33:21 2007 @@ -1,4 +1,4 @@ -XCOMM platform: $XFree86: xc/config/cf/linux.cf,v 3.245 2007/01/04 03:33:41 tsi Exp $ +XCOMM platform: $XFree86: xc/config/cf/linux.cf,v 3.246 2007/09/16 01:33:21 tsi Exp $ /* * Copyright (c) 1994-2006 by The XFree86 Project, Inc. @@ -229,10 +229,11 @@ # ifndef HasBasename # define HasBasename NO # endif - /* Proliferation of C99isms makes -ansi unpalatable... */ -# if !defined(DefaultCCOptions) && !defined(UseInstalled) && HasGcc -# define DefaultCCOptions GccWarningOptions -# endif +#endif + +/* Proliferation of C99isms makes -ansi unpalatable... */ +#if !defined(DefaultCCOptions) && !defined(UseInstalled) && HasGcc +# define DefaultCCOptions GccWarningOptions #endif #ifndef InstallXloadSetGID Index: xc/config/cf/lnxdoc.tmpl diff -u xc/config/cf/lnxdoc.tmpl:3.14 xc/config/cf/lnxdoc.tmpl:3.15 --- xc/config/cf/lnxdoc.tmpl:3.14 Mon Feb 20 08:08:31 2006 +++ xc/config/cf/lnxdoc.tmpl Mon Dec 8 08:44:19 2008 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/config/cf/lnxdoc.tmpl,v 3.14 2006/02/20 16:08:31 tsi Exp $ +XCOMM $XFree86: xc/config/cf/lnxdoc.tmpl,v 3.15 2008/12/08 16:44:19 tsi Exp $ XCOMM #ifndef HasSgmlFmt @@ -66,5 +66,4 @@ /* Some extra things to clean */ #undef DocFilesToClean -#define DocFilesToClean *.aux *.dvi *.log *.tex *.toc *.html *.ps *.latin1 - +#define DocFilesToClean *.aux *.dvi *.html *.latin1 *.log *.pdf *.ps *.tex *.toc Index: xc/config/cf/necLib.tmpl diff -u xc/config/cf/necLib.tmpl:1.2 xc/config/cf/necLib.tmpl:1.3 --- xc/config/cf/necLib.tmpl:1.2 Mon Jan 9 06:56:13 2006 +++ xc/config/cf/necLib.tmpl Fri Jan 4 09:50:10 2008 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/config/cf/necLib.tmpl,v 1.2 2006/01/09 14:56:13 dawes Exp $ +XCOMM $XFree86: xc/config/cf/necLib.tmpl,v 1.3 2008/01/04 17:50:10 tsi Exp $ /* * NEC shared library template @@ -20,7 +20,7 @@ #define SharedXmuRev 4.10 #endif #ifndef SharedXextRev -#define SharedXextRev 4.10 +#define SharedXextRev 4.11 #endif #ifndef SharedXinputRev #define SharedXinputRev 4.10 Index: xc/config/cf/nto.rules diff -u xc/config/cf/nto.rules:1.10 xc/config/cf/nto.rules:1.11 --- xc/config/cf/nto.rules:1.10 Wed Mar 24 19:36:21 2004 +++ xc/config/cf/nto.rules Tue Mar 18 12:36:52 2008 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/config/cf/nto.rules,v 1.10 2004/03/25 03:36:21 dawes Exp $ +XCOMM $XFree86: xc/config/cf/nto.rules,v 1.11 2008/03/18 19:36:52 tsi Exp $ XCOMM Rules for QNX/Neutrino XCOMM Note that some of these will disappear when we stop cross-compiling @@ -171,7 +171,13 @@ #ifndef ServerTargetWithFlags #define ServerTargetWithFlags(server,subdirs,objects,libs,syslibs,flags) @@\ AllTarget(ProgramTargetName(server)) @@\ -ProgramTargetName(server): subdirs objects libs @@\ + @@\ +Concat(server,DEPS) = objects libs @@\ + @@\ +$(Concat(server,DEPS)):: subdirs @@\ + $(_NULLCMD_) @@\ + @@\ +ProgramTargetName(server): objects libs @@\ MoveToBakFile($@) @@\ LinkRule($@,$(LDOPTIONS),objects,libs $(LDLIBS) syslibs) @@\ @@\ Index: xc/config/cf/sgi.cf diff -u xc/config/cf/sgi.cf:1.28 xc/config/cf/sgi.cf:1.30 --- xc/config/cf/sgi.cf:1.28 Tue Apr 3 08:17:55 2007 +++ xc/config/cf/sgi.cf Sun Apr 6 12:27:21 2008 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/config/cf/sgi.cf,v 1.28 2007/04/03 15:17:55 tsi Exp $ +XCOMM $XFree86: xc/config/cf/sgi.cf,v 1.30 2008/04/06 19:27:21 tsi Exp $ #ifndef OSName # define OSName DefaultOSName @@ -109,14 +109,21 @@ #define ServerSymbolTables #endif +#ifndef sgiCommonCCOptions +#define sgiCommonCCOptions \ + -xansi -D__mips__ \ + -woff 3968,3970 \ + -Wl,-woff,47 +#endif + /* this is for floating point, ANSI cpp */ #if OSMajorVersion < 5 /* Extra libraries provide : yp, sysV malloc, shared libc, and widechar */ # define ExtraLibraries -lsun -lmalloc -lc_s -lw -# define sgiCCOptions -xansi -D__STDC__=1 -float -D__mips__ -Wl,-woff,47 +# define sgiCCOptions -D__STDC__=1 -float sgiCommonCCOptions #else # if OSMajorVersion < 6 -# define sgiCCOptions -xansi -D__mips__ -Wl,-woff,47 +# define sgiCCOptions sgiCommonCCOptions # else # define CppCmd cc -E -cckr # define HasDlopen YES @@ -124,12 +131,12 @@ # ifdef Mips64Architecture /* set Mips64Architecture in host.def. Usually don't need it but we * (the X Consortium) want a 64-bit big-endian machine to test on. */ -# define sgiCCOptions -xansi -mips3 -64 -D__mips__ -Wl,-woff,47 +# define sgiCCOptions -mips3 -64 sgiCommonCCOptions # elif defined(MipsN32Architecture) /* Set MipsN32Architecture to build "new" 32-bit objs with a 32-bit kernel. */ -# define sgiCCOptions -xansi -mips3 -n32 -D__mips__ -Wl,-woff,47 +# define sgiCCOptions -mips3 -n32 sgiCommonCCOptions # else -# define sgiCCOptions -xansi -32 -D__mips__ -Wl,-woff,47 +# define sgiCCOptions -32 sgiCommonCCOptions # endif # if OSMinorVersion == 2 /* if you haven't installed patch 1361, 1403, or 1645 on IRIX 6.2 then you @@ -317,8 +324,12 @@ #endif /* !HasGcc */ +#ifndef XF86Server +#define XF86Server NO +#endif + #ifndef DoLoadableServer -#define DoLoadableServer YES +#define DoLoadableServer XF86Server #endif #include Index: xc/config/cf/sunLib.tmpl diff -u xc/config/cf/sunLib.tmpl:3.14 xc/config/cf/sunLib.tmpl:3.15 --- xc/config/cf/sunLib.tmpl:3.14 Tue Jul 5 09:43:55 2005 +++ xc/config/cf/sunLib.tmpl Fri Jan 4 09:50:10 2008 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/config/cf/sunLib.tmpl,v 3.14 2005/07/05 16:43:55 tsi Exp $ +XCOMM $XFree86: xc/config/cf/sunLib.tmpl,v 3.15 2008/01/04 17:50:10 tsi Exp $ /* * SunOS shared library template @@ -27,7 +27,7 @@ #define SharedXmuRev 4.20 #endif #ifndef SharedXextRev -#define SharedXextRev 4.50 +#define SharedXextRev 4.51 #endif #ifndef SharedXiRev #define SharedXiRev 4.20 Index: xc/config/cf/sv3Lib.tmpl diff -u xc/config/cf/sv3Lib.tmpl:3.5 xc/config/cf/sv3Lib.tmpl:3.6 --- xc/config/cf/sv3Lib.tmpl:3.5 Mon Jan 9 06:56:13 2006 +++ xc/config/cf/sv3Lib.tmpl Fri Jan 4 09:50:10 2008 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/config/cf/sv3Lib.tmpl,v 3.5 2006/01/09 14:56:13 dawes Exp $ +XCOMM $XFree86: xc/config/cf/sv3Lib.tmpl,v 3.6 2008/01/04 17:50:10 tsi Exp $ /* * SVR3 shared library template * Copyright (c) 1992, 1993 by Thomas Wolfram, Berlin, Germany @@ -22,7 +22,7 @@ #define SharedXmuRev 6.0 #endif #ifndef SharedXextRev -#define SharedXextRev 6.0 +#define SharedXextRev 6.1 #endif #ifndef SharedXinputRev #define SharedXinputRev 6.0 Index: xc/config/cf/svr4.cf diff -u xc/config/cf/svr4.cf:3.55 xc/config/cf/svr4.cf:3.56 --- xc/config/cf/svr4.cf:3.55 Wed Sep 14 07:23:14 2005 +++ xc/config/cf/svr4.cf Sat Sep 15 18:37:26 2007 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/config/cf/svr4.cf,v 3.55 2005/09/14 14:23:14 tsi Exp $ +XCOMM $XFree86: xc/config/cf/svr4.cf,v 3.56 2007/09/16 01:37:26 tsi Exp $ /* * Copyright (c) 1994-2004 by The XFree86 Project, Inc. @@ -131,9 +131,6 @@ #ifndef LexCmd #define LexCmd /usr/ccs/bin/lex #endif -#ifndef MakeCmd -#define MakeCmd /usr/ccs/bin/make -#endif #ifndef YaccCmd #define YaccCmd /usr/ccs/bin/yacc #endif Index: xc/config/cf/xf86.tmpl diff -u xc/config/cf/xf86.tmpl:3.39 xc/config/cf/xf86.tmpl:3.40 --- xc/config/cf/xf86.tmpl:3.39 Mon Jun 26 17:52:48 2006 +++ xc/config/cf/xf86.tmpl Tue Mar 18 12:36:52 2008 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/config/cf/xf86.tmpl,v 3.39 2006/06/27 00:52:48 dawes Exp $ +XCOMM $XFree86: xc/config/cf/xf86.tmpl,v 3.40 2008/03/18 19:36:52 tsi Exp $ #ifdef BuilderEMailAddr BUILDERADDR = BuilderEMailAddr @@ -35,6 +35,11 @@ #define JoystickSupport NO #endif +#if UseStackTrace && HasGcc +/* Make stack traces more accurate */ +CCOPTIONS = ServerCCOptions -fno-omit-frame-pointer +#endif + /* * Module support: These overrides must be here, not in xf86.rules, * because they will replace rules after having seen the first lines Index: xc/config/cf/xf86site.def diff -u xc/config/cf/xf86site.def:3.193 xc/config/cf/xf86site.def:3.194 --- xc/config/cf/xf86site.def:3.193 Sat Apr 8 11:33:00 2006 +++ xc/config/cf/xf86site.def Sat Sep 15 17:14:39 2007 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/config/cf/xf86site.def,v 3.193 2006/04/08 18:33:00 dawes Exp $ +XCOMM $XFree86: xc/config/cf/xf86site.def,v 3.194 2007/09/16 00:14:39 tsi Exp $ /******************************************************************************/ /* * This file is to provide a quick method for most people to change the @@ -299,34 +299,6 @@ #define UseSeparateConfDir NO */ -/* - * To enable building the glide driver, you need to define - * HasGlide2 to YES and set the Glide2IncDir variable. - * HasGlide2 is per default NO. - * -#define HasGlide2 YES - */ - -/* - * Set the path to your Glide include files. - * -#define Glide2IncDir /usr/include/glide - */ - -/* - * Have glide 3? - * -#define HasGlide3 YES - */ - -/* - * Set the path to your Glide 3 include files. - * -#define Glide3IncDir /usr/include/glide3 - */ - - - /* * Unless you're a developer you shouldn't need to change anything * beyond this point. Index: xc/config/cf/xfree86.cf diff -u xc/config/cf/xfree86.cf:3.517 xc/config/cf/xfree86.cf:3.519 --- xc/config/cf/xfree86.cf:3.517 Sun Jul 1 08:14:49 2007 +++ xc/config/cf/xfree86.cf Wed Oct 15 13:54:07 2008 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/config/cf/xfree86.cf,v 3.517 2007/07/01 15:14:49 tsi Exp $ +XCOMM $XFree86: xc/config/cf/xfree86.cf,v 3.519 2008/10/15 20:54:07 tsi Exp $ /* * Copyright (c) 1994-2006 by The XFree86 Project, Inc. * All rights reserved. @@ -95,7 +95,7 @@ #ifndef ChangelogDateCmd # define ChangelogDateCmd if tail $(CHANGELOGFILE) | \ @@\ - fgrep '$$$(CHANGELOGID):' >/dev/null 2>&1; then \ @@\ + grep '\\$$$(CHANGELOGID): .* [0-9][0-9]*/[0-9][0-9]*/[0-9][0-9]*' >/dev/null 2>&1; then \ @@\ tail $(CHANGELOGFILE) | fgrep '$$$(CHANGELOGID):' | \ @@\ sed s,'.* \([0-9][0-9]*\)/\([0-9][0-9]*\)/\([0-9][0-9]*\).*,\1\2\3,'; \ @@\ else echo 0; fi @@ -446,14 +446,11 @@ siliconmotion vga dummy fbdev vesa # endif -/* DRI tdfx driver needs Glide, which is not available for AMD64 */ -# define TdfxDriDriver /**/ - # define DevelDRIDrivers /**/ # ifndef DriDrivers # define DriDrivers gamma i810 mga r128 radeon r200 \ - TdfxDriDriver DevelDRIDrivers + tdfx DevelDRIDrivers # endif #endif /*AMD64Arcitecture*/ @@ -908,11 +905,6 @@ DevelDrivers vga \ XF86OSCardDrivers XF86ExtraCardDrivers # endif -# if HasGlide3 -# define TdfxDriDriver tdfx -# else -# define TdfxDriDriver /**/ -# endif # ifndef DriDrivers # define DriDrivers gamma tdfx mga r128 radeon r200 # endif @@ -1065,10 +1057,7 @@ #endif /* The glide driver only works for the loadable server at the moment */ -#ifndef HasGlide2 -#define HasGlide2 NO -#endif -#if HasGlide2 && DoLoadableServer +#if DoLoadableServer #define GlideDriver glide #else #define GlideDriver /**/ Index: xc/config/makedepend/parse.c diff -u xc/config/makedepend/parse.c:1.18 xc/config/makedepend/parse.c:1.19 --- xc/config/makedepend/parse.c:1.18 Sun Jun 17 13:24:59 2007 +++ xc/config/makedepend/parse.c Sat Sep 15 20:44:16 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/config/makedepend/parse.c,v 1.19 2007/09/16 03:44:16 tsi Exp $ */ /* Copyright (c) 1993, 1994, 1998 The Open Group @@ -23,7 +24,6 @@ in this Software without prior written authorization from The Open Group. */ -/* $XFree86: xc/config/makedepend/parse.c,v 1.18 2007/06/17 20:24:59 tsi Exp $ */ #include "def.h" @@ -516,7 +516,7 @@ if (!*val) /* define statements without a value will get a value of 1 */ val = "1"; - if (args && (strlen(args)>0)) + if (strlen(args) > 0) define2(def, args, val, file); else define2(def, NULL, val, file); Index: xc/config/util/lndir.c diff -u xc/config/util/lndir.c:3.26 xc/config/util/lndir.c:3.27 --- xc/config/util/lndir.c:3.26 Thu Apr 12 08:53:03 2007 +++ xc/config/util/lndir.c Sat Sep 15 18:42:17 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/config/util/lndir.c,v 3.26 2007/04/12 15:53:03 tsi Exp $ */ +/* $XFree86: xc/config/util/lndir.c,v 3.27 2007/09/16 01:42:17 tsi Exp $ */ /* Create shadow link tree (after X11R4 script of the same name) Mark Reinhold (mbr@lcs.mit.edu)/3 January 1990 */ @@ -525,7 +525,7 @@ char *prog_name = av[0]; char *fn = NULL, *tn; struct stat fs, ts; - int ret = 0; + int ret = 0, len; while (++av, --ac) { if ((strcmp(*av, "-silent") == 0) || @@ -592,8 +592,8 @@ if (clean_only) { if (cleandir(tn) == -1) - exit(1); - exit(0); + return 1; + return 0; } /* from directory */ @@ -606,11 +606,18 @@ #endif quit (2, "%s: Not a directory", fn); + /* Strip off from directory's trailing self references */ + len = strlen(fn); + while ((--len > 1) && + ((fn[len] == '/') || + ((fn[len] == '.') && (fn[len - 1] == '/')))) + fn[len] = '\0'; + ret = dodir (fn, &fs, &ts, 0); if (ret == 0 && clean) if (cleandir(tn) < 0) ret = 1; - exit(ret); + return ret; } Index: xc/doc/hardcopy/Xext/shape.PS.gz Index: xc/doc/man/X11/XCreWin.man diff -u xc/doc/man/X11/XCreWin.man:1.7 xc/doc/man/X11/XCreWin.man:1.8 --- xc/doc/man/X11/XCreWin.man:1.7 Thu Feb 10 19:02:54 2005 +++ xc/doc/man/X11/XCreWin.man Mon Oct 8 08:11:29 2007 @@ -41,7 +41,7 @@ .\" of this documentation for any purpose. .\" It is provided ``as is'' without express or implied warranty. .\" -.\" $XFree86: xc/doc/man/X11/XCreWin.man,v 1.7 2005/02/11 03:02:54 dawes Exp $ +.\" $XFree86: xc/doc/man/X11/XCreWin.man,v 1.8 2007/10/08 15:11:29 tsi Exp $ .\" .ds xT X Toolkit Intrinsics \- C Language Interface .ds xW Athena X Widgets \- C Language X Toolkit Interface @@ -273,7 +273,7 @@ .LP .ZN XCreateWindow can generate -.ZN BadAlloc +.ZN BadAlloc , .ZN BadColor , .ZN BadCursor , .ZN BadMatch , Index: xc/doc/man/Xext/XShape.man diff -u xc/doc/man/Xext/XShape.man:1.6 xc/doc/man/Xext/XShape.man:1.7 --- xc/doc/man/Xext/XShape.man:1.6 Mon Jan 9 06:56:18 2006 +++ xc/doc/man/Xext/XShape.man Fri Jan 4 09:50:10 2008 @@ -1,3 +1,5 @@ +.\" $XFree86: xc/doc/man/Xext/XShape.man,v 1.7 2008/01/04 17:50:10 tsi Exp $ +.\" .\" Copyright (c) 1989, 1994 X Consortium .\" .\" Permission is hereby granted, free of charge, to any person obtaining a @@ -23,8 +25,6 @@ .\" dealing in this Software without prior written authorization from the .\" X Consortium. .\" -.\" $XFree86: xc/doc/man/Xext/XShape.man,v 1.6 2006/01/09 14:56:18 dawes Exp $ -.\" .de ZN .ie t \fB\^\\$1\^\fR\\$2 .el \fI\^\\$1\^\fP\\$2 @@ -160,6 +160,7 @@ .nf .ZN ShapeBounding .ZN ShapeClip +.ZN ShapeInput .in -.5i .fi .sp Index: xc/doc/specs/Xext/shape.ms diff -u xc/doc/specs/Xext/shape.ms:1.2 xc/doc/specs/Xext/shape.ms:1.3 --- xc/doc/specs/Xext/shape.ms:1.2 Mon Jan 9 06:56:33 2006 +++ xc/doc/specs/Xext/shape.ms Fri Jan 4 09:50:10 2008 @@ -1,5 +1,5 @@ .\" Use -ms and macros.t -.\" $XFree86: xc/doc/specs/Xext/shape.ms,v 1.2 2006/01/09 14:56:33 dawes Exp $ +.\" $XFree86: xc/doc/specs/Xext/shape.ms,v 1.3 2008/01/04 17:50:10 tsi Exp $ .\" edited for DP edits and code consistency w/ core protocol/xlib 4/1/96 .EH '''' .OH '''' @@ -15,7 +15,7 @@ Shape Extension Protocol\fP\s-2 .sp 3 .ce 3 -Version 1.0 +Version 1.1 X Consortium Standard X Version 11, Release 6.4 .sp 6 @@ -23,11 +23,15 @@ \s-1Keith Packard .sp 6p MIT X Consortium +.br +Intel Corporation .ps 9 .nr PS 9 .sp 8 .LP Copyright \(co 1989 X Consortium +.br +Copyright \(co 2006 Keith Packard .LP Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ``Software''), to deal @@ -42,13 +46,14 @@ THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN -AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. .LP -Except as contained in this notice, the name of the X Consortium shall not be -used in advertising or otherwise to promote the sale, use or other dealings -in this Software without prior written authorization from the X Consortium. +Except as contained in this notice, the name of the copyright holders shall not +be used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from the copyright +holders. .ps 10 .nr PS 10 .bp 1 @@ -72,8 +77,8 @@ example, round clocks and nonrectangular icons are desirable visual addition to the desktop. .LP -This extension provides mechanisms for changing the visible shape of a -window to an arbitrary, possibly disjoint, nonrectangular form. The intent +This extension provides mechanisms for changing both the visible and interactive shape of a +window to arbitrary, possibly disjoint, nonrectangular forms. The intent of the extension is to supplement the existing semantics, not replace them. In particular, it is desirable for clients that are unaware of the extension to still be able to cope reasonably with shaped windows. For @@ -86,19 +91,22 @@ .NH 1 Description .LP -Each window (even with no shapes specified) is defined by two regions: the -\fIbounding region\fP and the \fIclip region\fP. The bounding region is the area of the +Each window (even with no shapes specified) is defined by three regions: the +\fIbounding region\fP, the \fIclip region\fP and the \fIinput region\fP. The bounding region is the area of the parent window that the window will occupy (including border). The clip region is the subset of the bounding region that is available for subwindows and graphics. The area between the bounding region and the clip region is defined -to be the border of the window. +to be the border of the window. The input region is the subset of the +bounding region that can ``contain'' the pointer. .LP A nonshaped window will have a bounding region that is a rectangle spanning the window, including its border; the clip region will be a rectangle -filling the inside dimensions (not including the border). In this document, -these areas are referred to as the \fIdefault bounding region\fP and the -\fIdefault clip region\fP. For a window with inside size of \fIwidth\fP by -\fIheight\fP and border width \fIbwidth\fP, the default bounding and clip +filling the inside dimensions (not including the border); the input +region will match the bounding region. In this document, +these areas are referred to as the \fIdefault bounding region\fP, the +\fIdefault clip region\fP and the \fIdefault input region\fP. For a window with inside size of \fIwidth\fP by +\fIheight\fP and border width \fIbwidth\fP, the default bounding, clip +and input regions are the rectangles (relative to the window origin): .LP .sM @@ -112,13 +120,19 @@ clip.y = 0 clip.width = \fIwidth\fP clip.height = \fIheight\fP + +input.x = -\fIbwidth\fP +input.y = -\fIbwidth\fP +input.width = \fIwidth\fP + 2 * \fIbwidth\fP +input.height = \fIheight\fP + 2 * \fIbwidth\fP + .De .LP .eM -This extension allows a client to modify either or both of the bounding or -clip regions by specifying new regions that combine with the default -regions. These new regions are called the \fIclient bounding region\fP and -the \fIclient clip region\fP. They are specified relative to the origin of +This extension allows a client to modify any combination of the bounding, +clip or input regions by specifying new regions that combine with the default +regions. These new regions are called the \fIclient bounding region\fP, +the \fIclient clip region\fP and the \fIclient input region\fP. They are specified relative to the origin of the window and are always defined by offsets relative to the window origin (that is, region adjustments are not required when the window is moved). Three mechanisms for specifying regions are provided: a list of rectangles, @@ -171,6 +185,19 @@ contents beyond the effective bounding region with backing store. The window's origin (for graphics operations, background tiling, and subwindow placement) is not affected by the existence of a bounding region or clip region. +.LP +The \fIeffective input region\fP of a window is defined to be the intersection of the +client input region with both the default input region and the client bounding +region. Any portion of the client input region that is not included in both +the default input region and the client bounding region will not be included in +the effective input region on the screen. +.LP +Construction of the effective input region is dynamic; the client input region is +not mutated to obtain the effective input region. If a client input region is +specified that extends beyond the current default input region and the +window or its bounding region is later enlarged, the effective input region will +be enlarged to include more of the client input region if it is included in +the effective bounding region. .LP Areas that are inside the default bounding region but outside the effective bounding region are not part of the window; these areas of the screen will @@ -182,14 +209,14 @@ .LP An .PN InputOnly -window can have its bounding region set, but it is a +window can have its bounding or input region set, but it is a .PN Match error to attempt to set a clip region on an .PN InputOnly window or to specify its clip region as a source to a request in this extension. .LP -The server must accept changes to the clip region of a root window, but +The server must accept changes to the clip and input regions of a root window, but the server is permitted to ignore requested changes to the bounding region of a root window. If the server accepts bounding region changes, the contents of the screen outside the bounding region are implementation dependent. @@ -201,7 +228,8 @@ .LP SHAPE_KIND: .Pn { Bounding , -.PN Clip } +.PN Clip , +.PN Input } .LP SHAPE_OP: .Pn { Set , @@ -240,7 +268,7 @@ .eM This request can be used to ensure that the server version of the SHAPE extension is usable by the client. This document defines major version one -(1), minor version zero (0). +(1), minor version one (1). .LP .sM .PN "ShapeRectangles" @@ -458,7 +486,7 @@ .PN True causes the server to send the requesting client a .PN ShapeNotify -event whenever the bounding or clip region of the specified window is +event whenever the bounding, clip or input region of the specified window is altered by any client. Specifying enable as .PN False @@ -529,7 +557,7 @@ \fItime\fP\^: TIMESTAMP .LP .eM -Whenever the client bounding or clip shape of a window is modified, a +Whenever the client bounding, clip or input shape of a window is modified, a .PN ShapeNotify event is sent to each client that has used .PN ShapeSelectInput @@ -564,6 +592,7 @@ SHAPE_KIND 0 Bounding 1 Clip + 2 Input .De .LP .Ds 0 @@ -824,6 +853,13 @@ .KE .LP .KS +\fBinput region\fP +.IP +The subset of the bounding region which can ``contain'' the +pointer. +.KE +.LP +.KS \fBdefault bounding region\fP .IP The rectangular area, as described by the core protocol window size, that @@ -838,6 +874,13 @@ .KE .LP .KS +\fBdefault input region\fP +.IP +The rectangular area, as described by the core protocol window size, that +covers the interior of the window and its border. +.KE +.LP +.KS \fBclient bounding region\fP .IP The region associated with a window that is directly modified via this @@ -858,6 +901,16 @@ .KE .LP .KS +\fBclient input region\fP +.IP +The region associated with a window that is directly modified via this +extension when specified by +.PN ShapeInput . +This region is used in conjunction with the default input region +and the client bounding region to produce the effective input region. +.KE +.LP +.KS \fBeffective bounding region\fP .IP The actual shape of the window on the screen, including border and interior @@ -877,3 +930,14 @@ bounding region (if any). Otherwise, the effective clip region is the same as the default clip region. .KE +.LP +.KS +\fBeffective input region\fP +.IP +The actual shape of the window on the screen (excluding the effects of +overlapping windows) which can ``contain'' the pointer. When a window has a +client input region or a client bounding region, the effective input region is +the intersection of the default input region, the client input region (if any) +and the client bounding region (if any). Otherwise, the effective input region +is the same as the default input region. +.KE Index: xc/extras/Mesa/src/mesa/drivers/dri/common/dri_util.c diff -u xc/extras/Mesa/src/mesa/drivers/dri/common/dri_util.c:1.4 xc/extras/Mesa/src/mesa/drivers/dri/common/dri_util.c:1.5 --- xc/extras/Mesa/src/mesa/drivers/dri/common/dri_util.c:1.4 Fri Oct 14 08:15:54 2005 +++ xc/extras/Mesa/src/mesa/drivers/dri/common/dri_util.c Sat Sep 15 20:44:16 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/common/dri_util.c,v 1.4 2005/10/14 15:15:54 tsi Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/common/dri_util.c,v 1.5 2007/09/16 03:44:16 tsi Exp $ */ /** * \file dri_util.c * DRI utility functions. @@ -150,7 +150,7 @@ static __DRIscreen *glx_find_dri_screen(__DRInativeDisplay *d, int i) { PFNGLXFINDDRISCREEN findscreen = - (PFNGLXFINDDRISCREEN)glXGetProcAddress("__glXFindDRIScreen"); + (PFNGLXFINDDRISCREEN)glXGetProcAddress((const GLubyte *)"__glXFindDRIScreen"); if (!findscreen) { Index: xc/extras/Mesa/src/mesa/drivers/dri/gamma/gamma_tris.c diff -u xc/extras/Mesa/src/mesa/drivers/dri/gamma/gamma_tris.c:1.1.1.2 xc/extras/Mesa/src/mesa/drivers/dri/gamma/gamma_tris.c:1.2 --- xc/extras/Mesa/src/mesa/drivers/dri/gamma/gamma_tris.c:1.1.1.2 Fri Dec 10 07:06:05 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/gamma/gamma_tris.c Sat Sep 15 20:44:16 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/gamma/gamma_tris.c,v 1.2 2007/09/16 03:44:16 tsi Exp $ */ /* * Copyright 2001 by Alan Hourihane. * @@ -321,8 +322,8 @@ #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[4] = color[idx] #define LOCAL_VARS(n) \ - gammaContextPtr gmesa = GAMMA_CONTEXT(ctx); \ - GLuint color[n]; \ + gammaContextPtr gmesa = GAMMA_CONTEXT(ctx); \ + GLuint color[n] = {0, }; \ (void) color; Index: xc/extras/Mesa/src/mesa/drivers/dri/i810/i810tris.c diff -u xc/extras/Mesa/src/mesa/drivers/dri/i810/i810tris.c:1.1.1.2 xc/extras/Mesa/src/mesa/drivers/dri/i810/i810tris.c:1.2 --- xc/extras/Mesa/src/mesa/drivers/dri/i810/i810tris.c:1.1.1.2 Fri Dec 10 07:05:45 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/i810/i810tris.c Sat Sep 15 20:44:16 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/i810/i810tris.c,v 1.1.1.2 2004/12/10 15:05:45 alanh Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/i810/i810tris.c,v 1.2 2007/09/16 03:44:16 tsi Exp $ */ /************************************************************************** Copyright 2001 VA Linux Systems Inc., Fremont, California. @@ -269,7 +269,7 @@ #define LOCAL_VARS(n) \ i810ContextPtr imesa = I810_CONTEXT(ctx); \ - GLuint color[n], spec[n]; \ + GLuint color[n] = {0, }, spec[n] = {0, }; \ GLuint coloroffset = (imesa->vertex_size == 4 ? 3 : 4); \ GLboolean havespec = (imesa->vertex_size > 4); \ (void) color; (void) spec; (void) coloroffset; (void) havespec; Index: xc/extras/Mesa/src/mesa/drivers/dri/mga/mga_xmesa.h diff -u xc/extras/Mesa/src/mesa/drivers/dri/mga/mga_xmesa.h:1.2 xc/extras/Mesa/src/mesa/drivers/dri/mga/mga_xmesa.h:1.3 --- xc/extras/Mesa/src/mesa/drivers/dri/mga/mga_xmesa.h:1.2 Mon Dec 13 14:40:52 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/mga/mga_xmesa.h Sun Sep 16 09:38:21 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/mga/mga_xmesa.h,v 1.3 2007/09/16 16:38:21 tsi Exp $ */ /* * Copyright 2000-2001 VA Linux Systems, Inc. * All Rights Reserved. @@ -24,7 +25,6 @@ * Authors: * Keith Whitwell */ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/mga/mga_xmesa.h,v 1.2 2004/12/13 22:40:52 tsi Exp $ */ #ifndef _MGA_INIT_H_ #define _MGA_INIT_H_ @@ -47,7 +47,7 @@ int cpp; /* for front and back buffers */ GLint agpMode; - unsigned int irq; /* IRQ number (0 means none) */ + int irq; /* IRQ number (0 means none) */ GLboolean linecomp_sane; /* GL_TRUE if line comp. programmed correctly * by the DDX driver. */ Index: xc/extras/Mesa/src/mesa/drivers/dri/mga/mgatris.c diff -u xc/extras/Mesa/src/mesa/drivers/dri/mga/mgatris.c:1.1.1.2 xc/extras/Mesa/src/mesa/drivers/dri/mga/mgatris.c:1.2 --- xc/extras/Mesa/src/mesa/drivers/dri/mga/mgatris.c:1.1.1.2 Fri Dec 10 07:05:40 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/mga/mgatris.c Sat Sep 15 20:44:16 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/mga/mgatris.c,v 1.2 2007/09/16 03:44:16 tsi Exp $ */ /* * Copyright 2000-2001 VA Linux Systems, Inc. * All Rights Reserved. @@ -24,7 +25,6 @@ * Authors: * Keith Whitwell */ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/mga/mgatris.c,v 1.1.1.2 2004/12/10 15:05:40 alanh Exp $ */ #include "mtypes.h" #include "macros.h" @@ -394,7 +394,7 @@ #define LOCAL_VARS(n) \ mgaContextPtr mmesa = MGA_CONTEXT(ctx); \ - GLuint color[n], spec[n]; \ + GLuint color[n] = {0, }, spec[n] = {0, }; \ (void) color; (void) spec; Index: xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_screen.h diff -u xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_screen.h:1.1.1.2 xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_screen.h:1.2 --- xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_screen.h:1.1.1.2 Fri Dec 10 07:05:53 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_screen.h Sun Sep 16 09:38:21 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_screen.h,v 1.1.1.2 2004/12/10 15:05:53 alanh Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_screen.h,v 1.2 2007/09/16 16:38:21 tsi Exp $ */ /************************************************************************** Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., @@ -52,7 +52,7 @@ GLint cpp; GLint IsPCI; /* Current card is a PCI card */ GLint AGPMode; - unsigned int irq; /* IRQ number (0 means none) */ + int irq; /* IRQ number (0 means none) */ GLuint frontOffset; GLuint frontPitch; Index: xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_tris.c diff -u xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_tris.c:1.1.1.3 xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_tris.c:1.2 --- xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_tris.c:1.1.1.3 Fri Dec 10 07:32:58 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_tris.c Sat Sep 15 20:44:16 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_tris.c,v 1.1.1.3 2004/12/10 15:32:58 alanh Exp $ */ /* -*- c-basic-offset: 3 -*- */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r128/r128_tris.c,v 1.2 2007/09/16 03:44:16 tsi Exp $ */ /************************************************************************** Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and @@ -217,7 +217,7 @@ #define LOCAL_VARS(n) \ r128ContextPtr rmesa = R128_CONTEXT(ctx); \ - GLuint color[n], spec[n]; \ + GLuint color[n] = {0, }, spec[n] = {0, }; \ GLuint coloroffset = rmesa->coloroffset; \ GLuint specoffset = rmesa->specoffset; \ GLboolean havespec = (rmesa->specoffset != 0); \ Index: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_cmdbuf.c diff -u xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_cmdbuf.c:1.1.1.2 xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_cmdbuf.c:1.2 --- xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_cmdbuf.c:1.1.1.2 Fri Dec 10 07:05:56 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_cmdbuf.c Wed Apr 2 14:02:29 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_cmdbuf.c,v 1.1.1.2 2004/12/10 15:05:56 alanh Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_cmdbuf.c,v 1.2 2008/04/02 21:02:29 tsi Exp $ */ /* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. @@ -44,7 +44,7 @@ #include "r200_ioctl.h" #include "r200_tcl.h" #include "r200_sanity.h" -#include "radeon_reg.h" +#include "r200_reg.h" static void print_state_atom( struct r200_state_atom *state ) { Index: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_ioctl.c diff -u xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_ioctl.c:1.5 xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_ioctl.c:1.7 --- xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_ioctl.c:1.5 Wed Dec 15 07:40:28 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_ioctl.c Wed Apr 2 14:02:29 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_ioctl.c,v 1.5 2004/12/15 15:40:28 tsi Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_ioctl.c,v 1.7 2008/04/02 21:02:29 tsi Exp $ */ /* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. @@ -47,7 +47,7 @@ #include "r200_ioctl.h" #include "r200_tcl.h" #include "r200_sanity.h" -#include "radeon_reg.h" +#include "r200_reg.h" #include "vblank.h" @@ -642,7 +642,7 @@ int clear; gp.param = RADEON_PARAM_LAST_CLEAR; - gp.value = (int *)&clear; + gp.value = &clear; ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp) ); Index: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_reg.h diff -u xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_reg.h:1.1.1.2 xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_reg.h:1.2 --- xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_reg.h:1.1.1.2 Fri Dec 10 07:06:00 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_reg.h Wed Apr 2 14:02:29 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_reg.h,v 1.1.1.2 2004/12/10 15:06:00 alanh Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_reg.h,v 1.2 2008/04/02 21:02:29 tsi Exp $ */ /* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. @@ -30,6 +30,8 @@ #ifndef _R200_REG_H_ #define _R200_REG_H_ +#include "radeon_reg.h" + #define R200_PP_MISC 0x1c14 #define R200_REF_ALPHA_MASK 0x000000ff #define R200_ALPHA_TEST_FAIL (0 << 8) @@ -1028,6 +1030,7 @@ #define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) #define R200_TXC_ARG_A_MASK (31 << 0) #define R200_TXC_ARG_A_SHIFT 0 +#ifndef R200_TXC_ARG_B_ZERO /* Might be in radeon_reg.h */ #define R200_TXC_ARG_B_ZERO (0<<5) #define R200_TXC_ARG_B_CURRENT_COLOR (2<<5) #define R200_TXC_ARG_B_CURRENT_ALPHA (3<<5) @@ -1051,8 +1054,10 @@ #define R200_TXC_ARG_B_R5_ALPHA (21<<5) #define R200_TXC_ARG_B_TFACTOR1_COLOR (26<<5) #define R200_TXC_ARG_B_TFACTOR1_ALPHA (27<<5) +#endif #define R200_TXC_ARG_B_MASK (31 << 5) #define R200_TXC_ARG_B_SHIFT 5 +#ifndef R200_TXC_ARG_C_ZERO /* Might be in radeon_reg.h */ #define R200_TXC_ARG_C_ZERO (0<<10) #define R200_TXC_ARG_C_CURRENT_COLOR (2<<10) #define R200_TXC_ARG_C_CURRENT_ALPHA (3<<10) @@ -1076,6 +1081,7 @@ #define R200_TXC_ARG_C_R5_ALPHA (21<<10) #define R200_TXC_ARG_C_TFACTOR1_COLOR (26<<10) #define R200_TXC_ARG_C_TFACTOR1_ALPHA (27<<10) +#endif #define R200_TXC_ARG_C_MASK (31 << 10) #define R200_TXC_ARG_C_SHIFT 10 #define R200_TXC_COMP_ARG_A (1 << 16) @@ -1173,6 +1179,7 @@ #define R200_TXA_ARG_A_TFACTOR1_BLUE (27) #define R200_TXA_ARG_A_MASK (31 << 0) #define R200_TXA_ARG_A_SHIFT 0 +#ifndef R200_TXA_ARG_B_ZERO /* Might be in radeon_reg.h */ #define R200_TXA_ARG_B_ZERO (0<<5) #define R200_TXA_ARG_B_CURRENT_ALPHA (2<<5) /* guess */ #define R200_TXA_ARG_B_CURRENT_BLUE (3<<5) /* guess */ @@ -1196,8 +1203,10 @@ #define R200_TXA_ARG_B_R5_BLUE (21<<5) #define R200_TXA_ARG_B_TFACTOR1_ALPHA (26<<5) #define R200_TXA_ARG_B_TFACTOR1_BLUE (27<<5) +#endif #define R200_TXA_ARG_B_MASK (31 << 5) #define R200_TXA_ARG_B_SHIFT 5 +#ifndef R200_TXA_ARG_C_ZERO /* Might be in radeon_reg.h */ #define R200_TXA_ARG_C_ZERO (0<<10) #define R200_TXA_ARG_C_CURRENT_ALPHA (2<<10) /* guess */ #define R200_TXA_ARG_C_CURRENT_BLUE (3<<10) /* guess */ @@ -1221,6 +1230,7 @@ #define R200_TXA_ARG_C_R5_BLUE (21<<10) #define R200_TXA_ARG_C_TFACTOR1_ALPHA (26<<10) #define R200_TXA_ARG_C_TFACTOR1_BLUE (27<<10) +#endif #define R200_TXA_ARG_C_MASK (31 << 10) #define R200_TXA_ARG_C_SHIFT 10 #define R200_TXA_COMP_ARG_A (1 << 16) Index: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_sanity.c diff -u xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_sanity.c:1.2 xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_sanity.c:1.3 --- xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_sanity.c:1.2 Mon Feb 28 19:48:45 2005 +++ xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_sanity.c Wed Apr 2 14:02:29 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_sanity.c,v 1.2 2005/03/01 03:48:45 dawes Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_sanity.c,v 1.3 2008/04/02 21:02:29 tsi Exp $ */ /************************************************************************** Copyright 2002 ATI Technologies Inc., Ontario, Canada, and @@ -41,7 +41,6 @@ #include "r200_context.h" #include "r200_ioctl.h" #include "r200_sanity.h" -#include "radeon_reg.h" #include "r200_reg.h" /* Set this '1' to get more verbiage. Index: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.c diff -u xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.c:1.7 xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.c:1.9 --- xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.c:1.7 Mon Dec 13 14:40:53 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.c Wed Apr 2 14:02:29 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.c,v 1.7 2004/12/13 22:40:53 tsi Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.c,v 1.9 2008/04/02 21:02:29 tsi Exp $ */ /* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. @@ -46,7 +46,7 @@ #include "r200_context.h" #include "r200_ioctl.h" #include "radeon_macros.h" -#include "radeon_reg.h" +#include "r200_reg.h" #include "utils.h" #include "vblank.h" @@ -303,7 +303,7 @@ drm_radeon_getparam_t gp; gp.param = RADEON_PARAM_GART_BUFFER_OFFSET; - gp.value = &screen->gart_buffer_offset; + gp.value = (int *)&screen->gart_buffer_offset; ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); @@ -315,7 +315,7 @@ if (sPriv->drmMinor >= 6) { gp.param = RADEON_PARAM_GART_BASE; - gp.value = &screen->gart_base; + gp.value = (int *)&screen->gart_base; ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); Index: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.h diff -u xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.h:1.1.1.2 xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.h:1.2 --- xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.h:1.1.1.2 Fri Dec 10 07:05:58 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.h Sun Sep 16 09:38:21 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.h,v 1.1.1.2 2004/12/10 15:05:58 alanh Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_screen.h,v 1.2 2007/09/16 16:38:21 tsi Exp $ */ /* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. @@ -64,7 +64,7 @@ int cpp; int IsPCI; /* Current card is a PCI card */ int AGPMode; - unsigned int irq; /* IRQ number (0 means none) */ + int irq; /* IRQ number (0 means none) */ unsigned int fbLocation; unsigned int frontOffset; @@ -87,7 +87,7 @@ drmBufMapPtr buffers; - __volatile__ int32_t *scratch; + __volatile__ u_int32_t *scratch; __DRIscreenPrivate *driScreen; unsigned int sarea_priv_offset; Index: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_swtcl.c diff -u xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_swtcl.c:1.4 xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_swtcl.c:1.5 --- xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_swtcl.c:1.4 Fri Dec 10 07:41:01 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_swtcl.c Sat Sep 15 20:44:16 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_swtcl.c,v 1.4 2004/12/10 15:41:01 alanh Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_swtcl.c,v 1.5 2007/09/16 03:44:16 tsi Exp $ */ /* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. @@ -480,10 +480,10 @@ #undef INIT #define LOCAL_VARS(n) \ - r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - GLuint color[n], spec[n]; \ - GLuint coloroffset = rmesa->swtcl.coloroffset; \ - GLuint specoffset = rmesa->swtcl.specoffset; \ + r200ContextPtr rmesa = R200_CONTEXT(ctx); \ + GLuint color[n] = {0, }, spec[n] = {0, }; \ + GLuint coloroffset = rmesa->swtcl.coloroffset; \ + GLuint specoffset = rmesa->swtcl.specoffset; \ (void) color; (void) spec; (void) coloroffset; (void) specoffset; /*********************************************************************** Index: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_texmem.c diff -u xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_texmem.c:1.1.1.4 xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_texmem.c:1.2 --- xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_texmem.c:1.1.1.4 Fri Dec 10 07:33:02 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_texmem.c Wed Apr 2 14:02:29 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_texmem.c,v 1.1.1.4 2004/12/10 15:33:02 alanh Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/r200/r200_texmem.c,v 1.2 2008/04/02 21:02:29 tsi Exp $ */ /************************************************************************** Copyright (C) Tungsten Graphics 2002. All Rights Reserved. @@ -43,7 +43,7 @@ #include "context.h" #include "colormac.h" #include "macros.h" -#include "radeon_reg.h" /* gets definition for usleep */ +#include "r200_reg.h" /* gets definition for usleep */ #include "r200_context.h" #include "r200_state.h" #include "r200_ioctl.h" Index: xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.c diff -u xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.c:1.7 xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.c:1.8 --- xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.c:1.7 Mon Dec 13 14:40:53 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.c Sun Sep 16 09:38:21 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.c,v 1.7 2004/12/13 22:40:53 tsi Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.c,v 1.8 2007/09/16 16:38:21 tsi Exp $ */ /************************************************************************** Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and @@ -223,7 +223,7 @@ drm_radeon_getparam_t gp; gp.param = RADEON_PARAM_GART_BUFFER_OFFSET; - gp.value = &screen->gart_buffer_offset; + gp.value = (int *)&screen->gart_buffer_offset; ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); Index: xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.h diff -u xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.h:1.2 xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.h:1.3 --- xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.h:1.2 Mon Dec 13 14:40:53 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.h Sun Sep 16 09:38:21 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.h,v 1.2 2004/12/13 22:40:53 tsi Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.h,v 1.3 2007/09/16 16:38:21 tsi Exp $ */ /************************************************************************** Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and @@ -65,7 +65,7 @@ int cpp; int IsPCI; /* Current card is a PCI card */ int AGPMode; - unsigned int irq; /* IRQ number (0 means none) */ + int irq; /* IRQ number (0 means none) */ unsigned int fbLocation; unsigned int frontOffset; Index: xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c diff -u xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c:1.6 xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c:1.7 --- xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c:1.6 Mon Dec 13 14:40:54 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c Sat Sep 15 20:44:16 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c,v 1.6 2004/12/13 22:40:54 tsi Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c,v 1.7 2007/09/16 03:44:16 tsi Exp $ */ /************************************************************************** Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and @@ -941,7 +941,7 @@ #define LOCAL_VARS(n) \ radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \ - GLuint color[n], spec[n]; \ + GLuint color[n] = {0, }, spec[n] = {0, }; \ GLuint coloroffset = (rmesa->swtcl.vertex_size == 4 ? 3 : 4); \ GLboolean havespec = (rmesa->swtcl.vertex_size > 4); \ (void) color; (void) spec; (void) coloroffset; (void) havespec; Index: xc/extras/Mesa/src/mesa/drivers/dri/tdfx/tdfx_glide.h diff -u xc/extras/Mesa/src/mesa/drivers/dri/tdfx/tdfx_glide.h:1.1.1.1 xc/extras/Mesa/src/mesa/drivers/dri/tdfx/tdfx_glide.h:1.2 --- xc/extras/Mesa/src/mesa/drivers/dri/tdfx/tdfx_glide.h:1.1.1.1 Thu Apr 8 02:17:20 2004 +++ xc/extras/Mesa/src/mesa/drivers/dri/tdfx/tdfx_glide.h Sat Sep 15 17:14:40 2007 @@ -2,7 +2,7 @@ * This file defines macros and types necessary for accessing glide3. */ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/tdfx/tdfx_glide.h,v 1.1.1.1 2004/04/08 09:17:20 alanh Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/dri/tdfx/tdfx_glide.h,v 1.2 2007/09/16 00:14:40 tsi Exp $ */ #ifndef NEWGLIDE_H #define NEWGLIDE_H @@ -13,19 +13,12 @@ typedef signed char FxI8; typedef unsigned short FxU16; typedef signed short FxI16; -#if defined(__alpha__) || defined (__LP64__) typedef signed int FxI32; typedef unsigned int FxU32; -#else -typedef signed long FxI32; -typedef unsigned long FxU32; -#endif -typedef unsigned long AnyPtr; typedef int FxBool; typedef float FxFloat; typedef double FxDouble; -typedef unsigned long FxColor_t; typedef struct { float r, g, b, a; Index: xc/extras/Mesa/src/mesa/drivers/x11/xm_api.c diff -u xc/extras/Mesa/src/mesa/drivers/x11/xm_api.c:1.5 xc/extras/Mesa/src/mesa/drivers/x11/xm_api.c:1.6 --- xc/extras/Mesa/src/mesa/drivers/x11/xm_api.c:1.5 Fri Dec 10 07:30:11 2004 +++ xc/extras/Mesa/src/mesa/drivers/x11/xm_api.c Sun Nov 4 11:57:14 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Mesa/src/mesa/drivers/x11/xm_api.c,v 1.5 2004/12/10 15:30:11 alanh Exp $ */ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/x11/xm_api.c,v 1.6 2007/11/04 19:57:14 tsi Exp $ */ /* * Mesa 3-D graphics library * Version: 6.1 @@ -96,7 +96,7 @@ /* * Lookup tables for HPCR pixel format: */ -static short hpcr_rgbTbl[3][256] = { +static const short hpcr_rgbTbl[3][256] = { { 16, 16, 17, 17, 18, 18, 19, 19, 20, 20, 21, 21, 22, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29, 29, 30, 30, 31, 31, @@ -1044,7 +1044,7 @@ * Compute component-to-pixel lookup tables and dithering kernel */ { - static GLubyte kernel[16] = { + static const GLubyte kernel[16] = { 0*16, 8*16, 2*16, 10*16, 12*16, 4*16, 14*16, 6*16, 3*16, 11*16, 1*16, 9*16, @@ -2012,8 +2012,18 @@ */ void XMesaDestroyBuffer( XMesaBuffer b ) { + XMesaBuffer buf; int client = 0; + for (buf = XMesaBufferList; ; buf = buf->Next) { + if (!buf) { + _mesa_problem(NULL, "XMesaBDestroyBuffer(%p) - attempt to free" + " an unknown buffer\n", b); + return; + } + if (buf == b) break; + } + #ifdef XFree86Server if (b->frontbuffer) client = CLIENT_ID(b->frontbuffer->id); @@ -2592,15 +2602,6 @@ } -void XMesaReset( void ) -{ - while (XMesaBufferList) - XMesaDestroyBuffer(XMesaBufferList); - - XMesaBufferList = NULL; -} - - unsigned long XMesaDitherColor( XMesaContext xmesa, GLint x, GLint y, GLfloat red, GLfloat green, GLfloat blue, GLfloat alpha ) Index: xc/extras/Mesa/src/mesa/drivers/x11/xmesaP.h diff -u xc/extras/Mesa/src/mesa/drivers/x11/xmesaP.h:1.1.1.2 xc/extras/Mesa/src/mesa/drivers/x11/xmesaP.h:1.2 --- xc/extras/Mesa/src/mesa/drivers/x11/xmesaP.h:1.1.1.2 Thu Jun 10 07:23:34 2004 +++ xc/extras/Mesa/src/mesa/drivers/x11/xmesaP.h Sun Nov 4 11:57:14 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/extras/Mesa/src/mesa/drivers/x11/xmesaP.h,v 1.2 2007/11/04 19:57:14 tsi Exp $ */ /* * Mesa 3-D graphics library * Version: 6.1 @@ -518,7 +519,6 @@ extern void XMesaSetVisualDisplay( XMesaDisplay *dpy, XMesaVisual v ); extern GLboolean XMesaForceCurrent(XMesaContext c); extern GLboolean XMesaLoseCurrent(XMesaContext c); -extern void XMesaReset( void ); #endif Index: xc/extras/Mesa/src/mesa/tnl_dd/t_dd_dmatmp.h diff -u xc/extras/Mesa/src/mesa/tnl_dd/t_dd_dmatmp.h:1.1.1.3 xc/extras/Mesa/src/mesa/tnl_dd/t_dd_dmatmp.h:1.2 --- xc/extras/Mesa/src/mesa/tnl_dd/t_dd_dmatmp.h:1.1.1.3 Fri Dec 10 07:06:55 2004 +++ xc/extras/Mesa/src/mesa/tnl_dd/t_dd_dmatmp.h Sat Sep 15 20:44:17 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/extras/Mesa/src/mesa/tnl_dd/t_dd_dmatmp.h,v 1.2 2007/09/16 03:44:17 tsi Exp $ */ /* * Mesa 3-D graphics library * Version: 6.1 @@ -702,7 +703,6 @@ /* Emit whole number of lines in total and in each buffer: */ count -= (count-start) & 1; - currentsz -= currentsz & 1; dmasz -= dmasz & 1; currentsz = GET_CURRENT_VB_MAX_ELTS(); Index: xc/extras/Xpm/lib/s_popen.c diff -u xc/extras/Xpm/lib/s_popen.c:1.3 xc/extras/Xpm/lib/s_popen.c:1.4 --- xc/extras/Xpm/lib/s_popen.c:1.3 Thu Mar 24 18:22:50 2005 +++ xc/extras/Xpm/lib/s_popen.c Sat Sep 15 20:44:17 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/Xpm/lib/s_popen.c,v 1.3 2005/03/25 02:22:50 dawes Exp $ */ +/* $XFree86: xc/extras/Xpm/lib/s_popen.c,v 1.4 2007/09/16 03:44:17 tsi Exp $ */ /* * Copyright (C) 2004 The X.Org fundation * @@ -58,7 +58,7 @@ char *cmdcpy; - if(cmd == NULL || cmd == "") + if(cmd == NULL || *cmd == '\0') return(NULL); if(type[0] != 'r' && type[0] != 'w') Index: xc/extras/ogl-sample/main/gfx/lib/glu/libtess/tess.c diff -u xc/extras/ogl-sample/main/gfx/lib/glu/libtess/tess.c:1.3 xc/extras/ogl-sample/main/gfx/lib/glu/libtess/tess.c:1.4 --- xc/extras/ogl-sample/main/gfx/lib/glu/libtess/tess.c:1.3 Sat Oct 27 20:32:22 2001 +++ xc/extras/ogl-sample/main/gfx/lib/glu/libtess/tess.c Sun Apr 6 12:17:40 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/extras/ogl-sample/main/gfx/lib/glu/libtess/tess.c,v 1.4 2008/04/06 19:17:40 tsi Exp $ */ /* ** License Applicability. Except to the extent portions of this file are ** made subject to an alternative license as permitted in the SGI Free @@ -36,7 +37,6 @@ ** Author: Eric Veach, July 1994. ** */ -/* $XFree86: xc/extras/ogl-sample/main/gfx/lib/glu/libtess/tess.c,v 1.3 2001/10/28 03:32:22 tsi Exp $ */ #include "gluos.h" #include @@ -275,7 +275,7 @@ void GLAPIENTRY gluTessCallback( GLUtesselator *tess, GLenum which, - GLvoid (GLAPIENTRY *fn)(GLvoid)) + GLvoid (GLAPIENTRY *fn)(void)) { switch( which ) { case GLU_TESS_BEGIN: Index: xc/extras/ogl-sample/main/gfx/lib/glu/libutil/quad.c diff -u xc/extras/ogl-sample/main/gfx/lib/glu/libutil/quad.c:1.4 xc/extras/ogl-sample/main/gfx/lib/glu/libutil/quad.c:1.5 --- xc/extras/ogl-sample/main/gfx/lib/glu/libutil/quad.c:1.4 Tue Mar 4 08:25:05 2003 +++ xc/extras/ogl-sample/main/gfx/lib/glu/libutil/quad.c Sun Apr 6 12:17:40 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/extras/ogl-sample/main/gfx/lib/glu/libutil/quad.c,v 1.5 2008/04/06 19:17:40 tsi Exp $ */ /* ** License Applicability. Except to the extent portions of this file are ** made subject to an alternative license as permitted in the SGI Free @@ -32,7 +33,6 @@ ** compliant with the OpenGL(R) version 1.2.1 Specification. ** */ -/* $XFree86: xc/extras/ogl-sample/main/gfx/lib/glu/libutil/quad.c,v 1.4 2003/03/04 16:25:05 tsi Exp $ */ #include "gluos.h" #include "gluint.h" @@ -90,7 +90,7 @@ void GLAPIENTRY gluQuadricCallback(GLUquadric *qobj, GLenum which, - GLvoid (GLAPIENTRY *fn)(GLvoid)) + GLvoid (GLAPIENTRY *fn)(void)) { switch (which) { case GLU_ERROR: Index: xc/extras/x86emu/src/x86emu/decode.c diff -u xc/extras/x86emu/src/x86emu/decode.c:1.13 xc/extras/x86emu/src/x86emu/decode.c:1.14 --- xc/extras/x86emu/src/x86emu/decode.c:1.13 Sat Oct 23 08:29:25 2004 +++ xc/extras/x86emu/src/x86emu/decode.c Wed Oct 15 13:59:10 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/extras/x86emu/src/x86emu/decode.c,v 1.14 2008/10/15 20:59:10 tsi Exp $ */ /**************************************************************************** * * Realmode X86 Emulator Library @@ -37,8 +38,6 @@ * ****************************************************************************/ -/* $XFree86: xc/extras/x86emu/src/x86emu/decode.c,v 1.13 2004/10/23 15:29:25 dawes Exp $ */ - #include "x86emu/x86emui.h" /*----------------------------- Implementation ----------------------------*/ @@ -833,6 +832,7 @@ int sib; if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ switch (rm) { case 0: DECODE_PRINTF("[EAX]"); @@ -862,21 +862,22 @@ } HALT_SYS(); } else { + /* 16-bit addressing */ switch (rm) { case 0: DECODE_PRINTF("[BX+SI]"); - return M.x86.R_BX + M.x86.R_SI; + return (M.x86.R_BX + M.x86.R_SI) & 0xffff; case 1: DECODE_PRINTF("[BX+DI]"); - return M.x86.R_BX + M.x86.R_DI; + return (M.x86.R_BX + M.x86.R_DI) & 0xffff; case 2: DECODE_PRINTF("[BP+SI]"); M.x86.mode |= SYSMODE_SEG_DS_SS; - return M.x86.R_BP + M.x86.R_SI; + return (M.x86.R_BP + M.x86.R_SI) & 0xffff; case 3: DECODE_PRINTF("[BP+DI]"); M.x86.mode |= SYSMODE_SEG_DS_SS; - return M.x86.R_BP + M.x86.R_DI; + return (M.x86.R_BP + M.x86.R_DI) & 0xffff; case 4: DECODE_PRINTF("[SI]"); return M.x86.R_SI; @@ -918,6 +919,7 @@ displacement = (s8)fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ switch (rm) { case 0: DECODE_PRINTF2("%d[EAX]", displacement); @@ -948,34 +950,35 @@ } HALT_SYS(); } else { + /* 16-bit addressing */ switch (rm) { case 0: DECODE_PRINTF2("%d[BX+SI]", displacement); - return M.x86.R_BX + M.x86.R_SI + displacement; + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; case 1: DECODE_PRINTF2("%d[BX+DI]", displacement); - return M.x86.R_BX + M.x86.R_DI + displacement; + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; case 2: DECODE_PRINTF2("%d[BP+SI]", displacement); M.x86.mode |= SYSMODE_SEG_DS_SS; - return M.x86.R_BP + M.x86.R_SI + displacement; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; case 3: DECODE_PRINTF2("%d[BP+DI]", displacement); M.x86.mode |= SYSMODE_SEG_DS_SS; - return M.x86.R_BP + M.x86.R_DI + displacement; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; case 4: DECODE_PRINTF2("%d[SI]", displacement); - return M.x86.R_SI + displacement; + return (M.x86.R_SI + displacement) & 0xffff; case 5: DECODE_PRINTF2("%d[DI]", displacement); - return M.x86.R_DI + displacement; + return (M.x86.R_DI + displacement) & 0xffff; case 6: DECODE_PRINTF2("%d[BP]", displacement); M.x86.mode |= SYSMODE_SEG_DS_SS; - return M.x86.R_BP + displacement; + return (M.x86.R_BP + displacement) & 0xffff; case 7: DECODE_PRINTF2("%d[BX]", displacement); - return M.x86.R_BX + displacement; + return (M.x86.R_BX + displacement) & 0xffff; } HALT_SYS(); } @@ -1009,6 +1012,7 @@ } if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ switch (rm) { case 0: DECODE_PRINTF2("%08x[EAX]", displacement); @@ -1040,34 +1044,35 @@ } HALT_SYS(); } else { + /* 16-bit addressing */ switch (rm) { case 0: DECODE_PRINTF2("%04x[BX+SI]", displacement); - return M.x86.R_BX + M.x86.R_SI + displacement; + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; case 1: DECODE_PRINTF2("%04x[BX+DI]", displacement); - return M.x86.R_BX + M.x86.R_DI + displacement; + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; case 2: DECODE_PRINTF2("%04x[BP+SI]", displacement); M.x86.mode |= SYSMODE_SEG_DS_SS; - return M.x86.R_BP + M.x86.R_SI + displacement; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; case 3: DECODE_PRINTF2("%04x[BP+DI]", displacement); M.x86.mode |= SYSMODE_SEG_DS_SS; - return M.x86.R_BP + M.x86.R_DI + displacement; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; case 4: DECODE_PRINTF2("%04x[SI]", displacement); - return M.x86.R_SI + displacement; + return (M.x86.R_SI + displacement) & 0xffff; case 5: DECODE_PRINTF2("%04x[DI]", displacement); - return M.x86.R_DI + displacement; + return (M.x86.R_DI + displacement) & 0xffff; case 6: DECODE_PRINTF2("%04x[BP]", displacement); M.x86.mode |= SYSMODE_SEG_DS_SS; - return M.x86.R_BP + displacement; + return (M.x86.R_BP + displacement) & 0xffff; case 7: DECODE_PRINTF2("%04x[BX]", displacement); - return M.x86.R_BX + displacement; + return (M.x86.R_BX + displacement) & 0xffff; } HALT_SYS(); } Index: xc/extras/x86emu/src/x86emu/ops.c diff -u xc/extras/x86emu/src/x86emu/ops.c:1.11 xc/extras/x86emu/src/x86emu/ops.c:1.12 --- xc/extras/x86emu/src/x86emu/ops.c:1.11 Tue Nov 9 20:08:27 2004 +++ xc/extras/x86emu/src/x86emu/ops.c Wed Oct 15 13:59:10 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/extras/x86emu/src/x86emu/ops.c,v 1.12 2008/10/15 20:59:10 tsi Exp $ */ /**************************************************************************** * * Realmode X86 Emulator Library @@ -70,8 +71,6 @@ * ****************************************************************************/ -/* $XFree86: xc/extras/x86emu/src/x86emu/ops.c,v 1.11 2004/11/10 04:08:27 dawes Exp $ */ - #include "x86emu/x86emui.h" /*----------------------------- Implementation ----------------------------*/ @@ -9421,9 +9420,16 @@ ****************************************************************************/ static void x86emuOp_aad(u8 X86EMU_UNUSED(op1)) { + u8 a; + START_OF_INSTR(); DECODE_PRINTF("AAD\n"); - (void) fetch_byte_imm(); + a = fetch_byte_imm(); + if (a != 10) { + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); + } TRACE_AND_STEP(); M.x86.R_AX = aad_word(M.x86.R_AX); DECODE_CLEAR_SEGOVR(); Index: xc/extras/x86emu/src/x86emu/ops2.c diff -u xc/extras/x86emu/src/x86emu/ops2.c:1.7 xc/extras/x86emu/src/x86emu/ops2.c:1.8 --- xc/extras/x86emu/src/x86emu/ops2.c:1.7 Fri Feb 6 09:15:28 2004 +++ xc/extras/x86emu/src/x86emu/ops2.c Wed Oct 15 13:59:11 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/extras/x86emu/src/x86emu/ops2.c,v 1.8 2008/10/15 20:59:11 tsi Exp $ */ /**************************************************************************** * * Realmode X86 Emulator Library @@ -37,7 +38,6 @@ * instructions. * ****************************************************************************/ -/* $XFree86: xc/extras/x86emu/src/x86emu/ops2.c,v 1.7 2004/02/06 17:15:28 tsi Exp $ */ #include "x86emu/x86emui.h" @@ -66,6 +66,40 @@ /**************************************************************************** REMARKS: +Handles opcode 0x0f,0x31 +****************************************************************************/ +static void x86emuOp2_rdtsc(u8 X86EMU_UNUSED(op2)) +{ +#ifdef __HAS_LONG_LONG__ + static u64 counter = 0; +#else + static u32 counter = 0; +#endif + + counter += 0x10000; + + /* read timestamp counter */ + /* + * Note that instead of actually trying to accurately measure this, we just + * increase the counter by a fixed amount every time we hit one of these + * instructions. Feel free to come up with a better method. + */ + START_OF_INSTR(); + DECODE_PRINTF("RDTSC\n"); + TRACE_AND_STEP(); +#ifdef __HAS_LONG_LONG__ + M.x86.R_EAX = counter & 0xffffffff; + M.x86.R_EDX = counter >> 32; +#else + M.x86.R_EAX = counter; + M.x86.R_EDX = 0; +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: Handles opcode 0x0f,0x80-0x8F ****************************************************************************/ static void x86emuOp2_long_jump(u8 op2) @@ -131,7 +165,7 @@ break; case 0x8d: name = "JNL\t"; - cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF))); break; case 0x8e: name = "JLE\t"; @@ -295,6 +329,20 @@ } /**************************************************************************** +REMARKS: CPUID takes EAX/ECX as inputs, writes EAX/EBX/ECX/EDX as output +Handles opcode 0x0f,0xa2 +****************************************************************************/ +static void x86emuOp2_cpuid(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("CPUID\n"); + TRACE_AND_STEP(); + cpuid(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** REMARKS: Handles opcode 0x0f,0xa3 ****************************************************************************/ @@ -700,10 +748,9 @@ END_OF_INSTR(); } -#if 0 /**************************************************************************** REMARKS: -Handles opcode 0x0f,0xaa +Handles opcode 0x0f,0xab ****************************************************************************/ static void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) { @@ -839,7 +886,6 @@ DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } -#endif /**************************************************************************** REMARKS: @@ -2132,7 +2178,7 @@ uint srcoffset; START_OF_INSTR(); - DECODE_PRINTF("BSF\n"); + DECODE_PRINTF("BSF\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch(mod) { case 0: @@ -2212,25 +2258,25 @@ break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg, *dstreg; + u32 srcval, *dstreg; - srcreg = DECODE_RM_LONG_REGISTER(rl); + srcval = *DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 0; *dstreg < 32; (*dstreg)++) - if ((*srcreg >> *dstreg) & 1) break; + if ((srcval >> *dstreg) & 1) break; } else { - u16 *srcreg, *dstreg; + u16 srcval, *dstreg; - srcreg = DECODE_RM_WORD_REGISTER(rl); + srcval = *DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 0; *dstreg < 16; (*dstreg)++) - if ((*srcreg >> *dstreg) & 1) break; + if ((srcval >> *dstreg) & 1) break; } break; } @@ -2248,7 +2294,7 @@ uint srcoffset; START_OF_INSTR(); - DECODE_PRINTF("BSF\n"); + DECODE_PRINTF("BSR\t"); FETCH_DECODE_MODRM(mod, rh, rl); switch(mod) { case 0: @@ -2328,25 +2374,25 @@ break; case 3: /* register to register */ if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg, *dstreg; + u32 srcval, *dstreg; - srcreg = DECODE_RM_LONG_REGISTER(rl); + srcval = *DECODE_RM_LONG_REGISTER(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_LONG_REGISTER(rh); TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 31; *dstreg > 0; (*dstreg)--) - if ((*srcreg >> *dstreg) & 1) break; + if ((srcval >> *dstreg) & 1) break; } else { - u16 *srcreg, *dstreg; + u16 srcval, *dstreg; - srcreg = DECODE_RM_WORD_REGISTER(rl); + srcval = *DECODE_RM_WORD_REGISTER(rl); DECODE_PRINTF(","); dstreg = DECODE_RM_WORD_REGISTER(rh); TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); for(*dstreg = 15; *dstreg > 0; (*dstreg)--) - if ((*srcreg >> *dstreg) & 1) break; + if ((srcval >> *dstreg) & 1) break; } break; } @@ -2583,7 +2629,7 @@ /* 0x2f */ x86emuOp2_illegal_op, /* 0x30 */ x86emuOp2_illegal_op, -/* 0x31 */ x86emuOp2_illegal_op, +/* 0x31 */ x86emuOp2_rdtsc, /* 0x32 */ x86emuOp2_illegal_op, /* 0x33 */ x86emuOp2_illegal_op, /* 0x34 */ x86emuOp2_illegal_op, @@ -2703,7 +2749,7 @@ /* 0xa0 */ x86emuOp2_push_FS, /* 0xa1 */ x86emuOp2_pop_FS, -/* 0xa2 */ x86emuOp2_illegal_op, +/* 0xa2 */ x86emuOp2_cpuid, /* 0xa3 */ x86emuOp2_bt_R, /* 0xa4 */ x86emuOp2_shld_IMM, /* 0xa5 */ x86emuOp2_shld_CL, @@ -2712,7 +2758,7 @@ /* 0xa8 */ x86emuOp2_push_GS, /* 0xa9 */ x86emuOp2_pop_GS, /* 0xaa */ x86emuOp2_illegal_op, -/* 0xab */ x86emuOp2_bt_R, +/* 0xab */ x86emuOp2_bts_R, /* 0xac */ x86emuOp2_shrd_IMM, /* 0xad */ x86emuOp2_shrd_CL, /* 0xae */ x86emuOp2_illegal_op, Index: xc/extras/x86emu/src/x86emu/prim_ops.c diff -u xc/extras/x86emu/src/x86emu/prim_ops.c:1.3 xc/extras/x86emu/src/x86emu/prim_ops.c:1.4 --- xc/extras/x86emu/src/x86emu/prim_ops.c:1.3 Mon Mar 28 20:00:29 2005 +++ xc/extras/x86emu/src/x86emu/prim_ops.c Wed Oct 15 13:59:11 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/extras/x86emu/src/x86emu/prim_ops.c,v 1.3 2005/03/29 04:00:29 tsi Exp $ */ +/* $XFree86: xc/extras/x86emu/src/x86emu/prim_ops.c,v 1.4 2008/10/15 20:59:11 tsi Exp $ */ /**************************************************************************** * * Realmode X86 Emulator Library @@ -2104,7 +2104,7 @@ void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) { #ifdef __HAS_LONG_LONG__ - s64 res = (s32)d * (s32)s; + s64 res = (s64)(s32)d * (s32)s; *res_lo = (u32)res; *res_hi = (u32)(res >> 32); @@ -2196,7 +2196,7 @@ void mul_long(u32 s) { #ifdef __HAS_LONG_LONG__ - u64 res = (u32)M.x86.R_EAX * (u32)s; + u64 res = (u64)M.x86.R_EAX * s; M.x86.R_EAX = (u32)res; M.x86.R_EDX = (u32)(res >> 32); @@ -2930,3 +2930,161 @@ { div_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s); } #endif + +/* + * CPUID emulation. For now, only levels 0 and 1 are supported. If the host + * architecture supports CPUID, pass that implementation's results to the + * emulation. If running on a 386 or 486 that does not support CPUID, provide + * a reasonable simulation (instead of SIGILL'ing). On all other host + * architectures, the emulator will report itself as a 486DX4. + * + * Note that, in level 0's case, the "GenuineIntel" string is in EBX:EDX:ECX, + * not in EBX:ECX:EDX as one might have expected. + */ + +#if defined(__i386__) || defined(__amd64__) || defined(__x86_64__) +/* No need to worry about PIC on x86_64 */ +#if defined(__PIC__) && !defined(__amd64__) && !defined(__x86_64__) +#define CPUID() \ + __asm__ __volatile__ \ + ( \ + "pushl %%ebx\n\t" \ + "cpuid\n\t" \ + "movl %%ebx, %1\n\t" \ + "popl %%ebx" \ + : "=a" (M.x86.R_EAX), \ + "=r" (M.x86.R_EBX), \ + "=c" (M.x86.R_ECX), \ + "=d" (M.x86.R_EDX) \ + : "a" (M.x86.R_EAX), \ + "c" (M.x86.R_ECX) \ + : "cc" \ + ) +#else +#define CPUID() \ + __asm__ __volatile__ \ + ( \ + "cpuid" \ + : "=a" (M.x86.R_EAX), \ + "=b" (M.x86.R_EBX), \ + "=c" (M.x86.R_ECX), \ + "=d" (M.x86.R_EDX) \ + : "a" (M.x86.R_EAX), \ + "c" (M.x86.R_ECX) \ + : "cc" \ + ) +#endif +#endif + +void +cpuid(void) +{ + if (M.x86.R_EAX > 1) { + M.x86.R_EAX = M.x86.R_EBX = M.x86.R_ECX = M.x86.R_EDX = 0; + } else { + +#if defined(__amd64__) || defined(__x86_64__) + + u32 level = M.x86.R_EAX; + + CPUID(); + if (level == 0) { + /* Upto level one supported */ + if (M.x86.R_EAX > 1) + M.x86.R_EAX = 1; + } else { + /* Only TSC and VME */ + M.x86.R_EDX &= 0x00000012; + } + +#else /* !x86_64 */ + +#if defined(__i386__) + + u32 level = M.x86.R_EAX; + u32 ecx, eflags; + + /* + * Determine if the AC & ID bits in EFLAGS can be modified. Might as + * well use EBX as the needed work register and not care about PIC. + */ + __asm__ __volatile__ + ( + "pushl %%ebx\n\t" /* Save work register */ + "pushfl\n\t" /* Get EFLAGS */ + "popl %%eax\n\t" + "movl %%eax,%%ebx\n\t" /* Save original */ + "xorl $0x240000,%%eax\n\t" /* Toggle AC & ID bits */ + "pushl %%eax\n\t" /* Copy to EFLAGS */ + "popfl\n\t" + "pushfl\n\t" /* Get new EFLAGS */ + "popl %%eax\n\t" + "xorl %%ebx,%%eax\n\t" /* Logical difference */ + "pushl %%ebx\n\t" /* Restore original EFLAGS */ + "popfl\n\t" + "popl %%ebx" /* Restore work register */ + : "=a" (eflags) + ); + + if ((eflags & 0x240000) != 0x240000) { + /* 386 or pre-DX4 486; Simulate CPUID */ + if (level == 0) { + M.x86.R_EAX = 0; /* No level supported */ + /* "GenuineIntel" byte-swapped (but not really...) */ + M.x86.R_EBX = 0x756e6547; /* "uneG" */ + M.x86.R_EDX = 0x49656e69; /* "Ieni" */ + M.x86.R_ECX = 0x6c65746e; /* "letn" */ + } else { + if (!(eflags & 0x040000)) + M.x86.R_EAX = 0x00000300; + else + M.x86.R_EAX = 0x00000400; + M.x86.R_EBX = M.x86.R_ECX = M.x86.R_EDX = 0; + } + } else { + /* 486DX4 or later */ + ecx = M.x86.R_ECX; + M.x86.R_EAX = 0; + CPUID(); + if (level == 0) { + /* Upto level one supported */ + if (M.x86.R_EAX > 1) + M.x86.R_EAX = 1; + } else { + if (M.x86.R_EAX == 0) { + /* Level one not supported; Simulate it */ + M.x86.R_EAX = 0x00000400; + M.x86.R_EBX = M.x86.R_ECX = M.x86.R_EDX = 0; + } else { + M.x86.R_EAX = 1; + M.x86.R_ECX = ecx; + CPUID(); + /* Only TSC and VME */ + M.x86.R_EDX &= 0x00000012; + } + } + } + +#else /* !amd64 && !i386 */ + + /* Emulate a 486DX4 */ + if (M.x86.R_EAX == 0) { + M.x86.R_EAX = 1; /* Upto one level supported */ + /* "GenuineIntel" byte-swapped (but not really...) */ + M.x86.R_EBX = 0x756e6547; /* "uneG" */ + M.x86.R_EDX = 0x49656e69; /* "Ieni" */ + M.x86.R_ECX = 0x6c65746e; /* "letn" */ + } else { + M.x86.R_EAX = 0x00000480; + M.x86.R_EBX = 0x00000000; + M.x86.R_ECX = 0x00000000; + M.x86.R_EDX = 0x00000002; /* VME only */ + } + +#endif + +#endif + + } + +} Index: xc/extras/x86emu/src/x86emu/x86emu/prim_ops.h diff -u xc/extras/x86emu/src/x86emu/x86emu/prim_ops.h:1.1.1.1 xc/extras/x86emu/src/x86emu/x86emu/prim_ops.h:1.2 --- xc/extras/x86emu/src/x86emu/x86emu/prim_ops.h:1.1.1.1 Sat Jan 22 20:23:53 2000 +++ xc/extras/x86emu/src/x86emu/x86emu/prim_ops.h Wed Oct 15 13:59:11 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/extras/x86emu/src/x86emu/x86emu/prim_ops.h,v 1.2 2008/10/15 20:59:11 tsi Exp $ */ /**************************************************************************** * * Realmode X86 Emulator Library @@ -134,7 +135,8 @@ void push_word (u16 w); void push_long (u32 w); u16 pop_word (void); -u32 pop_long (void); +u32 pop_long (void); +void cpuid (void); #if defined(__HAVE_INLINE_ASSEMBLER__) && !defined(PRIM_OPS_NO_REDEFINE_ASM) Index: xc/include/Imakefile diff -u xc/include/Imakefile:3.31 xc/include/Imakefile:3.32 --- xc/include/Imakefile:3.31 Fri Oct 14 08:15:54 2005 +++ xc/include/Imakefile Sun Sep 23 13:46:16 2007 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/include/Imakefile,v 3.31 2005/10/14 15:15:54 tsi Exp $ +XCOMM $XFree86: xc/include/Imakefile,v 3.32 2007/09/23 20:46:16 tsi Exp $ #define IHaveSubdirs #define PassCDebugFlags /**/ @@ -48,17 +48,19 @@ MakeSubdirs($(SUBDIRS)) DependSubdirs($(SUBDIRS)) -InstallDriverSDKNonExecFile(X.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(Xalloca.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(Xarch.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(Xdefs.h,$(DRIVERSDKINCLUDEDIR)) +InstallDriverSDKNonExecFile(X.h,$(DRIVERSDKINCLUDEDIR)/X11) +InstallDriverSDKNonExecFile(XF86keysym.h,$(DRIVERSDKINCLUDEDIR)/X11) +InstallDriverSDKNonExecFile(Xalloca.h,$(DRIVERSDKINCLUDEDIR)/X11) +InstallDriverSDKNonExecFile(Xarch.h,$(DRIVERSDKINCLUDEDIR)/X11) InstallDriverSDKNonExecFile(Xdefs.h,$(DRIVERSDKINCLUDEDIR)/X11) -InstallDriverSDKNonExecFile(Xfuncproto.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(Xfuncs.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(Xmd.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(Xosdefs.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(Xproto.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(Xprotostr.h,$(DRIVERSDKINCLUDEDIR)) +InstallDriverSDKNonExecFile(Xfuncproto.h,$(DRIVERSDKINCLUDEDIR)/X11) +InstallDriverSDKNonExecFile(Xfuncs.h,$(DRIVERSDKINCLUDEDIR)/X11) +InstallDriverSDKNonExecFile(Xmd.h,$(DRIVERSDKINCLUDEDIR)/X11) +InstallDriverSDKNonExecFile(Xosdefs.h,$(DRIVERSDKINCLUDEDIR)/X11) +InstallDriverSDKNonExecFile(Xproto.h,$(DRIVERSDKINCLUDEDIR)/X11) +InstallDriverSDKNonExecFile(Xprotostr.h,$(DRIVERSDKINCLUDEDIR)/X11) +InstallDriverSDKNonExecFile(keysym.h,$(DRIVERSDKINCLUDEDIR)/X11) +InstallDriverSDKNonExecFile(keysymdef.h,$(DRIVERSDKINCLUDEDIR)/X11) #if BuildGlxExt || BuildGLXLibrary XCOMM For the Linux/OpenGL base standard Index: xc/include/GL/glu.h diff -u xc/include/GL/glu.h:1.3 xc/include/GL/glu.h:1.4 --- xc/include/GL/glu.h:1.3 Sat Jan 31 18:12:08 2004 +++ xc/include/GL/glu.h Sun Apr 6 12:17:40 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/include/GL/glu.h,v 1.3 2004/02/01 02:12:08 dawes Exp $ */ +/* $XFree86: xc/include/GL/glu.h,v 1.4 2008/04/06 19:17:40 tsi Exp $ */ /* ** License Applicability. Except to the extent portions of this file are @@ -259,7 +259,7 @@ #ifdef __cplusplus typedef GLvoid (*_GLUfuncptr)(); #else -typedef GLvoid (*_GLUfuncptr)(GLvoid); +typedef GLvoid (*_GLUfuncptr)(void); #endif extern void gluBeginCurve (GLUnurbs* nurb); Index: xc/include/extensions/Imakefile diff -u xc/include/extensions/Imakefile:3.61 xc/include/extensions/Imakefile:3.62 --- xc/include/extensions/Imakefile:3.61 Mon Jan 9 06:58:16 2006 +++ xc/include/extensions/Imakefile Sun Sep 23 13:46:17 2007 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/include/extensions/Imakefile,v 3.61 2006/01/09 14:58:16 dawes Exp $ +XCOMM $XFree86: xc/include/extensions/Imakefile,v 3.62 2007/09/23 20:46:17 tsi Exp $ #if BuildScreenSaverExt || BuildScreenSaverLibrary SCREENSAVERHEADERS = saver.h saverproto.h scrnsaver.h @@ -88,19 +88,24 @@ InstallMultipleFlags($(HEADERS),$(INCDIR)/X11/extensions,$(INSTINCFLAGS)) #endif -InstallDriverSDKNonExecFile(XI.h,$(DRIVERSDKINCLUDEDIR)/extensions) -InstallDriverSDKNonExecFile(XIproto.h,$(DRIVERSDKINCLUDEDIR)/extensions) -InstallDriverSDKNonExecFile(Xv.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(Xvproto.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(dpms.h,$(DRIVERSDKINCLUDEDIR)/extensions) -InstallDriverSDKNonExecFile(xf86dga1str.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(xf86dgastr.h,$(DRIVERSDKINCLUDEDIR)/extensions) -InstallDriverSDKNonExecFile(xf86rush.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(xf86rushstr.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(renderproto.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(Xv.h,$(DRIVERSDKINCLUDEDIR)/extensions) -InstallDriverSDKNonExecFile(XvMC.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(Xvlib.h,$(DRIVERSDKINCLUDEDIR)/extensions) +InstallDriverSDKNonExecFile(XI.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(XIproto.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(XKB.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(XKBproto.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(XKBsrv.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(XKBstr.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) InstallDriverSDKNonExecFile(Xv.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) -InstallDriverSDKNonExecFile(Xvlib.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) - +InstallDriverSDKNonExecFile(XvMC.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(Xvproto.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(dpms.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(panoramiXproto.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(randr.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(render.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(renderproto.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(xf86dga.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(xf86dga1.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(xf86dga1str.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(xf86dgastr.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(xf86misc.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(xf86rush.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) +InstallDriverSDKNonExecFile(xf86rushstr.h,$(DRIVERSDKINCLUDEDIR)/X11/extensions) Index: xc/include/extensions/shape.h diff -u xc/include/extensions/shape.h:1.5 xc/include/extensions/shape.h:1.6 --- xc/include/extensions/shape.h:1.5 Mon Jan 9 06:58:19 2006 +++ xc/include/extensions/shape.h Fri Jan 4 09:50:10 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/include/extensions/shape.h,v 1.5 2006/01/09 14:58:19 dawes Exp $ */ +/* $XFree86: xc/include/extensions/shape.h,v 1.6 2008/01/04 17:50:10 tsi Exp $ */ /************************************************************ Copyright 1989, 1998 The Open Group @@ -48,6 +48,7 @@ #define ShapeBounding 0 #define ShapeClip 1 +#define ShapeInput 2 #define ShapeNotifyMask (1L << 0) #define ShapeNotify 0 Index: xc/include/extensions/shapestr.h diff -u xc/include/extensions/shapestr.h:1.3 xc/include/extensions/shapestr.h:1.4 --- xc/include/extensions/shapestr.h:1.3 Fri Oct 14 08:15:54 2005 +++ xc/include/extensions/shapestr.h Fri Jan 4 09:50:10 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/include/extensions/shapestr.h,v 1.4 2008/01/04 17:50:10 tsi Exp $ */ /************************************************************ Copyright 1989, 1998 The Open Group @@ -24,8 +25,6 @@ ********************************************************/ -/* $XFree86: xc/include/extensions/shapestr.h,v 1.3 2005/10/14 15:15:54 tsi Exp $ */ - #ifndef _SHAPESTR_H_ #define _SHAPESTR_H_ @@ -42,7 +41,7 @@ #define SHAPENAME "SHAPE" #define SHAPE_MAJOR_VERSION 1 /* current version numbers */ -#define SHAPE_MINOR_VERSION 0 +#define SHAPE_MINOR_VERSION 1 typedef struct _ShapeQueryVersion { CARD8 reqType; /* always ShapeReqCode */ Index: xc/include/extensions/xtrapbits.h diff -u xc/include/extensions/xtrapbits.h:1.1 xc/include/extensions/xtrapbits.h:1.2 --- xc/include/extensions/xtrapbits.h:1.1 Fri Nov 2 15:29:26 2001 +++ xc/include/extensions/xtrapbits.h Sat Sep 15 20:44:17 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/include/extensions/xtrapbits.h,v 1.1 2001/11/02 23:29:26 dawes Exp $ */ +/* $XFree86: xc/include/extensions/xtrapbits.h,v 1.2 2007/09/16 03:44:17 tsi Exp $ */ /* * This include file is designed to be a portable way for systems to define * bit field manipulation of arrays of bits. @@ -78,6 +78,11 @@ (BitIsTrue((array),(bit)) ? True : False) #define BitSet(array,bit,value) /* Set bit to given value in array */ \ - (value) ? BitTrue((array),(bit)) : BitFalse((array),(bit)) + do { \ + if (value) \ + BitTrue((array),(bit)); \ + else \ + BitFalse((array),(bit)); \ + } while (0) #endif /* __XTRAPBITS__ */ Index: xc/include/fonts/Imakefile diff -u xc/include/fonts/Imakefile:3.9 xc/include/fonts/Imakefile:3.10 --- xc/include/fonts/Imakefile:3.9 Fri Oct 14 08:15:54 2005 +++ xc/include/fonts/Imakefile Sun Sep 23 13:46:17 2007 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/include/fonts/Imakefile,v 3.9 2005/10/14 15:15:54 tsi Exp $ +XCOMM $XFree86: xc/include/fonts/Imakefile,v 3.10 2007/09/23 20:46:17 tsi Exp $ HEADERS = FS.h FSproto.h fsmasks.h \ font.h fontproto.h fontstruct.h @@ -12,7 +12,7 @@ #endif -InstallDriverSDKNonExecFile(font.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(fontproto.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(fontstruct.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(fsmasks.h,$(DRIVERSDKINCLUDEDIR)) +InstallDriverSDKNonExecFile(font.h,$(DRIVERSDKINCLUDEDIR)/X11/fonts) +InstallDriverSDKNonExecFile(fontproto.h,$(DRIVERSDKINCLUDEDIR)/X11/fonts) +InstallDriverSDKNonExecFile(fontstruct.h,$(DRIVERSDKINCLUDEDIR)/X11/fonts) +InstallDriverSDKNonExecFile(fsmasks.h,$(DRIVERSDKINCLUDEDIR)/X11/fonts) Index: xc/lib/GL/GL/Imakefile diff -u xc/lib/GL/GL/Imakefile:1.31 xc/lib/GL/GL/Imakefile:1.32 --- xc/lib/GL/GL/Imakefile:1.31 Fri Dec 10 08:06:56 2004 +++ xc/lib/GL/GL/Imakefile Sat Sep 15 17:14:40 2007 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/lib/GL/GL/Imakefile,v 1.31 2004/12/10 16:06:56 alanh Exp $ +XCOMM $XFree86: xc/lib/GL/GL/Imakefile,v 1.32 2007/09/16 00:14:40 tsi Exp $ /* * Copyright (c) 1994-2004 by The XFree86 Project, Inc. * All rights reserved. @@ -145,7 +145,7 @@ DRVDOBJS = $(TDFXDOBJS) $(MESADOBJS) $(DRMDOBJS) DRVPOBJS = $(TDFXPOBJS) $(MESAPOBJS) $(DRMPOBJS) -OTHERREQUIREDLIBS = -lglide3 -ldl +OTHERREQUIREDLIBS = DlLibrary #elif GlxBuiltInI810 Index: xc/lib/GL/glx/glxcmds.c diff -u xc/lib/GL/glx/glxcmds.c:1.39 xc/lib/GL/glx/glxcmds.c:1.40 --- xc/lib/GL/glx/glxcmds.c:1.39 Mon Apr 9 08:37:11 2007 +++ xc/lib/GL/glx/glxcmds.c Sat Sep 15 18:49:13 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/lib/GL/glx/glxcmds.c,v 1.39 2007/04/09 15:37:11 tsi Exp $ */ +/* $XFree86: xc/lib/GL/glx/glxcmds.c,v 1.40 2007/09/16 01:49:13 tsi Exp $ */ /* ** License Applicability. Except to the extent portions of this file are ** made subject to an alternative license as permitted in the SGI Free @@ -47,8 +47,10 @@ #include "glapi.h" #ifdef GLX_DIRECT_RENDERING #include "indirect_init.h" +#ifdef XF86VIDMODE #include #endif +#endif #include "glxextensions.h" #include "glcontextmodes.h" #include Index: xc/lib/X11/ConnDis.c diff -u xc/lib/X11/ConnDis.c:3.34 xc/lib/X11/ConnDis.c:3.35 --- xc/lib/X11/ConnDis.c:3.34 Sun Feb 19 16:14:35 2006 +++ xc/lib/X11/ConnDis.c Wed Oct 15 13:59:11 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/lib/X11/ConnDis.c,v 3.35 2008/10/15 20:59:11 tsi Exp $ */ /* Copyright 1989, 1998 The Open Group @@ -23,7 +24,6 @@ in this Software without prior written authorization from The Open Group. */ -/* $XFree86: xc/lib/X11/ConnDis.c,v 3.34 2006/02/20 00:14:35 dawes Exp $ */ /* * This file contains operating system dependencies. @@ -56,7 +56,7 @@ #include "Xintconn.h" -/* prototyes */ +/* prototypes */ static void GetAuthorization( XtransConnInfo trans_conn, int family, @@ -143,12 +143,18 @@ char* address = addrbuf; XtransConnInfo trans_conn = NULL; /* transport connection object */ int connect_stat; +#if defined(LOCALCONN) || defined(TCPCONN) + Bool reset_hostname = False; /* Reset hostname? */ +#endif #ifdef LOCALCONN struct utsname sys; +# ifdef UNIXCONN + Bool try_unix_socket = False; /* Try unix if local fails */ +# endif +#endif #ifdef TCPCONN char *tcphostname = NULL; /* A place to save hostname pointer */ #endif -#endif p = display_name; @@ -215,19 +221,28 @@ #ifdef LOCALCONN /* check if phostname == localnodename AND protocol not specified */ - if (!pprotocol && phostname && uname(&sys) >= 0 && + if (!pprotocol && (!phostname || (phostname && uname(&sys) >= 0 && !strncmp(phostname, sys.nodename, (strlen(sys.nodename) < strlen(phostname) ? - strlen(phostname) : strlen(sys.nodename)))) + strlen(phostname) : strlen(sys.nodename)))))) { -#ifdef TCPCONN /* * We'll first attempt to connect using the local transport. If + * that fails, we'll try again using the Unix socket transport. If * this fails (which is the case if sshd X protocol forwarding is * being used), retry using tcp and this hostname. */ - tcphostname = copystring(phostname, strlen(phostname)); +#ifdef UNIXCONN + try_unix_socket = True; +#endif +#ifdef TCPCONN + if (phostname) + tcphostname = copystring(phostname, strlen(phostname)); + else + tcphostname = copystring("localhost", 9); #endif + if (!phostname) + reset_hostname = True; Xfree (phostname); phostname = copystring ("unix", 4); } @@ -281,12 +296,18 @@ #if defined(TCPCONN) || defined(UNIXCONN) || defined(LOCALCONN) || defined(MNX_TCPCONN) || defined(OS2PIPECONN) if (!pprotocol) { - if (!phostname) + if (!phostname) { #if defined(UNIXCONN) || defined(LOCALCONN) || defined(OS2PIPECONN) pprotocol = copystring ("local", 5); +#if defined(TCPCONN) + tcphostname = copystring("localhost", 9); +#endif + } else + { #endif pprotocol = copystring ("tcp", 3); + } } #endif @@ -317,7 +338,7 @@ } #endif -#if defined(LOCALCONN) && defined(TCPCONN) +#if defined(TCPCONN) connect: #endif /* @@ -331,6 +352,7 @@ (pdpynum ? strlen(pdpynum) : 0); if (olen > sizeof addrbuf) address = Xmalloc (olen); } + if (!address) goto bad; sprintf(address,"%s/%s:%d", pprotocol ? pprotocol : "", @@ -389,6 +411,7 @@ } if (address != addrbuf) Xfree (address); + address = addrbuf; if( trans_conn == NULL ) goto bad; @@ -404,6 +427,16 @@ * * [host] : [:] dpy . scr \0 */ +#if defined(LOCALCONN) || defined(TCPCONN) + /* + * If we computed the host name, get rid of it so that + * XDisplayString() and XDisplayName() agree. + */ + if (reset_hostname) { + Xfree (phostname); + phostname = NULL; + } +#endif len = ((phostname ? strlen(phostname) : 0) + 1 + (dnet ? 1 : 0) + strlen(pdpynum) + 1 + (pscrnum ? strlen(pscrnum) : 1) + 1); *fullnamep = (char *) Xmalloc (len); @@ -420,6 +453,9 @@ if (phostname) Xfree (phostname); if (pdpynum) Xfree (pdpynum); if (pscrnum) Xfree (pscrnum); +#ifdef TCPCONN + if (tcphostname) Xfree (tcphostname); +#endif GetAuthorization(trans_conn, family, (char *) saddr, saddrlen, idisplay, auth_namep, auth_namelenp, auth_datap, auth_datalenp); @@ -434,12 +470,23 @@ if (saddr) free ((char *) saddr); if (pprotocol) Xfree (pprotocol); if (phostname) Xfree (phostname); + if (address && address != addrbuf) { Xfree(address); address = addrbuf; } -#if defined(LOCALCONN) && defined(TCPCONN) +#if defined(LOCALCONN) && defined(UNIXCONN) + if (try_unix_socket) { + pprotocol = copystring ("unix", 4); + phostname = NULL; + try_unix_socket = False; /* Do this only once */ + goto connect; + } +#endif + +#if defined(TCPCONN) if (tcphostname) { pprotocol = copystring("tcp", 3); phostname = tcphostname; tcphostname = NULL; + reset_hostname = True; goto connect; } #endif @@ -1110,15 +1157,20 @@ static unsigned long unix_addr = 0xFFFFFFFF; unsigned long the_addr; unsigned short the_port; + unsigned long the_utime; + struct timeval tp; + X_GETTIMEOFDAY(&tp); _XLockMutex(_Xglobal_lock); the_addr = unix_addr--; _XUnlockMutex(_Xglobal_lock); + the_utime = (unsigned long) tp.tv_usec; the_port = getpid (); - - xdmcp_data[j++] = (the_addr >> 24) & 0xFF; - xdmcp_data[j++] = (the_addr >> 16) & 0xFF; - xdmcp_data[j++] = (the_addr >> 8) & 0xFF; + + xdmcp_data[j++] = (the_utime >> 24) & 0xFF; + xdmcp_data[j++] = (the_utime >> 16) & 0xFF; + xdmcp_data[j++] = ((the_utime >> 8) & 0xF0) + | ((the_addr >> 8) & 0x0F); xdmcp_data[j++] = (the_addr >> 0) & 0xFF; xdmcp_data[j++] = (the_port >> 8) & 0xFF; xdmcp_data[j++] = (the_port >> 0) & 0xFF; Index: xc/lib/X11/XKBMisc.c diff -u xc/lib/X11/XKBMisc.c:3.8 xc/lib/X11/XKBMisc.c:3.9 --- xc/lib/X11/XKBMisc.c:3.8 Mon Apr 9 08:37:11 2007 +++ xc/lib/X11/XKBMisc.c Sat Sep 15 20:44:17 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/lib/X11/XKBMisc.c,v 3.8 2007/04/09 15:37:11 tsi Exp $ */ +/* $XFree86: xc/lib/X11/XKBMisc.c,v 3.9 2007/09/16 03:44:17 tsi Exp $ */ /************************************************************ Copyright (c) 1993 by Silicon Graphics Computer Systems, Inc. @@ -659,7 +659,7 @@ int width,nOldGroups,oldWidth,newTypes[XkbNumKbdGroups]; if ((!xkb) || (!XkbKeycodeInRange(xkb,key)) || (!xkb->map) || - (!xkb->map->types)||(!newTypes)||((groups&XkbAllGroupsMask)==0)|| + (!xkb->map->types)||((groups&XkbAllGroupsMask)==0)|| (nGroups>XkbNumKbdGroups)) { return BadMatch; } Index: xc/lib/X11/imRm.c diff -u xc/lib/X11/imRm.c:3.14 xc/lib/X11/imRm.c:3.15 --- xc/lib/X11/imRm.c:3.14 Mon Jan 9 06:58:42 2006 +++ xc/lib/X11/imRm.c Sat Sep 15 20:44:17 2007 @@ -29,7 +29,7 @@ makoto@sm.sony.co.jp ******************************************************************/ -/* $XFree86: xc/lib/X11/imRm.c,v 3.14 2006/01/09 14:58:42 dawes Exp $ */ +/* $XFree86: xc/lib/X11/imRm.c,v 3.15 2007/09/16 03:44:17 tsi Exp $ */ #include #include @@ -508,7 +508,7 @@ if(XGetGeometry(im->core.display, (Drawable)ic->core.focus_window, &root_return, &x_return, &y_return, &width_return, &height_return, &border_width_return, &depth_return) - == (Status)NULL) { + == Success) { return True; } area.x = 0; @@ -537,7 +537,7 @@ return True; } if(XGetWindowAttributes(im->core.display, ic->core.client_window, - &win_attr) == (Status)NULL) { + &win_attr) == Success) { return True; } Index: xc/lib/X11/lcFile.c diff -u xc/lib/X11/lcFile.c:3.34 xc/lib/X11/lcFile.c:3.35 --- xc/lib/X11/lcFile.c:3.34 Sun Mar 27 18:50:59 2005 +++ xc/lib/X11/lcFile.c Sat Sep 15 20:44:17 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/lib/X11/lcFile.c,v 3.35 2007/09/16 03:44:17 tsi Exp $ */ /* * * Copyright IBM Corporation 1993 @@ -22,7 +23,6 @@ * SOFTWARE. * */ -/* $XFree86: xc/lib/X11/lcFile.c,v 3.34 2005/03/28 02:50:59 dawes Exp $ */ #include #include @@ -366,8 +366,7 @@ char buf[PATH_MAX], *name; name = NULL; - if ((5 + (args[i] ? strlen (args[i]) : 0) + - (cat ? strlen (cat) : 0)) < PATH_MAX) { + if ((5 + (args[i] ? strlen (args[i]) : 0) + strlen (cat)) < PATH_MAX) { sprintf(buf, "%s/%s.dir", args[i], cat); name = resolve_name(siname, buf, RtoL); } Index: xc/lib/X11/lcGenConv.c diff -u xc/lib/X11/lcGenConv.c:3.29 xc/lib/X11/lcGenConv.c:3.30 --- xc/lib/X11/lcGenConv.c:3.29 Mon Jan 9 06:58:43 2006 +++ xc/lib/X11/lcGenConv.c Sat Sep 15 20:44:17 2007 @@ -34,7 +34,7 @@ * 2000 * Modifier: Ivan Pascal The XFree86 Project */ -/* $XFree86: xc/lib/X11/lcGenConv.c,v 3.29 2006/01/09 14:58:43 dawes Exp $ */ +/* $XFree86: xc/lib/X11/lcGenConv.c,v 3.30 2007/09/16 03:44:17 tsi Exp $ */ /* * A generic locale loader for all kinds of ISO-2022 based codesets. @@ -841,6 +841,8 @@ return unconv_num; } +#ifdef STDCVT + static int stdc_mbstowcs( XlcConv conv, @@ -889,6 +891,8 @@ return unconv_num; } +#endif /* STDCVT */ + static int wcstombs_org( XlcConv conv, @@ -1007,6 +1011,8 @@ return unconv_num; } +#ifdef STDCVT + static int stdc_wcstombs( XlcConv conv, @@ -1048,6 +1054,8 @@ return unconv_num; } +#endif /* STDCVT */ + static int wcstocts( XlcConv conv, @@ -1200,6 +1208,8 @@ return unconv_num; } +#ifdef STDCVT + static int stdc_wcstocts( XlcConv conv, @@ -1236,6 +1246,8 @@ return (unconv_num1 + unconv_num2); } +#endif /* STDCVT */ + static int ctstowcs( XlcConv conv, @@ -1523,6 +1535,8 @@ return unconv_num; } +#ifdef STDCVT + static int stdc_ctstowcs( XlcConv conv, @@ -1595,6 +1609,8 @@ return (unconv_num1 + unconv_num2); } +#endif /* STDCVT */ + static int mbstocts( XlcConv conv, @@ -2052,6 +2068,8 @@ return unconv_num; } +#ifdef STDCVT + static int stdc_wcstostr( XlcConv conv, @@ -2088,6 +2106,8 @@ return (unconv_num1 + unconv_num2); } +#endif /* STDCVT */ + static int wctocs( XlcConv conv, @@ -2179,6 +2199,8 @@ return 0; } +#ifdef STDCVT + static int stdc_wctocs( XlcConv conv, @@ -2230,6 +2252,8 @@ return 0; } +#endif /* STDCVT */ + static int wcstocs( XlcConv conv, @@ -2328,7 +2352,7 @@ return(0); } -#endif +#endif /* STDCVT */ static int ctstombs( @@ -2581,6 +2605,8 @@ return unconv_num; } +#ifdef STDCVT + static int stdc_strtowcs( XlcConv conv, @@ -2617,6 +2643,8 @@ return (unconv_num1 + unconv_num2); } +#endif /* STDCVT */ + /* -------------------------------------------------------------------------- */ /* Close */ /* -------------------------------------------------------------------------- */ Index: xc/lib/XThrStub/UIThrStubs.c diff -u xc/lib/XThrStub/UIThrStubs.c:3.8 xc/lib/XThrStub/UIThrStubs.c:3.9 --- xc/lib/XThrStub/UIThrStubs.c:3.8 Tue Mar 29 10:17:00 2005 +++ xc/lib/XThrStub/UIThrStubs.c Wed Oct 15 13:59:11 2008 @@ -1,5 +1,5 @@ /* - * $XFree86: xc/lib/XThrStub/UIThrStubs.c,v 3.8 2005/03/29 18:17:00 tsi Exp $ + * $XFree86: xc/lib/XThrStub/UIThrStubs.c,v 3.9 2008/10/15 20:59:11 tsi Exp $ * * Copyright (c) 1995 David E. Wexelblat. All rights reserved * @@ -94,6 +94,9 @@ * distinguishing each of the drafts. */ +#include +#include + #ifdef CTHREADS #include typedef cthread_t xthread_t; @@ -149,43 +152,77 @@ #include #endif typedef pthread_t xthread_t; -#if defined(__GNUC__) && (__GNUC__ >= 3) -xthread_t pthread_self() __attribute__ ((weak, alias ("_Xthr_self_stub_"))); -int pthread_mutex_init() __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); -int pthread_mutex_destroy() __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); -int pthread_mutex_lock() __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); -int pthread_mutex_unlock() __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); -int pthread_cond_init() __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); -int pthread_cond_destroy() __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); -int pthread_cond_wait() __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); -int pthread_cond_signal() __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); -int pthread_cond_broadcast() __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); -int pthread_key_create() __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); -void *pthread_getspecific() __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); -int pthread_setspecific() __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); +#if defined(__GNUC__) && (__GNUC__ >= 2) && \ + ((__GNUC__ > 2) || (__GNUC_MINOR__ >= 95)) +xthread_t pthread_self() + __attribute__ ((weak, alias ("_Xthr_self_stub_"))); + +int pthread_mutex_init() + __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); +int pthread_mutex_destroy() + __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); +int pthread_mutex_lock() + __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); +int pthread_mutex_unlock() + __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); + +int pthread_cond_init() + __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); +int pthread_cond_destroy() + __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); +int pthread_cond_wait() + __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); +int pthread_cond_signal() + __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); +int pthread_cond_broadcast() + __attribute__ ((weak, alias ("_Xthr_zero_stub_"))); + +/* These are added for libGL */ +int pthread_key_create() + __attribute__ ((weak, alias ("_Xthr_key_create_stub_"))); +int pthread_key_delete() + __attribute__ ((weak, alias ("_Xthr_key_delete_stub_"))); +void *pthread_getspecific() + __attribute__ ((weak, alias ("_Xthr_getspecific_stub_"))); +int pthread_setspecific() + __attribute__ ((weak, alias ("_Xthr_setspecific_stub_"))); + +int pthread_once() + __attribute__ ((weak, alias ("_Xthr_once_stub_"))); + #if defined(_DECTHREADS_) || defined(linux) /* See Xthreads.h! */ -int pthread_equal() __attribute__ ((weak, alias ("_Xthr_equal_stub_"))); +int pthread_equal() + __attribute__ ((weak, alias ("_Xthr_equal_stub_"))); #endif /* _DECTHREADS_ || linux */ #else /* __GNUC__ */ -#pragma weak pthread_self = _Xthr_self_stub_ -#pragma weak pthread_mutex_init = _Xthr_zero_stub_ -#pragma weak pthread_mutex_destroy = _Xthr_zero_stub_ -#pragma weak pthread_mutex_lock = _Xthr_zero_stub_ -#pragma weak pthread_mutex_unlock = _Xthr_zero_stub_ -#pragma weak pthread_cond_init = _Xthr_zero_stub_ -#pragma weak pthread_cond_destroy = _Xthr_zero_stub_ -#pragma weak pthread_cond_wait = _Xthr_zero_stub_ -#pragma weak pthread_cond_signal = _Xthr_zero_stub_ +#pragma weak pthread_self = _Xthr_self_stub_ + +#pragma weak pthread_mutex_init = _Xthr_zero_stub_ +#pragma weak pthread_mutex_destroy = _Xthr_zero_stub_ +#pragma weak pthread_mutex_lock = _Xthr_zero_stub_ +#pragma weak pthread_mutex_unlock = _Xthr_zero_stub_ + +#pragma weak pthread_cond_init = _Xthr_zero_stub_ +#pragma weak pthread_cond_destroy = _Xthr_zero_stub_ +#pragma weak pthread_cond_wait = _Xthr_zero_stub_ +#pragma weak pthread_cond_signal = _Xthr_zero_stub_ #pragma weak pthread_cond_broadcast = _Xthr_zero_stub_ + /* These are added for libGL */ -#pragma weak pthread_key_create = _Xthr_zero_stub_ -#pragma weak pthread_getspecific = _Xthr_zero_stub_ -#pragma weak pthread_setspecific = _Xthr_zero_stub_ +#pragma weak pthread_key_create = _Xthr_key_create_stub_ +#pragma weak pthread_key_delete = _Xthr_key_delete_stub_ +#pragma weak pthread_getspecific = _Xthr_getspecific_stub_ +#pragma weak pthread_setspecific = _Xthr_setspecific_stub_ + +#pragma weak pthread_once = _Xthr_once_stub_ + #if defined(_DECTHREADS_) || defined(linux) -#pragma weak pthread_equal = _Xthr_equal_stub_ /* See Xthreads.h! */ +/* See Xthreads.h! */ +#pragma weak pthread_equal = _Xthr_equal_stub_ #endif /* _DECTHREADS_ || linux */ #endif /* __GNUC__ */ + #if defined(_DECTHREADS_) || defined(linux) int _Xthr_equal_stub_(xthread_t a, xthread_t b) @@ -198,6 +235,10 @@ #endif /* SVR4 */ #endif /* CTHREADS */ +#ifndef NULL +#define NULL ((void *)0) +#endif + xthread_t _Xthr_self_stub_(void); xthread_t @@ -215,3 +256,67 @@ return(0); } +int _Xthr_once_stub_(void *, void (*)(void)); +int +_Xthr_once_stub_(void *id, void (*routine)(void)) +{ + static char done = 0; + + if (done) + return 0; + + (*routine)(); + done = 1; + + return 0; +} + +static void **keys = NULL; +static unsigned int last_key = 0; + +int _Xthr_key_create_stub_(unsigned int *, void (*)(void *)); +int +_Xthr_key_create_stub_(unsigned int *key, void (*destructor)(void *)) +{ + void **newkeys = realloc(keys, (last_key + 1) * sizeof(*keys)); + + if (!newkeys) + return ENOMEM; + + keys = newkeys; + keys[last_key] = NULL; + *key = last_key++; + return 0; +} + +int _Xthr_key_delete_stub_(unsigned int); +int +_Xthr_key_delete_stub_(unsigned int key) +{ + if (key >= last_key) + return EINVAL; + + keys[key] = NULL; + return 0; +} + +void * _Xthr_getspecific_stub_(unsigned int); +void * +_Xthr_getspecific_stub_(unsigned int key) +{ + if (key >= last_key) + return NULL; + + return keys[key]; +} + +int _Xthr_setspecific_stub_(unsigned int, void *); +int +_Xthr_setspecific_stub_(unsigned int key, void *value) +{ + if (key >= last_key) + return EINVAL; + + keys[key] = value; + return 0; +} Index: xc/lib/Xaw/XawIm.c diff -u xc/lib/Xaw/XawIm.c:1.16 xc/lib/Xaw/XawIm.c:1.17 --- xc/lib/Xaw/XawIm.c:1.16 Mon Jan 9 06:59:05 2006 +++ xc/lib/Xaw/XawIm.c Sat Sep 15 20:44:17 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/lib/Xaw/XawIm.c,v 1.17 2007/09/16 03:44:17 tsi Exp $ */ /* * Copyright 1991 by OMRON Corporation * @@ -50,7 +51,6 @@ in this Software without prior written authorization from The Open Group. */ -/* $XFree86: xc/lib/Xaw/XawIm.c,v 1.16 2006/01/09 14:59:05 dawes Exp $ */ #include #include @@ -183,14 +183,14 @@ return(NULL); } -static XContext extContext = (XContext)NULL; +static XContext extContext = (XContext)0; static XawVendorShellExtPart * SetExtPart(VendorShellWidget w, XawVendorShellExtWidget vew) { contextDataRec *contextData; - if (extContext == (XContext)NULL) extContext = XUniqueContext(); + if (extContext == (XContext)0) extContext = XUniqueContext(); contextData = XtNew(contextDataRec); contextData->parent = (Widget)w; @@ -295,13 +295,13 @@ } } -static XContext errContext = (XContext)NULL; +static XContext errContext = (XContext)0; static Widget SetErrCnxt(Widget w, XIM xim) { contextErrDataRec *contextErrData; - if (errContext == (XContext)NULL) errContext = XUniqueContext(); + if (errContext == (XContext)0) errContext = XUniqueContext(); contextErrData = XtNew(contextErrDataRec); contextErrData->widget = w; @@ -1402,12 +1402,12 @@ return; XtFree( (char*) ve->im.resources ); - if (extContext != (XContext)NULL && + if (extContext != (XContext)0 && !XFindContext (XtDisplay (w), (Window)w, extContext, (XPointer*)&contextData)) XtFree( (char*) contextData ); - if (errContext != (XContext)NULL && + if (errContext != (XContext)0 && !XFindContext (XDisplayOfIM( ve->im.xim ), (Window) ve->im.xim, errContext, (XPointer*) &contextErrData)) XtFree( (char*) contextErrData ); Index: xc/lib/Xft/Xft.man diff -u xc/lib/Xft/Xft.man:1.7 xc/lib/Xft/Xft.man:1.8 --- xc/lib/Xft/Xft.man:1.7 Wed Sep 15 10:38:21 2004 +++ xc/lib/Xft/Xft.man Thu Jan 3 08:17:47 2008 @@ -1,7 +1,8 @@ .\" -.\" $XFree86: xc/lib/Xft/Xft.man,v 1.7 2004/09/15 17:38:21 herrb Exp $ +.\" $XFree86: xc/lib/Xft/Xft.man,v 1.8 2008/01/03 16:17:47 tsi Exp $ +.\" +.\" Copyright 2000 Keith Packard, member of The XFree86 Project, Inc. .\" -.\" Copyright 2000 Keith Packard, member of The XFree86 Project, Inc..\" .\" Permission to use, copy, modify, distribute, and sell this software and its .\" documentation for any purpose is hereby granted without fee, provided that .\" the above copyright notice appear in all copies and that both that Index: xc/lib/Xft/xftswap.c diff -u xc/lib/Xft/xftswap.c:1.1 xc/lib/Xft/xftswap.c:1.2 --- xc/lib/Xft/xftswap.c:1.1 Thu Feb 14 23:37:35 2002 +++ xc/lib/Xft/xftswap.c Fri Sep 28 08:53:26 2007 @@ -1,5 +1,5 @@ /* - * $XFree86: xc/lib/Xft/xftswap.c,v 1.1 2002/02/15 07:37:35 keithp Exp $ + * $XFree86: xc/lib/Xft/xftswap.c,v 1.2 2007/09/28 15:53:26 tsi Exp $ * * Copyright © 2002 Keith Packard, member of The XFree86 Project, Inc. * @@ -28,7 +28,7 @@ int XftNativeByteOrder (void) { - int whichbyte = 1; + static const int whichbyte = 1; if (*((char *) &whichbyte)) return LSBFirst; @@ -117,6 +117,11 @@ image->height * image->bytes_per_line >> 1); break; default: - break; + return; } + + if (MSBFirst == image->byte_order) + image->byte_order = LSBFirst; + else + image->byte_order = MSBFirst; } Index: xc/lib/Xp/XpContext.c diff -u xc/lib/Xp/XpContext.c:1.8 xc/lib/Xp/XpContext.c:1.9 --- xc/lib/Xp/XpContext.c:1.8 Mon Jan 9 06:59:19 2006 +++ xc/lib/Xp/XpContext.c Sat Sep 15 20:44:17 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/lib/Xp/XpContext.c,v 1.9 2007/09/16 03:44:17 tsi Exp $ */ /****************************************************************************** ****************************************************************************** ** @@ -33,7 +34,6 @@ ** ****************************************************************************** *****************************************************************************/ -/* $XFree86: xc/lib/Xp/XpContext.c,v 1.8 2006/01/09 14:59:19 dawes Exp $ */ #define NEED_REPLIES @@ -75,7 +75,7 @@ if ( locale == (char *) NULL ) req->localeLen = 0; - else if ( *locale == (char) NULL ) + else if ( *locale == (char) 0 ) req->localeLen = 0; else { locale_len = strlen( locale ); Index: xc/lib/Xp/XpJob.c diff -u xc/lib/Xp/XpJob.c:1.7 xc/lib/Xp/XpJob.c:1.8 --- xc/lib/Xp/XpJob.c:1.7 Tue Mar 22 19:11:25 2005 +++ xc/lib/Xp/XpJob.c Wed Oct 15 13:59:11 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/lib/Xp/XpJob.c,v 1.8 2008/10/15 20:59:11 tsi Exp $ */ /****************************************************************************** ****************************************************************************** ** @@ -33,7 +34,6 @@ ** ****************************************************************************** *****************************************************************************/ -/* $XFree86: xc/lib/Xp/XpJob.c,v 1.7 2005/03/23 03:11:25 dawes Exp $ */ #if defined(sun) && defined(i386) && defined(SVR4) && !defined(__EXTENSIONS__) #define __EXTENSIONS__ @@ -44,6 +44,9 @@ #include #include "XpExtUtil.h" #include +#ifdef XTHREADS +#include +#endif #ifndef WIN32 #define X_INCLUDE_PWD_H #define XOS_USE_XLIB_LOCKING Index: xc/lib/Xp/XpNotifyPdm.c diff -u xc/lib/Xp/XpNotifyPdm.c:1.9 xc/lib/Xp/XpNotifyPdm.c:1.10 --- xc/lib/Xp/XpNotifyPdm.c:1.9 Tue Mar 22 19:11:25 2005 +++ xc/lib/Xp/XpNotifyPdm.c Sat Sep 15 20:44:17 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/lib/Xp/XpNotifyPdm.c,v 1.10 2007/09/16 03:44:17 tsi Exp $ */ /****************************************************************************** ****************************************************************************** ** @@ -40,7 +41,6 @@ ** ****************************************************************************** *****************************************************************************/ -/* $XFree86: xc/lib/Xp/XpNotifyPdm.c,v 1.9 2005/03/23 03:11:25 dawes Exp $ */ #include #include @@ -229,7 +229,7 @@ /* * Error - cannot determine or establish a selection_display. */ - return( (Status) NULL ); + return( (Status) 0 ); } /* @@ -266,7 +266,7 @@ XCloseDisplay( *selection_display ); *selection_display = (Display *) NULL; } - return( (Status) NULL ); + return( (Status) 0 ); } status = XmbTextListToTextProperty( *selection_display, list, 6, @@ -281,7 +281,7 @@ XCloseDisplay( *selection_display ); *selection_display = (Display *) NULL; } - return( (Status) NULL ); + return( (Status) 0 ); } *type = text_prop.encoding; @@ -361,7 +361,7 @@ return( (Status) 0 ); if (!ticket) - return( (Status) 1 );; + return( (Status) 1 ); /* * Break down the remaining ticket data and build the Index: xc/lib/Xp/XpPrinter.c diff -u xc/lib/Xp/XpPrinter.c:1.10 xc/lib/Xp/XpPrinter.c:1.11 --- xc/lib/Xp/XpPrinter.c:1.10 Mon Jan 9 06:59:19 2006 +++ xc/lib/Xp/XpPrinter.c Sat Sep 15 20:44:17 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/lib/Xp/XpPrinter.c,v 1.11 2007/09/16 03:44:17 tsi Exp $ */ /****************************************************************************** ****************************************************************************** ** @@ -33,7 +34,6 @@ ** ****************************************************************************** *****************************************************************************/ -/* $XFree86: xc/lib/Xp/XpPrinter.c,v 1.10 2006/01/09 14:59:19 dawes Exp $ */ #define NEED_REPLIES @@ -88,7 +88,7 @@ */ if ( printer_name == (char *) NULL ) req->printerNameLen = 0; - else if ( *printer_name == (char) NULL ) + else if ( *printer_name == (char) 0 ) req->printerNameLen = 0; else { printer_name_len = strlen( printer_name ); @@ -98,7 +98,7 @@ if ( locale == (char *) NULL ) req->localeLen = 0; - else if ( *locale == (char) NULL ) + else if ( *locale == (char) 0 ) req->localeLen = 0; else { locale_len = strlen( locale ); Index: xc/lib/Xxf86vm/XF86VMode.c diff -u xc/lib/Xxf86vm/XF86VMode.c:3.35 xc/lib/Xxf86vm/XF86VMode.c:3.36 --- xc/lib/Xxf86vm/XF86VMode.c:3.35 Mon Jan 9 06:59:26 2006 +++ xc/lib/Xxf86vm/XF86VMode.c Wed Oct 15 13:59:11 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/lib/Xxf86vm/XF86VMode.c,v 3.35 2006/01/09 14:59:26 dawes Exp $ */ +/* $XFree86: xc/lib/Xxf86vm/XF86VMode.c,v 3.36 2008/10/15 20:59:11 tsi Exp $ */ /* Copyright (c) 1995 Kaleb S. KEITHLEY @@ -966,11 +966,11 @@ if (rep.vendorLength) _XReadPad(dpy, monitor->vendor, rep.vendorLength); else - monitor->vendor = ""; + monitor->vendor = strdup(""); if (rep.modelLength) _XReadPad(dpy, monitor->model, rep.modelLength); else - monitor->model = ""; + monitor->model = strdup(""); UnlockDisplay(dpy); SyncHandle(); Index: xc/lib/font/bitmap/pcfread.c diff -u xc/lib/font/bitmap/pcfread.c:1.25 xc/lib/font/bitmap/pcfread.c:1.26 --- xc/lib/font/bitmap/pcfread.c:1.25 Tue Jul 25 08:54:11 2006 +++ xc/lib/font/bitmap/pcfread.c Tue Mar 18 12:50:44 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/lib/font/bitmap/pcfread.c,v 1.26 2008/03/18 19:50:44 tsi Exp $ */ /* Copyright 1990, 1998 The Open Group @@ -25,7 +26,6 @@ from The Open Group. */ -/* $XFree86: xc/lib/font/bitmap/pcfread.c,v 1.25 2006/07/25 15:54:11 tsi Exp $ */ /* * Author: Keith Packard, MIT X Consortium @@ -582,6 +582,9 @@ pFont->info.lastRow = pcfGetINT16(file, format); pFont->info.defaultCh = pcfGetINT16(file, format); if (IS_EOF(file)) goto Bail; + if ((pFont->info.firstCol > pFont->info.lastCol) || + (pFont->info.firstRow > pFont->info.lastRow) || + ((pFont->info.lastCol - pFont->info.firstCol) > 255)) goto Bail; nencoding = (pFont->info.lastCol - pFont->info.firstCol + 1) * (pFont->info.lastRow - pFont->info.firstRow + 1); @@ -720,6 +723,9 @@ pFontInfo->lastRow = pcfGetINT16(file, format); pFontInfo->defaultCh = pcfGetINT16(file, format); if (IS_EOF(file)) goto Bail; + if ((pFontInfo->firstCol > pFontInfo->lastCol) || + (pFontInfo->firstRow > pFontInfo->lastRow) || + ((pFontInfo->lastCol - pFontInfo->firstCol) > 255)) goto Bail; nencoding = (pFontInfo->lastCol - pFontInfo->firstCol + 1) * (pFontInfo->lastRow - pFontInfo->firstRow + 1); Index: xc/programs/Xserver/Imakefile diff -u xc/programs/Xserver/Imakefile:3.331 xc/programs/Xserver/Imakefile:3.332 --- xc/programs/Xserver/Imakefile:3.331 Fri May 11 17:30:18 2007 +++ xc/programs/Xserver/Imakefile Mon Dec 31 17:41:59 2007 @@ -1,7 +1,7 @@ /* * Server Master Makefile */ -XCOMM $XFree86: xc/programs/Xserver/Imakefile,v 3.331 2007/05/12 00:30:18 tsi Exp $ +XCOMM $XFree86: xc/programs/Xserver/Imakefile,v 3.332 2008/01/01 01:41:59 tsi Exp $ /* * Copyright (c) 1994-2007 by The XFree86 Project, Inc. @@ -212,13 +212,13 @@ STATICEXTS = $(XKBEXT) $(XINPUTEXT) $(LBXEXT) $(SITEEXTS) $(RANDRLIB) \ $(RENDERLIB) - MISCEXT = Xext/LibraryTargetName(ext) + MISCEXT = $(MISCDIR)/LibraryTargetName(ext) LOADABLEEXTS = $(MISCEXT) $(DBEEXT) $(RECORDEXT) $(GLXEXT) $(XTRAPEXT) EXTENSIONS = $(LOADABLEEXTS) $(STATICEXTS) - EXTDIRS = Xext $(XKBDIR) $(XIDIR) $(GLXDIR) $(LBXDIRS) $(DBEDIR) \ - $(RECORDDIR) $(RANDRDIR) $(RENDERDIR) $(XTRAPDIR) \ - $(SITEEXTDIRS) + EXTDIRS = $(MISCDIR) $(XKBDIR) $(XIDIR) $(GLXDIR) $(LBXDIRS) \ + $(DBEDIR) $(RECORDDIR) $(RANDRDIR) $(RENDERDIR) \ + $(XTRAPDIR) $(SITEEXTDIRS) STDDIRS = include mi $(XPDDXDIR) $(XPFBDIRS) #if BuildLBX || GzipFontCompression @@ -352,7 +352,7 @@ STACKTRACELIB = $(TOP)/util/memleak/LibraryTargetName(stacktrace) #endif #if DoLoadableServer - BASEEXTS = Xext/LibraryTargetName(exts) + BASEEXTS = $(MISCDIR)/LibraryTargetName(exts) XF86EXTENSIONS = $(BASEEXTS) $(STATICEXTS) XF86LIBS = $(MEMDEBUGLIB) $(XF86INIT) $(XF86COMLIB) $(XF86PARSLIB) \ $(XF86OSLIB) $(STACKTRACELIB) Index: xc/programs/Xserver/GL/apple/aglGlx.c diff -u xc/programs/Xserver/GL/apple/aglGlx.c:1.4 xc/programs/Xserver/GL/apple/aglGlx.c:1.5 --- xc/programs/Xserver/GL/apple/aglGlx.c:1.4 Fri Dec 10 09:52:46 2004 +++ xc/programs/Xserver/GL/apple/aglGlx.c Sun Nov 4 11:57:14 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/GL/apple/aglGlx.c,v 1.5 2007/11/04 19:57:14 tsi Exp $ */ /* * GLX implementation that uses Apple's AGL.framework for OpenGL * @@ -32,7 +33,6 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -/* $XFree86: xc/programs/Xserver/GL/apple/aglGlx.c,v 1.4 2004/12/10 17:52:46 alanh Exp $ */ #include "quartzCommon.h" #include @@ -118,6 +118,7 @@ NULL, /* Set up pVisualPriv in probe */ 0, /* Set up numVisuals in probe */ 0, /* Set up numUsableVisuals in probe */ + NULL, /* GLextensions is overwritten by __glXScreenInit */ "Vendor String", /* GLXvendor is overwritten by __glXScreenInit */ "Version String", /* GLXversion is overwritten by __glXScreenInit */ "Extensions String", /* GLXextensions is overwritten by __glXScreenInit */ Index: xc/programs/Xserver/GL/apple/indirect.c diff -u xc/programs/Xserver/GL/apple/indirect.c:1.4 xc/programs/Xserver/GL/apple/indirect.c:1.5 --- xc/programs/Xserver/GL/apple/indirect.c:1.4 Fri Dec 10 09:52:46 2004 +++ xc/programs/Xserver/GL/apple/indirect.c Sun Nov 4 11:57:14 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/GL/apple/indirect.c,v 1.5 2007/11/04 19:57:14 tsi Exp $ */ /* * GLX implementation that uses Apple's OpenGL.framework * (Indirect rendering path) @@ -31,7 +32,6 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -/* $XFree86: xc/programs/Xserver/GL/apple/indirect.c,v 1.4 2004/12/10 17:52:46 alanh Exp $ */ #include "dri.h" #include "quartz.h" @@ -117,6 +117,7 @@ NULL, /* Set up pVisualPriv in probe */ 0, /* Set up numVisuals in probe */ 0, /* Set up numUsableVisuals in probe */ + NULL, /* GLextensions is overwritten by __glXScreenInit */ "Vendor String", /* GLXvendor is overwritten by __glXScreenInit */ "Version String", /* GLXversion is overwritten by __glXScreenInit */ "Extensions String", /* GLXextensions is overwritten by __glXScreenInit */ Index: xc/programs/Xserver/GL/mesa/GLcore/GLcore-def.cpp diff -u xc/programs/Xserver/GL/mesa/GLcore/GLcore-def.cpp:1.1 xc/programs/Xserver/GL/mesa/GLcore/GLcore-def.cpp:1.2 --- xc/programs/Xserver/GL/mesa/GLcore/GLcore-def.cpp:1.1 Sun Feb 24 16:45:41 2002 +++ xc/programs/Xserver/GL/mesa/GLcore/GLcore-def.cpp Sun Nov 4 11:57:14 2007 @@ -1468,7 +1468,6 @@ XMesaLoseCurrent XMesaMakeCurrent XMesaMakeCurrent2 -XMesaReset XMesaSetFXmode XMesaSetVisualDisplay XMesaSwapBuffers @@ -1480,4 +1479,4 @@ xmesa_get_points_func xmesa_get_triangle_func -/* $XFree86: xc/programs/Xserver/GL/mesa/GLcore/GLcore-def.cpp,v 1.1 2002/02/25 00:45:41 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/GL/mesa/GLcore/GLcore-def.cpp,v 1.2 2007/11/04 19:57:14 tsi Exp $ */ Index: xc/programs/Xserver/GL/mesa/X/xf86glx.c diff -u xc/programs/Xserver/GL/mesa/X/xf86glx.c:1.6 xc/programs/Xserver/GL/mesa/X/xf86glx.c:1.7 --- xc/programs/Xserver/GL/mesa/X/xf86glx.c:1.6 Fri Dec 17 08:38:03 2004 +++ xc/programs/Xserver/GL/mesa/X/xf86glx.c Sun Nov 4 11:57:14 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/GL/mesa/X/xf86glx.c,v 1.6 2004/12/17 16:38:03 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/GL/mesa/X/xf86glx.c,v 1.7 2007/11/04 19:57:14 tsi Exp $ */ /************************************************************************** Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. @@ -84,6 +84,7 @@ NULL, /* Set up pVisualPriv in probe */ 0, /* Set up numVisuals in probe */ 0, /* Set up numUsableVisuals in probe */ + NULL, /* GLextensions is overwritten by __glXScreenInit */ "Vendor String", /* GLXvendor is overwritten by __glXScreenInit */ "Version String", /* GLXversion is overwritten by __glXScreenInit */ "Extensions String", /* GLXextensions is overwritten by __glXScreenInit */ @@ -653,8 +654,6 @@ { int i, j; - XMesaReset(); - for (i = 0; i < screenInfo.numScreens; i++) { for (j = 0; j < MESAScreens[i].num_vis; j++) { if (MESAScreens[i].xm_vis[j]) { Index: xc/programs/Xserver/Xext/EVI.c diff -u xc/programs/Xserver/Xext/EVI.c:3.13 xc/programs/Xserver/Xext/EVI.c:3.14 --- xc/programs/Xserver/Xext/EVI.c:3.13 Fri Oct 14 08:16:11 2005 +++ xc/programs/Xserver/Xext/EVI.c Tue Mar 18 12:50:45 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/Xext/EVI.c,v 3.14 2008/03/18 19:50:45 tsi Exp $ */ /************************************************************ Copyright (c) 1997 by Silicon Graphics Computer Systems, Inc. Permission to use, copy, modify, and distribute this @@ -20,7 +21,6 @@ OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ********************************************************/ -/* $XFree86: xc/programs/Xserver/Xext/EVI.c,v 3.13 2005/10/14 15:16:11 tsi Exp $ */ #include #include @@ -31,6 +31,7 @@ #include #include "EVIstruct.h" #include "modinit.h" +#include "scrnintstr.h" #ifdef EVI #if 0 @@ -85,10 +86,18 @@ { REQUEST(xEVIGetVisualInfoReq); xEVIGetVisualInfoReply rep; - int n, n_conflict, n_info, sz_info, sz_conflict; + int i, n, n_conflict, n_info, sz_info, sz_conflict; VisualID32 *conflict; + CARD32 total_visuals = 0; xExtendedVisualInfo *eviInfo; int status; + + /* Prevent REQUEST_FIXED_SIZE overflows */ + for (i = 0; i < screenInfo.numScreens; i++) + total_visuals += screenInfo.screens[i]->numVisuals; + if (stuff->n_visual > total_visuals) + return BadValue; + REQUEST_FIXED_SIZE(xEVIGetVisualInfoReq, stuff->n_visual * sz_VisualID32); status = eviPriv->getVisualInfo((VisualID32 *)&stuff[1], (int)stuff->n_visual, &eviInfo, &n_info, &conflict, &n_conflict); Index: xc/programs/Xserver/Xext/cup.c diff -u xc/programs/Xserver/Xext/cup.c:1.14 xc/programs/Xserver/Xext/cup.c:1.15 --- xc/programs/Xserver/Xext/cup.c:1.14 Fri Oct 14 08:16:11 2005 +++ xc/programs/Xserver/Xext/cup.c Tue Mar 18 12:50:45 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/Xext/cup.c,v 1.15 2008/03/18 19:50:45 tsi Exp $ */ /* Copyright 1997, 1998 The Open Group @@ -23,7 +24,6 @@ in this Software without prior written authorization from The Open Group. */ -/* $XFree86: xc/programs/Xserver/Xext/cup.c,v 1.14 2005/10/14 15:16:11 tsi Exp $ */ #define NEED_REPLIES #define NEED_EVENTS @@ -196,6 +196,9 @@ REQUEST_SIZE_MATCH (xXcupGetReservedColormapEntriesReq); + if (stuff->screen > screenInfo.numScreens) + return BadValue; + #ifndef HAVE_SPECIAL_DESKTOP_COLORS citems[CUP_BLACK_PIXEL].pixel = screenInfo.screens[stuff->screen]->blackPixel; Index: xc/programs/Xserver/Xext/sampleEVI.c diff -u xc/programs/Xserver/Xext/sampleEVI.c:3.7 xc/programs/Xserver/Xext/sampleEVI.c:3.8 --- xc/programs/Xserver/Xext/sampleEVI.c:3.7 Fri Oct 14 08:16:11 2005 +++ xc/programs/Xserver/Xext/sampleEVI.c Tue Mar 18 12:50:45 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/Xext/sampleEVI.c,v 3.8 2008/03/18 19:50:45 tsi Exp $ */ /************************************************************ Copyright (c) 1997 by Silicon Graphics Computer Systems, Inc. Permission to use, copy, modify, and distribute this @@ -20,7 +21,6 @@ OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ********************************************************/ -/* $XFree86: xc/programs/Xserver/Xext/sampleEVI.c,v 3.7 2005/10/14 15:16:11 tsi Exp $ */ #include #include @@ -40,24 +40,37 @@ VisualID32 **conflict_rn, int *n_conflict_rn) { - int max_sz_evi = n_visual * sz_xExtendedVisualInfo * screenInfo.numScreens; + CARD32 max_sz_evi; VisualID32 *temp_conflict; xExtendedVisualInfo *evi; int max_visuals = 0, max_sz_conflict, sz_conflict = 0; int visualI, scrI, sz_evi = 0, conflictI, n_conflict; - *evi_rn = evi = (xExtendedVisualInfo *)xalloc(max_sz_evi); - if (!*evi_rn) - return BadAlloc; + + if ((CARD32)n_visual > + (((CARD32)(-1L) / sz_xExtendedVisualInfo) / screenInfo.numScreens)) + return BadAlloc; + for (scrI = 0; scrI < screenInfo.numScreens; scrI++) { if (screenInfo.screens[scrI]->numVisuals > max_visuals) max_visuals = screenInfo.screens[scrI]->numVisuals; } - max_sz_conflict = n_visual * sz_VisualID32 * screenInfo.numScreens * max_visuals; + + if ((CARD32)n_visual > (((CARD32)(-1L) / sz_VisualID32) / max_visuals)) + return BadAlloc; + + max_sz_evi = n_visual * sz_xExtendedVisualInfo * screenInfo.numScreens; + *evi_rn = evi = (xExtendedVisualInfo *)xalloc(max_sz_evi); + if (!*evi_rn) + return BadAlloc; + + max_sz_conflict = + n_visual * sz_VisualID32 * screenInfo.numScreens * max_visuals; temp_conflict = (VisualID32 *)xalloc(max_sz_conflict); if (!temp_conflict) { xfree(*evi_rn); return BadAlloc; } + for (scrI = 0; scrI < screenInfo.numScreens; scrI++) { for (visualI = 0; visualI < n_visual; visualI++) { evi[sz_evi].core_visual_id = visual[visualI]; Index: xc/programs/Xserver/Xext/security.c diff -u xc/programs/Xserver/Xext/security.c:1.21 xc/programs/Xserver/Xext/security.c:1.23 --- xc/programs/Xserver/Xext/security.c:1.21 Sat Sep 2 09:44:03 2006 +++ xc/programs/Xserver/Xext/security.c Wed Oct 15 13:59:11 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/Xext/security.c,v 1.23 2008/10/15 20:59:11 tsi Exp $ */ /* Copyright 1996, 1998 The Open Group @@ -69,7 +70,6 @@ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $XFree86: xc/programs/Xserver/Xext/security.c,v 1.21 2006/09/02 16:44:03 dawes Exp $ */ #include "dixstruct.h" #include "extnsionst.h" @@ -683,9 +683,12 @@ swaps(&stuff->nbytesAuthProto, n); swaps(&stuff->nbytesAuthData, n); swapl(&stuff->valueMask, n); - values = (CARD32 *)(&stuff[1]) + - ((stuff->nbytesAuthProto + (unsigned)3) >> 2) + + nvalues = ((stuff->nbytesAuthProto + (unsigned)3) >> 2) + ((stuff->nbytesAuthData + (unsigned)3) >> 2); + if (nvalues > + (stuff->length - (sz_xSecurityGenerateAuthorizationReq >> 2))) + return BadLength; + values = (CARD32 *)(&stuff[1]) + nvalues; nvalues = (((CARD32 *)stuff) + stuff->length) - values; SwapLongs(values, nvalues); return ProcSecurityGenerateAuthorization(client); @@ -1642,7 +1645,7 @@ return; #ifndef __UNIXOS2__ - f = fopen(SecurityPolicyFile, "r"); + f = Fopen(SecurityPolicyFile, "r"); #else f = fopen((char*)__XOS2RedirRoot(SecurityPolicyFile), "r"); #endif @@ -1728,7 +1731,7 @@ } #endif /* PROPDEBUG */ - fclose(f); + Fclose(f); } /* SecurityLoadPropertyAccessList */ Index: xc/programs/Xserver/Xext/shape.c diff -u xc/programs/Xserver/Xext/shape.c:3.21 xc/programs/Xserver/Xext/shape.c:3.22 --- xc/programs/Xserver/Xext/shape.c:3.21 Fri Oct 14 08:16:11 2005 +++ xc/programs/Xserver/Xext/shape.c Fri Jan 4 09:50:10 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xext/shape.c,v 3.21 2005/10/14 15:16:11 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xext/shape.c,v 3.22 2008/01/04 17:50:10 tsi Exp $ */ /************************************************************ Copyright 1989, 1998 The Open Group @@ -314,7 +314,6 @@ RegionPtr srcRgn; RegionPtr *destRgn; CreateDftPtr createDefault; - int destBounding; REQUEST_AT_LEAST_SIZE (xShapeRectanglesReq); UpdateCurrentTime(); @@ -323,13 +322,14 @@ return BadWindow; switch (stuff->destKind) { case ShapeBounding: - destBounding = 1; createDefault = CreateBoundingShape; break; case ShapeClip: - destBounding = 0; createDefault = CreateClipShape; break; + case ShapeInput: + createDefault = CreateBoundingShape; + break; default: client->errorValue = stuff->destKind; return BadValue; @@ -353,10 +353,19 @@ if (!pWin->optional) MakeWindowOptional (pWin); - if (destBounding) + switch (stuff->destKind) { + case ShapeBounding: destRgn = &pWin->optional->boundingShape; - else + break; + case ShapeClip: destRgn = &pWin->optional->clipShape; + break; + case ShapeInput: + destRgn = &pWin->optional->inputShape; + break; + default: + return BadValue; + } return RegionOperate (client, pWin, (int)stuff->destKind, destRgn, srcRgn, (int)stuff->op, @@ -402,7 +411,6 @@ RegionPtr *destRgn; PixmapPtr pPixmap; CreateDftPtr createDefault; - int destBounding; REQUEST_SIZE_MATCH (xShapeMaskReq); UpdateCurrentTime(); @@ -411,13 +419,14 @@ return BadWindow; switch (stuff->destKind) { case ShapeBounding: - destBounding = 1; createDefault = CreateBoundingShape; break; case ShapeClip: - destBounding = 0; createDefault = CreateClipShape; break; + case ShapeInput: + createDefault = CreateBoundingShape; + break; default: client->errorValue = stuff->destKind; return BadValue; @@ -440,10 +449,19 @@ if (!pWin->optional) MakeWindowOptional (pWin); - if (destBounding) + switch (stuff->destKind) { + case ShapeBounding: destRgn = &pWin->optional->boundingShape; - else + break; + case ShapeClip: destRgn = &pWin->optional->clipShape; + break; + case ShapeInput: + destRgn = &pWin->optional->inputShape; + break; + default: + return BadValue; + } return RegionOperate (client, pWin, (int)stuff->destKind, destRgn, srcRgn, (int)stuff->op, @@ -498,7 +516,6 @@ CreateDftPtr createDefault; CreateDftPtr createSrc; RegionPtr tmp; - int destBounding; REQUEST_SIZE_MATCH (xShapeCombineReq); UpdateCurrentTime(); @@ -509,13 +526,14 @@ MakeWindowOptional (pDestWin); switch (stuff->destKind) { case ShapeBounding: - destBounding = 1; createDefault = CreateBoundingShape; break; case ShapeClip: - destBounding = 0; createDefault = CreateClipShape; break; + case ShapeInput: + createDefault = CreateBoundingShape; + break; default: client->errorValue = stuff->destKind; return BadValue; @@ -534,6 +552,10 @@ srcRgn = wClipShape (pSrcWin); createSrc = CreateClipShape; break; + case ShapeInput: + srcRgn = wInputShape (pSrcWin); + createSrc = CreateBoundingShape; + break; default: client->errorValue = stuff->srcKind; return BadValue; @@ -552,10 +574,19 @@ if (!pDestWin->optional) MakeWindowOptional (pDestWin); - if (destBounding) + switch (stuff->destKind) { + case ShapeBounding: destRgn = &pDestWin->optional->boundingShape; - else + break; + case ShapeClip: destRgn = &pDestWin->optional->clipShape; + break; + case ShapeInput: + destRgn = &pDestWin->optional->inputShape; + break; + default: + return BadValue; + } return RegionOperate (client, pDestWin, (int)stuff->destKind, destRgn, srcRgn, (int)stuff->op, @@ -615,6 +646,9 @@ case ShapeClip: srcRgn = wClipShape(pWin); break; + case ShapeInput: + srcRgn = wInputShape (pWin); + break; default: client->errorValue = stuff->destKind; return BadValue; @@ -867,7 +901,8 @@ pHead = (ShapeEventPtr *) LookupIDByType(pWin->drawable.id, EventType); if (!pHead) return; - if (which == ShapeBounding) { + switch (which) { + case ShapeBounding: region = wBoundingShape(pWin); if (region) { extents = *REGION_EXTENTS(pWin->drawable.pScreen, region); @@ -879,7 +914,8 @@ extents.y2 = pWin->drawable.height + wBorderWidth (pWin); shaped = xFalse; } - } else { + break; + case ShapeClip: region = wClipShape(pWin); if (region) { extents = *REGION_EXTENTS(pWin->drawable.pScreen, region); @@ -891,6 +927,22 @@ extents.y2 = pWin->drawable.height; shaped = xFalse; } + break; + case ShapeInput: + region = wInputShape(pWin); + if (region) { + extents = *REGION_EXTENTS(pWin->drawable.pScreen, region); + shaped = xTrue; + } else { + extents.x1 = -wBorderWidth (pWin); + extents.y1 = -wBorderWidth (pWin); + extents.x2 = pWin->drawable.width + wBorderWidth (pWin); + extents.y2 = pWin->drawable.height + wBorderWidth (pWin); + shaped = xFalse; + } + break; + default: + return; } for (pShapeEvent = *pHead; pShapeEvent; pShapeEvent = pShapeEvent->next) { client = pShapeEvent->client; @@ -972,6 +1024,9 @@ case ShapeClip: region = wClipShape(pWin); break; + case ShapeInput: + region = wInputShape (pWin); + break; default: client->errorValue = stuff->kind; return BadValue; @@ -994,6 +1049,12 @@ rects->width = pWin->drawable.width; rects->height = pWin->drawable.height; break; + case ShapeInput: + rects->x = - (int) wBorderWidth (pWin); + rects->y = - (int) wBorderWidth (pWin); + rects->width = pWin->drawable.width + wBorderWidth (pWin); + rects->height = pWin->drawable.height + wBorderWidth (pWin); + break; } } else { BoxPtr box; Index: xc/programs/Xserver/Xext/shm.c diff -u xc/programs/Xserver/Xext/shm.c:3.48 xc/programs/Xserver/Xext/shm.c:3.50 --- xc/programs/Xserver/Xext/shm.c:3.48 Sun Feb 19 16:14:35 2006 +++ xc/programs/Xserver/Xext/shm.c Wed Oct 15 13:59:11 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xext/shm.c,v 3.48 2006/02/20 00:14:35 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/Xext/shm.c,v 3.50 2008/10/15 20:59:11 tsi Exp $ */ /************************************************************ Copyright 1989, 1998 The Open Group @@ -714,6 +714,7 @@ PixmapPtr pMap = NULL; DrawablePtr pDraw; DepthPtr pDepth; + CARD32 width, height, depth, size; int i, j, result; ShmDescPtr shmdesc; REQUEST(xShmCreatePixmapReq); @@ -726,24 +727,34 @@ LEGAL_NEW_RESOURCE(stuff->pid, client); VERIFY_GEOMETRABLE(pDraw, stuff->drawable, client); VERIFY_SHMPTR(stuff->shmseg, stuff->offset, TRUE, shmdesc, client); - if (!stuff->width || !stuff->height) + + width = stuff->width; + height = stuff->height; + depth = stuff->depth; + + if (!width || !height || !depth) { client->errorValue = 0; return BadValue; } + if ((width > 32767) || (height > 32767)) + return BadAlloc; + if (stuff->depth != 1) { pDepth = pDraw->pScreen->allowedDepths; for (i=0; ipScreen->numDepths; i++, pDepth++) - if (pDepth->depth == stuff->depth) + if (pDepth->depth == depth) goto CreatePmap; - client->errorValue = stuff->depth; + client->errorValue = depth; return BadValue; } CreatePmap: - VERIFY_SHMSIZE(shmdesc, stuff->offset, - PixmapBytePad(stuff->width, stuff->depth) * stuff->height, - client); + size = PixmapBytePad(width, depth) * height; + if (stuff->offset >= (CARD32)(-size)) + return BadAlloc; + + VERIFY_SHMSIZE(shmdesc, stuff->offset, size, client); if(!(newPix = (PanoramiXRes *) xalloc(sizeof(PanoramiXRes)))) return BadAlloc; @@ -759,8 +770,7 @@ FOR_NSCREENS(j) { pScreen = screenInfo.screens[j]; - pMap = (*shmFuncs[j]->CreatePixmap)(pScreen, - stuff->width, stuff->height, stuff->depth, + pMap = (*shmFuncs[j]->CreatePixmap)(pScreen, width, height, depth, shmdesc->addr + stuff->offset); if (pMap) { @@ -834,8 +844,12 @@ return BadValue; } - VERIFY_SHMSIZE(shmdesc, stuff->offset, length * stuff->totalHeight, - client); + if (stuff->totalHeight && + (length > ((shmdesc->size - stuff->offset) / stuff->totalHeight))) { + client->errorValue = stuff->totalWidth; + return BadValue; + } + if (stuff->srcX > stuff->totalWidth) { client->errorValue = stuff->srcX; @@ -1034,6 +1048,7 @@ int i; ShmDescPtr shmdesc; REQUEST(xShmCreatePixmapReq); + CARD32 width, height, depth, size; REQUEST_SIZE_MATCH(xShmCreatePixmapReq); client->errorValue = stuff->pid; @@ -1042,27 +1057,36 @@ LEGAL_NEW_RESOURCE(stuff->pid, client); VERIFY_GEOMETRABLE(pDraw, stuff->drawable, client); VERIFY_SHMPTR(stuff->shmseg, stuff->offset, TRUE, shmdesc, client); - if (!stuff->width || !stuff->height) + + width = stuff->width; + height = stuff->height; + depth = stuff->depth; + + if (!width || !height || !depth) { client->errorValue = 0; return BadValue; } + if ((width > 32767) || (height > 32767)) + return BadAlloc; + if (stuff->depth != 1) { pDepth = pDraw->pScreen->allowedDepths; for (i=0; ipScreen->numDepths; i++, pDepth++) - if (pDepth->depth == stuff->depth) + if (pDepth->depth == depth) goto CreatePmap; - client->errorValue = stuff->depth; + client->errorValue = depth; return BadValue; } CreatePmap: - VERIFY_SHMSIZE(shmdesc, stuff->offset, - PixmapBytePad(stuff->width, stuff->depth) * stuff->height, - client); + size = PixmapBytePad(width, depth) * height; + if (stuff->offset >= (CARD32)(-size)) + return BadAlloc; + + VERIFY_SHMSIZE(shmdesc, stuff->offset, size, client); pMap = (*shmFuncs[pDraw->pScreen->myNum]->CreatePixmap)( - pDraw->pScreen, stuff->width, - stuff->height, stuff->depth, + pDraw->pScreen, width, height, depth, shmdesc->addr + stuff->offset); if (pMap) { @@ -1077,7 +1101,7 @@ return(client->noClientException); } } - return (BadAlloc); + return BadAlloc; } static int Index: xc/programs/Xserver/Xext/xf86misc.c diff -u xc/programs/Xserver/Xext/xf86misc.c:3.49 xc/programs/Xserver/Xext/xf86misc.c:3.50 --- xc/programs/Xserver/Xext/xf86misc.c:3.49 Wed Jan 3 18:48:11 2007 +++ xc/programs/Xserver/Xext/xf86misc.c Tue Mar 18 12:50:45 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xext/xf86misc.c,v 3.49 2007/01/04 02:48:11 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xext/xf86misc.c,v 3.50 2008/03/18 19:50:45 tsi Exp $ */ /* * Copyright (c) 1995, 1996 The XFree86 Project, Inc @@ -609,6 +609,8 @@ size+= (stuff->vallen + 3) >> 2; if (client->req_len < size) return BadLength; + if (stuff->screen > screenInfo.numScreens) + return BadValue; if (stuff->typelen) { if (!(msgtype = xalloc(stuff->typelen))) return BadAlloc; Index: xc/programs/Xserver/Xi/chgfctl.c diff -u xc/programs/Xserver/Xi/chgfctl.c:3.5 xc/programs/Xserver/Xi/chgfctl.c:3.6 --- xc/programs/Xserver/Xi/chgfctl.c:3.5 Fri Oct 14 08:16:14 2005 +++ xc/programs/Xserver/Xi/chgfctl.c Tue Mar 18 12:50:45 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xi/chgfctl.c,v 3.5 2005/10/14 15:16:14 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xi/chgfctl.c,v 3.6 2008/03/18 19:50:45 tsi Exp $ */ /************************************************************ @@ -500,8 +500,7 @@ StringFeedbackPtr s; xStringFeedbackCtl *f; { - register char n; - register long *p; + char n; int i, j; KeySym *syms, *sup_syms; @@ -509,12 +508,7 @@ if (client->swapped) { swaps(&f->length,n); /* swapped num_keysyms in calling proc */ - p = (long *) (syms); - for (i=0; inum_keysyms; i++) - { - swapl(p, n); - p++; - } + SwapLongs((CARD32 *)syms, f->num_keysyms); } if (f->num_keysyms > s->ctrl.max_symbols) Index: xc/programs/Xserver/Xi/chgkmap.c diff -u xc/programs/Xserver/Xi/chgkmap.c:3.4 xc/programs/Xserver/Xi/chgkmap.c:3.5 --- xc/programs/Xserver/Xi/chgkmap.c:3.4 Fri Oct 14 08:16:14 2005 +++ xc/programs/Xserver/Xi/chgkmap.c Tue Mar 18 12:50:45 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xi/chgkmap.c,v 3.4 2005/10/14 15:16:14 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xi/chgkmap.c,v 3.5 2008/03/18 19:50:45 tsi Exp $ */ /************************************************************ Copyright 1989, 1998 The Open Group @@ -74,22 +74,17 @@ int SProcXChangeDeviceKeyMapping(client) - register ClientPtr client; + ClientPtr client; { - register char n; - register long *p; - register int i, count; + char n; + unsigned int count; REQUEST(xChangeDeviceKeyMappingReq); swaps(&stuff->length, n); REQUEST_AT_LEAST_SIZE(xChangeDeviceKeyMappingReq); - p = (long *) &stuff[1]; count = stuff->keyCodes * stuff->keySymsPerKeyCode; - for (i = 0; i < count; i++) - { - swapl(p, n); - p++; - } + REQUEST_FIXED_SIZE(xChangeDeviceKeyMappingReq, count * sizeof(CARD32)); + SwapLongs((CARD32 *)(&stuff[1]), count); return(ProcXChangeDeviceKeyMapping(client)); } @@ -106,10 +101,14 @@ int ret; unsigned len; DeviceIntPtr dev; + unsigned int count; REQUEST(xChangeDeviceKeyMappingReq); REQUEST_AT_LEAST_SIZE(xChangeDeviceKeyMappingReq); + count = stuff->keyCodes * stuff->keySymsPerKeyCode; + REQUEST_FIXED_SIZE(xChangeDeviceKeyMappingReq, count * sizeof(CARD32)); + dev = LookupDeviceIntRec (stuff->deviceid); if (dev == NULL) { Index: xc/programs/Xserver/Xi/chgprop.c diff -u xc/programs/Xserver/Xi/chgprop.c:3.4 xc/programs/Xserver/Xi/chgprop.c:3.5 --- xc/programs/Xserver/Xi/chgprop.c:3.4 Fri Oct 14 08:16:14 2005 +++ xc/programs/Xserver/Xi/chgprop.c Tue Mar 18 12:50:45 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xi/chgprop.c,v 3.4 2005/10/14 15:16:14 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xi/chgprop.c,v 3.5 2008/03/18 19:50:45 tsi Exp $ */ /************************************************************ Copyright 1989, 1998 The Open Group @@ -78,21 +78,16 @@ SProcXChangeDeviceDontPropagateList(client) register ClientPtr client; { - register char n; - register long *p; - register int i; + char n; REQUEST(xChangeDeviceDontPropagateListReq); swaps(&stuff->length, n); REQUEST_AT_LEAST_SIZE(xChangeDeviceDontPropagateListReq); swapl(&stuff->window, n); swaps(&stuff->count, n); - p = (long *) &stuff[1]; - for (i=0; icount; i++) - { - swapl(p, n); - p++; - } + REQUEST_FIXED_SIZE(xChangeDeviceDontPropagateListReq, + stuff->count * sizeof(CARD32)); + SwapLongs((CARD32 *)(&stuff[1]), stuff->count); return(ProcXChangeDeviceDontPropagateList(client)); } Index: xc/programs/Xserver/Xi/grabdev.c diff -u xc/programs/Xserver/Xi/grabdev.c:3.4 xc/programs/Xserver/Xi/grabdev.c:3.5 --- xc/programs/Xserver/Xi/grabdev.c:3.4 Fri Oct 14 08:16:14 2005 +++ xc/programs/Xserver/Xi/grabdev.c Tue Mar 18 12:50:45 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xi/grabdev.c,v 3.4 2005/10/14 15:16:14 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xi/grabdev.c,v 3.5 2008/03/18 19:50:45 tsi Exp $ */ /************************************************************ Copyright 1989, 1998 The Open Group @@ -80,9 +80,7 @@ SProcXGrabDevice(client) register ClientPtr client; { - register char n; - register long *p; - register int i; + char n; REQUEST(xGrabDeviceReq); swaps(&stuff->length, n); @@ -90,12 +88,11 @@ swapl(&stuff->grabWindow, n); swapl(&stuff->time, n); swaps(&stuff->event_count, n); - p = (long *) &stuff[1]; - for (i=0; ievent_count; i++) - { - swapl(p, n); - p++; - } + + if (stuff->length != (sizeof(xGrabDeviceReq) >> 2) + stuff->event_count) + return BadLength; + + SwapLongs((CARD32 *)(&stuff[1]), stuff->event_count); return(ProcXGrabDevice(client)); } Index: xc/programs/Xserver/Xi/grabdevb.c diff -u xc/programs/Xserver/Xi/grabdevb.c:3.4 xc/programs/Xserver/Xi/grabdevb.c:3.5 --- xc/programs/Xserver/Xi/grabdevb.c:3.4 Fri Oct 14 08:16:14 2005 +++ xc/programs/Xserver/Xi/grabdevb.c Tue Mar 18 12:50:45 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xi/grabdevb.c,v 3.4 2005/10/14 15:16:14 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xi/grabdevb.c,v 3.5 2008/03/18 19:50:45 tsi Exp $ */ /************************************************************ Copyright 1989, 1998 The Open Group @@ -77,9 +77,7 @@ SProcXGrabDeviceButton(client) register ClientPtr client; { - register char n; - register long *p; - register int i; + char n; REQUEST(xGrabDeviceButtonReq); swaps(&stuff->length, n); @@ -87,12 +85,9 @@ swapl(&stuff->grabWindow, n); swaps(&stuff->modifiers, n); swaps(&stuff->event_count, n); - p = (long *) &stuff[1]; - for (i=0; ievent_count; i++) - { - swapl(p, n); - p++; - } + REQUEST_FIXED_SIZE(xGrabDeviceButtonReq, + stuff->event_count * sizeof(CARD32)); + SwapLongs((CARD32 *)(&stuff[1]), stuff->event_count); return(ProcXGrabDeviceButton(client)); } Index: xc/programs/Xserver/Xi/grabdevk.c diff -u xc/programs/Xserver/Xi/grabdevk.c:3.4 xc/programs/Xserver/Xi/grabdevk.c:3.5 --- xc/programs/Xserver/Xi/grabdevk.c:3.4 Fri Oct 14 08:16:14 2005 +++ xc/programs/Xserver/Xi/grabdevk.c Tue Mar 18 12:50:45 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xi/grabdevk.c,v 3.4 2005/10/14 15:16:14 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xi/grabdevk.c,v 3.5 2008/03/18 19:50:45 tsi Exp $ */ /************************************************************ Copyright 1989, 1998 The Open Group @@ -77,9 +77,7 @@ SProcXGrabDeviceKey(client) register ClientPtr client; { - register char n; - register long *p; - register int i; + char n; REQUEST(xGrabDeviceKeyReq); swaps(&stuff->length, n); @@ -87,12 +85,8 @@ swapl(&stuff->grabWindow, n); swaps(&stuff->modifiers, n); swaps(&stuff->event_count, n); - p = (long *) &stuff[1]; - for (i=0; ievent_count; i++) - { - swapl(p, n); - p++; - } + REQUEST_FIXED_SIZE(xGrabDeviceKeyReq, stuff->event_count * sizeof(CARD32)); + SwapLongs((CARD32 *)(&stuff[1]), stuff->event_count); return(ProcXGrabDeviceKey(client)); } Index: xc/programs/Xserver/Xi/selectev.c diff -u xc/programs/Xserver/Xi/selectev.c:3.4 xc/programs/Xserver/Xi/selectev.c:3.5 --- xc/programs/Xserver/Xi/selectev.c:3.4 Fri Oct 14 08:16:14 2005 +++ xc/programs/Xserver/Xi/selectev.c Tue Mar 18 12:50:45 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xi/selectev.c,v 3.4 2005/10/14 15:16:14 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xi/selectev.c,v 3.5 2008/03/18 19:50:45 tsi Exp $ */ /************************************************************ Copyright 1989, 1998 The Open Group @@ -81,21 +81,16 @@ SProcXSelectExtensionEvent (client) register ClientPtr client; { - register char n; - register long *p; - register int i; + char n; REQUEST(xSelectExtensionEventReq); swaps(&stuff->length, n); REQUEST_AT_LEAST_SIZE(xSelectExtensionEventReq); swapl(&stuff->window, n); swaps(&stuff->count, n); - p = (long *) &stuff[1]; - for (i=0; icount; i++) - { - swapl(p, n); - p++; - } + REQUEST_FIXED_SIZE(xSelectExtensionEventReq, + stuff->count * sizeof(CARD32)); + SwapLongs((CARD32 *)(&stuff[1]), stuff->count); return(ProcXSelectExtensionEvent(client)); } Index: xc/programs/Xserver/Xi/sendexev.c diff -u xc/programs/Xserver/Xi/sendexev.c:3.4 xc/programs/Xserver/Xi/sendexev.c:3.5 --- xc/programs/Xserver/Xi/sendexev.c:3.4 Fri Oct 14 08:16:14 2005 +++ xc/programs/Xserver/Xi/sendexev.c Tue Mar 18 12:50:45 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xi/sendexev.c,v 3.4 2005/10/14 15:16:14 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xi/sendexev.c,v 3.5 2008/03/18 19:50:45 tsi Exp $ */ /************************************************************ Copyright 1989, 1998 The Open Group @@ -80,9 +80,8 @@ SProcXSendExtensionEvent(client) register ClientPtr client; { - register char n; - register long *p; - register int i; + char n; + int i; xEvent eventT; xEvent *eventP; EventSwapPtr proc; @@ -92,22 +91,23 @@ REQUEST_AT_LEAST_SIZE(xSendExtensionEventReq); swapl(&stuff->destination, n); swaps(&stuff->count, n); + if (stuff->length != + ((sizeof(xSendExtensionEventReq) >> 2) + stuff->count + + (stuff->num_events * (sizeof(xEvent) >> 2)))) + return BadLength; + eventP = (xEvent *) &stuff[1]; for (i=0; inum_events; i++,eventP++) { proc = EventSwapVector[eventP->u.u.type & 0177]; - if (proc == NotImplemented) /* no swapping proc; invalid event type? */ + if (proc == NotImplemented) /* no swapping proc; invalid event type? */ return (BadValue); (*proc)(eventP, &eventT); *eventP = eventT; } - p = (long *) (((xEvent *) &stuff[1]) + stuff->num_events); - for (i=0; icount; i++) - { - swapl(p, n); - p++; - } + SwapLongs((CARD32 *)((xEvent *)(&stuff[1]) + stuff->num_events), + stuff->count); return(ProcXSendExtensionEvent(client)); } Index: xc/programs/Xserver/Xprint/Init.c diff -u xc/programs/Xserver/Xprint/Init.c:1.19 xc/programs/Xserver/Xprint/Init.c:1.20 --- xc/programs/Xserver/Xprint/Init.c:1.19 Tue Jan 23 10:02:56 2007 +++ xc/programs/Xserver/Xprint/Init.c Mon Dec 31 18:02:34 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xprint/Init.c,v 1.19 2007/01/23 18:02:56 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xprint/Init.c,v 1.20 2008/01/01 02:02:34 tsi Exp $ */ /* (c) Copyright 1996 Hewlett-Packard Company (c) Copyright 1996 International Business Machines Corp. @@ -716,53 +716,66 @@ char line[256]; FILE *fp = fopen(configFileName, "r"); - while(fgets(line, 256, fp) != (char *)NULL) + if(!fp) { - char *tok, *ptr; - if((tok = strtok(line, " \t\012")) != (char *)NULL) + ErrorF("Xp Extension: Can't open file %s\n", configFileName); + configFileName = (char *)NULL; + } + else + { + while(fgets(line, 256, fp) != (char *)NULL) { - if(tok[0] == (char)'#') continue; - if(strcmp(tok, "Printer") == 0) + char *tok, *ptr; + if((tok = strtok(line, " \t\012")) != (char *)NULL) { - while((tok = strtok((char *)NULL, " \t")) != (char *)NULL) + if(tok[0] == (char)'#') + continue; + if(strcmp(tok, "Printer") == 0) { - if ((ptr = MbStrchr(tok, '\012')) != 0) - *ptr = (char)'\0'; - AddPrinterDbName(tok); + while((tok = strtok((char *)NULL, " \t")) != + (char *)NULL) + { + if ((ptr = MbStrchr(tok, '\012')) != 0) + *ptr = (char)'\0'; + AddPrinterDbName(tok); + } } - } - else if(strcmp(tok, "Map") == 0) - { - char *name, *qualifier; + else if(strcmp(tok, "Map") == 0) + { + char *name, *qualifier; - if((tok = strtok((char *)NULL, " \t\012")) == (char *)NULL) - continue; - name = strdup(tok); - if((tok = strtok((char *)NULL, " \t\012")) == (char *)NULL) + if((tok = strtok((char *)NULL, " \t\012")) == + (char *)NULL) + continue; + name = strdup(tok); + if((tok = strtok((char *)NULL, " \t\012")) == + (char *)NULL) + { + xfree(name); + continue; + } + qualifier = strdup(tok); + AddNameMap(name, qualifier); + } + else if(strcmp(tok, "Augment_Printer_List") == 0) { - xfree(name); - continue; + if((tok = strtok((char *)NULL, " \t\012")) == + (char *)NULL) + continue; + + if(strcmp(tok, "%default%") == 0) + continue; + defaultAugment = FALSE; + if(strcmp(tok, "%none%") == 0) + continue; + AugmentPrinterDb(tok); } - qualifier = strdup(tok); - AddNameMap(name, qualifier); - } - else if(strcmp(tok, "Augment_Printer_List") == 0) - { - if((tok = strtok((char *)NULL, " \t\012")) == (char *)NULL) - continue; - - if(strcmp(tok, "%default%") == 0) - continue; - defaultAugment = FALSE; - if(strcmp(tok, "%none%") == 0) - continue; - AugmentPrinterDb(tok); + else + break; /* XXX Generate an error? */ } - else - break; /* XXX Generate an error? */ } + fclose(fp); } - fclose(fp); } if(defaultAugment == TRUE) Index: xc/programs/Xserver/Xprint/attributes.c diff -u xc/programs/Xserver/Xprint/attributes.c:1.24 xc/programs/Xserver/Xprint/attributes.c:1.25 --- xc/programs/Xserver/Xprint/attributes.c:1.24 Mon Apr 9 08:37:13 2007 +++ xc/programs/Xserver/Xprint/attributes.c Sat Sep 15 20:44:17 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xprint/attributes.c,v 1.24 2007/04/09 15:37:13 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xprint/attributes.c,v 1.25 2007/09/16 03:44:17 tsi Exp $ */ /* (c) Copyright 1996 Hewlett-Packard Company (c) Copyright 1996 International Business Machines Corp. @@ -268,8 +268,8 @@ for(;*quarks; quarks++) xrm_name[1] = xrm_class[1] = *quarks; - xrm_name[2] = (XrmQuark)NULL; - xrm_class[2] = (XrmQuark)NULL; + xrm_name[2] = (XrmQuark)0; + xrm_class[2] = (XrmQuark)0; if(XrmQGetResource (*sourceDB, xrm_name, xrm_class, &rep_type, &realVal)) { @@ -317,7 +317,7 @@ */ xrm_name[0] = XrmStringToQuark (qualifierName); xrm_name[1] = XrmStringToQuark ("xp-model-identifier"); - xrm_name[2] = (XrmQuark)NULL; + xrm_name[2] = (XrmQuark)0; XrmQGetResource (systemAttributes.printers, xrm_name, xrm_name, &rep_type, &value); @@ -350,9 +350,9 @@ modelDB = systemAttributes.printers; xrm_name[0] = XrmStringToQuark (qualifierName); - xrm_name[1] = (XrmQuark)NULL; + xrm_name[1] = (XrmQuark)0; xrm_class[0] = XrmStringToQuark((char *)value.addr); - xrm_class[1] = (XrmQuark)NULL; + xrm_class[1] = (XrmQuark)0; enumStruct.pDb = &printerDB; enumStruct.qualifier = (char *)qualifierName; enumStruct.modelId = (char *)value.addr; @@ -397,7 +397,7 @@ */ xrm_name[0] = XrmStringToQuark (printerName); xrm_name[1] = XrmStringToQuark ("xp-model-identifier"); - xrm_name[2] = (XrmQuark)NULL; + xrm_name[2] = (XrmQuark)0; XrmQGetResource (systemAttributes.printers, xrm_name, xrm_name, &rep_type, &value); /* @@ -408,9 +408,9 @@ xrm_class[0] = XrmStringToQuark((char *)value.addr); else xrm_class[0] = xrm_name[0]; - xrm_class[1] = (XrmQuark)NULL; + xrm_class[1] = (XrmQuark)0; - xrm_name[1] = (XrmQuark)NULL; + xrm_name[1] = (XrmQuark)0; enumStruct.pDb = &builtDB; enumStruct.qualifier = (char *)qualifierName; @@ -615,7 +615,7 @@ return NULL_STRING; xrm_name[0] = XrmStringToQuark (attributeName); - xrm_name[1] = (XrmQuark)NULL; + xrm_name[1] = (XrmQuark)0; XrmQGetResource(systemAttributes.server, xrm_name, xrm_name, &rep_type, &value); @@ -648,12 +648,12 @@ return NULL_STRING; xrm_name[0] = XrmStringToQuark ("qualifier"); - xrm_name[1] = (XrmQuark)NULL; + xrm_name[1] = (XrmQuark)0; XrmQGetResource(db, xrm_name, xrm_name, &rep_type, &value); xrm_name[0] = XrmStringToQuark (value.addr); xrm_name[1] = XrmStringToQuark (attributeName); - xrm_name[2] = (XrmQuark)NULL; + xrm_name[2] = (XrmQuark)0; if(XrmQGetResource(db, xrm_name, xrm_name, &rep_type, &value)) return (char *)value.addr; else @@ -698,7 +698,7 @@ } bindings[0] = XrmBindLoosely; quarks[0] = XrmStringToQuark(attributeName); - quarks[1] = (XrmQuark)NULL; + quarks[1] = (XrmQuark)0; XrmQPutStringResource(&db, bindings, quarks, value ? value : ""); } Index: xc/programs/Xserver/Xprint/pcl/PclColor.c diff -u xc/programs/Xserver/Xprint/pcl/PclColor.c:1.11 xc/programs/Xserver/Xprint/pcl/PclColor.c:1.12 --- xc/programs/Xserver/Xprint/pcl/PclColor.c:1.11 Mon Jan 9 06:59:43 2006 +++ xc/programs/Xserver/Xprint/pcl/PclColor.c Tue Mar 18 12:50:45 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/Xprint/pcl/PclColor.c,v 1.12 2008/03/18 19:50:45 tsi Exp $ */ /******************************************************************* ** ** ********************************************************* @@ -44,7 +45,6 @@ dealings in this Software without prior written authorization from said copyright holders. */ -/* $XFree86: xc/programs/Xserver/Xprint/pcl/PclColor.c,v 1.11 2006/01/09 14:59:43 dawes Exp $ */ #include #include @@ -677,7 +677,7 @@ unsigned char *data; long size; - if ((fp=fopen(name, "r")) == NULL) { + if ((fp=Fopen(name, "r")) == NULL) { return(NULL); } @@ -717,7 +717,7 @@ return(NULL); } - fclose(fp); + Fclose(fp); return(data); } Index: xc/programs/Xserver/Xprint/pcl/PclPrint.c diff -u xc/programs/Xserver/Xprint/pcl/PclPrint.c:1.9 xc/programs/Xserver/Xprint/pcl/PclPrint.c:1.10 --- xc/programs/Xserver/Xprint/pcl/PclPrint.c:1.9 Fri Oct 14 08:16:16 2005 +++ xc/programs/Xserver/Xprint/pcl/PclPrint.c Mon Dec 31 17:42:00 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xprint/pcl/PclPrint.c,v 1.9 2005/10/14 15:16:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xprint/pcl/PclPrint.c,v 1.10 2008/01/01 01:42:00 tsi Exp $ */ /******************************************************************* ** ** ********************************************************* @@ -129,9 +129,6 @@ PclContextPrivPtr priv = (PclContextPrivPtr) pCon->devPrivates[PclContextPrivateIndex].ptr; -#ifdef CCP_DEBUG - FILE *xpoutput; -#endif FILE *fp; int retVal; char *fileName, *trailer; @@ -199,16 +196,6 @@ rewind( priv->pJobFile ); stat( priv->jobFileName, &statBuf ); -#ifdef CCP_DEBUG - unlink( "/users/prince/XpOutput" ); - xpoutput = fopen( "/users/prince/XpOutput", "w" ); - - rewind( priv->pJobFile ); - TransferBytes( priv->pJobFile, xpoutput, - (int)statBuf.st_size ); - fclose( xpoutput ); -#endif - XpSubmitJob( priv->jobFileName, pCon ); fclose( priv->pJobFile ); unlink( priv->jobFileName ); Index: xc/programs/Xserver/Xprint/ps/PsPrint.c diff -u xc/programs/Xserver/Xprint/ps/PsPrint.c:1.12 xc/programs/Xserver/Xprint/ps/PsPrint.c:1.13 --- xc/programs/Xserver/Xprint/ps/PsPrint.c:1.12 Fri Oct 14 08:16:16 2005 +++ xc/programs/Xserver/Xprint/ps/PsPrint.c Mon Dec 31 18:02:34 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/Xprint/ps/PsPrint.c,v 1.12 2005/10/14 15:16:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/Xprint/ps/PsPrint.c,v 1.13 2008/01/01 02:02:34 tsi Exp $ */ /* Copyright 1996, 1998 The Open Group @@ -241,13 +241,16 @@ FILE *file; file = fopen(priv->jobFileName, "r"); - if (!file || (fstat(fileno(file), &buffer) < 0)) + if (!file) r = BadAlloc; - else + else if (fstat(fileno(file), &buffer) < 0) { + fclose(file); + r = BadAlloc; + } else { r = XpSendDocumentData(priv->getDocClient, file, buffer.st_size, priv->getDocBufSize); - if (file) fclose(file); + } (void) XpFinishDocData(priv->getDocClient); Index: xc/programs/Xserver/Xprint/ps/PsText.c diff -u xc/programs/Xserver/Xprint/ps/PsText.c:1.14 xc/programs/Xserver/Xprint/ps/PsText.c:1.15 --- xc/programs/Xserver/Xprint/ps/PsText.c:1.14 Mon Jan 9 06:59:45 2006 +++ xc/programs/Xserver/Xprint/ps/PsText.c Mon Dec 31 18:02:34 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/Xprint/ps/PsText.c,v 1.15 2008/01/01 02:02:34 tsi Exp $ */ /* Copyright 1996, 1998 The Open Group @@ -72,7 +73,6 @@ ** ********************************************************* ** ********************************************************************/ -/* $XFree86: xc/programs/Xserver/Xprint/ps/PsText.c,v 1.14 2006/01/09 14:59:45 dawes Exp $ */ #include "Ps.h" #include "gcstruct.h" @@ -83,15 +83,12 @@ static int readFontName(char *fileName, char *file_name, char *dlfnam) { FILE *file; - struct stat statb; char buf[256]; char *front, *fn; file = fopen(fileName, "r"); if(file) { - if (fstat (fileno(file), &statb) == -1) - return 0; while(fgets(buf, 255, file)) { if((fn = strstr(buf, " -"))) @@ -110,9 +107,9 @@ } } } + fclose(file); } file_name[0] = '\0'; - fclose(file); return 0; } Index: xc/programs/Xserver/dbe/dbe.c diff -u xc/programs/Xserver/dbe/dbe.c:3.16 xc/programs/Xserver/dbe/dbe.c:3.17 --- xc/programs/Xserver/dbe/dbe.c:3.16 Tue Jan 9 09:26:01 2007 +++ xc/programs/Xserver/dbe/dbe.c Wed Oct 15 13:59:12 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/dbe/dbe.c,v 3.17 2008/10/15 20:59:12 tsi Exp $ */ /****************************************************************************** * * Copyright (c) 1994, 1995 Hewlett-Packard Company @@ -29,7 +30,6 @@ * DIX DBE code * *****************************************************************************/ -/* $XFree86: xc/programs/Xserver/dbe/dbe.c,v 3.16 2007/01/09 17:26:01 tsi Exp $ */ /* INCLUDES */ @@ -402,7 +402,7 @@ xDbeSwapAction swapAction; VisualID visual; int status; - + int add_index; REQUEST_SIZE_MATCH(xDbeAllocateBackBufferNameReq); @@ -475,14 +475,6 @@ return(BadAlloc); } - /* Make the window priv a DBE window priv resource. */ - if (!AddResource(stuff->buffer, dbeWindowPrivResType, - (pointer)pDbeWindowPriv)) - { - xfree(pDbeWindowPriv); - return(BadAlloc); - } - /* Fill out window priv information. */ pDbeWindowPriv->pWindow = pWin; pDbeWindowPriv->width = pWin->drawable.width; @@ -496,13 +488,13 @@ /* Initialize the buffer ID list. */ pDbeWindowPriv->maxAvailableIDs = DBE_INIT_MAX_IDS; - pDbeWindowPriv->IDs[0] = stuff->buffer; - for (i = 1; i < DBE_INIT_MAX_IDS; i++) - { + + add_index = 0; + for (i = 1; i < DBE_INIT_MAX_IDS; i++) + { pDbeWindowPriv->IDs[i] = DBE_FREE_ID_ELEMENT; } - /* Actually connect the window priv to the window. */ pWin->devPrivates[dbeWindowPrivIndex].ptr = (pointer)pDbeWindowPriv; @@ -567,16 +559,7 @@ pDbeWindowPriv->maxAvailableIDs += DBE_INCR_MAX_IDS; } - /* Finally, record the buffer ID in the array. */ - pDbeWindowPriv->IDs[i] = stuff->buffer; - - /* Associate the new ID with an existing window priv. */ - if (!AddResource(stuff->buffer, dbeWindowPrivResType, - (pointer)pDbeWindowPriv)) - { - pDbeWindowPriv->IDs[i] = DBE_FREE_ID_ELEMENT; - return(BadAlloc); - } + add_index = i; } /* else -- A buffer is already associated with the window. */ @@ -585,13 +568,27 @@ status = (*pDbeScreenPriv->AllocBackBufferName)(pWin, stuff->buffer, stuff->swapAction); - if ((status != Success) && (pDbeWindowPriv->nBufferIDs == 0)) + if (status == Success) { + pDbeWindowPriv->IDs[add_index] = stuff->buffer; + if (!AddResource(stuff->buffer, dbeWindowPrivResType, + (pointer)pDbeWindowPriv)) + { + pDbeWindowPriv->IDs[add_index] = DBE_FREE_ID_ELEMENT; + + if (pDbeWindowPriv->nBufferIDs == 0) { + status = BadAlloc; + goto out_free; + } + } + } else { /* The DDX buffer allocation routine failed for the first buffer of * this window. */ - xfree(pDbeWindowPriv); - return(status); + + if (pDbeWindowPriv->nBufferIDs == 0) { + goto out_free; + } } /* Increment the number of buffers (XIDs) associated with this window. */ @@ -603,6 +600,11 @@ return(status); +out_free: + pWin->devPrivates[dbeWindowPrivIndex].ptr = NULL; + xfree(pDbeWindowPriv); + return(status); + } /* ProcDbeAllocateBackBufferName() */ Index: xc/programs/Xserver/dix/devices.c diff -u xc/programs/Xserver/dix/devices.c:3.23 xc/programs/Xserver/dix/devices.c:3.24 --- xc/programs/Xserver/dix/devices.c:3.23 Fri Oct 14 08:16:21 2005 +++ xc/programs/Xserver/dix/devices.c Sat Sep 15 20:44:18 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/dix/devices.c,v 3.23 2005/10/14 15:16:21 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/dix/devices.c,v 3.24 2007/09/16 03:44:18 tsi Exp $ */ /************************************************************ Copyright 1987, 1998 The Open Group @@ -732,7 +732,7 @@ for (i=0; ictrl.symbols_supported+i) = *symbols++; for (i=0; ictrl.symbols_displayed+i) = (KeySym) NULL; + *(feedc->ctrl.symbols_displayed+i) = (KeySym) 0; feedc->ctrl.id = 0; if ( (feedc->next = dev->stringfeed) ) feedc->ctrl.id = dev->stringfeed->ctrl.id + 1; Index: xc/programs/Xserver/dix/dispatch.c diff -u xc/programs/Xserver/dix/dispatch.c:3.36 xc/programs/Xserver/dix/dispatch.c:3.37 --- xc/programs/Xserver/dix/dispatch.c:3.36 Fri Oct 14 08:16:21 2005 +++ xc/programs/Xserver/dix/dispatch.c Fri Jan 4 09:50:11 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/dix/dispatch.c,v 3.37 2008/01/04 17:50:11 tsi Exp $ */ /************************************************************ Copyright 1987, 1989, 1998 The Open Group @@ -67,8 +68,6 @@ * * *****************************************************************/ -/* $XFree86: xc/programs/Xserver/dix/dispatch.c,v 3.36 2005/10/14 15:16:21 tsi Exp $ */ - #ifdef PANORAMIX_DEBUG #include int ProcInitialConnection(); @@ -1230,6 +1229,12 @@ && (!wBoundingShape(pWin) || POINT_IN_REGION(pWin->drawable.pScreen, &pWin->borderSize, x, y, &box)) + + && (!wInputShape(pWin) || + POINT_IN_REGION(pWin->drawable.pScreen, + wInputShape(pWin), + x - pWin->drawable.x, + y - pWin->drawable.y, &box)) #endif ) { Index: xc/programs/Xserver/dix/dixfonts.c diff -u xc/programs/Xserver/dix/dixfonts.c:3.36 xc/programs/Xserver/dix/dixfonts.c:3.37 --- xc/programs/Xserver/dix/dixfonts.c:3.36 Mon Dec 25 09:04:59 2006 +++ xc/programs/Xserver/dix/dixfonts.c Tue Mar 18 12:50:45 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/dix/dixfonts.c,v 3.36 2006/12/25 17:04:59 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/dix/dixfonts.c,v 3.37 2008/03/18 19:50:45 tsi Exp $ */ /************************************************************************ Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. @@ -350,6 +350,12 @@ err = BadFontName; goto bail; } + if ((pfont->info.firstCol > pfont->info.lastCol) || + (pfont->info.firstRow > pfont->info.lastRow) || + ((pfont->info.lastCol - pfont->info.firstCol) > 255)) { + err = AllocError; + goto bail; + } if (!pfont->fpe) pfont->fpe = fpe; pfont->refcnt++; Index: xc/programs/Xserver/dix/events.c diff -u xc/programs/Xserver/dix/events.c:3.60 xc/programs/Xserver/dix/events.c:3.61 --- xc/programs/Xserver/dix/events.c:3.60 Thu May 24 09:51:39 2007 +++ xc/programs/Xserver/dix/events.c Fri Jan 4 09:50:11 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/dix/events.c,v 3.60 2007/05/24 16:51:39 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/dix/events.c,v 3.61 2008/01/04 17:50:11 tsi Exp $ */ /************************************************************ Copyright 1987, 1998 The Open Group @@ -1901,26 +1901,32 @@ XYToWindow(int x, int y) { WindowPtr pWin; + BoxRec box; spriteTraceGood = 1; /* root window still there */ pWin = ROOT->firstChild; while (pWin) { if ((pWin->mapped) && - (x >= pWin->drawable.x - wBorderWidth (pWin)) && - (x < pWin->drawable.x + (int)pWin->drawable.width + - wBorderWidth(pWin)) && - (y >= pWin->drawable.y - wBorderWidth (pWin)) && - (y < pWin->drawable.y + (int)pWin->drawable.height + - wBorderWidth (pWin)) + (x >= pWin->drawable.x - wBorderWidth (pWin)) && + (x < pWin->drawable.x + (int)pWin->drawable.width + + wBorderWidth(pWin)) && + (y >= pWin->drawable.y - wBorderWidth (pWin)) && + (y < pWin->drawable.y + (int)pWin->drawable.height + + wBorderWidth (pWin)) #ifdef SHAPE - /* When a window is shaped, a further check - * is made to see if the point is inside - * borderSize - */ - && (!wBoundingShape(pWin) || PointInBorderSize(pWin, x, y)) + /* When a window is shaped, a further check + * is made to see if the point is inside + * borderSize + */ + && (!wBoundingShape(pWin) || PointInBorderSize(pWin, x, y)) + && (!wInputShape(pWin) || + POINT_IN_REGION(pWin->drawable.pScreen, + wInputShape(pWin), + x - pWin->drawable.x, + y - pWin->drawable.y, &box)) #endif - ) + ) { if (spriteTraceGood >= spriteTraceSize) { @@ -2163,7 +2169,12 @@ x = xoff - panoramiXdataPtr[i].x; y = yoff - panoramiXdataPtr[i].y; - if(POINT_IN_REGION(pScreen, &pWin->borderClip, x, y, &box)) + if(POINT_IN_REGION(pScreen, &pWin->borderClip, x, y, &box) + && (!wInputShape(pWin) || + POINT_IN_REGION(pWin->drawable.pScreen, + wInputShape(pWin), + x - pWin->drawable.x, + y - pWin->drawable.y, &box))) return TRUE; } Index: xc/programs/Xserver/dix/main.c diff -u xc/programs/Xserver/dix/main.c:3.55 xc/programs/Xserver/dix/main.c:3.56 --- xc/programs/Xserver/dix/main.c:3.55 Mon Feb 5 06:54:15 2007 +++ xc/programs/Xserver/dix/main.c Fri Oct 31 12:10:29 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/dix/main.c,v 3.55 2007/02/05 14:54:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/dix/main.c,v 3.56 2008/10/31 19:10:29 tsi Exp $ */ /*********************************************************** Copyright 1987, 1998 The Open Group @@ -471,7 +471,6 @@ if (dispatchException & DE_TERMINATE) { - CloseWellKnownConnections(); OsCleanup(TRUE); ddxGiveUp(); break; Index: xc/programs/Xserver/dix/window.c diff -u xc/programs/Xserver/dix/window.c:3.40 xc/programs/Xserver/dix/window.c:3.41 --- xc/programs/Xserver/dix/window.c:3.40 Sun Dec 10 07:58:26 2006 +++ xc/programs/Xserver/dix/window.c Fri Jan 4 09:50:11 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/dix/window.c,v 3.41 2008/01/04 17:50:11 tsi Exp $ */ /* Copyright 1987, 1998 The Open Group @@ -69,8 +70,6 @@ * * *****************************************************************/ -/* $XFree86: xc/programs/Xserver/dix/window.c,v 3.40 2006/12/10 15:58:26 tsi Exp $ */ - #include "misc.h" #include "scrnintstr.h" #include "os.h" @@ -406,6 +405,7 @@ #ifdef SHAPE pWin->optional->boundingShape = NULL; pWin->optional->clipShape = NULL; + pWin->optional->inputShape = NULL; #endif #ifdef XINPUT pWin->optional->inputMasks = NULL; @@ -791,6 +791,8 @@ REGION_DESTROY(pScreen, wBoundingShape (pWin)); if (wClipShape (pWin)) REGION_DESTROY(pScreen, wClipShape (pWin)); + if (wInputShape (pWin)) + REGION_DESTROY(pScreen, wInputShape (pWin)); #endif if (pWin->borderIsPixel == FALSE) (*pScreen->DestroyPixmap)(pWin->border.pixmap); @@ -3097,7 +3099,12 @@ if (!pWin->realized) return (FALSE); if (POINT_IN_REGION(pWin->drawable.pScreen, &pWin->borderClip, - x, y, &box)) + x, y, &box) + && (!wInputShape(pWin) || + POINT_IN_REGION(pWin->drawable.pScreen, + wInputShape(pWin), + x - pWin->drawable.x, + y - pWin->drawable.y, &box))) return(TRUE); return(FALSE); } @@ -3472,6 +3479,8 @@ return; if (optional->clipShape != NULL) return; + if (optional->inputShape != NULL) + return; #endif #ifdef XINPUT if (optional->inputMasks != NULL) @@ -3517,6 +3526,7 @@ #ifdef SHAPE optional->boundingShape = NULL; optional->clipShape = NULL; + optional->inputShape = NULL; #endif #ifdef XINPUT optional->inputMasks = NULL; Index: xc/programs/Xserver/hw/darwin/bundle/Dutch.lproj/Credits.rtf diff -u xc/programs/Xserver/hw/darwin/bundle/Dutch.lproj/Credits.rtf:1.8 xc/programs/Xserver/hw/darwin/bundle/Dutch.lproj/Credits.rtf:1.9 --- xc/programs/Xserver/hw/darwin/bundle/Dutch.lproj/Credits.rtf:1.8 Mon Apr 2 17:21:07 2007 +++ xc/programs/Xserver/hw/darwin/bundle/Dutch.lproj/Credits.rtf Thu Nov 27 08:56:21 2008 @@ -19,6 +19,7 @@ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural \f1\b \cf0 \ +\pard\tx1440\tx2880\tx4320\tx5760\tx7200\qc \f1\b \cf0 Contributors to XFree86 4.4: \f0\b0 \ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural Index: xc/programs/Xserver/hw/darwin/bundle/English.lproj/Credits.rtf diff -u xc/programs/Xserver/hw/darwin/bundle/English.lproj/Credits.rtf:1.13 xc/programs/Xserver/hw/darwin/bundle/English.lproj/Credits.rtf:1.14 --- xc/programs/Xserver/hw/darwin/bundle/English.lproj/Credits.rtf:1.13 Mon Apr 2 17:21:07 2007 +++ xc/programs/Xserver/hw/darwin/bundle/English.lproj/Credits.rtf Thu Nov 27 08:56:21 2008 @@ -19,6 +19,7 @@ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural \f1\b \cf0 \ +\pard\tx1440\tx2880\tx4320\tx5760\tx7200\qc \f1\b \cf0 Contributors to XFree86 4.4: \f0\b0 \ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural Index: xc/programs/Xserver/hw/darwin/bundle/French.lproj/Credits.rtf diff -u xc/programs/Xserver/hw/darwin/bundle/French.lproj/Credits.rtf:1.9 xc/programs/Xserver/hw/darwin/bundle/French.lproj/Credits.rtf:1.10 --- xc/programs/Xserver/hw/darwin/bundle/French.lproj/Credits.rtf:1.9 Mon Apr 2 17:21:08 2007 +++ xc/programs/Xserver/hw/darwin/bundle/French.lproj/Credits.rtf Thu Nov 27 08:56:21 2008 @@ -19,6 +19,7 @@ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural \f1\b \cf0 \ +\pard\tx1440\tx2880\tx4320\tx5760\tx7200\qc \f1\b \cf0 Contributors to XFree86 4.4: \f0\b0 \ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural Index: xc/programs/Xserver/hw/darwin/bundle/German.lproj/Credits.rtf diff -u xc/programs/Xserver/hw/darwin/bundle/German.lproj/Credits.rtf:1.8 xc/programs/Xserver/hw/darwin/bundle/German.lproj/Credits.rtf:1.9 --- xc/programs/Xserver/hw/darwin/bundle/German.lproj/Credits.rtf:1.8 Mon Apr 2 17:21:08 2007 +++ xc/programs/Xserver/hw/darwin/bundle/German.lproj/Credits.rtf Thu Nov 27 08:56:21 2008 @@ -19,6 +19,7 @@ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural \f1\b \cf0 \ +\pard\tx1440\tx2880\tx4320\tx5760\tx7200\qc \f1\b \cf0 Contributors to XFree86 4.4: \f0\b0 \ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural Index: xc/programs/Xserver/hw/darwin/bundle/Portuguese.lproj/Credits.rtf diff -u xc/programs/Xserver/hw/darwin/bundle/Portuguese.lproj/Credits.rtf:1.6 xc/programs/Xserver/hw/darwin/bundle/Portuguese.lproj/Credits.rtf:1.7 --- xc/programs/Xserver/hw/darwin/bundle/Portuguese.lproj/Credits.rtf:1.6 Mon Apr 2 17:21:08 2007 +++ xc/programs/Xserver/hw/darwin/bundle/Portuguese.lproj/Credits.rtf Thu Nov 27 08:56:21 2008 @@ -19,6 +19,7 @@ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural \f1\b \cf0 \ +\pard\tx1440\tx2880\tx4320\tx5760\tx7200\qc \f1\b \cf0 Contributors to XFree86 4.4: \f0\b0 \ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural Index: xc/programs/Xserver/hw/darwin/bundle/Spanish.lproj/Credits.rtf diff -u xc/programs/Xserver/hw/darwin/bundle/Spanish.lproj/Credits.rtf:1.8 xc/programs/Xserver/hw/darwin/bundle/Spanish.lproj/Credits.rtf:1.9 --- xc/programs/Xserver/hw/darwin/bundle/Spanish.lproj/Credits.rtf:1.8 Mon Apr 2 17:21:08 2007 +++ xc/programs/Xserver/hw/darwin/bundle/Spanish.lproj/Credits.rtf Thu Nov 27 08:56:21 2008 @@ -19,6 +19,7 @@ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural \f1\b \cf0 \ +\pard\tx1440\tx2880\tx4320\tx5760\tx7200\qc \f1\b \cf0 Contributors to XFree86 4.4: \f0\b0 \ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural Index: xc/programs/Xserver/hw/darwin/bundle/Swedish.lproj/Credits.rtf diff -u xc/programs/Xserver/hw/darwin/bundle/Swedish.lproj/Credits.rtf:1.8 xc/programs/Xserver/hw/darwin/bundle/Swedish.lproj/Credits.rtf:1.9 --- xc/programs/Xserver/hw/darwin/bundle/Swedish.lproj/Credits.rtf:1.8 Mon Apr 2 17:21:08 2007 +++ xc/programs/Xserver/hw/darwin/bundle/Swedish.lproj/Credits.rtf Thu Nov 27 08:56:21 2008 @@ -19,6 +19,7 @@ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural \f1\b \cf0 \ +\pard\tx1440\tx2880\tx4320\tx5760\tx7200\qc \f1\b \cf0 Contributors to XFree86 4.4: \f0\b0 \ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural Index: xc/programs/Xserver/hw/darwin/bundle/ko.lproj/Credits.rtf diff -u xc/programs/Xserver/hw/darwin/bundle/ko.lproj/Credits.rtf:1.8 xc/programs/Xserver/hw/darwin/bundle/ko.lproj/Credits.rtf:1.9 --- xc/programs/Xserver/hw/darwin/bundle/ko.lproj/Credits.rtf:1.8 Mon Apr 2 17:21:08 2007 +++ xc/programs/Xserver/hw/darwin/bundle/ko.lproj/Credits.rtf Thu Nov 27 08:56:21 2008 @@ -19,6 +19,7 @@ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural \f1\b \cf0 \ +\pard\tx1440\tx2880\tx4320\tx5760\tx7200\qc \f1\b \cf0 Contributors to XFree86 4.4: \f0\b0 \ \pard\tx1440\tx2880\tx4320\tx5760\tx7200\ql\qnatural Index: xc/programs/Xserver/hw/dmx/dmxwindow.c diff -u xc/programs/Xserver/hw/dmx/dmxwindow.c:1.3 xc/programs/Xserver/hw/dmx/dmxwindow.c:1.4 --- xc/programs/Xserver/hw/dmx/dmxwindow.c:1.3 Sun Jan 30 09:48:44 2005 +++ xc/programs/Xserver/hw/dmx/dmxwindow.c Fri Jan 4 09:50:11 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/dmx/dmxwindow.c,v 1.3 2005/01/30 17:48:44 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/dmx/dmxwindow.c,v 1.4 2008/01/04 17:50:11 tsi Exp $ */ /* * Copyright 2001-2004 Red Hat Inc., Durham, North Carolina. * @@ -1047,6 +1047,29 @@ ShapeClip, 0, 0, None, ShapeSet); } + /* Now, set the input shape */ + if (wInputShape(pWindow)) { + pBox = REGION_RECTS(wInputShape(pWindow)); + nRect = nBox = REGION_NUM_RECTS(wInputShape(pWindow)); + pRectFirst = pRect = xalloc(nRect * sizeof(*pRect)); + while (nBox--) { + pRect->x = pBox->x1; + pRect->y = pBox->y1; + pRect->width = pBox->x2 - pBox->x1; + pRect->height = pBox->y2 - pBox->y1; + pBox++; + pRect++; + } + XShapeCombineRectangles(dmxScreen->beDisplay, pWinPriv->window, + ShapeInput, 0, 0, + pRectFirst, nRect, + ShapeSet, YXBanded); + xfree(pRectFirst); + } else { + XShapeCombineMask(dmxScreen->beDisplay, pWinPriv->window, + ShapeInput, 0, 0, None, ShapeSet); + } + if (XShapeInputSelected(dmxScreen->beDisplay, pWinPriv->window)) { ErrorF("Input selected for window %x on Screen %d\n", (unsigned int)pWinPriv->window, pScreen->myNum); Index: xc/programs/Xserver/hw/dmx/config/Imakefile diff -u xc/programs/Xserver/hw/dmx/config/Imakefile:1.4 xc/programs/Xserver/hw/dmx/config/Imakefile:1.5 --- xc/programs/Xserver/hw/dmx/config/Imakefile:1.4 Fri Oct 14 08:16:25 2005 +++ xc/programs/Xserver/hw/dmx/config/Imakefile Mon Dec 31 17:42:00 2007 @@ -1,23 +1,26 @@ -XCOMM $XFree86: xc/programs/Xserver/hw/dmx/config/Imakefile,v 1.4 2005/10/14 15:16:25 tsi Exp $ +XCOMM $XFree86: xc/programs/Xserver/hw/dmx/config/Imakefile,v 1.5 2008/01/01 01:42:00 tsi Exp $ #include YFLAGS = -d -LIBSRCS = parser.c scanner.c dmxparse.c dmxprint.c dmxcompat.c dmxconfig.c -LIBOBJS = parser.o scanner.o dmxparse.o dmxprint.o dmxcompat.o dmxconfig.o +LIBSRCS = parser.c scanner.c dmxparse.c dmxconfig.c +LIBOBJS = parser.o scanner.o dmxparse.o dmxconfig.o CONFIGSRCS = xdmxconfig.c dmxlog.c Canvas.c CONFIGOBJS = xdmxconfig.o dmxlog.o Canvas.o -COMPATSRCS = vdltodmx.c -COMPATOBJS = vdltodmx.o +COMPATSRCS = vdltodmx.c dmxcompat.c +COMPATOBJS = vdltodmx.o dmxcompat.o TESTSRCS = dmxtodmx.c TESTOBJS = dmxtodmx.o -SRCS = $(LIBSRCS) $(CONFIGSRCS) $(COMPATSRCS) $(TESTSRCS) -OBJS = $(LIBOBJS) $(CONFIGOBJS) $(COMPATOBJS) $(TESTOBJS) +PRINTSRCS = dmxprint.c +PRINTOBJS = dmxprint.o + +SRCS = $(LIBSRCS) $(CONFIGSRCS) $(COMPATSRCS) $(TESTSRCS) $(PRINTSRCS) +OBJS = $(LIBOBJS) $(CONFIGOBJS) $(COMPATOBJS) $(TESTOBJS) $(PRINTOBJS) EXES = xdmxconfig vdltodmx dmxtodmx @@ -37,18 +40,18 @@ NormalLibraryObjectRule() NormalLibraryTarget(dmxconfig,$(LIBOBJS)) -NormalProgramTarget(xdmxconfig,$(CONFIGOBJS),\ +NormalProgramTarget(xdmxconfig,$(CONFIGOBJS) $(PRINTOBJS),\ libdmxconfig.a XawClientDepLibs $(DEPXTOOLLIB),\ $(LOCAL_LIBRARIES) XawClientLibs $(XTOOLLIB),NullParameter) AllTarget(ProgramTargetName(xdmxconfig)) InstallProgram(xdmxconfig,$(BINDIR)) -NormalProgramTarget(vdltodmx,$(COMPATOBJS),libdmxconfig.a,\ +NormalProgramTarget(vdltodmx,$(COMPATOBJS) $(PRINTOBJS),libdmxconfig.a,\ $(LOCAL_LIBRARIES),NullParameter) AllTarget(ProgramTargetName(vdltodmx)) InstallProgram(vdltodmx,$(BINDIR)) -NormalProgramTarget(dmxtodmx,$(TESTOBJS),libdmxconfig.a,\ +NormalProgramTarget(dmxtodmx,$(TESTOBJS) $(PRINTOBJS),libdmxconfig.a,\ $(LOCAL_LIBRARIES),NullParameter) AllTarget(ProgramTargetName(dmxtodmx)) InstallProgram(dmxtodmx,$(BINDIR)) Index: xc/programs/Xserver/hw/dmx/input/usb-other.c diff -u xc/programs/Xserver/hw/dmx/input/usb-other.c:1.1 xc/programs/Xserver/hw/dmx/input/usb-other.c:1.2 --- xc/programs/Xserver/hw/dmx/input/usb-other.c:1.1 Wed Jun 30 13:21:44 2004 +++ xc/programs/Xserver/hw/dmx/input/usb-other.c Sat Sep 15 18:54:22 2007 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/dmx/input/usb-other.c,v 1.1 2004/06/30 20:21:44 martin Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/dmx/input/usb-other.c,v 1.2 2007/09/16 01:54:22 tsi Exp $ */ /* * Copyright 2002 Red Hat Inc., Durham, North Carolina. * @@ -138,7 +138,7 @@ } else info->numAbsAxes = priv->numAbs; for (j = 0; j < info->numAbsAxes; j++) { - ioctl(priv->fd, EVIOCGABS(j), abs); + ioctl(priv->fd, EVIOCGABS(j), absolute); info->minval[1+j] = absolute[1]; info->maxval[1+j] = absolute[2]; info->res[1+j] = absolute[3]; Index: xc/programs/Xserver/hw/tinyx/igs/igsdraw.c diff -u xc/programs/Xserver/hw/tinyx/igs/igsdraw.c:1.3 xc/programs/Xserver/hw/tinyx/igs/igsdraw.c:1.4 --- xc/programs/Xserver/hw/tinyx/igs/igsdraw.c:1.3 Fri Feb 17 19:31:36 2006 +++ xc/programs/Xserver/hw/tinyx/igs/igsdraw.c Sat Sep 15 19:10:20 2007 @@ -1,5 +1,5 @@ /* - * $XFree86: xc/programs/Xserver/hw/tinyx/igs/igsdraw.c,v 1.3 2006/02/18 03:31:36 dawes Exp $ + * $XFree86: xc/programs/Xserver/hw/tinyx/igs/igsdraw.c,v 1.4 2007/09/16 02:10:20 tsi Exp $ * * Copyright © 2000 Keith Packard * @@ -175,7 +175,7 @@ for (y = 0; y < 8; y++) { bits = pix[stipY * pixStride]; - FbRotLeft (bits, stipX); + bits = FbRotLeft (bits, stipX); tmp[y] = (CARD8) bits; stipY++; if (stipY == pPixmap->drawable.height) Index: xc/programs/Xserver/hw/tinyx/sis530/sisdraw.c diff -u xc/programs/Xserver/hw/tinyx/sis530/sisdraw.c:1.3 xc/programs/Xserver/hw/tinyx/sis530/sisdraw.c:1.4 --- xc/programs/Xserver/hw/tinyx/sis530/sisdraw.c:1.3 Fri Feb 17 19:31:37 2006 +++ xc/programs/Xserver/hw/tinyx/sis530/sisdraw.c Sat Sep 15 19:10:22 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/hw/tinyx/sis530/sisdraw.c,v 1.4 2007/09/16 02:10:22 tsi Exp $ */ /* * Copyright © 1999 Keith Packard * @@ -19,7 +20,6 @@ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ -/* $XFree86: xc/programs/Xserver/hw/tinyx/sis530/sisdraw.c,v 1.3 2006/02/18 03:31:37 dawes Exp $ */ /* * Copyright (c) 2004 by The XFree86 Project, Inc. * All rights reserved. @@ -849,7 +849,7 @@ for (y = 0; y < 8; y++) { bits = stip[stipY<<1]; - FbRotLeft(bits, rot); + bits = FbRotLeft(bits, rot); SisInvertBits32(bits); sis->u.general.mask[y] = (CARD8) bits; stipY++; Index: xc/programs/Xserver/hw/tinyx/trio/s3.h diff -u xc/programs/Xserver/hw/tinyx/trio/s3.h:1.1 xc/programs/Xserver/hw/tinyx/trio/s3.h:1.2 --- xc/programs/Xserver/hw/tinyx/trio/s3.h:1.1 Wed Jun 2 15:43:03 2004 +++ xc/programs/Xserver/hw/tinyx/trio/s3.h Sat Sep 15 20:44:18 2007 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/hw/tinyx/trio/s3.h,v 1.2 2007/09/16 03:44:18 tsi Exp $ */ /* * Copyright © 1999 Keith Packard * @@ -19,7 +20,6 @@ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ -/* $XFree86: xc/programs/Xserver/hw/tinyx/trio/s3.h,v 1.1 2004/06/02 22:43:03 dawes Exp $ */ /* * Copyright (c) 2004 by The XFree86 Project, Inc. * All rights reserved. @@ -1065,7 +1065,7 @@ ((crtc)->ge_screen_width_2 << 2)) #define crtc_set_ge_screen_width(crtc,v) { \ - (crtc)->ge_screen_width_0_1 = (v); \ + (crtc)->ge_screen_width_0_1 = (v) & 0x3; \ (crtc)->ge_screen_width_2 = (v) >> 2; \ } Index: xc/programs/Xserver/hw/xfree86/Imakefile diff -u xc/programs/Xserver/hw/xfree86/Imakefile:3.93 xc/programs/Xserver/hw/xfree86/Imakefile:3.94 --- xc/programs/Xserver/hw/xfree86/Imakefile:3.93 Tue Jun 27 20:20:27 2006 +++ xc/programs/Xserver/hw/xfree86/Imakefile Sat Sep 15 20:36:21 2007 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/Imakefile,v 3.93 2006/06/28 03:20:27 dawes Exp $ +XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/Imakefile,v 3.94 2007/09/16 03:36:21 tsi Exp $ /* * Copyright (c) 1994-2006 by The XFree86 Project, Inc. * All rights reserved. @@ -274,6 +274,7 @@ InstallNamedNonExec(Options,Options,$(LIBDIR)) InstallDriverSDKNamedNonExec($(XF86CONFIG),XF86Config.eg,$(DRIVERSDKDIR)) +InstallDriverSDKNonExecFile(xf86Version.h,$(DRIVERSDKINCLUDEDIR)) MakeSubdirs($(SUBDIRS)) DependSubdirs($(SUBDIRS)) Index: xc/programs/Xserver/hw/xfree86/xf86Date.h diff -u xc/programs/Xserver/hw/xfree86/xf86Date.h:1.144 xc/programs/Xserver/hw/xfree86/xf86Date.h:1.176 --- xc/programs/Xserver/hw/xfree86/xf86Date.h:1.144 Sun Aug 12 17:57:47 2007 +++ xc/programs/Xserver/hw/xfree86/xf86Date.h Sun Dec 14 09:33:00 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/xf86Date.h,v 1.144 2007/08/13 00:57:47 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf86Date.h,v 1.176 2008/12/14 17:33:00 tsi Exp $ */ /* * Copyright (c) 2004-2007 by The XFree86 Project, Inc. * All rights reserved. @@ -48,6 +48,6 @@ #ifndef XF86_DATE -#define XF86_DATE "12 August 2007" +#define XF86_DATE "15 December 2008" #endif Index: xc/programs/Xserver/hw/xfree86/xf86Version.h diff -u xc/programs/Xserver/hw/xfree86/xf86Version.h:3.658 xc/programs/Xserver/hw/xfree86/xf86Version.h:3.690 --- xc/programs/Xserver/hw/xfree86/xf86Version.h:3.658 Sun Aug 12 17:57:47 2007 +++ xc/programs/Xserver/hw/xfree86/xf86Version.h Sun Dec 14 09:33:00 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/xf86Version.h,v 3.658 2007/08/13 00:57:47 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/xf86Version.h,v 3.690 2008/12/14 17:33:00 tsi Exp $ */ /* * Copyright (c) 1994-2007 by The XFree86 Project, Inc. @@ -50,7 +50,7 @@ #ifndef XF86_VERSION_NUMERIC #define XF86_VERSION_MAJOR 4 -#define XF86_VERSION_MINOR 7 +#define XF86_VERSION_MINOR 8 #define XF86_VERSION_PATCH 0 #define XF86_VERSION_SNAP 0 Index: xc/programs/Xserver/hw/xfree86/common/Imakefile diff -u xc/programs/Xserver/hw/xfree86/common/Imakefile:3.168 xc/programs/Xserver/hw/xfree86/common/Imakefile:3.169 --- xc/programs/Xserver/hw/xfree86/common/Imakefile:3.168 Tue Jun 27 20:20:27 2006 +++ xc/programs/Xserver/hw/xfree86/common/Imakefile Sat Sep 15 20:36:21 2007 @@ -1,4 +1,4 @@ -XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/common/Imakefile,v 3.168 2006/06/28 03:20:27 dawes Exp $ +XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/common/Imakefile,v 3.169 2007/09/16 03:36:21 tsi Exp $ #include @@ -224,11 +224,6 @@ NormalLibraryTarget(xf86,$(OBJS)) LinkFile(xf86IniExt.c,$(SERVERSRC)/mi/miinitext.c) -LinkSourceFile(xf86Version.h,..) -LinkSourceFile(xf86Pci.h,$(XF86OSSRC)/bus) -#ifdef SparcArchitecture -LinkSourceFile(xf86Sbus.h,$(XF86OSSRC)/bus) -#endif #if HasPerl MODEDEFSRCS = ../etc/vesamodes ../etc/extramodes @@ -259,12 +254,10 @@ InstallDriverSDKNonExecFile(xf86.h,$(DRIVERSDKINCLUDEDIR)) InstallDriverSDKNonExecFile(xf86Module.h,$(DRIVERSDKINCLUDEDIR)) InstallDriverSDKNonExecFile(xf86Opt.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(xf86Pci.h,$(DRIVERSDKINCLUDEDIR)) InstallDriverSDKNonExecFile(xf86PciInfo.h,$(DRIVERSDKINCLUDEDIR)) InstallDriverSDKNonExecFile(xf86Priv.h,$(DRIVERSDKINCLUDEDIR)) InstallDriverSDKNonExecFile(xf86Privstr.h,$(DRIVERSDKINCLUDEDIR)) InstallDriverSDKNonExecFile(xf86Resources.h,$(DRIVERSDKINCLUDEDIR)) -InstallDriverSDKNonExecFile(xf86Version.h,$(DRIVERSDKINCLUDEDIR)) InstallDriverSDKNonExecFile(xf86Xinput.h,$(DRIVERSDKINCLUDEDIR)) InstallDriverSDKNonExecFile(xf86cmap.h,$(DRIVERSDKINCLUDEDIR)) InstallDriverSDKNonExecFile(xf86fbman.h,$(DRIVERSDKINCLUDEDIR)) Index: xc/programs/Xserver/hw/xfree86/common/xf86Bus.c diff -u xc/programs/Xserver/hw/xfree86/common/xf86Bus.c:1.99 xc/programs/Xserver/hw/xfree86/common/xf86Bus.c:1.101 --- xc/programs/Xserver/hw/xfree86/common/xf86Bus.c:1.99 Mon Apr 9 08:37:14 2007 +++ xc/programs/Xserver/hw/xfree86/common/xf86Bus.c Thu Apr 24 13:54:54 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Bus.c,v 1.99 2007/04/09 15:37:14 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Bus.c,v 1.101 2008/04/24 20:54:54 tsi Exp $ */ /* * Copyright (c) 1997-2007 by The XFree86 Project, Inc. * All rights reserved. @@ -1181,6 +1181,10 @@ { memType ret; + /* A range starting at zero is always a conflict */ + if (rgp->rBase == 0) + return 1; + while(pRes) { if (!needCheck(pRes,rgp->type, entityIndex ,state)) { pRes = pRes->next; @@ -1198,7 +1202,7 @@ || (rgp->rEnd != pRes->block_end)) return ret; } - break; + break; case ResSparse: if ((rgp->rBase & rgp->rMask) != rgp->rBase) { xf86Msg(X_ERROR,"sparse io range (base: 0x%lx mask: 0x%lx)" @@ -1348,17 +1352,18 @@ switch (list->res_type & ResExtMask) { case ResBlock: xf86ErrorFVerb(verb, - "\t[%d] %d\t%ld\t0x%08lx - 0x%08lx (0x%lx)", + "\t[%3d] %3d %3ld 0x%08lx - 0x%08lx (0x%08lx)", i, list->entityIndex, (list->res_type & ResDomain) >> 24, list->block_begin, list->block_end, list->block_end - list->block_begin + 1); break; case ResSparse: - xf86ErrorFVerb(verb, "\t[%d] %d\t%ld\t0x%08lx - 0x%08lx", + xf86ErrorFVerb(verb, + "\t[%3d] %3d %3ld 0x%08lx - 0x%08lx", i, list->entityIndex, (list->res_type & ResDomain) >> 24, - list->sparse_base,list->sparse_mask); + list->sparse_base, list->sparse_mask); break; default: list = list->next; @@ -1819,15 +1824,10 @@ range.type = (range.type & ~ResAccMask) | (access & ResAccMask); } range.type &= ~ResEstimated; /* Not allowed for drivers */ -#if !(defined(__alpha__) && defined(linux)) - /* On Alpha Linux, do not check for conflicts, trust the kernel. */ if (checkConflict(&range, Acc, entityIndex, SETUP,TRUE)) res = xf86AddResToList(res,&range,entityIndex); else -#endif - { Acc = xf86AddResToList(Acc,&range,entityIndex); - } list++; } if (list_f) Index: xc/programs/Xserver/hw/xfree86/common/xf86Config.c diff -u xc/programs/Xserver/hw/xfree86/common/xf86Config.c:3.295 xc/programs/Xserver/hw/xfree86/common/xf86Config.c:3.296 --- xc/programs/Xserver/hw/xfree86/common/xf86Config.c:3.295 Sun Mar 11 10:38:02 2007 +++ xc/programs/Xserver/hw/xfree86/common/xf86Config.c Thu May 1 09:13:22 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Config.c,v 3.295 2007/03/11 17:38:02 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Config.c,v 3.296 2008/05/01 16:13:22 tsi Exp $ */ /* @@ -2057,7 +2057,6 @@ xf86Msg(from, "Xinerama: enabled.\n"); #endif - xf86MsgVerb(X_INFO, 3, "Checking for unused ServerFlags options:\n"); xf86ShowUnusedOptionsVerb(-1, f->options, 3); return f; } Index: xc/programs/Xserver/hw/xfree86/common/xf86Configure.c diff -u xc/programs/Xserver/hw/xfree86/common/xf86Configure.c:3.94 xc/programs/Xserver/hw/xfree86/common/xf86Configure.c:3.96 --- xc/programs/Xserver/hw/xfree86/common/xf86Configure.c:3.94 Sun Mar 11 10:38:02 2007 +++ xc/programs/Xserver/hw/xfree86/common/xf86Configure.c Sun Nov 23 09:32:22 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Configure.c,v 3.94 2007/03/11 17:38:02 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Configure.c,v 3.96 2008/11/23 17:32:22 tsi Exp $ */ /* * Copyright 2000-2002 by Alan Hourihane, Flint Mountain, North Wales. * @@ -912,6 +912,7 @@ if (!(filename = (char *)ALLOCATE_LOCAL(strlen(home) + strlen(configfile) + 3))) + goto bail; if (home[0] == '/' && home[1] == '\0') home[0] = '\0'; @@ -1048,7 +1049,6 @@ ErrorF("To test the server, run 'XFree86 -xf86config %s'\n\n", filename); bail: - CloseWellKnownConnections(); OsCleanup(TRUE); AbortDDX(); fflush(stderr); Index: xc/programs/Xserver/hw/xfree86/common/xf86DoProbe.c diff -u xc/programs/Xserver/hw/xfree86/common/xf86DoProbe.c:1.21 xc/programs/Xserver/hw/xfree86/common/xf86DoProbe.c:1.22 --- xc/programs/Xserver/hw/xfree86/common/xf86DoProbe.c:1.21 Mon Feb 5 07:03:46 2007 +++ xc/programs/Xserver/hw/xfree86/common/xf86DoProbe.c Fri Oct 31 12:10:40 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86DoProbe.c,v 1.21 2007/02/05 15:03:46 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86DoProbe.c,v 1.22 2008/10/31 19:10:40 tsi Exp $ */ /* * Copyright (c) 1999-2005 by The XFree86 Project, Inc. * All rights reserved. @@ -120,7 +120,6 @@ } } - CloseWellKnownConnections(); OsCleanup(TRUE); AbortDDX(); fflush(stderr); Index: xc/programs/Xserver/hw/xfree86/common/xf86Init.c diff -u xc/programs/Xserver/hw/xfree86/common/xf86Init.c:3.249 xc/programs/Xserver/hw/xfree86/common/xf86Init.c:3.250 --- xc/programs/Xserver/hw/xfree86/common/xf86Init.c:3.249 Mon Feb 5 07:03:46 2007 +++ xc/programs/Xserver/hw/xfree86/common/xf86Init.c Fri Oct 31 12:10:40 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Init.c,v 3.249 2007/02/05 15:03:46 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Init.c,v 3.250 2008/10/31 19:10:40 tsi Exp $ */ /* * Loosely based on code bearing the following copyright: @@ -953,7 +953,6 @@ /* XXX Should this be before or after loading dependent modules? */ if (xf86ProbeOnly) { - CloseWellKnownConnections(); OsCleanup(TRUE); AbortDDX(); fflush(stderr); Index: xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h diff -u xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h:1.165 xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h:1.169 --- xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h:1.165 Tue Apr 11 18:07:31 2006 +++ xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h Wed Apr 30 08:43:47 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h,v 1.165 2006/04/12 01:07:31 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h,v 1.169 2008/04/30 15:43:47 tsi Exp $ */ /* * Copyright (c) 1995-2003 by The XFree86 Project, Inc. @@ -76,11 +76,8 @@ #define PCI_VENDOR_REAL3D 0x003D #define PCI_VENDOR_COMPAQ 0x0E11 #define PCI_VENDOR_ATI 0x1002 -#define PCI_VENDOR_AVANCE 0x1005 #define PCI_VENDOR_TSENG 0x100C -#define PCI_VENDOR_NS 0x100B #define PCI_VENDOR_WEITEK 0x100E -#define PCI_VENDOR_VIDEOLOGIC 0x1010 #define PCI_VENDOR_DIGITAL 0x1011 #define PCI_VENDOR_CIRRUS 0x1013 #define PCI_VENDOR_AMD 0x1022 @@ -89,38 +86,28 @@ #define PCI_VENDOR_DELL 0x1028 #define PCI_VENDOR_MATROX 0x102B #define PCI_VENDOR_CHIPSTECH 0x102C -#define PCI_VENDOR_MIRO 0x1031 -#define PCI_VENDOR_NEC 0x1033 #define PCI_VENDOR_SIS 0x1039 #define PCI_VENDOR_HP 0x103C #define PCI_VENDOR_SGS 0x104A #define PCI_VENDOR_TI 0x104C -#define PCI_VENDOR_SONY 0x104D #define PCI_VENDOR_OAK 0x104E -#define PCI_VENDOR_MOTOROLA 0x1057 #define PCI_VENDOR_NUMNINE 0x105D #define PCI_VENDOR_CYRIX 0x1078 #define PCI_VENDOR_SUN 0x108E -#define PCI_VENDOR_DIAMOND 0x1092 -#define PCI_VENDOR_BROOKTREE 0x109E #define PCI_VENDOR_NEOMAGIC 0x10C8 #define PCI_VENDOR_NVIDIA 0x10DE #define PCI_VENDOR_IMS 0x10E0 -#define PCI_VENDOR_INTEGRAPHICS 0x10EA #define PCI_VENDOR_CREATIVE 0x1102 #define PCI_VENDOR_ALLIANCE 0x1142 #define PCI_VENDOR_RENDITION 0x1163 #define PCI_VENDOR_3DFX 0x121A #define PCI_VENDOR_SMI 0x126F #define PCI_VENDOR_ENSONIQ 0x1274 -#define PCI_VENDOR_TRITECH 0x1292 #define PCI_VENDOR_NVIDIA_SGS 0x12D2 #define PCI_VENDOR_VMWARE 0x15AD #define PCI_VENDOR_XGI 0x18CA #define PCI_VENDOR_AST 0x1A03 #define PCI_VENDOR_3DLABS 0x3D3D -#define PCI_VENDOR_AVANCE_2 0x4005 -#define PCI_VENDOR_HERCULES 0x4843 #define PCI_VENDOR_S3 0x5333 #define PCI_VENDOR_INTEL 0x8086 #define PCI_VENDOR_ARK 0xEDD8 @@ -133,26 +120,37 @@ /* Real 3D */ #define PCI_CHIP_I740_PCI 0x00D1 -/* Compaq */ -#define PCI_CHIP_QV1280 0x3033 - /* ATI */ +#define PCI_CHIP_RV380_3150 0x3150 +#define PCI_CHIP_RV380_3151 0x3151 +#define PCI_CHIP_RV380_3152 0x3152 +#define PCI_CHIP_RV380_3153 0x3153 +#define PCI_CHIP_RV380_3154 0x3154 +#define PCI_CHIP_RV380_3156 0x3156 +#define PCI_CHIP_RV380_3E50 0x3E50 +#define PCI_CHIP_RV380_3E51 0x3E51 +#define PCI_CHIP_RV380_3E52 0x3E52 +#define PCI_CHIP_RV380_3E53 0x3E53 +#define PCI_CHIP_RV380_3E54 0x3E54 +#define PCI_CHIP_RV380_3E56 0x3E56 #define PCI_CHIP_RS100_4136 0x4136 #define PCI_CHIP_RS200_4137 0x4137 #define PCI_CHIP_R300_AD 0x4144 #define PCI_CHIP_R300_AE 0x4145 #define PCI_CHIP_R300_AF 0x4146 #define PCI_CHIP_R300_AG 0x4147 -#define PCI_CHIP_R350_AH 0x4148 -#define PCI_CHIP_R350_AI 0x4149 -#define PCI_CHIP_R350_AJ 0x414A -#define PCI_CHIP_R350_AK 0x414B -#define PCI_CHIP_RV350_AP 0x4150 -#define PCI_CHIP_RV350_AQ 0x4151 -#define PCI_CHIP_RV360_AR 0x4152 -#define PCI_CHIP_RV350_AS 0x4153 -#define PCI_CHIP_RV350_AT 0x4154 -#define PCI_CHIP_RV350_AV 0x4156 +#define PCI_CHIP_R350_AH 0x4148 +#define PCI_CHIP_R350_AI 0x4149 +#define PCI_CHIP_R350_AJ 0x414A +#define PCI_CHIP_R350_AK 0x414B +#define PCI_CHIP_RV350_AP 0x4150 +#define PCI_CHIP_RV350_AQ 0x4151 +#define PCI_CHIP_RV360_AR 0x4152 +#define PCI_CHIP_RV350_AS 0x4153 +#define PCI_CHIP_RV350_AT 0x4154 +#define PCI_CHIP_RV350_4155 0x4155 +#define PCI_CHIP_RV350_AV 0x4156 +#define PCI_CHIP_RV350_AW 0x4157 #define PCI_CHIP_MACH32 0x4158 #define PCI_CHIP_RS250_4237 0x4237 #define PCI_CHIP_R200_BB 0x4242 @@ -185,6 +183,20 @@ #define PCI_CHIP_RV250_Ie 0x4965 #define PCI_CHIP_RV250_If 0x4966 #define PCI_CHIP_RV250_Ig 0x4967 +#define PCI_CHIP_R420_JH 0x4A48 +#define PCI_CHIP_R420_JI 0x4A49 +#define PCI_CHIP_R420_JJ 0x4A4A +#define PCI_CHIP_R420_JK 0x4A4B +#define PCI_CHIP_R420_JL 0x4A4C +#define PCI_CHIP_R420_JM 0x4A4D +#define PCI_CHIP_R420_JN 0x4A4E +#define PCI_CHIP_R420_4A4F 0x4A4F +#define PCI_CHIP_R420_JP 0x4A50 +#define PCI_CHIP_R420_4A54 0x4A54 +#define PCI_CHIP_R481_4B49 0x4B49 +#define PCI_CHIP_R481_4B4A 0x4B4A +#define PCI_CHIP_R481_4B4B 0x4B4B +#define PCI_CHIP_R481_4B4C 0x4B4C #define PCI_CHIP_MACH64LB 0x4C42 #define PCI_CHIP_MACH64LD 0x4C44 #define PCI_CHIP_RAGE128LE 0x4C45 @@ -212,16 +224,16 @@ #define PCI_CHIP_R300_NE 0x4E45 #define PCI_CHIP_R300_NF 0x4E46 #define PCI_CHIP_R300_NG 0x4E47 -#define PCI_CHIP_R350_NH 0x4E48 -#define PCI_CHIP_R350_NI 0x4E49 -#define PCI_CHIP_R360_NJ 0x4E4A -#define PCI_CHIP_R350_NK 0x4E4B -#define PCI_CHIP_RV350_NP 0x4E50 -#define PCI_CHIP_RV350_NQ 0x4E51 -#define PCI_CHIP_RV350_NR 0x4E52 -#define PCI_CHIP_RV350_NS 0x4E53 -#define PCI_CHIP_RV350_NT 0x4E54 -#define PCI_CHIP_RV350_NV 0x4E56 +#define PCI_CHIP_R350_NH 0x4E48 +#define PCI_CHIP_R350_NI 0x4E49 +#define PCI_CHIP_R360_NJ 0x4E4A +#define PCI_CHIP_R350_NK 0x4E4B +#define PCI_CHIP_RV350_NP 0x4E50 +#define PCI_CHIP_RV350_NQ 0x4E51 +#define PCI_CHIP_RV350_NR 0x4E52 +#define PCI_CHIP_RV350_NS 0x4E53 +#define PCI_CHIP_RV350_NT 0x4E54 +#define PCI_CHIP_RV350_NV 0x4E56 #define PCI_CHIP_RAGE128PA 0x5041 #define PCI_CHIP_RAGE128PB 0x5042 #define PCI_CHIP_RAGE128PC 0x5043 @@ -262,6 +274,12 @@ #define PCI_CHIP_RV200_QX 0x5158 #define PCI_CHIP_RV100_QY 0x5159 #define PCI_CHIP_RV100_QZ 0x515A +#define PCI_CHIP_RN50_515E 0x515E +#define PCI_CHIP_R200_Qh 0x5168 +#define PCI_CHIP_R200_Qi 0x5169 +#define PCI_CHIP_R200_Qj 0x516A +#define PCI_CHIP_R200_Qk 0x516B +#define PCI_CHIP_R200_Ql 0x516C #define PCI_CHIP_RAGE128RE 0x5245 #define PCI_CHIP_RAGE128RF 0x5246 #define PCI_CHIP_RAGE128RG 0x5247 @@ -281,6 +299,31 @@ #define PCI_CHIP_RAGE128TS 0x5453 #define PCI_CHIP_RAGE128TT 0x5454 #define PCI_CHIP_RAGE128TU 0x5455 +#define PCI_CHIP_RV370_5460 0x5460 +#define PCI_CHIP_RV370_5461 0x5461 +#define PCI_CHIP_RV370_5462 0x5462 +#define PCI_CHIP_RV370_5463 0x5463 +#define PCI_CHIP_RV370_5464 0x5464 +#define PCI_CHIP_RV370_5465 0x5465 +#define PCI_CHIP_RV370_5466 0x5466 +#define PCI_CHIP_RV370_5467 0x5467 +#define PCI_CHIP_R423_UH 0x5548 +#define PCI_CHIP_R423_UI 0x5549 +#define PCI_CHIP_R423_UJ 0x554A +#define PCI_CHIP_R423_UK 0x554B +#define PCI_CHIP_R430_554C 0x554C +#define PCI_CHIP_R430_554D 0x554D +#define PCI_CHIP_R430_554E 0x554E +#define PCI_CHIP_R430_554F 0x554F +#define PCI_CHIP_R423_5550 0x5550 +#define PCI_CHIP_R423_UQ 0x5551 +#define PCI_CHIP_R423_UR 0x5552 +#define PCI_CHIP_R423_UT 0x5554 +#define PCI_CHIP_RV410_564A 0x564A +#define PCI_CHIP_RV410_564B 0x564B +#define PCI_CHIP_RV410_564F 0x564F +#define PCI_CHIP_RV410_5652 0x5652 +#define PCI_CHIP_RV410_5653 0x5653 #define PCI_CHIP_MACH64VT 0x5654 #define PCI_CHIP_MACH64VU 0x5655 #define PCI_CHIP_MACH64VV 0x5656 @@ -288,12 +331,48 @@ #define PCI_CHIP_RS300_5835 0x5835 #define PCI_CHIP_RS300_5836 0x5836 #define PCI_CHIP_RS300_5837 0x5837 +#define PCI_CHIP_RS480_5954 0x5954 +#define PCI_CHIP_RS480_5955 0x5955 #define PCI_CHIP_RV280_5960 0x5960 #define PCI_CHIP_RV280_5961 0x5961 #define PCI_CHIP_RV280_5962 0x5962 #define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV280_5965 0x5965 +#define PCI_CHIP_RN50_5969 0x5969 +#define PCI_CHIP_RS482_5974 0x5974 +#define PCI_CHIP_RS482_5975 0x5975 +#define PCI_CHIP_RS400_5A41 0x5A41 +#define PCI_CHIP_RS400_5A42 0x5A42 +#define PCI_CHIP_RC410_5A61 0x5A61 +#define PCI_CHIP_RC410_5A62 0x5A62 +#define PCI_CHIP_RV370_5B60 0x5B60 +#define PCI_CHIP_RV370_5B61 0x5B61 +#define PCI_CHIP_RV370_5B62 0x5B62 +#define PCI_CHIP_RV370_5B63 0x5B63 +#define PCI_CHIP_RV370_5B64 0x5B64 +#define PCI_CHIP_RV370_5B65 0x5B65 +#define PCI_CHIP_RV370_5B66 0x5B66 +#define PCI_CHIP_RV370_5B67 0x5B67 #define PCI_CHIP_RV280_5C61 0x5C61 #define PCI_CHIP_RV280_5C63 0x5C63 +#define PCI_CHIP_R430_5D48 0x5D48 +#define PCI_CHIP_R430_5D49 0x5D49 +#define PCI_CHIP_R430_5D4A 0x5D4A +#define PCI_CHIP_R480_5D4C 0x5D4C +#define PCI_CHIP_R480_5D4D 0x5D4D +#define PCI_CHIP_R480_5D4E 0x5D4E +#define PCI_CHIP_R480_5D4F 0x5D4F +#define PCI_CHIP_R480_5D50 0x5D50 +#define PCI_CHIP_R480_5D52 0x5D52 +#define PCI_CHIP_R423_5D57 0x5D57 +#define PCI_CHIP_RV410_5E48 0x5E48 +#define PCI_CHIP_RV410_5E4A 0x5E4A +#define PCI_CHIP_RV410_5E4B 0x5E4B +#define PCI_CHIP_RV410_5E4C 0x5E4C +#define PCI_CHIP_RV410_5E4D 0x5E4D +#define PCI_CHIP_RV410_5E4F 0x5E4F +#define PCI_CHIP_RS350_7834 0x7834 +#define PCI_CHIP_RS350_7835 0x7835 /* Avance Logic */ #define PCI_CHIP_ALG2064 0x2064 @@ -364,9 +443,6 @@ #define PCI_CHIP_9880 0x9880 #define PCI_CHIP_9910 0x9910 -/* ALI */ -#define PCI_CHIP_M1435 0x1435 - /* Matrox */ #define PCI_CHIP_MGA2085 0x0518 #define PCI_CHIP_MGA2064 0x0519 @@ -376,11 +452,10 @@ #define PCI_CHIP_MGAG200_PCI 0x0520 #define PCI_CHIP_MGAG200 0x0521 #define PCI_CHIP_MGAG400 0x0525 -#define PCI_CHIP_MGAG550 0x2527 #define PCI_CHIP_IMPRESSION 0x0D10 #define PCI_CHIP_MGAG100_PCI 0x1000 #define PCI_CHIP_MGAG100 0x1001 - +#define PCI_CHIP_MGAG550 0x2527 #define PCI_CARD_G400_TH 0x2179 #define PCI_CARD_MILL_G200_SD 0xFF00 #define PCI_CARD_PROD_G100_SD 0xFF01 @@ -389,21 +464,15 @@ #define PCI_CARD_MARV_G200_SD 0xFF04 /* Chips & Tech */ +#define PCI_CHIP_69000 0x00C0 #define PCI_CHIP_65545 0x00D8 #define PCI_CHIP_65548 0x00DC #define PCI_CHIP_65550 0x00E0 #define PCI_CHIP_65554 0x00E4 #define PCI_CHIP_65555 0x00E5 #define PCI_CHIP_68554 0x00F4 -#define PCI_CHIP_69000 0x00C0 #define PCI_CHIP_69030 0x0C30 -/* Miro */ -#define PCI_CHIP_ZR36050 0x5601 - -/* NEC */ -#define PCI_CHIP_POWER_VR 0x0046 - /* SiS */ #define PCI_CHIP_SG86C201 0x0001 #define PCI_CHIP_SG86C202 0x0002 @@ -414,25 +483,25 @@ #define PCI_CHIP_SG86C205 0x0205 #define PCI_CHIP_SG86C215 0x0215 #define PCI_CHIP_SG86C225 0x0225 +#define PCI_CHIP_SIS300 0x0300 +#define PCI_CHIP_SIS315H 0x0310 +#define PCI_CHIP_SIS315PRO 0x0325 +#define PCI_CHIP_SIS330 0x0330 #define PCI_CHIP_85C501 0x0406 #define PCI_CHIP_85C496 0x0496 #define PCI_CHIP_85C601 0x0601 #define PCI_CHIP_85C5107 0x5107 +#define PCI_CHIP_SIS540 0x5300 +#define PCI_CHIP_SIS550 0x5315 #define PCI_CHIP_85C5511 0x5511 #define PCI_CHIP_85C5513 0x5513 #define PCI_CHIP_SIS5571 0x5571 #define PCI_CHIP_SIS5597_2 0x5597 +#define PCI_CHIP_SIS630 0x6300 #define PCI_CHIP_SIS530 0x6306 +#define PCI_CHIP_SIS650 0x6325 #define PCI_CHIP_SIS6326 0x6326 #define PCI_CHIP_SIS7001 0x7001 -#define PCI_CHIP_SIS300 0x0300 -#define PCI_CHIP_SIS315H 0x0310 -#define PCI_CHIP_SIS315PRO 0x0325 -#define PCI_CHIP_SIS330 0x0330 -#define PCI_CHIP_SIS630 0x6300 -#define PCI_CHIP_SIS540 0x5300 -#define PCI_CHIP_SIS550 0x5315 -#define PCI_CHIP_SIS650 0x6325 #define PCI_CHIP_SIS730 0x7300 /* Hewlett-Packard */ @@ -472,10 +541,6 @@ #define PCI_CHIP_HUMMINGBIRD 0xA001 #define PCI_CHIP_TOMATILLO 0xA801 -/* BrookTree */ -#define PCI_CHIP_BT848 0x0350 -#define PCI_CHIP_BT849 0x0351 - /* NVIDIA */ #define PCI_CHIP_NV1 0x0008 #define PCI_CHIP_DAC64 0x0009 @@ -538,7 +603,6 @@ #define PCI_CHIP_BANSHEE 0x0003 #define PCI_CHIP_VOODOO3 0x0005 #define PCI_CHIP_VOODOO5 0x0009 - #define PCI_CARD_VOODOO3_2000 0x0036 #define PCI_CARD_VOODOO3_3000 0x003A @@ -578,17 +642,17 @@ #define PCI_CHIP_TRIO64V2_DXGX 0x8901 #define PCI_CHIP_PLATO_PX 0x8902 #define PCI_CHIP_Trio3D 0x8904 -#define PCI_CHIP_Trio3D_2X 0x8A13 #define PCI_CHIP_VIRGE_DXGX 0x8A01 #define PCI_CHIP_VIRGE_GX2 0x8A10 +#define PCI_CHIP_Trio3D_2X 0x8A13 #define PCI_CHIP_SAVAGE3D 0x8A20 #define PCI_CHIP_SAVAGE3D_MV 0x8A21 #define PCI_CHIP_SAVAGE4 0x8A22 +#define PCI_CHIP_PROSAVAGE_PM 0x8A25 +#define PCI_CHIP_PROSAVAGE_KM 0x8A26 #define PCI_CHIP_VIRGE_MX 0x8C01 #define PCI_CHIP_VIRGE_MXPLUS 0x8C01 #define PCI_CHIP_VIRGE_MXP 0x8C03 -#define PCI_CHIP_PROSAVAGE_PM 0x8A25 -#define PCI_CHIP_PROSAVAGE_KM 0x8A26 #define PCI_CHIP_SAVAGE_MX_MV 0x8C10 #define PCI_CHIP_SAVAGE_MX 0x8C11 #define PCI_CHIP_SAVAGE_IX_MV 0x8C12 @@ -601,19 +665,16 @@ #define PCI_CHIP_2000MT 0xA0A1 #define PCI_CHIP_2000MI 0xA0A9 -/* Tritech Microelectronics */ -#define PCI_CHIP_TR25202 0xFC02 - /* Neomagic */ #define PCI_CHIP_NM2070 0x0001 #define PCI_CHIP_NM2090 0x0002 #define PCI_CHIP_NM2093 0x0003 -#define PCI_CHIP_NM2097 0x0083 #define PCI_CHIP_NM2160 0x0004 #define PCI_CHIP_NM2200 0x0005 #define PCI_CHIP_NM2230 0x0025 #define PCI_CHIP_NM2360 0x0006 #define PCI_CHIP_NM2380 0x0016 +#define PCI_CHIP_NM2097 0x0083 /* Intel */ #define PCI_CHIP_I815_BRIDGE 0x1130 Index: xc/programs/Xserver/hw/xfree86/common/xf86Resources.h diff -u xc/programs/Xserver/hw/xfree86/common/xf86Resources.h:1.17 xc/programs/Xserver/hw/xfree86/common/xf86Resources.h:1.19 --- xc/programs/Xserver/hw/xfree86/common/xf86Resources.h:1.17 Thu Jun 2 20:18:31 2005 +++ xc/programs/Xserver/hw/xfree86/common/xf86Resources.h Thu Apr 24 13:54:54 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Resources.h,v 1.17 2005/06/03 03:18:31 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86Resources.h,v 1.19 2008/04/24 20:54:54 tsi Exp $ */ /* * Copyright (c) 1999-2002 by The XFree86 Project, Inc. @@ -154,9 +154,9 @@ #define RES_SHARED_8514 res8514Shared #define _PCI_AVOID_PC_STYLE \ - {ResExcIoSparse | ResBus, 0x0100, 0xFFFF0300}, \ - {ResExcIoSparse | ResBus, 0x0200, 0xFFFF0200}, \ - {ResExcMemBlock | ResBus, 0xA0000, 0x000FFFFF} + {ResExcIoSparse | ResBus, 0x00000100, (int)0xFFFF0300}, \ + {ResExcIoSparse | ResBus, 0x00000200, (int)0xFFFF0200}, \ + {ResExcMemBlock | ResBus, 0x00000000, 0x000FFFFF} extern resRange PciAvoid[]; Index: xc/programs/Xserver/hw/xfree86/common/xf86pciBus.c diff -u xc/programs/Xserver/hw/xfree86/common/xf86pciBus.c:3.92 xc/programs/Xserver/hw/xfree86/common/xf86pciBus.c:3.96 --- xc/programs/Xserver/hw/xfree86/common/xf86pciBus.c:3.92 Thu Feb 15 11:31:49 2007 +++ xc/programs/Xserver/hw/xfree86/common/xf86pciBus.c Thu May 1 10:11:34 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86pciBus.c,v 3.92 2007/02/15 19:31:49 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86pciBus.c,v 3.96 2008/05/01 17:11:34 tsi Exp $ */ /* * Copyright (c) 1997-2007 by The XFree86 Project, Inc. * All rights reserved. @@ -186,20 +186,6 @@ sprintf(buffer, "%d@%d", busnum & 0x00ff, busnum >> 8); } -static Bool -IsBaseUnassigned(CARD32 base) -{ - CARD32 mask; - - if (base & PCI_MAP_IO) - mask = ~PCI_MAP_IO_ATTR_MASK; - else - mask = ~PCI_MAP_MEMORY_ATTR_MASK; - - base &= mask; - return (!base || (base == mask)); -} - static void FindPCIVideoInfo(void) { @@ -301,21 +287,6 @@ info->type[j] = 0; } - if (PCINONSYSTEMCLASSES(baseclass, subclass)) { - if (info->size[0] && IsBaseUnassigned(pcrp->pci_base0)) - pcrp->pci_base0 = pciCheckForBrokenBase(pcrp->tag, 0); - if (info->size[1] && IsBaseUnassigned(pcrp->pci_base1)) - pcrp->pci_base1 = pciCheckForBrokenBase(pcrp->tag, 1); - if (info->size[2] && IsBaseUnassigned(pcrp->pci_base2)) - pcrp->pci_base2 = pciCheckForBrokenBase(pcrp->tag, 2); - if (info->size[3] && IsBaseUnassigned(pcrp->pci_base3)) - pcrp->pci_base3 = pciCheckForBrokenBase(pcrp->tag, 3); - if (info->size[4] && IsBaseUnassigned(pcrp->pci_base4)) - pcrp->pci_base4 = pciCheckForBrokenBase(pcrp->tag, 4); - if (info->size[5] && IsBaseUnassigned(pcrp->pci_base5)) - pcrp->pci_base5 = pciCheckForBrokenBase(pcrp->tag, 5); - } - /* * 64-bit base addresses are checked for and avoided on 32-bit * platforms. @@ -464,19 +435,20 @@ fixPciSizeInfo(int entityIndex) { pciVideoPtr pvp; + pciConfigPtr pcp; resPtr pAcc; PCITAG tag; int j; if (! (pvp = xf86GetPciInfoForEntity(entityIndex))) return; - - tag = pciTag(pvp->bus,pvp->device,pvp->func); + pcp = pvp->thisCard; + tag = pcp->tag; for (j = 0; j < 6; j++) { if (pvp->validSize & (2 << j)) continue; pAcc = Acc; - if (pvp->memBase[j]) + if (!PCI_MAP_IS_IO((&pcp->pci_base0)[j])) { while (pAcc) { if (((pAcc->res_type & (ResPhysMask | ResBlock)) == (ResMem | ResBlock)) @@ -485,7 +457,7 @@ + SIZE(pvp->size[j])))) break; pAcc = pAcc->next; } - else if (pvp->ioBase[j]) + } else { while (pAcc) { if (((pAcc->res_type & (ResPhysMask | ResBlock)) == (ResIo | ResBlock)) @@ -494,7 +466,7 @@ + SIZE(pvp->size[j])))) break; pAcc = pAcc->next; } - else continue; + } pvp->size[j] = pciGetBaseSize(pvp->thisCard, j, TRUE, &pvp->validSize); if (pAcc) { pAcc->block_end = pvp->memBase[j] ? @@ -504,7 +476,7 @@ pAcc->res_type |= ResBios; } } - if (pvp->biosBase && !(pvp->validSize & (2 << 6))) { + if (!(pvp->validSize & (2 << 6))) { pAcc = Acc; while (pAcc) { if (((pAcc->res_type & (ResPhysMask | ResBlock)) == @@ -850,9 +822,9 @@ for (i = 0; i < 6; i++) { if (pvp->size[i] == old_bits) { - if ((((type & ResPhysMask) == ResIo) && pvp->ioBase[i] + if ((((type & ResPhysMask) == ResIo) && (B2I(TAG(pvp),pvp->ioBase[i]) == base)) || - (((type & ResPhysMask) == ResMem) && pvp->memBase[i] + (((type & ResPhysMask) == ResMem) && (B2M(TAG(pvp),pvp->memBase[i]) == base))) { pvp->size[i] = new_bits; break; /* to next device */ @@ -1250,14 +1222,14 @@ pciConfigPtr pcp; resPtr tmp; - if (!pvp) return FALSE; - tag = pciTag(pvp->bus,pvp->device,pvp->func); + if (!pvp || (pvp->size[prt] <= 0)) return FALSE; pcp = pvp->thisCard; + tag = pcp->tag; type &= ResAccMask; if (!type) type = ResShared; if (prt < 6) { - if (pvp->memBase[prt]) { + if (!PCI_MAP_IS_IO((&pcp->pci_base0)[prt])) { type |= ResMem; res_n = prt; p_base = &(pvp->memBase[res_n]); @@ -1267,7 +1239,7 @@ PCI_M_RANGE(range,tag,0,0xffffffff,ResExcMemBlock); resSize = xf86AddResToList(resSize,&range,-1); } - } else if (pvp->ioBase[prt]){ + } else { type |= ResIo; res_n = prt; p_base = &(pvp->ioBase[res_n]); @@ -1275,7 +1247,7 @@ p_type = pvp->type[res_n]; PCI_I_RANGE(range, tag, 0, 0xffffffff, ResExcIoBlock); resSize = xf86AddResToList(resSize, &range, -1); - } else return FALSE; + } } else if (prt == 6) { type |= ResMem; res_n = 0xff; /* special flag for bios rom */ @@ -1287,8 +1259,6 @@ resSize = xf86AddResToList(resSize,&range,-1); } else return FALSE; - if (! *p_base) return FALSE; - type |= (range.type & ResDomain) | ResBlock; /* setup avoid: PciAvoid is bus range: convert later */ @@ -1526,7 +1496,10 @@ } /* @@@ fake BIOS allocated resource */ range.type |= ResBios; - Acc = xf86AddResToList(Acc, &range,-1); + w = xf86AddResToList(NULL, &range, -1); + xf86MsgVerb(X_INFO, 3, "Resource relocated to:\n"); + xf86PrintResList(3, w); + Acc = xf86JoinResLists(w, Acc); return TRUE; @@ -2560,11 +2533,14 @@ m = n; while ((pvp1 = xf86PciVideoInfo[m++])) { if (!pvp1->validate) continue; + pcrp = pvp1->thisCard; + basep = &pcrp->pci_base0; for (i = 0; i<6; i++) { - if (pvp1->ioBase[i]) { + if (pvp1->size[i] <= 0) continue; + if (PCI_MAP_IS_IO(basep[i])) { PV_I_RANGE(range,pvp1,i,ResExcIoBlock); NonSys = xf86AddResToList(NonSys,&range,-1); - } else if (pvp1->memBase[i]) { + } else { PV_M_RANGE(range,pvp1,i,ResExcMemBlock); NonSys = xf86AddResToList(NonSys,&range,-1); } @@ -2625,14 +2601,20 @@ xf86MsgVerb(X_INFO, 3,"MEM/IO:\n"); xf86PrintResList(3,res_m_io); #endif + pcrp = pvp->thisCard; + basep = &pcrp->pci_base0; for (i = 0; i < 6; i++) { int j; - resPtr own = NULL; + resPtr own; + + if (pvp->size[i] <= 0) continue; + own = NULL; for (j = i+1; j < 6; j++) { - if (pvp->ioBase[j]) { + if (pvp->size[j] <= 0) continue; + if (PCI_MAP_IS_IO(basep[j])) { PV_I_RANGE(range,pvp,j,ResExcIoBlock); own = xf86AddResToList(own,&range,-1); - } else if (pvp->memBase[j]) { + } else { PV_M_RANGE(range,pvp,j,ResExcMemBlock); own = xf86AddResToList(own,&range,-1); } @@ -2641,7 +2623,7 @@ xf86MsgVerb(X_INFO, 3, "own:\n"); xf86PrintResList(3, own); #endif - if (pvp->ioBase[i]) { + if (PCI_MAP_IS_IO(basep[i])) { PV_I_RANGE(range,pvp,i,ResExcIoBlock); if (xf86IsSubsetOf(range,res_m_io) && ! ChkConflict(&range,own,SETUP) @@ -2657,7 +2639,7 @@ sleep(2); #endif fixPciResource(i, 0, pvp, range.type); - } else if (pvp->memBase[i]) { + } else { PV_M_RANGE(range,pvp,i,ResExcMemBlock); if (pvp->type[i] & PCI_MAP_MEMORY_CACHABLE) { if (xf86IsSubsetOf(range,res_mp) @@ -2678,19 +2660,6 @@ xf86MsgVerb(X_WARNING, 0, "****INVALID MEM ALLOCATION**** b: 0x%lx e: 0x%lx " "correcting\a\n", range.rBegin,range.rEnd); - if (ChkConflict(&range,own,SETUP)) { - xf86MsgVerb(X_INFO,3,"own\n"); - xf86PrintResList(3,own); - } - if (ChkConflict(&range,avoid,SETUP)) { - xf86MsgVerb(X_INFO,3,"avoid\n"); - xf86PrintResList(3,avoid); - } - if (ChkConflict(&range,NonSys,SETUP)) { - xf86MsgVerb(X_INFO,3,"NonSys\n"); - xf86PrintResList(3,NonSys); - } - #ifdef DEBUG sleep(2); #endif @@ -3265,7 +3234,7 @@ * At this point the adapter's compliance with PCI enablement/disablement * cannot be safely determined. */ - *pActivate = TRUE; + *pActivate = CAN_HARDFAIL_MASTER_ABORTS; return TRUE; } @@ -3488,7 +3457,7 @@ * Notify caller that probing the requested resources might generate * hard-failed master aborts. */ - *pUnRouted = TRUE; + *pUnRouted = CAN_HARDFAIL_MASTER_ABORTS; return TRUE; } @@ -3512,7 +3481,7 @@ return TRUE; } - return FALSE; + return !CAN_HARDFAIL_MASTER_ABORTS; } /* Index: xc/programs/Xserver/hw/xfree86/common/xf86sbusBus.c diff -u xc/programs/Xserver/hw/xfree86/common/xf86sbusBus.c:3.14 xc/programs/Xserver/hw/xfree86/common/xf86sbusBus.c:3.15 --- xc/programs/Xserver/hw/xfree86/common/xf86sbusBus.c:3.14 Thu Mar 15 07:38:36 2007 +++ xc/programs/Xserver/hw/xfree86/common/xf86sbusBus.c Thu Apr 24 12:29:34 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86sbusBus.c,v 3.15 2008/04/24 19:29:34 tsi Exp $ */ /* * SBUS bus-specific code. * @@ -20,7 +21,6 @@ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86sbusBus.c,v 3.14 2007/03/15 14:38:36 tsi Exp $ */ #include #include @@ -989,7 +989,7 @@ fbcursor.pos.x = x; fbcursor.pos.y = y; fbcursor.set = FB_CUR_SETPOS; - ioctl(psdp->fd, FBIOSCURSOR, &fbcursor); + ioctl(psdp->fd, FBIOSCURPOS, &fbcursor); } /* Set HW cursor hot spot */ Index: xc/programs/Xserver/hw/xfree86/doc/BUILD diff -u xc/programs/Xserver/hw/xfree86/doc/BUILD:3.36 xc/programs/Xserver/hw/xfree86/doc/BUILD:3.37 --- xc/programs/Xserver/hw/xfree86/doc/BUILD:3.36 Fri Aug 3 19:16:06 2007 +++ xc/programs/Xserver/hw/xfree86/doc/BUILD Sat Nov 22 14:57:25 2008 @@ -17,69 +17,69 @@ We recommend using gcc to build XFree86, but XFree86 generally builds with the native compiler for each OS platform. -1. How to get the XFree86 4.7.0 source +1. How to get the XFree86 4.8.0 source -The recommended way of getting the XFree86 4.7.0 source is to obtain it +The recommended way of getting the XFree86 4.8.0 source is to obtain it directly from the XFree86 CVS repository. There are several ways of doing that, and they are described at our CVS web page . -The CVS tag for this release is "xf-4_7_0". The tag for the maintenance -branch for this release is "xf-4_7-branch". +The CVS tag for this release is "xf-4_8_0". The tag for the maintenance +branch for this release is "xf-4_8-branch". -Another method of getting the XFree86 4.7.0 source is to either download the -4.7.0 source tarballs from the XFree86 ftp site. The procedure for this is +Another method of getting the XFree86 4.8.0 source is to either download the +4.8.0 source tarballs from the XFree86 ftp site. The procedure for this is as follows: - o The XFree86 4.7.0 source is contained in the files: + o The XFree86 4.8.0 source is contained in the files: - XFree86-4.7.0-src-1.tgz + XFree86-4.8.0-src-1.tgz - XFree86-4.7.0-src-2.tgz + XFree86-4.8.0-src-2.tgz - XFree86-4.7.0-src-3.tgz + XFree86-4.8.0-src-3.tgz - XFree86-4.7.0-src-4.tgz + XFree86-4.8.0-src-4.tgz - XFree86-4.7.0-src-5.tgz + XFree86-4.8.0-src-5.tgz - XFree86-4.7.0-src-6.tgz + XFree86-4.8.0-src-6.tgz - XFree86-4.7.0-src-7.tgz + XFree86-4.8.0-src-7.tgz - These can be found at ftp://ftp.xfree86.org/pub/XFree86/4.7.0/source/. - XFree86-4.7.0-src-4.tgz and XFree86-4.7.0-src-5.tgz contains the fonts. - XFree86-4.7.0-src-6.tgz contains the documentation source. - XFree86-4.7.0-src-7.tgz contains the hardcopy documentation. - XFree86-4.7.0-src-1.tgz, XFree86-4.7.0-src-2.tgz and - XFree86-4.7.0-src-3.tgz contains everything else. + These can be found at ftp://ftp.xfree86.org/pub/XFree86/4.8.0/source/. + XFree86-4.8.0-src-4.tgz and XFree86-4.8.0-src-5.tgz contains the fonts. + XFree86-4.8.0-src-6.tgz contains the documentation source. + XFree86-4.8.0-src-7.tgz contains the hardcopy documentation. + XFree86-4.8.0-src-1.tgz, XFree86-4.8.0-src-2.tgz and + XFree86-4.8.0-src-3.tgz contains everything else. If you do not need either the documentation or the fonts, then you need - only XFree86-4.7.0-src-1.tgz, XFree86-4.7.0-src-2.tgz and - XFree86-4.7.0-src-3.tgz. + only XFree86-4.8.0-src-1.tgz, XFree86-4.8.0-src-2.tgz and + XFree86-4.8.0-src-3.tgz. o Extract each of these files by running the following from a directory on a filesystem containing enough space (the full source requires around 270MB, with a similar amount being required for the compiled binaries): - gzip -d < XFree86-4.7.0-src-1.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-1.tgz | tar vxf - - gzip -d < XFree86-4.7.0-src-2.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-2.tgz | tar vxf - - gzip -d < XFree86-4.7.0-src-3.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-3.tgz | tar vxf - - gzip -d < XFree86-4.7.0-src-4.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-4.tgz | tar vxf - - gzip -d < XFree86-4.7.0-src-5.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-5.tgz | tar vxf - - gzip -d < XFree86-4.7.0-src-6.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-6.tgz | tar vxf - - gzip -d < XFree86-4.7.0-src-7.tgz | tar vxf - + gzip -d < XFree86-4.8.0-src-7.tgz | tar vxf - -Alternatively, if you already have a pristine copy of the XFree86 4.6.0 +Alternatively, if you already have a pristine copy of the XFree86 4.7.0 source, you can download patches from -ftp://ftp.xfree86.org/pub/XFree86/4.7.0/patches/ that will allow you to con- -vert it to 4.7.0. Information about which patch files to download and how to +ftp://ftp.xfree86.org/pub/XFree86/4.8.0/patches/ that will allow you to con- +vert it to 4.8.0. Information about which patch files to download and how to apply them can be found in the "How to get XFree86" section of the README for this release. @@ -102,8 +102,8 @@ sarily. Before making too many modifications, check the configuration param- eters specified in the xc/config/cf/README file. -If you are using just the XFree86-4.7.0-src-1.tgz, XFree86-4.7.0-src-2.tgz -and XFree86-4.7.0-src-3.tgz parts of the source dist, you will need to define +If you are using just the XFree86-4.8.0-src-1.tgz, XFree86-4.8.0-src-2.tgz +and XFree86-4.8.0-src-3.tgz parts of the source dist, you will need to define BuildFonts to NO. 3. Using a shadow directory of symbolic links for the build @@ -284,4 +284,4 @@ Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/BUILD.sgml,v 3.20 dawes Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/BUILD,v 3.36 2007/08/04 02:16:06 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/BUILD,v 3.37 2008/11/22 22:57:25 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/Install diff -u xc/programs/Xserver/hw/xfree86/doc/Install:1.40 xc/programs/Xserver/hw/xfree86/doc/Install:1.42 --- xc/programs/Xserver/hw/xfree86/doc/Install:1.40 Fri Aug 3 19:16:07 2007 +++ xc/programs/Xserver/hw/xfree86/doc/Install Sat Nov 22 14:57:25 2008 @@ -1,8 +1,8 @@ - Installation Details for XFree86® 4.7.0 + Installation Details for XFree86® 4.8.0 The XFree86 Project, Inc - 2 February 2005 + 12 August 2007 Abstract @@ -22,11 +22,11 @@ XFree86 CVS repository's "utils" module, and from our ftp site .) -2. Downloading the XFree86 4.7.0 binaries +2. Downloading the XFree86 4.8.0 binaries -We provide XFree86 4.7.0 binaries for a range of operating systems at our ftp -site and our web site -. Often during +We provide XFree86 4.8.0 binaries for a range of operating systems at our ftp +site and our web site +. Often during releases our site is heavily loaded. Instead of downloading directly from us we recommend that instead you use one of our mirror sites. @@ -71,9 +71,9 @@ that your target will not be be available for this release. This is likeliest possibility if you are looking more than about two weeks after the release date. Check here - for information about + for information about updates to our binary distributions, and here - for errata related to + for errata related to this release. Assuming that you have run the Xinstall.sh script and found the binary dis- @@ -138,9 +138,9 @@ If you miss some and want to install them later, go to the Manual Installa- tion (section 4., page 1) section. -3. Installing XFree86 4.7.0 using the Xinstall.sh script +3. Installing XFree86 4.8.0 using the Xinstall.sh script -We strongly recommend that our XFree86 4.7.0 binaries be installed using the +We strongly recommend that our XFree86 4.8.0 binaries be installed using the Xinstall.sh script we provide. There are a lot of steps in the manual installation process, and those steps can vary according to the platform and hardware setup. There is a description of the manual installation process @@ -284,9 +284,9 @@ After the X server configuration is done, it may be advisable to reboot, especially if you run xdm (or equivalent) or the font server (xfs). -4. Installing XFree86 4.7.0 manually +4. Installing XFree86 4.8.0 manually -This section contains information about manually installing the XFree86 4.7.0 +This section contains information about manually installing the XFree86 4.8.0 binary distributions. You should only use this method if you know what you're doing. The information here covers some common cases, but not every possible case. It also may not be complete or up to date. Use at your own @@ -393,7 +393,7 @@ /sbin/ldconfig -m /usr/X11R6/lib # For FreeBSD, NetBSD, OpenBSD /usr/X11R6/bin/mkfontdir /usr/X11R6/lib/X11/fonts/misc - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Install.sgml,v 1.22 dawes Exp $ + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Install.sgml,v 1.23 tsi Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/Install,v 1.40 2007/08/04 02:16:07 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/Install,v 1.42 2008/11/22 22:57:25 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/LICENSE diff -u xc/programs/Xserver/hw/xfree86/doc/LICENSE:1.52 xc/programs/Xserver/hw/xfree86/doc/LICENSE:1.54 --- xc/programs/Xserver/hw/xfree86/doc/LICENSE:1.52 Fri Aug 3 19:16:07 2007 +++ xc/programs/Xserver/hw/xfree86/doc/LICENSE Sat Nov 22 14:57:25 2008 @@ -49,14 +49,14 @@ 3.1 Open Source -We believe that all of the code in this release (4.7.0) of XFree86 meet the +We believe that all of the code in this release (4.8.0) of XFree86 meet the requirements of the Open Source Definition , as maintained by the Open Source Initiative (OSI) . 3.2 Free Software -We believe that most of the code in this release (4.7.0) of XFree86 meets the +We believe that most of the code in this release (4.8.0) of XFree86 meets the requirements of the Free Software definition as defined by the Free Software Foundation (FSF) . @@ -188,7 +188,7 @@ Copyright (C) 1999-2003 by Peter Kunzmann, Citron GmbH, Germany. -Copyright (C) 1994 through 2007 by Marc Aurele La France (TSI @ UQV), +Copyright (C) 1994 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org Copyright (C) 1996 by Steven Lang @@ -1631,7 +1631,7 @@ authorization from the Gnome Foundation or Bitstream Inc., respectively. For further information, contact: fonts at gnome dot org. - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LICENSE.sgml,v 1.45 tsi Exp $ + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LICENSE.sgml,v 1.46 tsi Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/LICENSE,v 1.52 2007/08/04 02:16:07 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/LICENSE,v 1.54 2008/11/22 22:57:25 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/README diff -u xc/programs/Xserver/hw/xfree86/doc/README:3.153 xc/programs/Xserver/hw/xfree86/doc/README:3.155 --- xc/programs/Xserver/hw/xfree86/doc/README:3.153 Fri Aug 3 19:16:07 2007 +++ xc/programs/Xserver/hw/xfree86/doc/README Sat Nov 22 14:57:25 2008 @@ -1,8 +1,8 @@ - README for XFree86® 4.7.0 + README for XFree86® 4.8.0 The XFree86 Project, Inc - April 2006 + August 2007 Abstract @@ -11,20 +11,20 @@ Linux, FreeBSD, NetBSD, OpenBSD and Solaris) on Intel and other platforms. This version is compatible with X11R6.6. -1. What is XFree86 4.7.0? +1. What is XFree86 4.8.0? -XFree86 4.7.0 is the tenth full release in the XFree86 4.x series. +XFree86 4.8.0 is the eleventh full release in the XFree86 4.x series. XFree86 4.x is the current XFree86 release series. The first release in this series was in early 2000. The core of XFree86 4.x is a modular X server. -The 4.7.0 version is a new release that includes additional hardware support, +The 4.8.0 version is a new release that includes additional hardware support, functional enhancements and bug fixes. Specific release enhancements can be viewed in the Release Notes. -Most modern PC video hardware is supported in XFree86 4.7.0, and most PC +Most modern PC video hardware is supported in XFree86 4.8.0, and most PC video hardware that isn't supported explicitly can be used with the "vesa" driver. The Release Notes has a table showing the drivers provided with -XFree86 4.7.0, and links to related documentation. +XFree86 4.8.0, and links to related documentation. XFree86® is produced by The XFree86 Project, Inc through the work of a group of volunteer independent developers. The XFree86 Project is a non-commercial @@ -61,7 +61,7 @@ 3. Pointers to additional information The documentation for this release can be found online at the XFree86 web -site . Documentation for the latest +site . Documentation for the latest release version can always be found here , and documentation for the latest pre-release snapshot can be found here . @@ -116,23 +116,23 @@ Current information about the XFree86 development process can be found at our web site . -6. How to get XFree86 4.7.0 +6. How to get XFree86 4.8.0 -XFree86 4.7.0 can be found at the XFree86 ftp server -. Information about obtaining +XFree86 4.8.0 can be found at the XFree86 ftp server +. Information about obtaining and installing binary distributions of this release can be found in the Installation Document. Information about obtaining the release in source form is given below. -The source for version 4.7.0 is split into seven tarballs: +The source for version 4.8.0 is split into seven tarballs: - XFree86-4.7.0-src-1.tgz - XFree86-4.7.0-src-2.tgz - XFree86-4.7.0-src-3.tgz - XFree86-4.7.0-src-4.tgz - XFree86-4.7.0-src-5.tgz - XFree86-4.7.0-src-6.tgz - XFree86-4.7.0-src-7.tgz + XFree86-4.8.0-src-1.tgz + XFree86-4.8.0-src-2.tgz + XFree86-4.8.0-src-3.tgz + XFree86-4.8.0-src-4.tgz + XFree86-4.8.0-src-5.tgz + XFree86-4.8.0-src-6.tgz + XFree86-4.8.0-src-7.tgz The first three contain everything except the fonts and general X11 documen- tation. Those three are sufficient for building XFree86 if you already have @@ -140,36 +140,36 @@ the source for the general X11 documentation. The seventh contains the gen- eral X11 documentation in hardcopy format. -A source patch relative to version 4.6.0 is also available. Because of its +A source patch relative to version 4.7.0 is also available. Because of its size, it is split into four parts. The patch files are: - XFree86-4.6.0-4.7.0.diff1.gz - XFree86-4.6.0-4.7.0.diff2.gz - XFree86-4.6.0-4.7.0.diff3.gz - XFree86-4.6.0-4.7.0.diff4.gz + XFree86-4.7.0-4.8.0.diff1.gz + XFree86-4.7.0-4.8.0.diff2.gz + XFree86-4.7.0-4.8.0.diff3.gz + XFree86-4.7.0-4.8.0.diff4.gz There is also a tarball and a cleanup script that handle files that have com- ponents that can't be included in a diff. These are: - XFree86-4.6.0-4.7.0-diff0.tgz - XFree86-4.6.0-4.7.0-cleanup.sh + XFree86-4.7.0-4.8.0-diff0.tgz + XFree86-4.7.0-4.8.0-cleanup.sh -These patches should be applied to a clean 4.6.0 source tree, working from +These patches should be applied to a clean 4.7.0 source tree, working from the directory containing the xc/ directory. The patches should be applied by running: - gzip -d < XFree86-4.6.0-4.7.0.diff1.gz | patch -p0 -E - gzip -d < XFree86-4.6.0-4.7.0.diff2.gz | patch -p0 -E - gzip -d < XFree86-4.6.0-4.7.0.diff3.gz | patch -p0 -E - gzip -d < XFree86-4.6.0-4.7.0.diff4.gz | patch -p0 -E + gzip -d < XFree86-4.7.0-4.8.0.diff1.gz | patch -p0 -E + gzip -d < XFree86-4.7.0-4.8.0.diff2.gz | patch -p0 -E + gzip -d < XFree86-4.7.0-4.8.0.diff3.gz | patch -p0 -E + gzip -d < XFree86-4.7.0-4.8.0.diff4.gz | patch -p0 -E - sh XFree86-4.6.0-4.7.0-cleanup.sh - gzip -d < XFree86-4.6.0-4.7.0-diff0.tgz | tar vxf - + sh XFree86-4.7.0-4.8.0-cleanup.sh + gzip -d < XFree86-4.7.0-4.8.0-diff0.tgz | tar vxf - To format the XFree86 documentation use the latest version of our doctools package available from the XFree86 CVS repository's "doctools" module, and from our ftp site . +tools-1.3.5.tgz>. The XFree86 source code for this and all releases/snapshots as well as devel- opment versions can also be accessed via the XFree86 CVS repository. Infor- @@ -177,8 +177,8 @@ on our web site. It's also possible to browse the XFree86 CVS repository at our CVSWeb server . The CVS tag for this version is -"xf-4_7_0". The CVS tag for the stable branch for this release is -"xf-4_7-branch". To check out the latest development version, don't specify +"xf-4_8_0". The CVS tag for the stable branch for this release is +"xf-4_8-branch". To check out the latest development version, don't specify any tag. 7. Reporting Bugs @@ -203,4 +203,4 @@ Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml,v 3.149 dawes Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/README,v 3.153 2007/08/04 02:16:07 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/README,v 3.155 2008/11/22 22:57:25 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/README.DECtga diff -u xc/programs/Xserver/hw/xfree86/doc/README.DECtga:3.38 xc/programs/Xserver/hw/xfree86/doc/README.DECtga:3.39 --- xc/programs/Xserver/hw/xfree86/doc/README.DECtga:3.38 Fri Aug 3 19:16:07 2007 +++ xc/programs/Xserver/hw/xfree86/doc/README.DECtga Sat Nov 22 14:57:26 2008 @@ -6,7 +6,7 @@ 1. DEC 21030 - o The DEC 21030 is supported by XFree86 4.7.0. The driver is now par- + o The DEC 21030 is supported by XFree86 4.8.0. The driver is now par- tially accelerated. The built-in graphics on the Multia is supported in 8-plane mode, and PCI cards with 8 or 16 MB framebuffers are supported in 24-plane mode. TGA2 (aka PowerStorm 3D30/4D20) cards are not cur- @@ -65,4 +65,4 @@ Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/DECtga.sgml,v 3.9 dawes Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.DECtga,v 3.38 2007/08/04 02:16:07 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.DECtga,v 3.39 2008/11/22 22:57:26 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/README.Darwin diff -u xc/programs/Xserver/hw/xfree86/doc/README.Darwin:1.28 xc/programs/Xserver/hw/xfree86/doc/README.Darwin:1.29 --- xc/programs/Xserver/hw/xfree86/doc/README.Darwin:1.28 Fri Aug 3 19:16:07 2007 +++ xc/programs/Xserver/hw/xfree86/doc/README.Darwin Sat Nov 22 14:57:26 2008 @@ -66,7 +66,7 @@ If you don't feel the need to live on the cutting edge, you can save some time and effort by using the precompiled binaries available on the XFree86 -FTP server at . Fol- +FTP server at . Fol- low the instructions in the Install document to install it. This will create three new directory trees, /usr/X11R6, /etc/X11 and /etc/fonts. On Mac OS X the Xquartz.tgz tarball is required in addition to the other tarballs @@ -211,4 +211,4 @@ Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Darwin.sgml,v 1.11 dawes Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.Darwin,v 1.28 2007/08/04 02:16:07 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.Darwin,v 1.29 2008/11/22 22:57:26 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/README.LynxOS diff -u xc/programs/Xserver/hw/xfree86/doc/README.LynxOS:3.50 xc/programs/Xserver/hw/xfree86/doc/README.LynxOS:3.51 --- xc/programs/Xserver/hw/xfree86/doc/README.LynxOS:3.50 Fri Aug 3 19:16:07 2007 +++ xc/programs/Xserver/hw/xfree86/doc/README.LynxOS Sat Nov 22 14:57:26 2008 @@ -1,4 +1,4 @@ - README for XFree86® 4.7.0 on LynxOS + README for XFree86® 4.8.0 on LynxOS Thomas Mueller @@ -13,16 +13,16 @@ See the Copyright Notice. -The sources for XFree86 4.7.0 are available by anonymous ftp from: +The sources for XFree86 4.8.0 are available by anonymous ftp from: -ftp://ftp.XFree86.org/pub/XFree86/4.7.0 +ftp://ftp.XFree86.org/pub/XFree86/4.8.0 Binaries of XFree86 for LynxOS x86 are available from: -ftp://ftp.XFree86.org/pub/XFree86/4.7.0/binaries/LynxOS +ftp://ftp.XFree86.org/pub/XFree86/4.8.0/binaries/LynxOS The binaries on the FTP site were built on the latest released LynxOS version -at the time XFree86 4.7.0 was released. In this case it is `LynxOS x86 +at the time XFree86 4.8.0 was released. In this case it is `LynxOS x86 3.0.1'. Because of changes made to the object format they don't run on LynxOS versions earlier than 3.0.0. @@ -34,7 +34,7 @@ 3.1.0' support has to be considered to be in `alpha state'. Initial tests were performed on LynxOS x86 only! -XFree86 4.7.0 supports LynxOS on the x86 and on the PowerPC platform. X +XFree86 4.8.0 supports LynxOS on the x86 and on the PowerPC platform. X servers are currently available only on the x86 platform. The X server may work with some PowerPC platforms supported by LynxOS though this has not (yet) been thoroughly tested. @@ -160,7 +160,7 @@ 3.5 X Server debug diagnostics output and other VT peculiarities Output made by the XFree86 X on its stdout or stderr will be lost after the -server switches to graphics mode. The XFree86 4.7.0 server stores its output +server switches to graphics mode. The XFree86 4.8.0 server stores its output in /usr/adm/XFree86.n.log (where n is the screen number). When the X server is running output made to other consoles will be lost. @@ -263,4 +263,4 @@ Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LynxOS.sgml,v 3.22 dawes Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.LynxOS,v 3.50 2007/08/04 02:16:07 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.LynxOS,v 3.51 2008/11/22 22:57:26 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/README.NetBSD diff -u xc/programs/Xserver/hw/xfree86/doc/README.NetBSD:3.102 xc/programs/Xserver/hw/xfree86/doc/README.NetBSD:3.103 --- xc/programs/Xserver/hw/xfree86/doc/README.NetBSD:3.102 Fri Aug 3 19:16:07 2007 +++ xc/programs/Xserver/hw/xfree86/doc/README.NetBSD Sat Nov 22 14:57:26 2008 @@ -1,4 +1,4 @@ - README for XFree86® 4.7.0 on NetBSD + README for XFree86® 4.8.0 on NetBSD Rich Murphey, David Dawes, Marc Wandschneider, Mark Weaver, Matthieu Herrb @@ -15,10 +15,10 @@ The sources for XFree86 are available by anonymous ftp from: -ftp://ftp.XFree86.org/pub/XFree86/4.7.0 +ftp://ftp.XFree86.org/pub/XFree86/4.8.0 Binaries for NetBSD 1.5 and later are available from: -ftp://ftp.XFree86.org/pub/XFree86/4.7.0/binaries/NetBSD +ftp://ftp.XFree86.org/pub/XFree86/4.8.0/binaries/NetBSD XFree86 also builds on other NetBSD architectures. See section Building on other architectures (section 8.4, page 1) for details. @@ -32,7 +32,7 @@ 3. New OS dependent features -See the Release Notes for non-OS dependent new features in XFree86 4.7.0. +See the Release Notes for non-OS dependent new features in XFree86 4.8.0. 3.1 New OS dependent features in 4.2.0 @@ -110,7 +110,7 @@ 5.1 About mouse configuration -XFree86 4.7.0 has support for the mouse driver included in the wscons console +XFree86 4.8.0 has support for the mouse driver included in the wscons console driver introduced by NetBSD 1.4. Specify ``wsmouse'' as the protocol and ``/dev/wsmouse0'' as the device in /etc/X11/XF86Config if you're using NetBSD 1.4 or later with a PS/2 mouse. @@ -228,14 +228,14 @@ access to the /dev/mem device when in multi-users mode. But XFree86 servers can take advantage (or require) linear access to the display memory. -Most XFree86 4.7.0 card drivers require linear memory access. There are two +Most XFree86 4.8.0 card drivers require linear memory access. There are two ways to allow XFree86 to access linear memory: The first way is to disable the kernel security feature by adding ``option INSECURE'' in the kernel configuration file and build a new kernel. The second way is to install the aperture driver, included in source form in -xc/programs/Xserver/hw/xfree86/etc/apNetBSD.shar in the XFree86 4.7.0 source +xc/programs/Xserver/hw/xfree86/etc/apNetBSD.shar in the XFree86 4.8.0 source distribution. Unpack it in a new directory of your choice by running: sh apNetBSD.shar @@ -380,4 +380,4 @@ Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/NetBSD.sgml,v 3.70 dawes Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.NetBSD,v 3.102 2007/08/04 02:16:07 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.NetBSD,v 3.103 2008/11/22 22:57:26 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/README.OpenBSD diff -u xc/programs/Xserver/hw/xfree86/doc/README.OpenBSD:1.57 xc/programs/Xserver/hw/xfree86/doc/README.OpenBSD:1.58 --- xc/programs/Xserver/hw/xfree86/doc/README.OpenBSD:1.57 Fri Aug 3 19:16:07 2007 +++ xc/programs/Xserver/hw/xfree86/doc/README.OpenBSD Sat Nov 22 14:57:26 2008 @@ -1,4 +1,4 @@ - README for XFree86® 4.7.0 on OpenBSD + README for XFree86® 4.8.0 on OpenBSD Matthieu Herrb @@ -13,13 +13,13 @@ See the Copyright Notice. -The sources for XFree86 4.7.0 are available by anonymous ftp from: +The sources for XFree86 4.8.0 are available by anonymous ftp from: -ftp://ftp.XFree86.org/pub/XFree86/4.7.0 +ftp://ftp.XFree86.org/pub/XFree86/4.8.0 Binaries for OpenBSD/i386 3.4 and later are available from: -ftp://ftp.XFree86.org/pub/XFree86/4.7.0/binaries/OpenBSD +ftp://ftp.XFree86.org/pub/XFree86/4.8.0/binaries/OpenBSD XFree86 also builds on other OpenBSD architectures. See section Building on other architectures (section 8., page 1) for details. @@ -31,7 +31,7 @@ 3. New OS dependent features -See the Release Notes for non-OS dependent new features in XFree86 4.7.0. +See the Release Notes for non-OS dependent new features in XFree86 4.8.0. 3.1 New OS related features in 4.4 @@ -144,7 +144,7 @@ 5.1 About mouse configuration -XFree86 4.7.0 has support for the mouse driver included in the new wscons +XFree86 4.8.0 has support for the mouse driver included in the new wscons console driver introduced by OpenBSD-2.9. Specify ``wsmouse'' as the proto- col and ``/dev/wsmouse0'' as the device in /etc/X11/XF86Config if you're using OpenBSD-2.9 or later with a PS/2 or USB mouse. @@ -307,4 +307,4 @@ Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/OpenBSD.sgml,v 1.36 dawes Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.OpenBSD,v 1.57 2007/08/04 02:16:07 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.OpenBSD,v 1.58 2008/11/22 22:57:26 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/README.chips diff -u xc/programs/Xserver/hw/xfree86/doc/README.chips:3.60 xc/programs/Xserver/hw/xfree86/doc/README.chips:3.61 --- xc/programs/Xserver/hw/xfree86/doc/README.chips:3.60 Fri Aug 3 19:16:07 2007 +++ xc/programs/Xserver/hw/xfree86/doc/README.chips Sat Nov 22 14:57:26 2008 @@ -6,7 +6,7 @@ 1. Introduction -With the release of XFree86 version 4.7.0, the Chips and Technologies driver +With the release of XFree86 version 4.8.0, the Chips and Technologies driver has been extensively rewritten and contains many new features. This driver must be considered work in progress, and those users wanting stability are encouraged to use the older XFree86 3.3.x versions. However this version of @@ -976,7 +976,7 @@ startx -- -depth 24 -fbbpp 32 8-8-8 RGB truecolor - however as XFree86 version 4.7.0 allows 32bpp pixmaps to be used + however as XFree86 version 4.8.0 allows 32bpp pixmaps to be used with framebuffers operating in 24bpp, this mode of operating will cost performance for no gain in functionality. @@ -1050,4 +1050,4 @@ Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/chips.sgml,v 3.39 dawes Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.chips,v 3.60 2007/08/04 02:16:07 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.chips,v 3.61 2008/11/22 22:57:26 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/README.mouse diff -u xc/programs/Xserver/hw/xfree86/doc/README.mouse:1.36 xc/programs/Xserver/hw/xfree86/doc/README.mouse:1.37 --- xc/programs/Xserver/hw/xfree86/doc/README.mouse:1.36 Fri Aug 3 19:16:07 2007 +++ xc/programs/Xserver/hw/xfree86/doc/README.mouse Sat Nov 22 14:57:26 2008 @@ -6,7 +6,7 @@ 1. Introduction -This document describes mouse support in XFree86 4.7.0. +This document describes mouse support in XFree86 4.8.0. Mouse configuration has often been a mysterious task for novice users. With XFree86 4.5.0 and later, mouse configuration is automatic for most common @@ -1001,4 +1001,4 @@ Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/mouse.sgml,v 1.16 dawes Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.mouse,v 1.36 2007/08/04 02:16:07 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.mouse,v 1.37 2008/11/22 22:57:26 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/README.s3virge diff -u xc/programs/Xserver/hw/xfree86/doc/README.s3virge:1.29 xc/programs/Xserver/hw/xfree86/doc/README.s3virge:1.30 --- xc/programs/Xserver/hw/xfree86/doc/README.s3virge:1.29 Fri Aug 3 19:16:07 2007 +++ xc/programs/Xserver/hw/xfree86/doc/README.s3virge Sat Nov 22 14:57:26 2008 @@ -6,7 +6,7 @@ 1. Supported hardware -The s3virge driver in XFree86 4.7.0 supports the S3 ViRGE, ViRGE DX, GX, GX2, +The s3virge driver in XFree86 4.8.0 supports the S3 ViRGE, ViRGE DX, GX, GX2, MX, MX+, and VX chipsets. It also supports Trio3D and Trio3D/2x chips. A majority of testing is done on ViRGE DX chips, making them the most stable to date. This release has added support for doublescan modes on DX. @@ -63,4 +63,4 @@ Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/s3virge.sgml,v 1.7 dawes Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.s3virge,v 1.29 2007/08/04 02:16:07 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/README.s3virge,v 1.30 2008/11/22 22:57:26 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/RELNOTES diff -u xc/programs/Xserver/hw/xfree86/doc/RELNOTES:3.155 xc/programs/Xserver/hw/xfree86/doc/RELNOTES:3.156 --- xc/programs/Xserver/hw/xfree86/doc/RELNOTES:3.155 Sun Aug 12 17:57:47 2007 +++ xc/programs/Xserver/hw/xfree86/doc/RELNOTES Sat Nov 22 14:57:26 2008 @@ -1,18 +1,18 @@ - Release Notes for XFree86® 4.7.0 + Release Notes for XFree86® 4.8.0 The XFree86 Project, Inc - August 2007 + December 2008 Abstract This document contains information about the various features and - their current status in the XFree86 4.7.0 release. + their current status in the XFree86 4.8.0 release. 1. Introduction to the 4.x Release Series XFree86 4.0 was the first official release of the XFree86 4 series. The cur- -rent release (4.7.0) is the latest in that series. The XFree86 4.x series +rent release (4.8.0) is the latest in that series. The XFree86 4.x series represents a significant redesign of the XFree86 X server, with a strong focus on modularity and configurability. @@ -72,13 +72,12 @@ through the Installation Document as it can point out which particular binary you should download. -The next section describes what is new in the latest version (4.7.0) compared -with the previous full release (4.6.0). There are many new features in this -release and we unfortunately do not have enough space to cover them all here. +The next section describes what is new in the latest version (4.8.0) compared +with the previous full release (4.7.0). -3. Summary of new features in 4.7.0. +3. Summary of new features in 4.8.0. -This is a sampling of the new features in XFree86 4.7.0. A more complete +This is a sampling of the new features in XFree86 4.8.0. A more complete list of changes can be found in the CHANGELOG that is part of the XFree86 source tree. It can also be viewed online at our CVSweb server , or the 'cvs log' information for individual @@ -834,42 +689,23 @@ New Features, Enhancements and Updates: Security Updates: - Josh Bressens, Chris Evans, Matthieu Herrb, Marc La - France, Sean Larsson, Victor Stinner, iDefense. + X.Org, Matthieu Herrb. - NVIDIA driver updates and new hardware support: - Mark Vojkovich - - Improved SPARC support: + Improved SPARC, PCI-X and PCI Express support: Marc La France. - Xterm enhancements and updates: - Thomas Dickey. - - DragonFly support: - David H. Dawes. - Integration: General Integration of Submissions: Marc La France, David H. Dawes. - Release Engineering: - David H. Dawes. - Patches and other submissions (in alphabetical order): - Andrew Aitchison, Marc Balmer, Etienne Bersac, Martin Bochnig, - Peter Breitenlohner, Josh Bressers, James Chacon, Yves de Cham- - plain, Alan Coopersmith, David Dawes, Eike Dehling, Thomas - Dickey, Matthias Drochner, Jay Estabrook, Chris Evans, Will L G, - Andriy Gapon, Charles M. Hannum, Frank J. R. Hanstick, Ben Har- - ris, Matthieu Herrb, Iain Hibbert, Martin Husemann, iDefense, - Milos Komarcevic, Marc La France, Sean Larrson, Michael Lorenz, - Jie Luo, Loic Mahe, Minoura Makoto, Martin Mares, Luke Mewburn, - NetBSD, Dmitry Pervushin, Alexander Pohoyda, Ty Sarna, SciFi, - Christopher Sekiya, Jamey Sharp, Victor Stinner, Frank van der - Linden, Shin Takemura, Mark Vojkovich, Nathan J. Williams, X.Org, - Christos Zoulos. + David Arlie, Alan Brown, Alex Chen, Yves de Champlain, Egbert + Eich, Matthieu Herrb, Matthias Hopf, Peter Hutterer, Pat Kane, + David Krause, Felix Kuehling, Marc La France, John Lumby, Paul + Mackerras, Keith Packard, Soran Sandmann Pedersen, Aaron Plat- + tner, Scitech, Miod Vallat, Christian Weisgerber, Dick Wesseling, + David Wong, X.Org. Webmaster: Georgina O. Economou @@ -896,7 +732,7 @@ This product includes software developed by X-Oz Technologies (http://www.x- oz.com/). - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTES.sgml,v 1.143 tsi Exp $ + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTES.sgml,v 1.144 tsi Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/RELNOTES,v 3.155 2007/08/13 00:57:47 dawes Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/RELNOTES,v 3.156 2008/11/22 22:57:26 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/Versions diff -u xc/programs/Xserver/hw/xfree86/doc/Versions:1.22 xc/programs/Xserver/hw/xfree86/doc/Versions:1.23 --- xc/programs/Xserver/hw/xfree86/doc/Versions:1.22 Fri Aug 3 19:16:07 2007 +++ xc/programs/Xserver/hw/xfree86/doc/Versions Sat Nov 22 14:57:27 2008 @@ -19,8 +19,8 @@ XFree86 release cycles occur approximately every 12 months and coincide with the calendar year. For example 4.0 was released in 2000; 4.1 in 2001; 4.2 in -2002; 4.3 in 2003; 4.4 in 2004; 4.5 in 2005; 4.6 in 2006 and 4.7 in 2007. So -it is safe to say that 4.8 will be released late in 2008. +2002; 4.3 in 2003; 4.4 in 2004; 4.5 in 2005; 4.6 in 2006; 4.7 in 2007 and 4.8 +in 2008. So it is safe to say that 4.8 will be released late in 2008. The development phase typically ends 1-3 months before the release date and is marked by the start of a feature freeze . The timing of releases and the @@ -33,8 +33,8 @@ update releases typically consist of source code patches plus binary updates that may be layered on top of the previous release. -The current release is 4.7.0, and the next release will be 4.8.0. No update -release is scheduled, but if one is needed it will be version 4.7.1. +The current release is 4.8.0, and the next release will be 4.9.0. No update +release is scheduled, but if one is needed it will be version 4.8.1. Aside from releases, snapshots of the development trunk are tagged in the CVS repository at regular intervals, normally every two weeks. Each snapshot has @@ -312,7 +312,7 @@ } } - Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Versions.sgml,v 1.9 tsi Exp $ + Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Versions.sgml,v 1.10 tsi Exp $ -$XFree86: xc/programs/Xserver/hw/xfree86/doc/Versions,v 1.22 2007/08/04 02:16:07 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/Versions,v 1.23 2008/11/22 22:57:27 tsi Exp $ Index: xc/programs/Xserver/hw/xfree86/doc/sgml/Install.sgml diff -u xc/programs/Xserver/hw/xfree86/doc/sgml/Install.sgml:1.22 xc/programs/Xserver/hw/xfree86/doc/sgml/Install.sgml:1.23 --- xc/programs/Xserver/hw/xfree86/doc/sgml/Install.sgml:1.22 Sun Feb 6 14:41:40 2005 +++ xc/programs/Xserver/hw/xfree86/doc/sgml/Install.sgml Sat Sep 15 16:43:41 2007 @@ -6,10 +6,10 @@ Installation Details for XFree86® &relvers; <author>The XFree86 Project, Inc -<date>2 February 2005 +<date>12 August 2007 <ident> -$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Install.sgml,v 1.22 2005/02/06 22:41:40 dawes Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Install.sgml,v 1.23 2007/09/15 23:43:41 tsi Exp $ </ident> <abstract> Index: xc/programs/Xserver/hw/xfree86/doc/sgml/LICENSE.sgml diff -u xc/programs/Xserver/hw/xfree86/doc/sgml/LICENSE.sgml:1.45 xc/programs/Xserver/hw/xfree86/doc/sgml/LICENSE.sgml:1.46 --- xc/programs/Xserver/hw/xfree86/doc/sgml/LICENSE.sgml:1.45 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/doc/sgml/LICENSE.sgml Mon Dec 31 16:39:59 2007 @@ -8,7 +8,7 @@ <date>April 2006</date> <ident> -$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LICENSE.sgml,v 1.45 2007/01/01 16:08:15 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/LICENSE.sgml,v 1.46 2008/01/01 00:39:59 tsi Exp $ </ident> <sect>Introduction @@ -176,7 +176,7 @@ Copyright (C) 2000, 2001 Ani Joshi<newline> Copyright (C) 2000 by Rainer Keller<newline> Copyright (C) 1999-2003 by Peter Kunzmann, Citron GmbH, Germany.<newline> -Copyright (C) 1994 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org<newline> +Copyright (C) 1994 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org<newline> Copyright (C) 1996 by Steven Lang<newline> Copyright (C) 1995, 1999 by Patrick Lecoanet, France.<newline> Copyright (C) 2001 by Patrick LERDA<newline> Index: xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml diff -u xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml:3.149 xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml:3.150 --- xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml:3.149 Tue Apr 11 18:39:22 2006 +++ xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml Thu Aug 16 09:06:31 2007 @@ -13,10 +13,10 @@ <title>README for XFree86® &relvers; <author>The XFree86 Project, Inc -<date>April 2006 +<date>August 2007 <ident> -$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml,v 3.149 2006/04/12 01:39:22 dawes Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/README.sgml,v 3.150 2007/08/16 16:06:31 dawes Exp $ </ident> <abstract> Index: xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTES.sgml diff -u xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTES.sgml:1.143 xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTES.sgml:1.144 --- xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTES.sgml:1.143 Fri Aug 3 19:16:08 2007 +++ xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTES.sgml Sat Nov 22 14:57:27 2008 @@ -6,10 +6,10 @@ <title>Release Notes for XFree86® &relvers; <author>The XFree86 Project, Inc -<date>August 2007 +<date>December 2008 <ident> -$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTES.sgml,v 1.143 2007/08/04 02:16:08 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/RELNOTES.sgml,v 1.144 2008/11/22 22:57:27 tsi Exp $ </ident> <abstract> @@ -122,8 +122,6 @@ The next section describes what is <bf>new</bf> in the latest version (&relvers;) compared with the previous full release (&prevfullrelvers;). ]]> -There are many new features in this release and we unfortunately do not have -enough space to cover them all here. </sect> @@ -150,33 +148,28 @@ <itemize> -<item><htmlurl name="CVE-2006-0747" -url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2006-0747">. -<item><htmlurl name="CVE-2006-1861" -url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2006-1861">. -<item><htmlurl name="CVE-2006-2661" -url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2006-2661">. -<item><htmlurl name="CVE-2006-6101" -url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2006-6101">. -<item><htmlurl name="CVE-2006-6102" -url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2006-6102">. -<item><htmlurl name="CVE-2006-6103" -url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2006-6103">. -<item><htmlurl name="CVE-2007-1003" -url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2007-1003">. -<item><htmlurl name="CVE-2007-1351" -url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2007-1351">. -<item><htmlurl name="CVE-2007-1352" -url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2007-1352">. -<item><htmlurl name="CVE-2007-1667" -url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2007-1667">. -<item><htmlurl name="CVE-2007-2754" -url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2007-2754">. +<item><htmlurl name="CVE-2007-5760" +url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2007-5760">. +<item><htmlurl name="CVE-2007-5958" +url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2007-5958">. +<item><htmlurl name="CVE-2007-6427" +url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2007-6427">. +<item><htmlurl name="CVE-2007-6428" +url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2007-6428">. +<item><htmlurl name="CVE-2007-6429" +url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2007-6429">. +<item><htmlurl name="CVE-2008-0006" +url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2008-0006">. +<item><htmlurl name="CVE-2008-1377" +url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2008-1377">. +<item><htmlurl name="CVE-2008-1379" +url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2008-1379">. +<item><htmlurl name="CVE-2008-2360" +url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2008-2360">. +<item><htmlurl name="CVE-2008-2361" +url="http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2008-2361">. </itemize> -<p> -In addition, a number of potential integer overflow problems in the Type 1 -font rendering code have been corrected. <sect1>Video Driver Enhancements <p> @@ -185,197 +178,58 @@ <p> <itemize> -<item>Fix bug that caused the version check between the ati and atimisc modules -to fail. +<item>Mach64 block transfers and XVideo support have been significantly sped +up on x86_64 platforms. -<item>The atimisc module's saving and restoring of the mode on server entry has -been made more reliable on 64-bit systems. +<item>A bug in atimisc's colourmap handling has been fixed. -<item>Fix bug that prevented detection of non-PCI adapters on systems that do -not provide accurate PCI resource sizes. +<item>Support has been added for dual head on Rage 128 Mobility's. -<item>Fix the radeon driver's saving and restoring of the mode on server entry. +<item>Add support for newer RADEONs. -</itemize> +<item>Fixed a memory leak in the RADEON driver. -<sect2>chips -<p> - -<itemize> -<item>Fix some of this driver's endianness problems. +<item>A Solaris hang has been corrected that occurred on UltraSPARCs with +either a Mach64 or RADEON adapter as the system console. </itemize> -<sect2>i128 +<sect2>i830 <p> <itemize> -<item>Resurrect support for Ti3026 RAMDACs found on the original I128 adapters. -Note that there are still issues with depth 8 visuals and hardware cursors. +<item>Fix bug that occurs when the amount of video memory initially reported by +the BIOS is zero. </itemize> -<sect2>mga -<p> - -<itemize> -<item>Add support for Matrox MGA G200e SE adapters. - -<item>Fix determination of the mode on server entry. -Also, save and restore it on VC switches. - -</itemize> - -<sect2>newport -<p> - -<itemize> -<item>Add support for the DPMS extension. - -</itemize> - -<sect2>nv -<p> - -<itemize> -<item>Add support for new hardware. - -</itemize> - -<sect2>pnozz -<p> - -<itemize> -<item>This accelerated driver supports the Weitek POWER 9100 SBUS adapters -found in some SPARC laptops. - -</itemize> - -<sect2>sunbw2, suncg14, suncg3, sunleo, suntcx -<p> - -<itemize> -<item>These drivers, intended for various SPARC SBUS and UPA adapters, can now -blank and unblank the screen correctly. - -</itemize> - -<sect2>sunffb -<p> - -<itemize> -<item>Prevent turning off the FPU on OpenBSD. - -<item>Fix bug that prevented use of this driver on SunOS and Solaris. - -<item>Workaround for VRAM corruption when unblanking FFB1 adapters. - -</itemize> - -<sect2>trident -<p> - -<itemize> -<item>Resave the mode on server entry when switching back to the server's -virtual console. - -</itemize> - -<sect1>Input Driver Enhancements - -<p> -<sect2>mouse +<sect1>XKB updates <p> <itemize> -<item>Do not disable 3-button mouse emulation even when the mouse is found to -actually have a third button. -This helps laptops, and the like, running systems that combine a touchpad and -an external mouse into one device. +<item>Fix a segfault in XKB that occrred when the system has no LEDs. </itemize> -<sect1>XKB updates +<sect1>SHAPE Extension <p> <itemize> -<item>Add an XKB geometry for Dell Inspiron 8000 notebook keyboard. - -<item>Add an XKB geometry for Enermax Aurora keyboards. - -<item>Add XKB keycodes for MacIntosh USB keyboards. - -<item>Add XKB definitions for X860x0 keyboards. - -<item>Update Macintosh french keymap. - -<item>Allow signed coordinates in XKB shape definitions. +<item>This extension has been updated to version 1.1. This adds input regions +to windows that scope the area within which pointer movements are reported to +the client. </itemize> -<sect1>X Server and Extension Updates - -<p> - -<sect2>Loader +<sect1>X Servers <p> -<itemize> -<item>Fixed support for <tt>R_ALPHA_GPRELHIGH</tt> relocations. - -<item>Added support for <tt>R_ALPHA_BRSGP</tt> relocations. - -<item>Fixed handling of archives on non-Linux SPARC. - -<item>Fixed support for <tt>R_SPARC_LO10</tt> and <tt>R_SPARC_OLO10</tt> -relocations. - -<item>Added support for most ELF SPARC relocation types. - -<item>Added an emulation of rand(3) calls. - -</itemize> - <sect2>XFree86 core server and modules <p> <itemize> -<item>Update -configure to detect when wscons support should be used for the -keyboard on OpenBSD. - -<item>Added preliminary support for PCI domains on OpenBSD/sparc64. This -currently requires a kernel change. - -<item>On the *BSD's, added support for absolute mouse position events and -horizontal scroll wheels. - -<item>Fixed a bug that caused an entire batch of mouse events to be rejected -when one of an unknown type was encountered. - -<item>Don't error out on unknown wskbd types on the *BSD's. - -<item>Fixed memory leaks in option processing. - -<item>Fixed area granularity handling in the framebuffer manager. - -<item>Reworked the sizing of PCI resources. More specifically, reduced the X -server's reliance on the OS to provide such information. - -<item>Added support for SBUS and UPA adapters on NetBSD and OpenBSD. - -<item>Added support for Solaris/amd64. - -<item>Added support for UltraSPARC IV systems, including support for PCI -Express. - -<item>Added support for DrangonFly, a variant of FreeBSD. - -<item>Added support for x86_64 architectures on the *BSD's. - -<item>Fixed page size determination in various server-related utilities. - -<item>Made the mmapr and mmapw utilities understand wscons mapping modes on -the *BSD's. +<item>A number of bugs in the PCI-X and PCI Express support introduced in the +previous release have been addressed. </itemize> @@ -383,138 +237,76 @@ <p> <itemize> -<item>Added an option to the TinyX servers to prevent them from probing -serial ports on Linux. - -</itemize> - -<sect2>Xsun -<p> - -<itemize> -<item>Changes to port the various Xsun servers to NetBSD/sparc have been merged -in. +<item>Fix stipples in the Xigs and Xsis530 servers. </itemize> -<sect2>XDarwin +<sect2>Xprt <p> <itemize> -<item>This X server has been heavily upgraded by integrating a wide selection -of changes from its now defunct X.Org implementation. +<item>A number of file descriptor leaks and double-closes have been fixed in +the Xprt server. </itemize> -<sect2>Xvfb +<sect2>Xdmx <p> <itemize> -<item>Fixed segfaults in Xvfb's command line parsing. +<item>Improved Xdmx's handling of USB devices. </itemize> -<sect2>cfb +<sect2>GLX and Mesa <p> <itemize> -<item>Fix a number of bugs in cfb24, even though it is no longer used by any -driver provided in the distribution. - -<item>Fix stipple handling on sparc64. +<item>Fix segfaults that could occur because buffers were being freeing too +early during X server termination. </itemize> -<sect2>fb +<sect2>XAA <p> <itemize> -<item>A problem that prevented the use of the GLX extension in some cases has -been corrected. - -<item>Fix fbCompose() for ABGR framebuffers. - -</itemize> - -<sect2>Render -<p> +<item>Fix handling of ceertain TE fonts with null glyphs that caused segfaults +in XAA. -<itemize> -<item>Endianness fix for RenderSetPictureClipRectangles request. +<item>A number of 64-bit and integer wraparound bugs have been corrected. </itemize> -<sect1>Library, Client and Utility Updates -<p> - -<sect2>restest -<p> -<itemize> -<item>This XRes extension client, originally written by Mark Vojkovich, has -been integrated, after rewriting it to prevent deadlocks that could occur when -displaying its results in an X session. - -</itemize> - -<sect2>xclock -<p> - -<itemize> -<item>Make an analog xclock, when using Render, update the minute hand at most -every minute instead of every update interval. -This makes it consistent with non-Render mode. - -</itemize> - -<sect2>xdm +<sect1>OS Support Updates <p> <itemize> -<item>Fixed a number of memory leaks. - -<item>Fixed bug that prevented an IPv6-aware xdm from accepting chooser -connections. - -</itemize> - -<sect2>xwd -<p> +<item>On SunOS/sparc or Solaris/sparc, the server now clears all framebuffers +on exit. -<itemize> -<item>This utility has been extended to allow selection of a rectangular region -to dump. +<item>To avoid screen corruption on SunOS and Solaris, the server now +redirects /dev/console output while it is running, and copies that data back to +/dev/console on server exit. This behaviour can be disabled through a command +line flag. </itemize> -<sect2>xterm +<sect1>Xft Library <p> <itemize> -<item>Xterm patches upto and including #215 have been integrated. - -<item>Change xterm, on various platforms, to not require that the OS define a -utmp group. - -</itemize> - -<sect1>I18n and Fonts -<p> -<itemize> -<item>Eliminated a number of issues related to the use of external fontconfig -and freetype2 libraries. - -<item>Updated the Serbian locale naming to reflect the country's name change -from "Yugoslavia" to "Serbia and MonteNegro". +<item>A byte-swapping issue in libXft's handling of XImages has been addressed. </itemize> -<sect1>OS Support Updates +<sect1>xdm <p> <itemize> -<item>Added support for PAM on Solaris and Darwin. - -<item>Added support for OpenPAM on FreeBSD and NetBSD. +<item>When using BSD authentication in xdm, wipe out the password as soon as +possible to prevent it from appearing in the address space of subsequently +forked child processes. </itemize> @@ -1172,72 +964,40 @@ <descrip> <tag>New Features, Enhancements and Updates:</tag> <descrip> - <tag>Security Updates:</tag> Josh Bressens, Chris Evans, Matthieu Herrb, - Marc La France, Sean Larsson, Victor Stinner, iDefense. - - <tag>NVIDIA driver updates and new hardware support:</tag>Mark Vojkovich - - <tag>Improved SPARC support:</tag> Marc La France. - - <tag>Xterm enhancements and updates:</tag>Thomas Dickey. + <tag>Security Updates:</tag>X.Org, Matthieu Herrb. - <tag>DragonFly support:</tag>David H. Dawes. + <tag>Improved SPARC, PCI-X and PCI Express support:</tag> Marc La France. </descrip> <tag>Integration:</tag> <descrip> <tag>General Integration of Submissions:</tag>Marc La France, David H. Dawes. </descrip> -<tag>Release Engineering:</tag>David H. Dawes. <tag>Patches and other submissions (in alphabetical order):</tag> -Andrew Aitchison, -Marc Balmer, -Etienne Bersac, -Martin Bochnig, -Peter Breitenlohner, -Josh Bressers, -James Chacon, +David Arlie, +Alan Brown, +Alex Chen, Yves de Champlain, -Alan Coopersmith, -David Dawes, -Eike Dehling, -Thomas Dickey, -Matthias Drochner, -Jay Estabrook, -Chris Evans, -Will L G, -Andriy Gapon, -Charles M. Hannum, -Frank J. R. Hanstick, -Ben Harris, +Egbert Eich, Matthieu Herrb, -Iain Hibbert, -Martin Husemann, -iDefense, -Milos Komarcevic, +Matthias Hopf, +Peter Hutterer, +Pat Kane, +David Krause, +Felix Kuehling, Marc La France, -Sean Larrson, -Michael Lorenz, -Jie Luo, -Loic Mahe, -Minoura Makoto, -Martin Mares, -Luke Mewburn, -NetBSD, -Dmitry Pervushin, -Alexander Pohoyda, -Ty Sarna, -SciFi, -Christopher Sekiya, -Jamey Sharp, -Victor Stinner, -Frank van der Linden, -Shin Takemura, -Mark Vojkovich, -Nathan J. Williams, -X.Org, -Christos Zoulos. +John Lumby, +Paul Mackerras, +Keith Packard, +Soran Sandmann Pedersen, +Aaron Plattner, +Scitech, +Miod Vallat, +Christian Weisgerber, +Dick Wesseling, +David Wong, +X.Org. <tag>Webmaster:</tag>Georgina O. Economou Index: xc/programs/Xserver/hw/xfree86/doc/sgml/Versions.sgml diff -u xc/programs/Xserver/hw/xfree86/doc/sgml/Versions.sgml:1.9 xc/programs/Xserver/hw/xfree86/doc/sgml/Versions.sgml:1.10 --- xc/programs/Xserver/hw/xfree86/doc/sgml/Versions.sgml:1.9 Fri Aug 3 19:16:08 2007 +++ xc/programs/Xserver/hw/xfree86/doc/sgml/Versions.sgml Sat Nov 22 14:57:28 2008 @@ -10,7 +10,7 @@ <date>6 February 2005 <ident> -$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Versions.sgml,v 1.9 2007/08/04 02:16:08 tsi Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/Versions.sgml,v 1.10 2008/11/22 22:57:28 tsi Exp $ </ident> <abstract> @@ -32,8 +32,9 @@ XFree86 release cycles occur approximately every 12 months and coincide with the calendar year. For example 4.0 was released in 2000; 4.1 in -2001; 4.2 in 2002; 4.3 in 2003; 4.4 in 2004; 4.5 in 2005; 4.6 in 2006 and 4.7 -in 2007. So it is safe to say that 4.8 will be released late in 2008. +2001; 4.2 in 2002; 4.3 in 2003; 4.4 in 2004; 4.5 in 2005; 4.6 in 2006; 4.7 +in 2007 and 4.8 in 2008. So it is safe to say that 4.8 will be released late +in 2008. The development phase typically ends 1-3 months before the release date and is marked by the start of a <bf>feature freeze </bf>. The timing of Index: xc/programs/Xserver/hw/xfree86/doc/sgml/defs.ent diff -u xc/programs/Xserver/hw/xfree86/doc/sgml/defs.ent:1.51 xc/programs/Xserver/hw/xfree86/doc/sgml/defs.ent:1.52 --- xc/programs/Xserver/hw/xfree86/doc/sgml/defs.ent:1.51 Fri Aug 3 19:16:08 2007 +++ xc/programs/Xserver/hw/xfree86/doc/sgml/defs.ent Sat Nov 22 14:57:28 2008 @@ -1,30 +1,30 @@ -<!-- $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/defs.ent,v 1.51 2007/08/04 02:16:08 tsi Exp $ --> +<!-- $XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/defs.ent,v 1.52 2008/11/22 22:57:28 tsi Exp $ --> <!-- shared entity definitions for the XFree86 documentation --> <!-- XFree86 version string --> -<!ENTITY relvers CDATA "4.7.0"> -<!ENTITY prevrelvers CDATA "4.6.0"> -<!ENTITY fullrelvers CDATA "4.7.0"> -<!ENTITY prevfullrelvers CDATA "4.6.0"> -<!ENTITY nextfullrelvers CDATA "4.8.0"> +<!ENTITY relvers CDATA "4.8.0"> +<!ENTITY prevrelvers CDATA "4.7.0"> +<!ENTITY fullrelvers CDATA "4.8.0"> +<!ENTITY prevfullrelvers CDATA "4.7.0"> +<!ENTITY nextfullrelvers CDATA "4.9.0"> <!ENTITY nextfullreldate CDATA "not scheduled"> -<!ENTITY nextupdrelvers CDATA "4.7.1"> -<!ENTITY srcvers CDATA "470"> -<!ENTITY prevsrcvers CDATA "460"> -<!ENTITY fullsrcvers CDATA "470"> -<!ENTITY prevfullsrcvers CDATA "460"> -<!ENTITY whichfullrel CDATA "tenth"> +<!ENTITY nextupdrelvers CDATA "4.8.1"> +<!ENTITY srcvers CDATA "480"> +<!ENTITY prevsrcvers CDATA "470"> +<!ENTITY fullsrcvers CDATA "490"> +<!ENTITY prevfullsrcvers CDATA "470"> +<!ENTITY whichfullrel CDATA "eleventh"> <!ENTITY whichupdaterel CDATA "none"> -<!ENTITY reltag CDATA "xf-4_7_0"> -<!ENTITY relbranchtag CDATA "xf-4_7-branch"> +<!ENTITY reltag CDATA "xf-4_8_0"> +<!ENTITY relbranchtag CDATA "xf-4_8-branch"> <!ENTITY rcnum CDATA "none"> <!-- Version of the most recent 3.3.x release --> <!ENTITY legacyvers CDATA "3.3.6"> <!-- doctools version strings --> -<!ENTITY doctoolsvers CDATA "1.3.4"> +<!ENTITY doctoolsvers CDATA "1.3.5"> <!-- utils version strings --> <!ENTITY utilsvers CDATA "1.1.3"> Index: xc/programs/Xserver/hw/xfree86/doc/sgml/index.pre diff -u xc/programs/Xserver/hw/xfree86/doc/sgml/index.pre:1.30 xc/programs/Xserver/hw/xfree86/doc/sgml/index.pre:1.31 --- xc/programs/Xserver/hw/xfree86/doc/sgml/index.pre:1.30 Tue Apr 11 18:39:22 2006 +++ xc/programs/Xserver/hw/xfree86/doc/sgml/index.pre Thu Aug 16 09:06:31 2007 @@ -8,10 +8,10 @@ <!-- Title information --> <title>Documentation for XFree86® version &relvers; <author>The XFree86 Project, Inc -<date>April 2006 +<date>August 2007 <!-- -$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/index.pre,v 1.30 2006/04/12 01:39:22 dawes Exp $ +$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/index.pre,v 1.31 2007/08/16 16:06:31 dawes Exp $ --> <p> Index: xc/programs/Xserver/hw/xfree86/drivers/ati/Imakefile diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/Imakefile:1.62 xc/programs/Xserver/hw/xfree86/drivers/ati/Imakefile:1.64 --- xc/programs/Xserver/hw/xfree86/drivers/ati/Imakefile:1.62 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/Imakefile Wed Apr 2 14:02:31 2008 @@ -1,6 +1,6 @@ -XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/Imakefile,v 1.62 2007/01/01 16:08:15 tsi Exp $ +XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/Imakefile,v 1.64 2008/04/02 21:02:31 tsi Exp $ XCOMM -XCOMM Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org +XCOMM Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org XCOMM XCOMM Permission to use, copy, modify, distribute, and sell this software and XCOMM its documentation for any purpose is hereby granted without fee, provided @@ -68,7 +68,8 @@ ativga.c atiwonder.c atiwonderio.c atixv.c $(MODSRCS2) SRCS3 = r128_accel.c r128_cursor.c r128_dga.c r128_driver.c \ r128_video.c $(DRISRCS3) $(MODSRCS3) -SRCS4 = radeon_accel.c radeon_cursor.c radeon_dga.c radeon_driver.c \ +SRCS4 = radeon_accel.c radeon_bios.c radeon_cursor.c \ + radeon_dga.c radeon_driver.c radeon_mergedfb.c \ radeon_video.c $(DRISRCS4) $(MODSRCS4) OBJS1 = ati.o atiadapter.o atibus.o atichip.o atiendian.o atiident.o \ @@ -82,7 +83,8 @@ ativga.o atiwonder.o atiwonderio.o atixv.o $(MODOBJS2) OBJS3 = r128_accel.o r128_cursor.o r128_dga.o r128_driver.o \ r128_video.o $(DRIOBJS3) $(MODOBJS3) -OBJS4 = radeon_accel.o radeon_cursor.o radeon_dga.o radeon_driver.o \ +OBJS4 = radeon_accel.o radeon_bios.o radeon_cursor.o \ + radeon_dga.o radeon_driver.o radeon_mergedfb.o \ radeon_video.o $(DRIOBJS4) $(MODOBJS4) SRCS = $(SRCS1) $(SRCS2) $(SRCS3) $(SRCS4) @@ -233,6 +235,7 @@ InstallDriverSDKNonExecFile(r128.h,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(r128_accel.c,$(DRIVERSDKDIR)/drivers/ati) +InstallDriverSDKNonExecFile(r128_common.h,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(r128_cursor.c,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(r128_dga.c,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(r128_dri.c,$(DRIVERSDKDIR)/drivers/ati) @@ -246,10 +249,13 @@ InstallDriverSDKNonExecFile(r128_sarea.h,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(r128_version.h,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(r128_video.c,$(DRIVERSDKDIR)/drivers/ati) -InstallDriverSDKNonExecFile(r128_common.h,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(radeon.h,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(radeon_accel.c,$(DRIVERSDKDIR)/drivers/ati) +InstallDriverSDKNonExecFile(radeon_accelfuncs.c,$(DRIVERSDKDIR)/drivers/ati) +InstallDriverSDKNonExecFile(radeon_bios.c,$(DRIVERSDKDIR)/drivers/ati) +InstallDriverSDKNonExecFile(radeon_common.h,$(DRIVERSDKDIR)/drivers/ati) +InstallDriverSDKNonExecFile(radeon_commonfuncs.c,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(radeon_cursor.c,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(radeon_dga.c,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(radeon_dri.c,$(DRIVERSDKDIR)/drivers/ati) @@ -257,6 +263,8 @@ InstallDriverSDKNonExecFile(radeon_dripriv.h,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(radeon_driver.c,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(radeon_macros.h,$(DRIVERSDKDIR)/drivers/ati) +InstallDriverSDKNonExecFile(radeon_mergedfb.c,$(DRIVERSDKDIR)/drivers/ati) +InstallDriverSDKNonExecFile(radeon_mergedfb.h,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(radeon_misc.c,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(radeon_probe.c,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(radeon_probe.h,$(DRIVERSDKDIR)/drivers/ati) @@ -264,8 +272,6 @@ InstallDriverSDKNonExecFile(radeon_sarea.h,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(radeon_version.h,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKNonExecFile(radeon_video.c,$(DRIVERSDKDIR)/drivers/ati) -InstallDriverSDKNonExecFile(radeon_common.h,$(DRIVERSDKDIR)/drivers/ati) -InstallDriverSDKNonExecFile(radeon_accelfuncs.c,$(DRIVERSDKDIR)/drivers/ati) InstallDriverSDKObjectModule(ati,$(DRIVERSDKMODULEDIR),drivers) InstallDriverSDKObjectModule(atimisc,$(DRIVERSDKMODULEDIR),drivers) Index: xc/programs/Xserver/hw/xfree86/drivers/ati/ati.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/ati.c:1.29 xc/programs/Xserver/hw/xfree86/drivers/ati/ati.c:1.30 --- xc/programs/Xserver/hw/xfree86/drivers/ati/ati.c:1.29 Thu Jun 28 06:17:14 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/ati.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ati.c,v 1.29 2007/06/28 13:17:14 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ati.c,v 1.30 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/ati.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/ati.h:1.13 xc/programs/Xserver/hw/xfree86/drivers/ati/ati.h:1.14 --- xc/programs/Xserver/hw/xfree86/drivers/ati/ati.h:1.13 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/ati.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ati.h,v 1.13 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ati.h,v 1.14 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1999 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.c:1.18 xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.c:1.19 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.c:1.18 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.c,v 1.18 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.c,v 1.19 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2001 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.h:1.9 xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.h:1.10 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.h:1.9 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.h,v 1.9 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaccel.h,v 1.10 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2001 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.c:1.22 xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.c:1.23 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.c:1.22 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.c,v 1.22 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.c,v 1.23 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.h:1.15 xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.h:1.16 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.h:1.15 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.h,v 1.15 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadapter.h,v 1.16 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.c:1.20 xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.c:1.21 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.c:1.20 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.c,v 1.20 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.c,v 1.21 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.h:1.12 xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.h:1.13 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.h:1.12 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.h,v 1.12 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiadjust.h,v 1.13 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.c:1.5 xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.c:1.6 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.c:1.5 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.c,v 1.5 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.c,v 1.6 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.h:1.5 xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.h:1.6 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.h:1.5 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.h,v 1.5 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiaudio.h,v 1.6 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.c:1.17 xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.c:1.18 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.c:1.17 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.c,v 1.17 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.c,v 1.18 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.h:1.13 xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.h:1.14 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.h:1.13 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.h,v 1.13 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atibank.h,v 1.14 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.c:1.23 xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.c:1.24 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.c:1.23 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.c,v 1.23 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.c,v 1.24 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.h:1.15 xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.h:1.16 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.h:1.15 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.h,v 1.15 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atibus.h,v 1.16 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.c:1.43 xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.c:1.46 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.c:1.43 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.c Wed Apr 30 08:43:47 2008 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.c,v 1.43 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.c,v 1.46 2008/04/30 15:43:47 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -78,25 +78,7 @@ "ATI Rage 128 Mobility M3", "ATI Rage 128 Mobility M4", "ATI unknown Rage 128" - "ATI Radeon 7200", - "ATI Radeon 7000 (VE)", - "ATI Radeon Mobility M6", - "ATI Radeon IGP320", - "ATI Radeon IGP330/340/350", - "ATI Radeon 7000 IGP", - "ATI Radeon 7500", - "ATI Radeon Mobility M7", - "ATI Radeon 8500/9100", - "ATI Radeon 9000", - "ATI Radeon Mobility M9", - "ATI Radeon 9000 IGP", - "ATI Radeon 9200", - "ATI Radeon Mobility M9+", - "ATI Radeon 9700/9500", - "ATI Radeon 9600", - "ATI Radeon 9800", - "ATI Radeon 9800XT", - "ATI unknown Radeon", + "ATI Radeon", "ATI Rage HDTV" }; @@ -610,123 +592,11 @@ case NewChipID('M', 'L'): return ATI_CHIP_RAGE128MOBILITY4; - case NewChipID('Q', 'D'): - case NewChipID('Q', 'E'): - case NewChipID('Q', 'F'): - case NewChipID('Q', 'G'): - return ATI_CHIP_RADEON; - - case NewChipID('Q', 'Y'): - case NewChipID('Q', 'Z'): - return ATI_CHIP_RADEONVE; - - case NewChipID('L', 'Y'): - case NewChipID('L', 'Z'): - return ATI_CHIP_RADEONMOBILITY6; - - case NewChipID('A', '6'): - case NewChipID('C', '6'): - return ATI_CHIP_RS100; - - case NewChipID('A', '7'): - case NewChipID('C', '7'): - return ATI_CHIP_RS200; - - case NewChipID('D', '7'): - case NewChipID('B', '7'): - return ATI_CHIP_RS250; - - case NewChipID('L', 'W'): - case NewChipID('L', 'X'): - return ATI_CHIP_RADEONMOBILITY7; - - case NewChipID('Q', 'H'): - case NewChipID('Q', 'I'): - case NewChipID('Q', 'J'): - case NewChipID('Q', 'K'): - case NewChipID('Q', 'L'): - case NewChipID('Q', 'M'): - case NewChipID('Q', 'N'): - case NewChipID('Q', 'O'): - case NewChipID('Q', 'h'): - case NewChipID('Q', 'i'): - case NewChipID('Q', 'j'): - case NewChipID('Q', 'k'): - case NewChipID('Q', 'l'): - case NewChipID('B', 'B'): - return ATI_CHIP_R200; - - case NewChipID('Q', 'W'): - case NewChipID('Q', 'X'): - return ATI_CHIP_RV200; - - case NewChipID('I', 'f'): - case NewChipID('I', 'g'): - return ATI_CHIP_RV250; - - case NewChipID('L', 'd'): - case NewChipID('L', 'f'): - case NewChipID('L', 'g'): - return ATI_CHIP_RADEONMOBILITY9; - - case NewChipID('X', '4'): - case NewChipID('X', '5'): - return ATI_CHIP_RS300; - - case NewChipID('Y', '\''): - case NewChipID('Y', 'a'): - case NewChipID('Y', 'b'): - case NewChipID('Y', 'd'): - return ATI_CHIP_RV280; - - case NewChipID('\\', 'a'): - case NewChipID('\\', 'c'): - return ATI_CHIP_RADEONMOBILITY9PLUS; - - case NewChipID('A', 'D'): - case NewChipID('A', 'E'): - case NewChipID('A', 'F'): - case NewChipID('A', 'G'): - case NewChipID('N', 'D'): - case NewChipID('N', 'E'): - case NewChipID('N', 'F'): - case NewChipID('N', 'G'): - return ATI_CHIP_R300; - - case NewChipID('A', 'H'): - case NewChipID('A', 'I'): - case NewChipID('A', 'J'): - case NewChipID('A', 'K'): - case NewChipID('N', 'H'): - case NewChipID('N', 'I'): - case NewChipID('N', 'K'): - return ATI_CHIP_R350; - - case NewChipID('A', 'P'): - case NewChipID('A', 'Q'): - case NewChipID('A', 'R'): - case NewChipID('A', 'S'): - case NewChipID('A', 'T'): - case NewChipID('A', 'V'): - case NewChipID('N', 'P'): - case NewChipID('N', 'Q'): - case NewChipID('N', 'R'): - case NewChipID('N', 'S'): - case NewChipID('N', 'T'): - case NewChipID('N', 'V'): - return ATI_CHIP_RV350; - - case NewChipID('N', 'J'): - return ATI_CHIP_R360; - case NewChipID('H', 'D'): return ATI_CHIP_HDTV; default: - /* - * Treat anything else as an unknown Radeon. Please keep the above - * up-to-date however, as it serves as a central chip list. - */ + /* Treat anything else as a Radeon */ return ATI_CHIP_Radeon; } } Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.h:1.32 xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.h:1.35 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.h:1.32 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.h Wed Apr 30 08:43:48 2008 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.h,v 1.32 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.h,v 1.35 2008/04/30 15:43:48 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -80,25 +80,7 @@ ATI_CHIP_RAGE128MOBILITY3, /* Rage128 */ ATI_CHIP_RAGE128MOBILITY4, /* Rage128 */ ATI_CHIP_Rage128, /* Last among Rage128's */ - ATI_CHIP_RADEON, /* Radeon */ - ATI_CHIP_RADEONVE, /* Radeon VE */ - ATI_CHIP_RADEONMOBILITY6, /* Radeon M6 */ - ATI_CHIP_RS100, /* IGP320 */ - ATI_CHIP_RS200, /* IGP340 */ - ATI_CHIP_RS250, /* Radoen 7000 IGP */ - ATI_CHIP_RV200, /* RV200 */ - ATI_CHIP_RADEONMOBILITY7, /* Radeon M7 */ - ATI_CHIP_R200, /* R200 */ - ATI_CHIP_RV250, /* RV250 */ - ATI_CHIP_RADEONMOBILITY9, /* Radeon M9 */ - ATI_CHIP_RS300, /* Radoen 9000 IGP */ - ATI_CHIP_RV280, /* RV250 */ - ATI_CHIP_RADEONMOBILITY9PLUS, /* Radeon M9+ */ - ATI_CHIP_R300, /* R300 */ - ATI_CHIP_RV350, /* RV350 */ - ATI_CHIP_R350, /* R350 */ - ATI_CHIP_R360, /* R360 */ - ATI_CHIP_Radeon, /* Last among Radeon's */ + ATI_CHIP_Radeon, /* Radeon */ ATI_CHIP_HDTV /* HDTV */ } ATIChipType; Index: xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.c:1.30 xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.c:1.31 --- xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.c:1.30 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.c,v 1.30 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.c,v 1.31 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.h:1.12 xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.h:1.13 --- xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.h:1.12 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.h,v 1.12 2007/01/01 16:08:15 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticlock.h,v 1.13 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.c:1.21 xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.c:1.22 --- xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.c:1.21 Mon Jan 1 08:08:15 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.c,v 1.21 2007/01/01 16:08:15 tsi Exp $*/ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.c,v 1.22 2008/01/01 00:39:59 tsi Exp $*/ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.h:1.9 xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.h:1.10 --- xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.h:1.9 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.h,v 1.9 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonfig.h,v 1.10 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.c:1.28 xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.c:1.29 --- xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.c:1.28 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.c,v 1.28 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.c,v 1.29 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.h:1.13 xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.h:1.14 --- xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.h:1.13 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.h,v 1.13 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticonsole.h,v 1.14 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/aticrtc.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/aticrtc.h:1.13 xc/programs/Xserver/hw/xfree86/drivers/ati/aticrtc.h:1.14 --- xc/programs/Xserver/hw/xfree86/drivers/ati/aticrtc.h:1.13 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/aticrtc.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticrtc.h,v 1.13 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticrtc.h,v 1.14 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.c:1.8 xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.c:1.9 --- xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.c:1.8 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.c,v 1.8 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.c,v 1.9 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2001 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.h:1.7 xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.h:1.8 --- xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.h:1.7 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.h,v 1.7 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/aticursor.h,v 1.8 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2001 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.c:1.25 xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.c:1.28 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.c:1.25 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.c Wed Apr 2 08:53:55 2008 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.c,v 1.25 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.c,v 1.28 2008/04/02 15:53:55 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -437,7 +437,7 @@ CARD8 fChanged[SizeOf(pATI->NewHW.lut) / 3]; - (void)memset(fChanged, SizeOf(fChanged), 0); + (void)memset(fChanged, 0, SizeOf(fChanged)); minShift = redShift; if (minShift > greenShift) @@ -447,7 +447,7 @@ for (i = 0; i < nColours; i++) { - if((Index = Indices[i]) < 0) + if ((Index = Indices[i]) < 0) continue; if (Index <= reds) Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.h:1.20 xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.h:1.21 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.h:1.20 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.h,v 1.20 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidac.h,v 1.21 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.c:1.5 xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.c:1.6 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.c:1.5 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.c,v 1.5 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.c,v 1.6 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.h:1.5 xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.h:1.6 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.h:1.5 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.h,v 1.5 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidecoder.h,v 1.6 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.c:1.17 xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.c:1.18 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.c:1.17 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.c,v 1.17 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.c,v 1.18 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.h:1.12 xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.h:1.13 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.h:1.12 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.h,v 1.12 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidga.h,v 1.13 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.c:1.27 xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.c:1.28 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.c:1.27 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.c,v 1.27 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.c,v 1.28 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.h:1.14 xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.h:1.15 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.h:1.14 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.h,v 1.14 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atidsp.h,v 1.15 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.c:1.6 xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.c:1.7 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.c:1.6 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.c,v 1.6 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.c,v 1.7 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2005 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2005 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.h:1.5 xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.h:1.6 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.h:1.5 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.h,v 1.5 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiendian.h,v 1.6 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2005 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2005 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.c:1.8 xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.c:1.9 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.c:1.8 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.c Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.c,v 1.8 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.c,v 1.9 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.h:1.5 xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.h:1.6 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.h:1.5 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.h Mon Dec 31 16:39:59 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.h,v 1.5 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atii2c.h,v 1.6 2008/01/01 00:39:59 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.c:1.16 xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.c:1.17 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.c:1.16 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.c Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.c,v 1.16 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.c,v 1.17 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.h:1.15 xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.h:1.16 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.h:1.15 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.h Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.h,v 1.15 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiident.h,v 1.16 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiio.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiio.h:1.19 xc/programs/Xserver/hw/xfree86/drivers/ati/atiio.h:1.20 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiio.h:1.19 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiio.h Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiio.h,v 1.19 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiio.h,v 1.20 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.c:1.25 xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.c:1.26 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.c:1.25 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.c Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.c,v 1.25 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.c,v 1.26 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.h:1.14 xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.h:1.15 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.h:1.14 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.h Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.h,v 1.14 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiload.h,v 1.15 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -45,6 +45,8 @@ #else /* XFree86LOADER */ +#include <X11/Xdefs.h> + #define ATILoadSubModule(pScreenInfo, Module, SymbolList) ((pointer)1) #define ATILoadVBEModule(pScreenInfo) ((pointer)1) #define ATILoadSubModules(pScreenInfo, pATI) ((pointer)1) Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.c:1.26 xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.c:1.27 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.c:1.26 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.c Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.c,v 1.26 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.c,v 1.27 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 1999 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.h:1.9 xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.h:1.10 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.h:1.9 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.h Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.h,v 1.9 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atilock.h,v 1.10 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 1999 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.c:1.60 xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.c:1.61 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.c:1.60 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.c Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.c,v 1.60 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.c,v 1.61 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.h:1.21 xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.h:1.22 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.h:1.21 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.h Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.h,v 1.21 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64.h,v 1.22 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.c:1.12 xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.c:1.13 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.c:1.12 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.c Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.c,v 1.12 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.c,v 1.13 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.h:1.5 xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.h:1.6 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.h:1.5 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.h Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.h,v 1.5 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64accel.h,v 1.6 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.c:1.7 xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.c:1.8 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.c:1.7 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.c Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.c,v 1.7 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.c,v 1.8 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.h:1.5 xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.h:1.6 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.h:1.5 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.h Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.h,v 1.5 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64cursor.h,v 1.6 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.c:1.5 xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.c:1.6 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.c:1.5 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.c Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.c,v 1.5 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.c,v 1.6 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.h:1.5 xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.h:1.6 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.h:1.5 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.h Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.h,v 1.5 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64i2c.h,v 1.6 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.c:1.11 xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.c:1.12 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.c:1.11 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.c Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.c,v 1.11 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.c,v 1.12 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.h:1.20 xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.h:1.23 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.h:1.20 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.h Thu May 8 08:47:19 2008 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.h,v 1.20 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64io.h,v 1.23 2008/05/08 15:47:19 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -296,12 +296,14 @@ */ #if defined(GCCUSESGAS) && \ - (defined(i386) || defined(__i386) || defined(__i386__)) + (defined(i386) || defined(__i386) || defined(__i386__) || \ + defined(amd64) || defined(__amd64) || defined(__amd64__) || \ + defined(x86_64) || defined(__x86_64) || defined(__x86_64__)) #define ATIMove32(_pDst, _pSrc, _nCount) \ do \ { \ - long d0, d1, d2; \ + int d0, d1, d2; \ __asm__ __volatile__ \ ( \ "cld\n\t" \ Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.c:1.12 xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.c:1.13 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.c:1.12 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.c Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.c,v 1.12 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.c,v 1.13 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.h:1.5 xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.h:1.6 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.h:1.5 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.h Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.h,v 1.5 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimach64xv.h,v 1.6 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimisc.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimisc.c:1.16 xc/programs/Xserver/hw/xfree86/drivers/ati/atimisc.c:1.17 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimisc.c:1.16 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimisc.c Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimisc.c,v 1.16 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimisc.c,v 1.17 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.c:1.27 xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.c:1.28 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.c:1.27 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.c Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.c,v 1.27 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.c,v 1.28 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.h:1.9 xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.h:1.10 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.h:1.9 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.h Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.h,v 1.9 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimode.h,v 1.10 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.c:1.24 xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.c:1.26 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.c:1.24 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.c Wed Apr 2 14:02:31 2008 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.c,v 1.24 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.c,v 1.26 2008/04/02 21:02:31 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -149,6 +149,7 @@ "R128Chipsets", "RADEONChipsets", "atiModuleData", + "gR128EntityIndex", "gRADEONEntityIndex", NULL }; Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.h:1.13 xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.h:1.14 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.h:1.13 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.h Mon Dec 31 16:40:00 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.h,v 1.13 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimodule.h,v 1.14 2008/01/01 00:40:00 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atimono.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atimono.h:1.11 xc/programs/Xserver/hw/xfree86/drivers/ati/atimono.h:1.12 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atimono.h:1.11 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atimono.h Mon Dec 31 16:40:01 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimono.h,v 1.11 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atimono.h,v 1.12 2008/01/01 00:40:01 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.c:1.27 xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.c:1.28 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.c:1.27 Mon Jan 1 08:08:16 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.c Mon Dec 31 16:40:01 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.c,v 1.27 2007/01/01 16:08:16 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.c,v 1.28 2008/01/01 00:40:01 tsi Exp $ */ /* - * Copyright 1999 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.h:1.17 xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.h:1.18 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.h:1.17 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.h Mon Dec 31 16:40:01 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.h,v 1.17 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atioption.h,v 1.18 2008/01/01 00:40:01 tsi Exp $ */ /* - * Copyright 1999 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.c:1.92 xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.c:1.98 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.c:1.92 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.c Thu May 15 11:04:25 2008 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.c,v 1.92 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.c,v 1.98 2008/05/15 18:04:25 tsi Exp $ */ /* - * Copyright 1999 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -721,7 +721,11 @@ if ((pVideo = pATI->PCIInfo)) { if (pVideo->ioBase[1]) + { pATI->CPIOBase = pVideo->ioBase[1] + pATI->DomainIOBase; + if (pATI->IODecoding == MEMORY_IO) + pATI->IODecoding = BLOCK_IO; + } /* Set MMIO address from PCI configuration space, if available */ if ((pATI->Block0Base = pVideo->memBase[2])) @@ -1465,11 +1469,6 @@ xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, "%s adapter detected.\n", ATIAdapterNames[pATI->Adapter]); - if (pATI->Chip >= ATI_CHIP_264GT) - xf86DrvMsg(pScreenInfo->scrnIndex, X_NOTICE, - "For information on using the multimedia capabilities\n of this" - " adapter, please see http://gatos.sf.net.\n"); - if ((pATI->DAC & ~0x0FU) == ATI_DAC_INTERNAL) { xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, @@ -2321,6 +2320,19 @@ else if ((pATI->NewHW.crtc == ATI_CRTC_MACH64) || (pATI->Chip >= ATI_CHIP_264CT)) { + if (pATI->Chip >= ATI_CHIP_264VTB) + { + pATIHW->bus_cntl = inr(BUS_CNTL); + + /* + * If the MMIO area at the end of the linear aperture is found + * enabled on entry, keep it enabled, on the premise that something + * other than the server is referencing it. + */ + if (!(pATIHW->bus_cntl & BUS_APER_REG_DIS)) + pATI->MMIOInLinear = TRUE; + } + if (pATI->depth >= 8) { /* Get adapter's linear aperture configuration */ @@ -2421,7 +2433,8 @@ ServerVideoRAM = pATI->VideoRAM; - if (pATI->Cursor > ATI_CURSOR_SOFTWARE) + if ((pATI->Cursor > ATI_CURSOR_SOFTWARE) && + (pATI->NewHW.crtc == ATI_CRTC_MACH64)) { /* * Allocate a 1 kB cursor image area at the top of the @@ -2644,8 +2657,8 @@ if ((pATI->Cursor > ATI_CURSOR_SOFTWARE) && !pATI->CursorBase) { xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, - "Unable to store hardware cursor image. Reverting to software" - " cursor.\n"); + "Hardware cursor not supported in this configuration. Reverting" + " to software cursor.\n"); pATI->Cursor = ATI_CURSOR_SOFTWARE; } @@ -2918,7 +2931,7 @@ } else { - switch(pATI->DAC) + switch (pATI->DAC) { case ATI_DAC_STG1700: case ATI_DAC_STG1702: Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.h:1.10 xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.h:1.11 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.h:1.10 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.h Mon Dec 31 16:40:01 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.h,v 1.10 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atipreinit.h,v 1.11 2008/01/01 00:40:01 tsi Exp $ */ /* - * Copyright 1999 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.c:1.39 xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.c:1.41 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.c:1.39 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.c Thu Apr 24 12:31:41 2008 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.c,v 1.39 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.c,v 1.41 2008/04/24 19:31:41 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -800,7 +800,7 @@ { if (!(Index & 15)) xf86ErrorFVerb(4, "\n 0x%02X: ", Index); - xf86ErrorFVerb(4, " 0x%08lX", + xf86ErrorFVerb(4, " %08lX", (unsigned long)pciReadLong(pPCI->tag, Index)); } } Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.h:1.15 xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.h:1.16 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.h:1.15 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.h Mon Dec 31 16:40:01 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.h,v 1.15 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprint.h,v 1.16 2008/01/01 00:40:01 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atipriv.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atipriv.h:1.9 xc/programs/Xserver/hw/xfree86/drivers/ati/atipriv.h:1.10 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atipriv.h:1.9 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atipriv.h Mon Dec 31 16:40:01 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atipriv.h,v 1.9 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atipriv.h,v 1.10 2008/01/01 00:40:01 tsi Exp $ */ /* - * Copyright 1999 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.c:1.77 xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.c:1.81 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.c:1.77 Tue Feb 13 10:30:09 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.c Wed Apr 2 08:53:55 2008 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.c,v 1.77 2007/02/13 18:30:09 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.c,v 1.81 2008/04/02 15:53:55 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -1494,14 +1494,29 @@ if (ProbeFlag != DoProbe) { - if (ProbeFlag == BadRouting) - xf86MsgVerb(X_INFO, 2, - ATI_NAME ": Unshared VGA not probed in domain %d" - " due to unsuitable PCI routing.\n", Domain); - else - xf86MsgVerb(X_INFO, 2, - ATI_NAME ": Unshared VGA not probed in domain %d" - " due to an I/O conflict.\n", Domain); + switch (ProbeFlag) + { + case BadRouting: + xf86MsgVerb(X_INFO, 2, + ATI_NAME ": Unshared VGA not probed in domain" + " %d due to unsuitable PCI routing.\n", + Domain); + break; + + case Allowed: + xf86MsgVerb(X_INFO, 2, + ATI_NAME ": Unshared VGA not probed in domain" + " %d due to a potential hard-failed master" + " abort.\n", Domain); + break; + + default: + xf86MsgVerb(X_INFO, 2, + ATI_NAME ": Unshared VGA not probed in domain" + " %d due to an I/O conflict.\n", Domain); + break; + } + break; } @@ -1560,14 +1575,30 @@ if (ProbeFlag != DoProbe) { - if (ProbeFlag == BadRouting) - xf86MsgVerb(X_INFO, 2, - ATI_NAME ": Unshared 8514/A not probed in domain" - " %d due to unsuitable PCI routing.\n", Domain); - else - xf86MsgVerb(X_INFO, 2, - ATI_NAME ": Unshared 8514/A not probed in domain" - " %d due to an I/O conflict.\n", Domain); + switch (ProbeFlag) + { + case BadRouting: + xf86MsgVerb(X_INFO, 2, + ATI_NAME ": Unshared 8514/A not probed in" + " domain %d due to unsuitable PCI routing.\n", + Domain); + break; + + case Allowed: + xf86MsgVerb(X_INFO, 2, + ATI_NAME ": Unshared 8514/A not probed in" + " domain %d due to a potential hard-failed" + " master abort.\n", Domain); + break; + + default: + xf86MsgVerb(X_INFO, 2, + ATI_NAME ": Unshared 8514/A not probed in" + " domain %d due to an I/O conflict.\n", + Domain); + break; + } + break; } @@ -1627,16 +1658,33 @@ if (ProbeFlag != DoProbe) { - if (ProbeFlag == BadRouting) - xf86MsgVerb(X_INFO, 2, - ATI_NAME ": Unshared Mach64 at I/O base 0x%04X" - " not probed in domain %d due to unsuitable PCI" - " routing.\n", Mach64SparseIOBases[i], Domain); - else - xf86MsgVerb(X_INFO, 2, - ATI_NAME ": Unshared Mach64 at I/O base 0x%04X" - " not probed in domain %d due to I/O conflict.\n", - Mach64SparseIOBases[i], Domain); + switch (ProbeFlag) + { + case BadRouting: + xf86MsgVerb(X_INFO, 2, + ATI_NAME ": Unshared Mach64 at I/O base" + " 0x%04X not probed in domain %d due to" + " unsuitable PCI routing.\n", + Mach64SparseIOBases[i], Domain); + break; + + case Allowed: + xf86MsgVerb(X_INFO, 2, + ATI_NAME ": Unshared Mach64 at I/O base" + " 0x%04X not probed in domain %d due to" + " a potential hard-failed master abort.\n", + Mach64SparseIOBases[i], Domain); + break; + + default: + xf86MsgVerb(X_INFO, 2, + ATI_NAME ": Unshared Mach64 at I/O base" + " 0x%04X not probed in domain %d due to I/O" + " conflict.\n", + Mach64SparseIOBases[i], Domain); + break; + } + continue; } @@ -1657,8 +1705,8 @@ { xf86MsgVerb(X_INFO, 2, ATI_NAME ": Unshared Mach64 at I/O base 0x%04X not" - " probed in domain %d due to a potential master" - " abort.\n", Mach64SparseIOBases[i], Domain); + " probed in domain %d due to a potential hard-failed" + " master abort.\n", Mach64SparseIOBases[i], Domain); ATISetSparseIOBases(ProbeFlags, Domain, Mach64SparseIOBases[i], 4, Allowed); @@ -2261,7 +2309,7 @@ BIOSBase = ((BIOS[1] << 8) | BIOS[0]) << 4; /* Look for its BIOS */ - for(; ; BIOSBase += 0x00000200U) + for (; ; BIOSBase += 0x00000200U) { if (!BIOSBase) goto SkipBiosSegment; Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.h:1.12 xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.h:1.13 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.h:1.12 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.h Mon Dec 31 16:40:01 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.h,v 1.12 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.h,v 1.13 2008/01/01 00:40:01 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiproto.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiproto.h:1.13 xc/programs/Xserver/hw/xfree86/drivers/ati/atiproto.h:1.14 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiproto.h:1.13 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiproto.h Mon Dec 31 16:40:01 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiproto.h,v 1.13 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiproto.h,v 1.14 2008/01/01 00:40:01 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiregs.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiregs.h:1.34 xc/programs/Xserver/hw/xfree86/drivers/ati/atiregs.h:1.35 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiregs.h:1.34 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiregs.h Mon Dec 31 16:40:01 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiregs.h,v 1.34 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiregs.h,v 1.35 2008/01/01 00:40:01 tsi Exp $ */ /* - * Copyright 1994 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1994 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.c:1.9 xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.c:1.10 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.c:1.9 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.c Mon Dec 31 16:40:01 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.c,v 1.9 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.c,v 1.10 2008/01/01 00:40:01 tsi Exp $ */ /* - * Copyright 2001 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.h:1.7 xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.h:1.8 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.h:1.7 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.h Mon Dec 31 16:40:01 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.h,v 1.7 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atirgb514.h,v 1.8 2008/01/01 00:40:01 tsi Exp $ */ /* - * Copyright 2001 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.c:1.40 xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.c:1.41 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.c:1.40 Tue Jan 23 10:02:59 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.c Mon Dec 31 16:40:01 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.c,v 1.40 2007/01/23 18:02:59 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.c,v 1.41 2008/01/01 00:40:01 tsi Exp $ */ /* - * Copyright 1999 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.h:1.13 xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.h:1.14 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.h:1.13 Tue Jan 23 10:02:59 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.h Mon Dec 31 16:40:01 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.h,v 1.13 2007/01/23 18:02:59 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiscreen.h,v 1.14 2008/01/01 00:40:01 tsi Exp $ */ /* - * Copyright 1999 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atistruct.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atistruct.h:1.50 xc/programs/Xserver/hw/xfree86/drivers/ati/atistruct.h:1.51 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atistruct.h:1.50 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atistruct.h Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atistruct.h,v 1.50 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atistruct.h,v 1.51 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 1999 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1999 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.c:1.5 xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.c:1.6 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.c:1.5 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.c Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.c,v 1.5 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.c,v 1.6 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.h:1.5 xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.h:1.6 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.h:1.5 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.h Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.h,v 1.5 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atituner.h,v 1.6 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 2003 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2003 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.c:1.12 xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.c:1.13 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.c:1.12 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.c Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.c,v 1.12 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.c,v 1.13 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.h:1.12 xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.h:1.13 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.h:1.12 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.h Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.h,v 1.12 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiutil.h,v 1.13 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.c:1.22 xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.c:1.23 --- xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.c:1.22 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.c Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.c,v 1.22 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.c,v 1.23 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.h:1.13 xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.h:1.14 --- xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.h:1.13 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.h Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.h,v 1.13 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativalid.h,v 1.14 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/ativersion.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/ativersion.h:1.90 xc/programs/Xserver/hw/xfree86/drivers/ati/ativersion.h:1.95 --- xc/programs/Xserver/hw/xfree86/drivers/ati/ativersion.h:1.90 Tue Feb 13 10:30:09 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/ativersion.h Thu May 15 11:04:25 2008 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativersion.h,v 1.90 2007/02/13 18:30:09 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativersion.h,v 1.95 2008/05/15 18:04:25 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -39,7 +39,7 @@ #define ATI_VERSION_MAJOR 7 #define ATI_VERSION_MINOR 0 -#define ATI_VERSION_PATCH 14 +#define ATI_VERSION_PATCH 18 #ifndef ATI_VERSION_EXTRA #define ATI_VERSION_EXTRA "" Index: xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.c:1.28 xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.c:1.29 --- xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.c:1.28 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.c Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.c,v 1.28 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.c,v 1.29 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.h:1.15 xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.h:1.16 --- xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.h:1.15 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.h Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.h,v 1.15 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.h,v 1.16 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.c:1.10 xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.c:1.11 --- xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.c:1.10 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.c Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.c,v 1.10 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.c,v 1.11 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.h:1.10 xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.h:1.11 --- xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.h:1.10 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.h Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.h,v 1.10 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativgaio.h,v 1.11 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.c:1.22 xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.c:1.23 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.c:1.22 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.c Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.c,v 1.22 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.c,v 1.23 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.h:1.13 xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.h:1.14 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.h:1.13 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.h Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.h,v 1.13 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atividmem.h,v 1.14 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.c:1.19 xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.c:1.20 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.c:1.19 Mon Jan 1 08:08:17 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.c Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.c,v 1.19 2007/01/01 16:08:17 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.c,v 1.20 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.h:1.14 xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.h:1.15 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.h:1.14 Mon Jan 1 08:08:18 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.h Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.h,v 1.14 2007/01/01 16:08:18 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonder.h,v 1.15 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 1997 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 1997 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.c:1.9 xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.c:1.10 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.c:1.9 Mon Jan 1 08:08:18 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.c Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.c,v 1.9 2007/01/01 16:08:18 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.c,v 1.10 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.h:1.9 xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.h:1.10 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.h:1.9 Mon Jan 1 08:08:18 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.h Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.h,v 1.9 2007/01/01 16:08:18 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atiwonderio.h,v 1.10 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.c:1.11 xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.c:1.12 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.c:1.11 Mon Jan 1 08:08:18 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.c Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.c,v 1.11 2007/01/01 16:08:18 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.c,v 1.12 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 2001 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.h:1.8 xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.h:1.9 --- xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.h:1.8 Mon Jan 1 08:08:18 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.h Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.h,v 1.8 2007/01/01 16:08:18 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/atixv.h,v 1.9 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 2001 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2001 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h:1.29 xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h:1.30 --- xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h:1.29 Tue Jan 9 09:04:45 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h Wed Apr 2 13:47:57 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h,v 1.29 2007/01/09 17:04:45 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h,v 1.30 2008/04/02 20:47:57 tsi Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and @@ -134,6 +134,13 @@ /* CRTC2 registers */ CARD32 crtc2_gen_cntl; + CARD32 crtc2_h_total_disp; + CARD32 crtc2_h_sync_strt_wid; + CARD32 crtc2_v_total_disp; + CARD32 crtc2_v_sync_strt_wid; + CARD32 crtc2_offset; + CARD32 crtc2_offset_cntl; + CARD32 crtc2_pitch; /* Flat panel registers */ CARD32 fp_crtc_h_total_disp; @@ -159,13 +166,29 @@ CARD32 ppll_div_3; CARD32 htotal_cntl; + /* Computed values for PLL2 */ + CARD32 dot_clock_freq_2; + CARD32 pll_output_freq_2; + int feedback_div_2; + int post_div_2; + + /* PLL2 registers */ + CARD32 p2pll_ref_div; + CARD32 p2pll_div_0; + CARD32 htotal_cntl2; + /* DDA register */ CARD32 dda_config; CARD32 dda_on_off; + /* DDA2 register */ + CARD32 dda2_config; + CARD32 dda2_on_off; + /* Pallet */ Bool palette_valid; CARD32 palette[256]; + CARD32 palette2[256]; } R128SaveRec, *R128SavePtr; typedef struct { @@ -185,6 +208,16 @@ DisplayModePtr mode; } R128FBLayout; +typedef enum +{ + MT_NONE, + MT_CRT, + MT_LCD, + MT_DFP, + MT_CTV, + MT_STV +} R128MonitorType; + typedef struct { EntityInfoPtr pEnt; pciVideoPtr PciInfo; @@ -301,7 +334,7 @@ Bool IsPCI; /* Current card is a PCI card */ drmSize pciSize; drm_handle_t pciMemHandle; - unsigned char *PCI; /* Map */ + drmAddress PCI; /* Map */ Bool allowPageFlip; /* Enable 3d page flipping */ Bool have3DWindows; /* Are there any 3d clients? */ @@ -310,7 +343,7 @@ drmSize agpSize; drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ unsigned long agpOffset; - unsigned char *AGP; /* Map */ + drmAddress AGP; /* Map */ int agpMode; Bool CCEInUse; /* CCE is currently active */ @@ -324,20 +357,20 @@ drm_handle_t ringHandle; /* Handle from drmAddMap */ drmSize ringMapSize; /* Size of map */ int ringSize; /* Size of ring (in MB) */ - unsigned char *ring; /* Map */ + drmAddress ring; /* Map */ int ringSizeLog2QW; unsigned long ringReadOffset; /* Offset into AGP space */ drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ drmSize ringReadMapSize; /* Size of map */ - unsigned char *ringReadPtr; /* Map */ + drmAddress ringReadPtr; /* Map */ /* CCE vertex/indirect buffer data */ unsigned long bufStart; /* Offset into AGP space */ drm_handle_t bufHandle; /* Handle from drmAddMap */ drmSize bufMapSize; /* Size of map */ int bufSize; /* Size of buffers (in MB) */ - unsigned char *buf; /* Map */ + drmAddress buf; /* Map */ int bufNumBufs; /* Number of buffers */ drmBufMapPtr buffers; /* Buffer map */ @@ -346,7 +379,7 @@ drm_handle_t agpTexHandle; /* Handle from drmAddMap */ drmSize agpTexMapSize; /* Size of map */ int agpTexSize; /* Size of AGP tex space (in MB) */ - unsigned char *agpTex; /* Map */ + drmAddress agpTex; /* Map */ int log2AGPTexGran; /* CCE 2D accleration */ @@ -400,6 +433,16 @@ I2CBusPtr pI2CBus; CARD32 DDCReg; + /****** Added for dualhead support *******************/ + Bool HasCRTC2; /* M3/M4 */ + Bool IsSecondary; /* second Screen */ + Bool IsPrimary; /* primary Screen */ + Bool UseCRT; /* force use CRT port as primary */ + Bool SwitchingMode; + R128MonitorType DisplayType; /* Monitor connected on */ + + Bool UseVGAHW; + } R128InfoRec, *R128InfoPtr; #define R128WaitForFifo(pScrn, entries) \ Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.man diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/r128.man:1.4 xc/programs/Xserver/hw/xfree86/drivers/ati/r128.man:1.5 --- xc/programs/Xserver/hw/xfree86/drivers/ati/r128.man:1.4 Tue Jun 4 16:04:50 2002 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128.man Wed Apr 2 13:47:58 2008 @@ -1,4 +1,4 @@ -.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.man,v 1.4 2002/06/04 23:04:50 dawes Exp $ +.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.man,v 1.5 2008/04/02 20:47:58 tsi Exp $ .\" shorthand for double quote that works everywhere. .ds q \N'34' .TH R128 __drivermansuffix__ __vendorversion__ @@ -19,7 +19,8 @@ acceleration of drawing primitives, hardware cursor, video modes up to 1800x1440 @ 70Hz, doublescan modes (e.g., 320x200 and 320x240), gamma correction at all pixel depths, a fully programming dot clock and robust -text mode restoration for VT switching. +text mode restoration for VT switching. Dualhead is supported on M3/M4 +mobile chips. .SH SUPPORTED HARDWARE The .B r128 @@ -124,6 +125,13 @@ Enable or disable viewing offscreen cache memory. A development debug option. Default: off. +.PP +.B Dualhead Note: +The video BIOS on some laptops interacts strangely with dualhead. +This can result in flickering and problems changing modes on crtc2. +If you experience these problems, try toggling your laptop's video +output switch (e.g. fn-f7, etc.) prior to starting X or switch to +another VT and back. .SH "SEE ALSO" XFree86(1), XF86Config(__filemansuffix__), xf86config(1), Xserver(1), X(__miscmansuffix__) .SH AUTHORS Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_accel.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/r128_accel.c:1.21 xc/programs/Xserver/hw/xfree86/drivers/ati/r128_accel.c:1.22 --- xc/programs/Xserver/hw/xfree86/drivers/ati/r128_accel.c:1.21 Mon Jan 24 08:58:35 2005 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128_accel.c Wed Apr 2 13:47:58 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_accel.c,v 1.21 2005/01/24 16:58:35 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_accel.c,v 1.22 2008/04/02 20:47:58 tsi Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and @@ -82,6 +82,7 @@ /* Driver data structures */ #include "r128.h" #include "r128_reg.h" +#include "r128_probe.h" #ifdef XF86DRI #include "r128_sarea.h" #define _XF86DRI_SERVER_ @@ -117,6 +118,8 @@ { R128_ROP3_ONE, R128_ROP3_ONE } /* GXset */ }; +extern int gR128EntityIndex; + /* Flush all dirty data in the Pixel Cache to memory. */ void R128EngineFlush(ScrnInfoPtr pScrn) { @@ -240,17 +243,23 @@ i = 0; do { ret = drmCommandNone(info->drmFD, DRM_R128_CCE_IDLE); - } while ( ret && errno == EBUSY && i++ < R128_IDLE_RETRY ); + } while ( ret && errno == EBUSY && i++ < (R128_IDLE_RETRY * R128_IDLE_RETRY) ); if (ret && ret != -EBUSY) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s: CCE idle %d\n", __FUNCTION__, ret); } + if (i > R128_IDLE_RETRY) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "%s: (DEBUG) CCE idle took i = %d\n", __FUNCTION__, i); + } + if (ret == 0) return; xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Idle timed out, resetting engine...\n"); + R128CCE_STOP(pScrn, info); R128EngineReset(pScrn); /* Always restart the engine when doing CCE 2D acceleration */ @@ -1020,7 +1029,7 @@ R128TRACE(("Pitch for acceleration = %d\n", info->pitch)); R128WaitForFifo(pScrn, 2); - OUTREG(R128_DEFAULT_OFFSET, 0); + OUTREG(R128_DEFAULT_OFFSET, pScrn->fbOffset); OUTREG(R128_DEFAULT_PITCH, info->pitch); R128WaitForFifo(pScrn, 4); @@ -1644,6 +1653,24 @@ &indirect, sizeof(drmR128Indirect)); } +/* This callback is required for multihead cards using XAA */ +static +void R128RestoreCCEAccelState(ScrnInfoPtr pScrn) +{ + R128InfoPtr info = R128PTR(pScrn); +/* unsigned char *R128MMIO = info->MMIO; needed for OUTREG below */ + /*xf86DrvMsg(pScrn->scrnIndex, X_INFO, "===>RestoreCP\n");*/ + + R128WaitForFifo(pScrn, 1); +/* is this needed on r128 + OUTREG( R128_DEFAULT_OFFSET, info->frontPitchOffset); +*/ + R128WaitForIdle(pScrn); + + /* FIXME: May need to restore other things, + like BKGD_CLK FG_CLK...*/ +} + static void R128CCEAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a) { R128InfoPtr info = R128PTR(pScrn); @@ -1704,9 +1731,29 @@ | HARDWARE_PATTERN_PROGRAMMED_ORIGIN | HARDWARE_PATTERN_SCREEN_ORIGIN | BIT_ORDER_IN_BYTE_LSBFIRST); + + if(!info->IsSecondary && xf86IsEntityShared(pScrn->entityList[0])) + a->RestoreAccelState = R128RestoreCCEAccelState; } #endif +/* This callback is required for multihead cards using XAA */ +static +void R128RestoreAccelState(ScrnInfoPtr pScrn) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + + R128WaitForFifo(pScrn, 2); + OUTREG(R128_DEFAULT_OFFSET, pScrn->fbOffset); + OUTREG(R128_DEFAULT_PITCH, info->pitch); + + /* FIXME: May need to restore other things, + like BKGD_CLK FG_CLK...*/ + + R128WaitForIdle(pScrn); +} + static void R128MMIOAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a) { R128InfoPtr info = R128PTR(pScrn); @@ -1785,6 +1832,20 @@ | LEFT_EDGE_CLIPPING | LEFT_EDGE_CLIPPING_NEGATIVE_X | SCANLINE_PAD_DWORD; + + if(xf86IsEntityShared(pScrn->entityList[0])) + { + DevUnion* pPriv; + R128EntPtr pR128Ent; + pPriv = xf86GetEntityPrivate(pScrn->entityList[0], gR128EntityIndex); + pR128Ent = pPriv->ptr; + + /*if there are more than one devices sharing this entity, we + have to assign this call back, otherwise the XAA will be + disabled */ + if(pR128Ent->HasSecondary || pR128Ent->BypassSecondary) + a->RestoreAccelState = R128RestoreAccelState; + } } /* Initialize XAA for supported acceleration and also initialize the Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_cursor.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/r128_cursor.c:1.6 xc/programs/Xserver/hw/xfree86/drivers/ati/r128_cursor.c:1.7 --- xc/programs/Xserver/hw/xfree86/drivers/ati/r128_cursor.c:1.6 Thu Feb 13 12:28:40 2003 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128_cursor.c Wed Apr 2 13:47:58 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_cursor.c,v 1.6 2003/02/13 20:28:40 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_cursor.c,v 1.7 2008/04/02 20:47:58 tsi Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and @@ -72,8 +72,16 @@ R128InfoPtr info = R128PTR(pScrn); unsigned char *R128MMIO = info->MMIO; - OUTREG(R128_CUR_CLR0, bg); - OUTREG(R128_CUR_CLR1, fg); + if(info->IsSecondary) + { + OUTREG(R128_CUR2_CLR0, bg); + OUTREG(R128_CUR2_CLR1, fg); + } + else + { + OUTREG(R128_CUR_CLR0, bg); + OUTREG(R128_CUR_CLR1, fg); + } } /* Set cursor position to (x,y) with offset into cursor bitmap at @@ -94,11 +102,25 @@ if (xorigin >= cursor->MaxWidth) xorigin = cursor->MaxWidth - 1; if (yorigin >= cursor->MaxHeight) yorigin = cursor->MaxHeight - 1; - OUTREG(R128_CUR_HORZ_VERT_OFF, R128_CUR_LOCK | (xorigin << 16) | yorigin); - OUTREG(R128_CUR_HORZ_VERT_POSN, (R128_CUR_LOCK + if(!info->IsSecondary) + { + OUTREG(R128_CUR_HORZ_VERT_OFF, R128_CUR_LOCK | (xorigin << 16) | yorigin); + OUTREG(R128_CUR_HORZ_VERT_POSN, (R128_CUR_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y))); - OUTREG(R128_CUR_OFFSET, info->cursor_start + yorigin * 16); + OUTREG(R128_CUR_OFFSET, info->cursor_start + yorigin * 16); + } + else + { + OUTREG(R128_CUR2_HORZ_VERT_OFF, (R128_CUR2_LOCK + | (xorigin << 16) + | yorigin)); + OUTREG(R128_CUR2_HORZ_VERT_POSN, (R128_CUR2_LOCK + | ((xorigin ? 0 : x) << 16) + | (yorigin ? 0 : y))); + OUTREG(R128_CUR2_OFFSET, + info->cursor_start + pScrn->fbOffset + yorigin * 16); + } } /* Copy cursor image from `image' to video memory. R128SetCursorPosition @@ -112,8 +134,16 @@ int y; CARD32 save; - save = INREG(R128_CRTC_GEN_CNTL); - OUTREG(R128_CRTC_GEN_CNTL, save & (CARD32)~R128_CRTC_CUR_EN); + if(!info->IsSecondary) + { + save = INREG(R128_CRTC_GEN_CNTL); + OUTREG(R128_CRTC_GEN_CNTL, save & (CARD32)~R128_CRTC_CUR_EN); + } + else + { + save = INREG(R128_CRTC2_GEN_CNTL); + OUTREG(R128_CRTC2_GEN_CNTL, save & (CARD32)~R128_CRTC2_CUR_EN); + } #if X_BYTE_ORDER == X_BIG_ENDIAN switch(info->CurrentLayout.pixel_bytes) { @@ -169,7 +199,11 @@ } - OUTREG(R128_CRTC_GEN_CNTL, save); + if(!info->IsSecondary) + OUTREG(R128_CRTC_GEN_CNTL, save); + else + OUTREG(R128_CRTC2_GEN_CNTL, save); + } /* Hide hardware cursor. */ @@ -178,7 +212,10 @@ R128InfoPtr info = R128PTR(pScrn); unsigned char *R128MMIO = info->MMIO; - OUTREGP(R128_CRTC_GEN_CNTL, 0, ~R128_CRTC_CUR_EN); + if(info->IsSecondary) + OUTREGP(R128_CRTC2_GEN_CNTL, 0, ~R128_CRTC2_CUR_EN); + else + OUTREGP(R128_CRTC_GEN_CNTL, 0, ~R128_CRTC_CUR_EN); } /* Show hardware cursor. */ @@ -187,7 +224,10 @@ R128InfoPtr info = R128PTR(pScrn); unsigned char *R128MMIO = info->MMIO; - OUTREGP(R128_CRTC_GEN_CNTL, R128_CRTC_CUR_EN, ~R128_CRTC_CUR_EN); + if(info->IsSecondary) + OUTREGP(R128_CRTC2_GEN_CNTL, R128_CRTC2_CUR_EN, ~R128_CRTC2_CUR_EN); + else + OUTREGP(R128_CRTC_GEN_CNTL, R128_CRTC_CUR_EN, ~R128_CRTC_CUR_EN); } /* Determine if hardware cursor is in use. */ Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.c:1.34 xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.c:1.35 --- xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.c:1.34 Tue Jan 9 09:04:45 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.c Wed Apr 2 13:47:58 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.c,v 1.34 2007/01/09 17:04:45 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_dri.c,v 1.35 2008/04/02 20:47:58 tsi Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and @@ -243,7 +243,7 @@ } pConfigs[i].auxBuffers = 0; pConfigs[i].level = 0; - if (accum || stencil) { + if (accum) { pConfigs[i].visualRating = GLX_SLOW_CONFIG; } else { pConfigs[i].visualRating = GLX_NONE; @@ -525,7 +525,7 @@ "[agp] ring handle = 0x%08lx\n", info->ringHandle); if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize, - (drmAddressPtr)&info->ring) < 0) { + &info->ring) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n"); return FALSE; } @@ -544,7 +544,7 @@ info->ringReadPtrHandle); if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize, - (drmAddressPtr)&info->ringReadPtr) < 0) { + &info->ringReadPtr) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring read ptr\n"); return FALSE; @@ -564,7 +564,7 @@ info->bufHandle); if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize, - (drmAddressPtr)&info->buf) < 0) { + &info->buf) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map vertex/indirect buffers\n"); return FALSE; @@ -584,7 +584,7 @@ info->agpTexHandle); if (drmMap(info->drmFD, info->agpTexHandle, info->agpTexMapSize, - (drmAddressPtr)&info->agpTex) < 0) { + &info->agpTex) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map AGP texture map\n"); return FALSE; @@ -669,7 +669,7 @@ "[pci] ring handle = 0x%08lx\n", info->ringHandle); if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize, - (drmAddressPtr)&info->ring) < 0) { + &info->ring) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n"); return FALSE; } @@ -691,7 +691,7 @@ info->ringReadPtrHandle); if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize, - (drmAddressPtr)&info->ringReadPtr) < 0) { + &info->ringReadPtr) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring read ptr\n"); return FALSE; @@ -714,7 +714,7 @@ info->bufHandle); if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize, - (drmAddressPtr)&info->buf) < 0) { + &info->buf) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map vertex/indirect buffers\n"); return FALSE; @@ -1297,6 +1297,7 @@ if (info->irq) { drmCtlUninstHandler(info->drmFD); info->irq = 0; + info->gen_int_cntl = 0; } /* De-allocate vertex buffers */ Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c:1.97 xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c:1.100 --- xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c:1.97 Tue Jan 23 10:02:59 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c Sun Apr 6 12:17:40 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c,v 1.97 2007/01/23 18:02:59 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c,v 1.100 2008/04/06 19:17:40 tsi Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and @@ -178,6 +178,7 @@ static const char *vgahwSymbols[] = { "vgaHWFreeHWRec", "vgaHWGetHWRec", + "vgaHWGetIOBase", "vgaHWGetIndex", "vgaHWLock", "vgaHWRestore", @@ -217,7 +218,6 @@ static const char *ddcSymbols[] = { "xf86PrintEDID", - "xf86DoEDID_DDC1", "xf86DoEDID_DDC2", NULL }; @@ -244,6 +244,7 @@ static const char *ramdacSymbols[] = { "xf86CreateCursorInfoRec", "xf86DestroyCursorInfoRec", + "xf86ForceHWCursor", "xf86InitCursor", NULL }; @@ -346,6 +347,16 @@ NULL); } +extern int gR128EntityIndex; + +static R128EntPtr R128EntPriv(ScrnInfoPtr pScrn) +{ + DevUnion *pPriv; + R128InfoPtr info = R128PTR(pScrn); + pPriv = xf86GetEntityPrivate(info->pEnt->index, gR128EntityIndex); + return pPriv->ptr; +} + /* Allocate our private R128InfoRec. */ static Bool R128GetRec(ScrnInfoPtr pScrn) { @@ -455,7 +466,7 @@ R128InfoPtr info = R128PTR(pScrn); unsigned char *R128MMIO = info->MMIO; - OUTREG8(R128_CLOCK_CNTL_INDEX, addr & 0x1f); + OUTREG8(R128_CLOCK_CNTL_INDEX, addr & 0x3f); return INREG(R128_CLOCK_CNTL_DATA); } @@ -489,10 +500,30 @@ { R128InfoPtr info = R128PTR(pScrn); unsigned char *R128MMIO = info->MMIO; - if(info->isDFP) - OUTREGP(R128_FP_GEN_CNTL, R128_FP_BLANK_DIS, ~R128_FP_BLANK_DIS); + + if(!info->IsSecondary) + { + switch(info->DisplayType) + { + case MT_LCD: + OUTREGP(R128_LVDS_GEN_CNTL, R128_LVDS_DISPLAY_DIS, + ~R128_LVDS_DISPLAY_DIS); + break; + case MT_CRT: + OUTREGP(R128_CRTC_EXT_CNTL, R128_CRTC_DISPLAY_DIS, ~R128_CRTC_DISPLAY_DIS); + break; + case MT_DFP: + OUTREGP(R128_FP_GEN_CNTL, R128_FP_BLANK_DIS, ~R128_FP_BLANK_DIS); + break; + case MT_NONE: + default: + break; + } + } else - OUTREGP(R128_CRTC_EXT_CNTL, R128_CRTC_DISPLAY_DIS, ~R128_CRTC_DISPLAY_DIS); + { + OUTREGP(R128_CRTC2_GEN_CNTL, R128_CRTC2_DISP_DIS, ~R128_CRTC2_DISP_DIS); + } } /* Unblank screen. */ @@ -501,12 +532,39 @@ R128InfoPtr info = R128PTR(pScrn); unsigned char *R128MMIO = info->MMIO; - if(info->isDFP) - OUTREGP(R128_FP_GEN_CNTL, 0, ~R128_FP_BLANK_DIS); + if(!info->IsSecondary) + { + switch(info->DisplayType) + { + case MT_LCD: + OUTREGP(R128_LVDS_GEN_CNTL, 0, + ~R128_LVDS_DISPLAY_DIS); + break; + case MT_CRT: + OUTREGP(R128_CRTC_EXT_CNTL, 0, ~R128_CRTC_DISPLAY_DIS); + break; + case MT_DFP: + OUTREGP(R128_FP_GEN_CNTL, 0, ~R128_FP_BLANK_DIS); + break; + case MT_NONE: + default: + break; + } + } else - OUTREGP(R128_CRTC_EXT_CNTL, 0, ~(R128_CRTC_DISPLAY_DIS | - R128_CRTC_VSYNC_DIS | - R128_CRTC_HSYNC_DIS)); + { + switch(info->DisplayType) + { + case MT_LCD: + case MT_DFP: + case MT_CRT: + OUTREGP(R128_CRTC2_GEN_CNTL, 0, ~R128_CRTC2_DISP_DIS); + break; + case MT_NONE: + default: + break; + } + } } /* Compute log base 2 of val. */ @@ -553,14 +611,23 @@ } else { xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, R128_VBIOS_SIZE); if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { + if (!xf86DomainHasBIOSSegments(xf86GetPciDomain(info->PciTag))) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "x86 video BIOS not available\n"); + xfree(info->VBIOS); + info->VBIOS = NULL; + return FALSE; + } + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Video BIOS not detected in PCI space!\n"); xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Attempting to read Video BIOS from legacy ISA space!\n"); + "Attempting to read Video BIOS from ISA space!\n"); info->BIOSAddr = 0x000c0000; xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, R128_VBIOS_SIZE, info->VBIOS); } } + if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { info->BIOSAddr = 0x00000000; xfree(info->VBIOS); @@ -569,7 +636,62 @@ "Video BIOS not found!\n"); } - if (info->VBIOS && info->HasPanelRegs) { + if (info->HasCRTC2) { + if (info->IsSecondary) { + /* there may be a way to detect this, for now, just assume + second head is CRT */ + info->DisplayType = MT_CRT; + + if (info->DisplayType > MT_NONE) { + DevUnion* pPriv; + R128EntPtr pR128Ent; + pPriv = xf86GetEntityPrivate(pScrn->entityList[0], + gR128EntityIndex); + pR128Ent = pPriv->ptr; + pR128Ent->HasSecondary = TRUE; + } else return FALSE; + } else { + /* really need some sort of detection here */ + if (info->HasPanelRegs) { + info->DisplayType = MT_LCD; + } else if (info->isDFP) { + info->DisplayType = MT_DFP; + } else { + /* DVI port has no monitor connected, try CRT port. + If something on CRT port, treat it as primary */ + if (xf86IsEntityShared(pScrn->entityList[0])) { + DevUnion* pPriv; + R128EntPtr pR128Ent; + pPriv = xf86GetEntityPrivate(pScrn->entityList[0], + gR128EntityIndex); + pR128Ent = pPriv->ptr; + pR128Ent->BypassSecondary = TRUE; + } + + info->DisplayType = MT_CRT; +#if 0 + { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "No monitor detected!!!\n"); + return FALSE; + } +#endif + } + } + } else { + /* Regular Radeon ASIC, only one CRTC, but it could be + used for DFP with a DVI output, like AIW board */ + if (info->isDFP) + info->DisplayType = MT_DFP; + else + info->DisplayType = MT_CRT; + } + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s Display == Type %d\n", + (info->IsSecondary ? "Secondary" : "Primary"), + info->DisplayType); + + if (info->VBIOS && info->DisplayType == MT_LCD) { info->FPBIOSstart = 0; /* FIXME: There should be direct access to the start of the FP info @@ -640,10 +762,10 @@ } if (!info->PanelXRes || !info->PanelYRes) { - info->HasPanelRegs = FALSE; - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Can't determine panel dimensions, and none specified. \ - Disabling programming of FP registers.\n"); + info->HasPanelRegs = FALSE; + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Can't determine panel dimensions, and none specified.\n" + "\tDisabling programming of FP registers.\n"); } return TRUE; @@ -915,12 +1037,13 @@ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "\n\nWARNING: Forcing the driver to use/not use the flat panel registers\nmight damage your flat panel. Use at your *OWN* *RISK*.\n\n"); } else { - info->isDFP = FALSE; - info->isPro2 = FALSE; + info->isDFP = FALSE; + info->isPro2 = FALSE; + info->HasCRTC2 = FALSE; switch (info->Chipset) { /* R128 Pro and Pro2 can have DFP, we will deal with it. No support for dual-head/xinerama yet. - M3 can also have DFP, no support for now */ + M3 can also have DFP, no support for now */ case PCI_CHIP_RAGE128TF: case PCI_CHIP_RAGE128TL: case PCI_CHIP_RAGE128TR: @@ -966,7 +1089,11 @@ case PCI_CHIP_RAGE128LE: case PCI_CHIP_RAGE128LF: case PCI_CHIP_RAGE128MF: - case PCI_CHIP_RAGE128ML: info->HasPanelRegs = TRUE; break; + case PCI_CHIP_RAGE128ML: + info->HasPanelRegs = TRUE; + /* which chips support dualhead? */ + info->HasCRTC2 = TRUE; + break; case PCI_CHIP_RAGE128RE: case PCI_CHIP_RAGE128RF: case PCI_CHIP_RAGE128RG: @@ -1008,12 +1135,14 @@ config file setting. BIOS_5_SCRATCH holds the display device on flat panel systems only. */ if (info->HasPanelRegs) { - char *Display = xf86GetOptValString(info->Options, OPTION_DISPLAY); + char *Display = xf86GetOptValString(info->Options, OPTION_DISPLAY); if (info->FBDev) xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Option \"Display\" ignored " "(framebuffer device determines display type)\n"); + else if (info->IsPrimary || info->IsSecondary) + info->BIOSDisplay = R128_DUALHEAD; else if (!Display || !xf86NameCmp(Display, "FP")) info->BIOSDisplay = R128_BIOS_DISPLAY_FP; else if (!xf86NameCmp(Display, "BIOS")) @@ -1070,13 +1199,35 @@ from = X_CONFIG; pScrn->videoRam = dev->videoRam; } - pScrn->videoRam &= ~1023; - info->FbMapSize = pScrn->videoRam * 1024; + xf86DrvMsg(pScrn->scrnIndex, from, "VideoRAM: %d kByte (%s)\n", pScrn->videoRam, info->ram->name); + if (info->IsPrimary) { + pScrn->videoRam /= 2; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Using %dk of videoram for primary head\n", + pScrn->videoRam); + } + + if (info->IsSecondary) { + pScrn->videoRam /= 2; + info->LinearAddr += pScrn->videoRam * 1024; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Using %dk of videoram for secondary head\n", + pScrn->videoRam); + } + + pScrn->videoRam &= ~1023; + info->FbMapSize = pScrn->videoRam * 1024; + + /* Flat panel (part 2) */ switch (info->BIOSDisplay) { + case R128_DUALHEAD: + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, + "Dual display\n"); + break; case R128_BIOS_DISPLAY_FP: xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Using flat panel for display\n"); @@ -1203,7 +1354,7 @@ if (!pVbe) { ret = FALSE; } else { - xf86SetDDCproperties(pScrn,xf86PrintEDID(vbeDoEDID(pVbe,pModule))); + xf86SetDDCproperties(pScrn,xf86PrintEDID(vbeDoEDID(pVbe,pModule))); vbeFree(pVbe); ret = TRUE; } @@ -1247,7 +1398,7 @@ unsigned char *R128MMIO = info->MMIO; val = INREG(info->DDCReg) - & ~(CARD32)(R128_GPIO_MONID_EN_0 | R128_GPIO_MONID_EN_3); + & ~(CARD32)(R128_GPIO_MONID_EN_0 | R128_GPIO_MONID_EN_3); val |= (Clock ? 0:R128_GPIO_MONID_EN_3); val |= (data ? 0:R128_GPIO_MONID_EN_0); OUTREG(info->DDCReg, val); @@ -1260,10 +1411,10 @@ R128InfoPtr info = R128PTR(pScrn); ModuleDescPtr pModule; if ((pModule = xf86LoadSubModule(pScrn, "i2c")) ) - xf86LoaderModReqSymLists(pModule, i2cSymbols,NULL); + xf86LoaderModReqSymLists(pModule, i2cSymbols,NULL); else{ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Failed to load i2c module\n"); + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Failed to load i2c module\n"); return FALSE; } @@ -1278,7 +1429,7 @@ info->pI2CBus->AcknTimeout = 5; if (!xf86I2CBusInit(info->pI2CBus)) { - return FALSE; + return FALSE; } return TRUE; } @@ -1293,47 +1444,49 @@ unsigned char *R128MMIO = info->MMIO; if(!R128I2cInit(pScrn)){ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "I2C initialization failed!\n"); + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "I2C initialization failed!\n"); } OUTREG(info->DDCReg, (INREG(info->DDCReg) - | R128_GPIO_MONID_MASK_0 | R128_GPIO_MONID_MASK_3)); + | R128_GPIO_MONID_MASK_0 | R128_GPIO_MONID_MASK_3)); OUTREG(info->DDCReg, INREG(info->DDCReg) - & ~(CARD32)(R128_GPIO_MONID_A_0 | R128_GPIO_MONID_A_3)); + & ~(CARD32)(R128_GPIO_MONID_A_0 | R128_GPIO_MONID_A_3)); MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, info->pI2CBus); if(!MonInfo) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "No DFP detected\n"); - return FALSE; + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "No DFP detected\n"); + return FALSE; } xf86SetDDCproperties(pScrn, MonInfo); ddc = pScrn->monitor->DDC; for(i=0; i<4; i++) { - if(ddc->det_mon[i].type == 0) - { - info->PanelXRes = - ddc->det_mon[i].section.d_timings.h_active; - info->PanelYRes = - ddc->det_mon[i].section.d_timings.v_active; - - info->HOverPlus = - ddc->det_mon[i].section.d_timings.h_sync_off; - info->HSyncWidth = - ddc->det_mon[i].section.d_timings.h_sync_width; - info->HBlank = - ddc->det_mon[i].section.d_timings.h_blanking; - info->VOverPlus = - ddc->det_mon[i].section.d_timings.v_sync_off; - info->VSyncWidth = - ddc->det_mon[i].section.d_timings.v_sync_width; - info->VBlank = - ddc->det_mon[i].section.d_timings.v_blanking; - } + if((ddc->det_mon[i].type == 0) && + (ddc->det_mon[i].section.d_timings.h_active > 0) && + (ddc->det_mon[i].section.d_timings.v_active > 0)) + { + info->PanelXRes = + ddc->det_mon[i].section.d_timings.h_active; + info->PanelYRes = + ddc->det_mon[i].section.d_timings.v_active; + + info->HOverPlus = + ddc->det_mon[i].section.d_timings.h_sync_off; + info->HSyncWidth = + ddc->det_mon[i].section.d_timings.h_sync_width; + info->HBlank = + ddc->det_mon[i].section.d_timings.h_blanking; + info->VOverPlus = + ddc->det_mon[i].section.d_timings.v_sync_off; + info->VSyncWidth = + ddc->det_mon[i].section.d_timings.v_sync_width; + info->VBlank = + ddc->det_mon[i].section.d_timings.v_blanking; + } } return TRUE; } @@ -1345,120 +1498,120 @@ xf86MonPtr ddc = pScrn->monitor->DDC; if(flag) /*HSync*/ { - for(i=0; i<4; i++) - { - if(ddc->det_mon[i].type == DS_RANGES) - { - pScrn->monitor->nHsync = 1; - pScrn->monitor->hsync[0].lo = - ddc->det_mon[i].section.ranges.min_h; - pScrn->monitor->hsync[0].hi = - ddc->det_mon[i].section.ranges.max_h; - return; - } - } - /*if no sync ranges detected in detailed timing table, - let's try to derive them from supported VESA modes - Are we doing too much here!!!? - **/ - i = 0; - if(ddc->timings1.t1 & 0x02) /*800x600@56*/ - { - pScrn->monitor->hsync[i].lo = - pScrn->monitor->hsync[i].hi = 35.2; - i++; - } - if(ddc->timings1.t1 & 0x04) /*640x480@75*/ - { - pScrn->monitor->hsync[i].lo = - pScrn->monitor->hsync[i].hi = 37.5; - i++; - } - if((ddc->timings1.t1 & 0x08) || (ddc->timings1.t1 & 0x01)) - { - pScrn->monitor->hsync[i].lo = - pScrn->monitor->hsync[i].hi = 37.9; - i++; - } - if(ddc->timings1.t2 & 0x40) - { - pScrn->monitor->hsync[i].lo = - pScrn->monitor->hsync[i].hi = 46.9; - i++; - } - if((ddc->timings1.t2 & 0x80) || (ddc->timings1.t2 & 0x08)) - { - pScrn->monitor->hsync[i].lo = - pScrn->monitor->hsync[i].hi = 48.1; - i++; - } - if(ddc->timings1.t2 & 0x04) - { - pScrn->monitor->hsync[i].lo = - pScrn->monitor->hsync[i].hi = 56.5; - i++; - } - if(ddc->timings1.t2 & 0x02) - { - pScrn->monitor->hsync[i].lo = - pScrn->monitor->hsync[i].hi = 60.0; - i++; - } - if(ddc->timings1.t2 & 0x01) - { - pScrn->monitor->hsync[i].lo = - pScrn->monitor->hsync[i].hi = 64.0; - i++; - } - pScrn->monitor->nHsync = i; + for(i=0; i<4; i++) + { + if(ddc->det_mon[i].type == DS_RANGES) + { + pScrn->monitor->nHsync = 1; + pScrn->monitor->hsync[0].lo = + ddc->det_mon[i].section.ranges.min_h; + pScrn->monitor->hsync[0].hi = + ddc->det_mon[i].section.ranges.max_h; + return; + } + } + /*if no sync ranges detected in detailed timing table, + let's try to derive them from supported VESA modes + Are we doing too much here!!!? + **/ + i = 0; + if(ddc->timings1.t1 & 0x02) /*800x600@56*/ + { + pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].hi = 35.2; + i++; + } + if(ddc->timings1.t1 & 0x04) /*640x480@75*/ + { + pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].hi = 37.5; + i++; + } + if((ddc->timings1.t1 & 0x08) || (ddc->timings1.t1 & 0x01)) + { + pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].hi = 37.9; + i++; + } + if(ddc->timings1.t2 & 0x40) + { + pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].hi = 46.9; + i++; + } + if((ddc->timings1.t2 & 0x80) || (ddc->timings1.t2 & 0x08)) + { + pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].hi = 48.1; + i++; + } + if(ddc->timings1.t2 & 0x04) + { + pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].hi = 56.5; + i++; + } + if(ddc->timings1.t2 & 0x02) + { + pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].hi = 60.0; + i++; + } + if(ddc->timings1.t2 & 0x01) + { + pScrn->monitor->hsync[i].lo = + pScrn->monitor->hsync[i].hi = 64.0; + i++; + } + pScrn->monitor->nHsync = i; } else /*Vrefresh*/ { - for(i=0; i<4; i++) - { - if(ddc->det_mon[i].type == DS_RANGES) - { - pScrn->monitor->nVrefresh = 1; - pScrn->monitor->vrefresh[0].lo = - ddc->det_mon[i].section.ranges.min_v; - pScrn->monitor->vrefresh[0].hi = - ddc->det_mon[i].section.ranges.max_v; - return; - } - } - i = 0; - if(ddc->timings1.t1 & 0x02) /*800x600@56*/ - { - pScrn->monitor->vrefresh[i].lo = - pScrn->monitor->vrefresh[i].hi = 56; - i++; - } - if((ddc->timings1.t1 & 0x01) || (ddc->timings1.t2 & 0x08)) - { - pScrn->monitor->vrefresh[i].lo = - pScrn->monitor->vrefresh[i].hi = 60; - i++; - } - if(ddc->timings1.t2 & 0x04) - { - pScrn->monitor->vrefresh[i].lo = - pScrn->monitor->vrefresh[i].hi = 70; - i++; - } - if((ddc->timings1.t1 & 0x08) || (ddc->timings1.t2 & 0x80)) - { - pScrn->monitor->vrefresh[i].lo = - pScrn->monitor->vrefresh[i].hi = 72; - i++; - } - if((ddc->timings1.t1 & 0x04) || (ddc->timings1.t2 & 0x40) - || (ddc->timings1.t2 & 0x02) || (ddc->timings1.t2 & 0x01)) - { - pScrn->monitor->vrefresh[i].lo = - pScrn->monitor->vrefresh[i].hi = 75; - i++; - } - pScrn->monitor->nVrefresh = i; + for(i=0; i<4; i++) + { + if(ddc->det_mon[i].type == DS_RANGES) + { + pScrn->monitor->nVrefresh = 1; + pScrn->monitor->vrefresh[0].lo = + ddc->det_mon[i].section.ranges.min_v; + pScrn->monitor->vrefresh[0].hi = + ddc->det_mon[i].section.ranges.max_v; + return; + } + } + i = 0; + if(ddc->timings1.t1 & 0x02) /*800x600@56*/ + { + pScrn->monitor->vrefresh[i].lo = + pScrn->monitor->vrefresh[i].hi = 56; + i++; + } + if((ddc->timings1.t1 & 0x01) || (ddc->timings1.t2 & 0x08)) + { + pScrn->monitor->vrefresh[i].lo = + pScrn->monitor->vrefresh[i].hi = 60; + i++; + } + if(ddc->timings1.t2 & 0x04) + { + pScrn->monitor->vrefresh[i].lo = + pScrn->monitor->vrefresh[i].hi = 70; + i++; + } + if((ddc->timings1.t1 & 0x08) || (ddc->timings1.t2 & 0x80)) + { + pScrn->monitor->vrefresh[i].lo = + pScrn->monitor->vrefresh[i].hi = 72; + i++; + } + if((ddc->timings1.t1 & 0x04) || (ddc->timings1.t2 & 0x40) + || (ddc->timings1.t2 & 0x02) || (ddc->timings1.t2 & 0x01)) + { + pScrn->monitor->vrefresh[i].lo = + pScrn->monitor->vrefresh[i].hi = 75; + i++; + } + pScrn->monitor->nVrefresh = i; } } @@ -1467,7 +1620,7 @@ here is our own validation routine. All modes between 640<=XRes<=MaxRes and 480<=YRes<=MaxYRes will be permitted. NOTE: RageProII doesn't support rmx, can only work with the - standard modes the monitor can support (scale). + standard modes the monitor can support (scale). ************/ static int R128ValidateFPModes(ScrnInfoPtr pScrn) @@ -1493,58 +1646,58 @@ /* If no mode specified in config, we use native resolution*/ if(!pScrn->display->modes[0]) { - pScrn->display->modes[0] = xnfalloc(16); - sprintf(pScrn->display->modes[0], "%dx%d", - info->PanelXRes, info->PanelYRes); + pScrn->display->modes[0] = xnfalloc(16); + sprintf(pScrn->display->modes[0], "%dx%d", + info->PanelXRes, info->PanelYRes); } for(i=0; pScrn->display->modes[i] != NULL; i++) { - if (sscanf(pScrn->display->modes[i], "%dx%d", &width, &height) == 2) - { + if (sscanf(pScrn->display->modes[i], "%dx%d", &width, &height) == 2) + { + + if(width < 640 || width > info->PanelXRes || + height < 480 || height > info->PanelYRes) + { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Mode %s is out of range.\n" + "Valid mode should be between 640x480-%dx%d\n", + pScrn->display->modes[i], info->PanelXRes, info->PanelYRes); + continue; + } - if(width < 640 || width > info->PanelXRes || - height < 480 || height > info->PanelYRes) - { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Mode %s is out of range.\n" - "Valid mode should be between 640x480-%dx%d\n", - pScrn->display->modes[i], info->PanelXRes, info->PanelYRes); - continue; - } - - new = xnfcalloc(1, sizeof(DisplayModeRec)); - new->prev = last; - new->name = xnfalloc(strlen(pScrn->display->modes[i]) + 1); - strcpy(new->name, pScrn->display->modes[i]); - new->HDisplay = new->CrtcHDisplay = width; - new->VDisplay = new->CrtcVDisplay = height; - - ddc = pScrn->monitor->DDC; - for(j=0; j<DET_TIMINGS; j++) - { - /*We use native mode clock only*/ - if(ddc->det_mon[j].type == 0){ - new->Clock = ddc->det_mon[j].section.d_timings.clock / 1000; - break; - } - } - - if(new->prev) new->prev->next = new; - last = new; - if(!first) first = new; - pScrn->display->virtualX = - pScrn->virtualX = MAX(pScrn->virtualX, width); - pScrn->display->virtualY = - pScrn->virtualY = MAX(pScrn->virtualY, height); - count++; - } - else - { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Mode name %s is invalid\n", pScrn->display->modes[i]); - continue; - } + new = xnfcalloc(1, sizeof(DisplayModeRec)); + new->prev = last; + new->name = xnfalloc(strlen(pScrn->display->modes[i]) + 1); + strcpy(new->name, pScrn->display->modes[i]); + new->HDisplay = new->CrtcHDisplay = width; + new->VDisplay = new->CrtcVDisplay = height; + + ddc = pScrn->monitor->DDC; + for(j=0; j<DET_TIMINGS; j++) + { + /*We use native mode clock only*/ + if(ddc->det_mon[j].type == 0){ + new->Clock = ddc->det_mon[j].section.d_timings.clock / 1000; + break; + } + } + + if(new->prev) new->prev->next = new; + last = new; + if(!first) first = new; + pScrn->display->virtualX = + pScrn->virtualX = MAX(pScrn->virtualX, width); + pScrn->display->virtualY = + pScrn->virtualY = MAX(pScrn->virtualY, height); + count++; + } + else + { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Mode name %s is invalid\n", pScrn->display->modes[i]); + continue; + } } if(last) @@ -1555,20 +1708,20 @@ /*FIXME: May need to validate line pitch here*/ { - int dummy = 0; - switch(pScrn->depth / 8) - { - case 1: - dummy = 128 - pScrn->virtualX % 128; - break; - case 2: - dummy = 32 - pScrn->virtualX % 32; - break; - case 3: - case 4: - dummy = 16 - pScrn->virtualX % 16; - } - pScrn->displayWidth = pScrn->virtualX + dummy; + int dummy = 0; + switch(pScrn->depth / 8) + { + case 1: + dummy = 128 - pScrn->virtualX % 128; + break; + case 2: + dummy = 32 - pScrn->virtualX % 32; + break; + case 3: + case 4: + dummy = 16 - pScrn->virtualX % 16; + } + pScrn->displayWidth = pScrn->virtualX + dummy; } } @@ -1587,66 +1740,70 @@ ModuleDescPtr pModule; if(info->isDFP) { - R128MapMem(pScrn); - info->BIOSDisplay = R128_BIOS_DISPLAY_FP; - /* validate if DFP really connected. */ - if(!R128GetDFPInfo(pScrn)) { - info->isDFP = FALSE; - info->BIOSDisplay = R128_BIOS_DISPLAY_CRT; - } else if(!info->isPro2) { - /* RageProII doesn't support rmx, we can't use native-mode - stretching for other non-native modes. It will rely on - whatever VESA modes monitor can support. */ - modesFound = R128ValidateFPModes(pScrn); - if(modesFound < 1) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "No valid mode found for this DFP/LCD\n"); - R128UnmapMem(pScrn); - return FALSE; - - } - } - R128UnmapMem(pScrn); + R128MapMem(pScrn); + info->BIOSDisplay = R128_BIOS_DISPLAY_FP; + /* validate if DFP really connected. */ + if(!R128GetDFPInfo(pScrn)) { + info->isDFP = FALSE; + info->BIOSDisplay = R128_BIOS_DISPLAY_CRT; + } else if(!info->isPro2) { + /* RageProII doesn't support rmx, we can't use native-mode + stretching for other non-native modes. It will rely on + whatever VESA modes monitor can support. */ + modesFound = R128ValidateFPModes(pScrn); + if(modesFound < 1) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "No valid mode found for this DFP/LCD\n"); + R128UnmapMem(pScrn); + return FALSE; + + } + } + R128UnmapMem(pScrn); } if(!info->isDFP || info->isPro2) { /* Get mode information */ - pScrn->progClock = TRUE; - clockRanges = xnfcalloc(sizeof(*clockRanges), 1); - clockRanges->next = NULL; - clockRanges->minClock = info->pll.min_pll_freq; - clockRanges->maxClock = info->pll.max_pll_freq * 10; - clockRanges->clockIndex = -1; - if (info->HasPanelRegs || info->isDFP) { - clockRanges->interlaceAllowed = FALSE; - clockRanges->doubleScanAllowed = FALSE; - } else { - clockRanges->interlaceAllowed = TRUE; - clockRanges->doubleScanAllowed = TRUE; - } - - if(pScrn->monitor->DDC) { - /*if we still don't know sync range yet, let's try EDID. - Note that, since we can have dual heads, the Xconfigurator - may not be able to probe both monitors correctly through - vbe probe function (R128ProbeDDC). Here we provide an - additional way to auto-detect sync ranges if they haven't - been added to XF86Config manually. - **/ - if(pScrn->monitor->nHsync <= 0) - R128SetSyncRangeFromEdid(pScrn, 1); - if(pScrn->monitor->nVrefresh <= 0) - R128SetSyncRangeFromEdid(pScrn, 0); - } + pScrn->progClock = TRUE; + clockRanges = xnfcalloc(sizeof(*clockRanges), 1); + clockRanges->next = NULL; + clockRanges->minClock = info->pll.min_pll_freq; + clockRanges->maxClock = info->pll.max_pll_freq * 10; + clockRanges->clockIndex = -1; + if (info->HasPanelRegs || info->isDFP) { + clockRanges->interlaceAllowed = FALSE; + clockRanges->doubleScanAllowed = FALSE; + } else { + clockRanges->interlaceAllowed = TRUE; + clockRanges->doubleScanAllowed = TRUE; + } - modesFound = xf86ValidateModes(pScrn, + if(pScrn->monitor->DDC) { + /*if we still don't know sync range yet, let's try EDID. + Note that, since we can have dual heads, the Xconfigurator + may not be able to probe both monitors correctly through + vbe probe function (R128ProbeDDC). Here we provide an + additional way to auto-detect sync ranges if they haven't + been added to XF86Config manually. + **/ + if(pScrn->monitor->nHsync <= 0) + R128SetSyncRangeFromEdid(pScrn, 1); + if(pScrn->monitor->nVrefresh <= 0) + R128SetSyncRangeFromEdid(pScrn, 0); + } + + modesFound = xf86ValidateModes(pScrn, pScrn->monitor->Modes, pScrn->display->modes, clockRanges, NULL, /* linePitches */ 8 * 64, /* minPitch */ 8 * 1024, /* maxPitch */ - 8 * 64, /* pitchInc */ +/* + * ATI docs say pitchInc must be 8 * 64, but this doesn't permit a pitch of + * 800 bytes, which is known to work on the Rage128 LF on clamshell iBooks + */ + 8 * 32, /* pitchInc */ 128, /* minHeight */ 2048, /* maxHeight */ pScrn->display->virtualX, @@ -1654,19 +1811,19 @@ info->FbMapSize, LOOKUP_BEST_REFRESH); - if (modesFound < 1 && info->FBDev) { + if (modesFound < 1 && info->FBDev) { fbdevHWUseBuildinMode(pScrn); pScrn->displayWidth = fbdevHWGetLineLength(pScrn)/(pScrn->bitsPerPixel/8); modesFound = 1; - } + } - if (modesFound == -1) return FALSE; - xf86PruneDriverModes(pScrn); - if (!modesFound || !pScrn->modes) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes found\n"); - return FALSE; - } - xf86SetCrtcForModes(pScrn, 0); + if (modesFound == -1) return FALSE; + xf86PruneDriverModes(pScrn); + if (!modesFound || !pScrn->modes) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes found\n"); + return FALSE; + } + xf86SetCrtcForModes(pScrn, 0); } /* Set DPI */ pScrn->currentMode = pScrn->modes; @@ -1865,7 +2022,8 @@ { R128InfoPtr info; xf86Int10InfoPtr pInt10 = NULL; - ModuleDescPtr pModule; + ModuleDescPtr pModule; + unsigned char *R128MMIO = NULL; R128TRACE(("R128PreInit\n")); @@ -1875,21 +2033,49 @@ info = R128PTR(pScrn); + info->IsSecondary = FALSE; + info->IsPrimary = FALSE; + info->SwitchingMode = FALSE; + info->pEnt = xf86GetEntityInfo(pScrn->entityList[0]); if (info->pEnt->location.type != BUS_PCI) goto fail; + if(xf86IsEntityShared(pScrn->entityList[0])) + { + if(xf86IsPrimInitDone(pScrn->entityList[0])) + { + DevUnion* pPriv; + R128EntPtr pR128Ent; + info->IsSecondary = TRUE; + pPriv = xf86GetEntityPrivate(pScrn->entityList[0], + gR128EntityIndex); + pR128Ent = pPriv->ptr; + if(pR128Ent->BypassSecondary) return FALSE; + pR128Ent->pSecondaryScrn = pScrn; + } + else + { + DevUnion* pPriv; + R128EntPtr pR128Ent; + info->IsPrimary = TRUE; + xf86SetPrimInitDone(pScrn->entityList[0]); + pPriv = xf86GetEntityPrivate(pScrn->entityList[0], + gR128EntityIndex); + pR128Ent = pPriv->ptr; + pR128Ent->pPrimaryScrn = pScrn; + pR128Ent->IsDRIEnabled = FALSE; + pR128Ent->BypassSecondary = FALSE; + pR128Ent->HasSecondary = FALSE; + pR128Ent->RestorePrimary = FALSE; + pR128Ent->IsSecondaryRestored = FALSE; + } + } + if (flags & PROBE_DETECT) { R128ProbeDDC(pScrn, info->pEnt->index); return TRUE; } - if (!(pModule = xf86LoadSubModule(pScrn, "vgahw"))) return FALSE; - xf86LoaderModReqSymLists(pModule, vgahwSymbols, NULL); - if (!vgaHWGetHWRec(pScrn)) { - R128FreeRec(pScrn); - return FALSE; - } - info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); info->PciTag = pciTag(info->PciInfo->bus, info->PciInfo->device, @@ -1919,15 +2105,15 @@ if (!R128PreInitWeight(pScrn)) goto fail; if(xf86GetOptValInteger(info->Options, OPTION_VIDEO_KEY, &(info->videoKey))) { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n", - info->videoKey); + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n", + info->videoKey); } else { - info->videoKey = 0x1E; + info->videoKey = 0x1E; } if (xf86ReturnOptValBool(info->Options, OPTION_SHOW_CACHE, FALSE)) { - info->showCache = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ShowCache enabled\n"); + info->showCache = TRUE; + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ShowCache enabled\n"); } if (xf86ReturnOptValBool(info->Options, OPTION_FBDEV, FALSE)) { @@ -1949,6 +2135,28 @@ if (!info->FBDev) if (!R128PreInitInt10(pScrn, &pInt10)) goto fail; + if (!R128MapMMIO(pScrn)) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Memory map of MMIO region failed\n"); + goto fail; + } + + R128MMIO = info->MMIO; + + /* + * Don't use vgaHW if the adapter is found to be in an accelerator video + * mode on entry, as vgaHW will not be able to save & restore video memory + * contents. + */ + info->UseVGAHW = !(INREG(R128_CRTC_GEN_CNTL) & R128_CRTC_EXT_DISP_EN); + if (info->UseVGAHW) { + if (!(pModule = xf86LoadSubModule(pScrn, "vgahw"))) goto fail1; + xf86LoaderModReqSymLists(pModule, vgahwSymbols, NULL); + if (!vgaHWGetHWRec(pScrn)) goto fail1; + + vgaHWGetIOBase(VGAHWPTR(pScrn)); + } + if (!R128PreInitConfig(pScrn)) goto fail; if (!R128GetBIOSParameters(pScrn, pInt10)) goto fail; @@ -1980,13 +2188,12 @@ if (pInt10) xf86FreeInt10(pInt10); - xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, - "For information on using the multimedia capabilities\n of this" - " adapter, please see http://gatos.sf.net.\n"); + if (R128MMIO) + R128UnmapMMIO(pScrn); return TRUE; - fail: +fail: /* Pre-init failed. */ /* Free the video bios (if applicable) */ @@ -1995,11 +2202,17 @@ info->VBIOS = NULL; } + if (info->UseVGAHW) + vgaHWFreeHWRec(pScrn); + +fail1: /* Free int10 info */ if (pInt10) xf86FreeInt10(pInt10); - vgaHWFreeHWRec(pScrn); + if (R128MMIO) + R128UnmapMMIO(pScrn); + R128FreeRec(pScrn); return FALSE; } @@ -2010,12 +2223,14 @@ { R128InfoPtr info = R128PTR(pScrn); unsigned char *R128MMIO = info->MMIO; - int i; + int i, j; int idx; unsigned char r, g, b; - /* Select palette 0 (main CRTC) if using FP-enabled chip */ - if (info->HasPanelRegs || info->isDFP) PAL_SELECT(0); + /* If the second monitor is connected, we also + need to deal with the secondary palette*/ + if (info->IsSecondary) j = 1; else j = 0; + PAL_SELECT(j); if (info->CurrentLayout.depth == 15) { /* 15bpp mode. This sends 32 values. */ @@ -2063,7 +2278,7 @@ #ifdef XF86DRI if (info->directRenderingEnabled) - FLUSH_RING(); + FLUSH_RING(); #endif pScreen->BlockHandler = info->BlockHandler; @@ -2071,7 +2286,7 @@ pScreen->BlockHandler = R128BlockHandler; if(info->VideoTimerCallback) { - (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); + (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); } } @@ -2094,6 +2309,7 @@ if (!R128MapMem(pScrn)) return FALSE; pScrn->fbOffset = 0; + if(info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024; #ifdef XF86DRI info->fbX = 0; info->fbY = 0; @@ -2147,7 +2363,30 @@ info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024); info->directRenderingEnabled = FALSE; } else { - info->directRenderingEnabled = R128DRIScreenInit(pScreen); + if(info->IsSecondary) + info->directRenderingEnabled = FALSE; + else + { + /* Xinerama has sync problem with DRI, disable it for now */ + if(xf86IsEntityShared(pScrn->entityList[0])) + { + DevUnion* pPriv; + R128EntPtr pR128Ent; + info->directRenderingEnabled = FALSE; + xf86DrvMsg(scrnIndex, X_WARNING, + "Direct Rendering Disabled -- " + "Dual-head configuration is not working with DRI " + "at present.\nPlease use only one Device/Screen " + "section in your XFConfig file.\n"); + pPriv = xf86GetEntityPrivate(pScrn->entityList[0], + gR128EntityIndex); + pR128Ent = pPriv->ptr; + pR128Ent->IsDRIEnabled = info->directRenderingEnabled; + } + else + info->directRenderingEnabled = + R128DRIScreenInit(pScreen); + } } } #endif @@ -2460,14 +2699,16 @@ /* DPMS setup - FIXME: also for mirror mode in non-fbdev case? - Michel */ if (info->FBDev) xf86DPMSInit(pScreen, fbdevHWDPMSSet, 0); + else { - if (!info->HasPanelRegs || info->BIOSDisplay == R128_BIOS_DISPLAY_CRT) - xf86DPMSInit(pScreen, R128DisplayPowerManagementSet, 0); - else if (info->HasPanelRegs || info->BIOSDisplay == R128_BIOS_DISPLAY_FP) + if (info->DisplayType == MT_LCD) xf86DPMSInit(pScreen, R128DisplayPowerManagementSetLCD, 0); + else + xf86DPMSInit(pScreen, R128DisplayPowerManagementSet, 0); } - R128InitVideo(pScreen); + if (!info->IsSecondary) + R128InitVideo(pScreen); /* Provide SaveScreen */ pScreen->SaveScreen = R128SaveScreen; @@ -2548,6 +2789,25 @@ OUTREG(R128_CRTC_PITCH, restore->crtc_pitch); } +/* Write CRTC2 registers. */ +static void R128RestoreCrtc2Registers(ScrnInfoPtr pScrn, + R128SavePtr restore) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + + OUTREGP(R128_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl, + R128_CRTC2_DISP_DIS); + + OUTREG(R128_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp); + OUTREG(R128_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid); + OUTREG(R128_CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp); + OUTREG(R128_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid); + OUTREG(R128_CRTC2_OFFSET, restore->crtc2_offset); + OUTREG(R128_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl); + OUTREG(R128_CRTC2_PITCH, restore->crtc2_pitch); +} + /* Write flat panel registers */ static void R128RestoreFPRegisters(ScrnInfoPtr pScrn, R128SavePtr restore) { @@ -2555,8 +2815,8 @@ unsigned char *R128MMIO = info->MMIO; CARD32 tmp; - - /*OUTREG(R128_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);*/ + if (info->BIOSDisplay != R128_DUALHEAD) + OUTREG(R128_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); OUTREG(R128_FP_HORZ_STRETCH, restore->fp_horz_stretch); OUTREG(R128_FP_VERT_STRETCH, restore->fp_vert_stretch); OUTREG(R128_FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp); @@ -2597,7 +2857,28 @@ R128InfoPtr info = R128PTR(pScrn); unsigned char *R128MMIO = info->MMIO; - OUTPLLP(pScrn, R128_PPLL_REF_DIV, R128_PPLL_ATOMIC_UPDATE_W, 0xffff); + while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R); + + OUTPLLP(pScrn, R128_PPLL_REF_DIV, R128_PPLL_ATOMIC_UPDATE_W, + ~R128_PPLL_ATOMIC_UPDATE_W); + +} + +static void R128PLL2WaitForReadUpdateComplete(ScrnInfoPtr pScrn) +{ + while (INPLL(pScrn, R128_P2PLL_REF_DIV) & R128_P2PLL_ATOMIC_UPDATE_R); +} + +static void R128PLL2WriteUpdate(ScrnInfoPtr pScrn) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + + while (INPLL(pScrn, R128_P2PLL_REF_DIV) & R128_P2PLL_ATOMIC_UPDATE_R); + + OUTPLLP(pScrn, R128_P2PLL_REF_DIV, + R128_P2PLL_ATOMIC_UPDATE_W, + ~(R128_P2PLL_ATOMIC_UPDATE_W)); } /* Write PLL registers. */ @@ -2606,33 +2887,44 @@ R128InfoPtr info = R128PTR(pScrn); unsigned char *R128MMIO = info->MMIO; - OUTREGP(R128_CLOCK_CNTL_INDEX, R128_PLL_DIV_SEL, 0xffff); + + OUTPLLP(pScrn, R128_VCLK_ECP_CNTL, + R128_VCLK_SRC_SEL_CPUCLK, + ~(R128_VCLK_SRC_SEL_MASK)); OUTPLLP(pScrn, R128_PPLL_CNTL, R128_PPLL_RESET | R128_PPLL_ATOMIC_UPDATE_EN | R128_PPLL_VGA_ATOMIC_UPDATE_EN, - 0xffff); + ~(R128_PPLL_RESET + | R128_PPLL_ATOMIC_UPDATE_EN + | R128_PPLL_VGA_ATOMIC_UPDATE_EN)); - R128PLLWaitForReadUpdateComplete(pScrn); + OUTREGP(R128_CLOCK_CNTL_INDEX, R128_PLL_DIV_SEL, ~(R128_PLL_DIV_SEL)); + +/* R128PLLWaitForReadUpdateComplete(pScrn);*/ OUTPLLP(pScrn, R128_PPLL_REF_DIV, restore->ppll_ref_div, ~R128_PPLL_REF_DIV_MASK); - R128PLLWriteUpdate(pScrn); +/* R128PLLWriteUpdate(pScrn); - R128PLLWaitForReadUpdateComplete(pScrn); + R128PLLWaitForReadUpdateComplete(pScrn);*/ OUTPLLP(pScrn, R128_PPLL_DIV_3, restore->ppll_div_3, ~R128_PPLL_FB3_DIV_MASK); - R128PLLWriteUpdate(pScrn); +/* R128PLLWriteUpdate(pScrn);*/ OUTPLLP(pScrn, R128_PPLL_DIV_3, restore->ppll_div_3, ~R128_PPLL_POST3_DIV_MASK); - R128PLLWriteUpdate(pScrn); + R128PLLWriteUpdate(pScrn); R128PLLWaitForReadUpdateComplete(pScrn); + OUTPLL(R128_HTOTAL_CNTL, restore->htotal_cntl); - R128PLLWriteUpdate(pScrn); +/* R128PLLWriteUpdate(pScrn);*/ - OUTPLLP(pScrn, R128_PPLL_CNTL, 0, ~R128_PPLL_RESET); + OUTPLLP(pScrn, R128_PPLL_CNTL, 0, ~(R128_PPLL_RESET + | R128_PPLL_SLEEP + | R128_PPLL_ATOMIC_UPDATE_EN + | R128_PPLL_VGA_ATOMIC_UPDATE_EN)); R128TRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", restore->ppll_ref_div, @@ -2643,6 +2935,82 @@ restore->ppll_ref_div & R128_PPLL_REF_DIV_MASK, restore->ppll_div_3 & R128_PPLL_FB3_DIV_MASK, (restore->ppll_div_3 & R128_PPLL_POST3_DIV_MASK) >> 16)); + + usleep(5000); /* let the clock lock */ + + OUTPLLP(pScrn, R128_VCLK_ECP_CNTL, + R128_VCLK_SRC_SEL_PPLLCLK, + ~(R128_VCLK_SRC_SEL_MASK)); + +} + +/* Write PLL2 registers. */ +static void R128RestorePLL2Registers(ScrnInfoPtr pScrn, R128SavePtr restore) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + + OUTPLLP(pScrn, R128_V2CLK_VCLKTV_CNTL, + R128_V2CLK_SRC_SEL_CPUCLK, + ~R128_V2CLK_SRC_SEL_MASK); + + OUTPLLP(pScrn, + R128_P2PLL_CNTL, + R128_P2PLL_RESET + | R128_P2PLL_ATOMIC_UPDATE_EN + | R128_P2PLL_VGA_ATOMIC_UPDATE_EN, + ~(R128_P2PLL_RESET + | R128_P2PLL_ATOMIC_UPDATE_EN + | R128_P2PLL_VGA_ATOMIC_UPDATE_EN)); + +#if 1 + OUTREGP(R128_CLOCK_CNTL_INDEX, 0, R128_PLL2_DIV_SEL_MASK); +#endif + + /*R128PLL2WaitForReadUpdateComplete(pScrn);*/ + + OUTPLLP(pScrn, R128_P2PLL_REF_DIV, restore->p2pll_ref_div, ~R128_P2PLL_REF_DIV_MASK); + +/* R128PLL2WriteUpdate(pScrn); + R128PLL2WaitForReadUpdateComplete(pScrn);*/ + + OUTPLLP(pScrn, R128_P2PLL_DIV_0, + restore->p2pll_div_0, ~R128_P2PLL_FB0_DIV_MASK); + +/* R128PLL2WriteUpdate(pScrn); + R128PLL2WaitForReadUpdateComplete(pScrn);*/ + + OUTPLLP(pScrn, R128_P2PLL_DIV_0, + restore->p2pll_div_0, ~R128_P2PLL_POST0_DIV_MASK); + + R128PLL2WriteUpdate(pScrn); + R128PLL2WaitForReadUpdateComplete(pScrn); + + OUTPLL(R128_HTOTAL2_CNTL, restore->htotal_cntl2); + +/* R128PLL2WriteUpdate(pScrn);*/ + + OUTPLLP(pScrn, R128_P2PLL_CNTL, 0, ~(R128_P2PLL_RESET + | R128_P2PLL_SLEEP + | R128_P2PLL_ATOMIC_UPDATE_EN + | R128_P2PLL_VGA_ATOMIC_UPDATE_EN)); + + R128TRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", + restore->p2pll_ref_div, + restore->p2pll_div_0, + restore->htotal_cntl2, + INPLL(pScrn, RADEON_P2PLL_CNTL))); + R128TRACE(("Wrote: rd=%d, fd=%d, pd=%d\n", + restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, + restore->p2pll_div_0 & RADEON_P2PLL_FB3_DIV_MASK, + (restore->p2pll_div_0 & RADEON_P2PLL_POST3_DIV_MASK) >>16)); + + usleep(5000); /* Let the clock to lock */ + + OUTPLLP(pScrn, R128_V2CLK_VCLKTV_CNTL, + R128_V2CLK_SRC_SEL_P2PLLCLK, + ~R128_V2CLK_SRC_SEL_MASK); + } /* Write DDA registers. */ @@ -2655,6 +3023,16 @@ OUTREG(R128_DDA_ON_OFF, restore->dda_on_off); } +/* Write DDA registers. */ +static void R128RestoreDDA2Registers(ScrnInfoPtr pScrn, R128SavePtr restore) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + + OUTREG(R128_DDA2_CONFIG, restore->dda2_config); + OUTREG(R128_DDA2_ON_OFF, restore->dda2_on_off); +} + /* Write palette data. */ static void R128RestorePalette(ScrnInfoPtr pScrn, R128SavePtr restore) { @@ -2664,27 +3042,113 @@ if (!restore->palette_valid) return; - /* Select palette 0 (main CRTC) if using FP-enabled chip */ - if (info->HasPanelRegs || info->isDFP) PAL_SELECT(0); + PAL_SELECT(1); + OUTPAL_START(0); + for (i = 0; i < 256; i++) { + R128WaitForFifo(pScrn, 32); /* delay */ + OUTPAL_NEXT_CARD32(restore->palette2[i]); + } + PAL_SELECT(0); OUTPAL_START(0); - for (i = 0; i < 256; i++) OUTPAL_NEXT_CARD32(restore->palette[i]); + for (i = 0; i < 256; i++) { + R128WaitForFifo(pScrn, 32); /* delay */ + OUTPAL_NEXT_CARD32(restore->palette[i]); + } + } /* Write out state to define a new video mode. */ static void R128RestoreMode(ScrnInfoPtr pScrn, R128SavePtr restore) { R128InfoPtr info = R128PTR(pScrn); + DevUnion* pPriv; + R128EntPtr pR128Ent; + static R128SaveRec restore0; R128TRACE(("R128RestoreMode(%p)\n", restore)); - R128RestoreCommonRegisters(pScrn, restore); - R128RestoreCrtcRegisters(pScrn, restore); - if (!(info->HasPanelRegs) || info->BIOSDisplay == R128_BIOS_DISPLAY_CRT){ - R128RestorePLLRegisters(pScrn, restore); - } - R128RestoreDDARegisters(pScrn, restore); - if (info->HasPanelRegs || info->isDFP) - R128RestoreFPRegisters(pScrn, restore); + if(!info->HasCRTC2) + { + R128RestoreCommonRegisters(pScrn, restore); + R128RestoreDDARegisters(pScrn, restore); + R128RestoreCrtcRegisters(pScrn, restore); + if((info->DisplayType == MT_DFP) || + (info->DisplayType == MT_LCD)) + { + R128RestoreFPRegisters(pScrn, restore); + } + R128RestorePLLRegisters(pScrn, restore); + return; + } + + pPriv = xf86GetEntityPrivate(pScrn->entityList[0], + gR128EntityIndex); + pR128Ent = pPriv->ptr; + + + /***** + When changing mode with Dual-head card (VE/M6), care must + be taken for the special order in setting registers. CRTC2 has + to be set before changing CRTC_EXT register. + In the dual-head setup, X server calls this routine twice with + primary and secondary pScrn pointers respectively. The calls + can come with different order. Regardless the order of X server issuing + the calls, we have to ensure we set registers in the right order!!! + Otherwise we may get a blank screen. + *****/ + + if(info->IsSecondary) + { + if (!pR128Ent->RestorePrimary && !info->SwitchingMode) + R128RestoreCommonRegisters(pScrn, restore); + R128RestoreDDA2Registers(pScrn, restore); + R128RestoreCrtc2Registers(pScrn, restore); + R128RestorePLL2Registers(pScrn, restore); + + if(info->SwitchingMode) return; + + pR128Ent->IsSecondaryRestored = TRUE; + + if(pR128Ent->RestorePrimary) + { + R128InfoPtr info0 = R128PTR(pR128Ent->pPrimaryScrn); + pR128Ent->RestorePrimary = FALSE; + + R128RestoreCrtcRegisters(pScrn, &restore0); + if((info0->DisplayType == MT_DFP) || + (info0->DisplayType == MT_LCD)) + { + R128RestoreFPRegisters(pScrn, &restore0); + } + + R128RestorePLLRegisters(pScrn, &restore0); + pR128Ent->IsSecondaryRestored = FALSE; + + } + } + else + { + if (!pR128Ent->IsSecondaryRestored) + R128RestoreCommonRegisters(pScrn, restore); + R128RestoreDDARegisters(pScrn, restore); + if(!pR128Ent->HasSecondary || pR128Ent->IsSecondaryRestored + || info->SwitchingMode) + { + pR128Ent->IsSecondaryRestored = FALSE; + R128RestoreCrtcRegisters(pScrn, restore); + if((info->DisplayType == MT_DFP) || + (info->DisplayType == MT_LCD)) + { + R128RestoreFPRegisters(pScrn, restore); + } + R128RestorePLLRegisters(pScrn, restore); + } + else + { + memcpy(&restore0, restore, sizeof(restore0)); + pR128Ent->RestorePrimary = TRUE; + } + } R128RestorePalette(pScrn, restore); } @@ -2735,7 +3199,8 @@ R128InfoPtr info = R128PTR(pScrn); unsigned char *R128MMIO = info->MMIO; - save->crtc2_gen_cntl = INREG(R128_CRTC2_GEN_CNTL); + if (info->BIOSDisplay != R128_DUALHEAD) + save->crtc2_gen_cntl = INREG(R128_CRTC2_GEN_CNTL); save->fp_crtc_h_total_disp = INREG(R128_FP_CRTC_H_TOTAL_DISP); save->fp_crtc_v_total_disp = INREG(R128_FP_CRTC_V_TOTAL_DISP); save->fp_gen_cntl = INREG(R128_FP_GEN_CNTL); @@ -2749,6 +3214,22 @@ save->tmds_transmitter_cntl = INREG(R128_TMDS_TRANSMITTER_CNTL); } +/* Read CRTC2 registers. */ +static void R128SaveCrtc2Registers(ScrnInfoPtr pScrn, R128SavePtr save) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + + save->crtc2_gen_cntl = INREG(R128_CRTC2_GEN_CNTL); + save->crtc2_h_total_disp = INREG(R128_CRTC2_H_TOTAL_DISP); + save->crtc2_h_sync_strt_wid = INREG(R128_CRTC2_H_SYNC_STRT_WID); + save->crtc2_v_total_disp = INREG(R128_CRTC2_V_TOTAL_DISP); + save->crtc2_v_sync_strt_wid = INREG(R128_CRTC2_V_SYNC_STRT_WID); + save->crtc2_offset = INREG(R128_CRTC2_OFFSET); + save->crtc2_offset_cntl = INREG(R128_CRTC2_OFFSET_CNTL); + save->crtc2_pitch = INREG(R128_CRTC2_PITCH); +} + /* Read PLL registers. */ static void R128SavePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr save) { @@ -2766,6 +3247,23 @@ (save->ppll_div_3 & R128_PPLL_POST3_DIV_MASK) >> 16)); } +/* Read PLL2 registers. */ +static void R128SavePLL2Registers(ScrnInfoPtr pScrn, R128SavePtr save) +{ + save->p2pll_ref_div = INPLL(pScrn, R128_P2PLL_REF_DIV); + save->p2pll_div_0 = INPLL(pScrn, R128_P2PLL_DIV_0); + save->htotal_cntl2 = INPLL(pScrn, R128_HTOTAL2_CNTL); + + R128TRACE(("Read: 0x%08x 0x%08x 0x%08x\n", + save->p2pll_ref_div, + save->p2pll_div_0, + save->htotal_cntl2)); + R128TRACE(("Read: rd=%d, fd=%d, pd=%d\n", + save->p2pll_ref_div & R128_P2PLL_REF_DIV_MASK, + save->p2pll_div_0 & R128_P2PLL_FB0_DIV_MASK, + (save->p2pll_div_0 & R128_P2PLL_POST0_DIV_MASK) >> 16)); +} + /* Read DDA registers. */ static void R128SaveDDARegisters(ScrnInfoPtr pScrn, R128SavePtr save) { @@ -2776,6 +3274,16 @@ save->dda_on_off = INREG(R128_DDA_ON_OFF); } +/* Read DDA2 registers. */ +static void R128SaveDDA2Registers(ScrnInfoPtr pScrn, R128SavePtr save) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + + save->dda2_config = INREG(R128_DDA2_CONFIG); + save->dda2_on_off = INREG(R128_DDA2_ON_OFF); +} + /* Read palette data. */ static void R128SavePalette(ScrnInfoPtr pScrn, R128SavePtr save) { @@ -2783,9 +3291,10 @@ unsigned char *R128MMIO = info->MMIO; int i; - /* Select palette 0 (main CRTC) if using FP-enabled chip */ - if (info->HasPanelRegs || info->isDFP) PAL_SELECT(0); - + PAL_SELECT(1); + INPAL_START(0); + for (i = 0; i < 256; i++) save->palette2[i] = INPAL_NEXT(); + PAL_SELECT(0); INPAL_START(0); for (i = 0; i < 256; i++) save->palette[i] = INPAL_NEXT(); save->palette_valid = TRUE; @@ -2794,15 +3303,29 @@ /* Save state that defines current video mode. */ static void R128SaveMode(ScrnInfoPtr pScrn, R128SavePtr save) { + R128InfoPtr info = R128PTR(pScrn); + R128TRACE(("R128SaveMode(%p)\n", save)); - R128SaveCommonRegisters(pScrn, save); - R128SaveCrtcRegisters(pScrn, save); - if (R128PTR(pScrn)->HasPanelRegs || R128PTR(pScrn)->isDFP) - R128SaveFPRegisters(pScrn, save); - R128SavePLLRegisters(pScrn, save); - R128SaveDDARegisters(pScrn, save); - R128SavePalette(pScrn, save); + if(info->IsSecondary) + { + R128SaveCrtc2Registers(pScrn, save); + R128SavePLL2Registers(pScrn, save); + R128SaveDDA2Registers(pScrn, save); + } + else + { + R128SaveCommonRegisters(pScrn, save); + R128SaveCrtcRegisters(pScrn, save); + if((info->DisplayType == MT_DFP) || + (info->DisplayType == MT_LCD)) + { + R128SaveFPRegisters(pScrn, save); + } + R128SavePLLRegisters(pScrn, save); + R128SaveDDARegisters(pScrn, save); + R128SavePalette(pScrn, save); + } R128TRACE(("R128SaveMode returns %p\n", save)); } @@ -2813,24 +3336,30 @@ R128InfoPtr info = R128PTR(pScrn); unsigned char *R128MMIO = info->MMIO; R128SavePtr save = &info->SavedReg; - vgaHWPtr hwp = VGAHWPTR(pScrn); R128TRACE(("R128Save\n")); if (info->FBDev) { fbdevHWSave(pScrn); return; } - vgaHWUnlock(hwp); - vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL); /* save mode, fonts, cmap */ - vgaHWLock(hwp); - R128SaveMode(pScrn, save); + if (!info->IsSecondary) { + if (info->UseVGAHW) { + vgaHWPtr hwp = VGAHWPTR(pScrn); + + vgaHWUnlock(hwp); + vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL); + vgaHWLock(hwp); + } - save->dp_datatype = INREG(R128_DP_DATATYPE); - save->gen_reset_cntl = INREG(R128_GEN_RESET_CNTL); - save->clock_cntl_index = INREG(R128_CLOCK_CNTL_INDEX); - save->amcgpio_en_reg = INREG(R128_AMCGPIO_EN_REG); - save->amcgpio_mask = INREG(R128_AMCGPIO_MASK); + save->dp_datatype = INREG(R128_DP_DATATYPE); + save->gen_reset_cntl = INREG(R128_GEN_RESET_CNTL); + save->clock_cntl_index = INREG(R128_CLOCK_CNTL_INDEX); + save->amcgpio_en_reg = INREG(R128_AMCGPIO_EN_REG); + save->amcgpio_mask = INREG(R128_AMCGPIO_MASK); + } + + R128SaveMode(pScrn, save); } /* Restore the original (text) mode. */ @@ -2839,7 +3368,6 @@ R128InfoPtr info = R128PTR(pScrn); unsigned char *R128MMIO = info->MMIO; R128SavePtr restore = &info->SavedReg; - vgaHWPtr hwp = VGAHWPTR(pScrn); R128TRACE(("R128Restore\n")); if (info->FBDev) { @@ -2848,16 +3376,33 @@ } R128Blank(pScrn); - OUTREG(R128_AMCGPIO_MASK, restore->amcgpio_mask); - OUTREG(R128_AMCGPIO_EN_REG, restore->amcgpio_en_reg); - OUTREG(R128_CLOCK_CNTL_INDEX, restore->clock_cntl_index); - OUTREG(R128_GEN_RESET_CNTL, restore->gen_reset_cntl); - OUTREG(R128_DP_DATATYPE, restore->dp_datatype); + + if (!info->IsSecondary) { + OUTREG(R128_AMCGPIO_MASK, restore->amcgpio_mask); + OUTREG(R128_AMCGPIO_EN_REG, restore->amcgpio_en_reg); + OUTREG(R128_CLOCK_CNTL_INDEX, restore->clock_cntl_index); + OUTREG(R128_GEN_RESET_CNTL, restore->gen_reset_cntl); + OUTREG(R128_DP_DATATYPE, restore->dp_datatype); + } R128RestoreMode(pScrn, restore); - vgaHWUnlock(hwp); - vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); - vgaHWLock(hwp); + if (info->UseVGAHW) { + if (!info->IsSecondary) { + vgaHWPtr hwp = VGAHWPTR(pScrn); + vgaHWUnlock(hwp); + vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS); + vgaHWLock(hwp); + } else { + R128EntPtr pR128Ent = R128EntPriv(pScrn); + ScrnInfoPtr pScrn0 = pR128Ent->pPrimaryScrn; + vgaHWPtr hwp0; + + hwp0 = VGAHWPTR(pScrn0); + vgaHWUnlock(hwp0); + vgaHWRestore(pScrn0, &hwp0->SavedReg, VGA_SR_MODE | VGA_SR_FONTS); + vgaHWLock(hwp0); + } + } R128WaitForVerticalSync(pScrn); R128Unblank(pScrn); @@ -2901,7 +3446,7 @@ int vsync_wid; int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 }; int hsync_fudge_fp[] = { 0x12, 0x11, 0x09, 0x09, 0x05, 0x05 }; - int hsync_fudge_fp_crt[] = { 0x12, 0x10, 0x08, 0x08, 0x04, 0x04 }; +/* int hsync_fudge_fp_crt[] = { 0x12, 0x10, 0x08, 0x08, 0x04, 0x04 }; */ switch (info->CurrentLayout.pixel_code) { case 4: format = 1; break; @@ -2917,18 +3462,11 @@ return FALSE; } - switch (info->BIOSDisplay) { - case R128_BIOS_DISPLAY_FP: + if ((info->DisplayType == MT_DFP) || + (info->DisplayType == MT_LCD)) hsync_fudge = hsync_fudge_fp[format-1]; - break; - case R128_BIOS_DISPLAY_FP_CRT: - hsync_fudge = hsync_fudge_fp_crt[format-1]; - break; - case R128_BIOS_DISPLAY_CRT: - default: + else hsync_fudge = hsync_fudge_default[format-1]; - break; - } save->crtc_gen_cntl = (R128_CRTC_EXT_DISP_EN | R128_CRTC_EN @@ -2943,7 +3481,19 @@ ? R128_CRTC_CSYNC_EN : 0)); - save->crtc_ext_cntl = R128_VGA_ATI_LINEAR | R128_XCRT_CNT_EN; + if((info->DisplayType == MT_DFP) || + (info->DisplayType == MT_LCD)) + { + save->crtc_ext_cntl = R128_VGA_ATI_LINEAR | + R128_XCRT_CNT_EN; + save->crtc_gen_cntl &= ~(R128_CRTC_DBL_SCAN_EN | + R128_CRTC_INTERLACE_EN); + } + else + save->crtc_ext_cntl = R128_VGA_ATI_LINEAR | + R128_XCRT_CNT_EN | + R128_CRTC_CRT_ON; + save->dac_cntl = (R128_DAC_MASK_ALL | R128_DAC_VGA_ADR_EN | (info->dac6bits ? 0 : R128_DAC_8BIT_EN)); @@ -2951,16 +3501,16 @@ if(info->isDFP && !info->isPro2) { - if(info->PanelXRes < mode->CrtcHDisplay) - mode->HDisplay = mode->CrtcHDisplay = info->PanelXRes; - if(info->PanelYRes < mode->CrtcVDisplay) - mode->VDisplay = mode->CrtcVDisplay = info->PanelYRes; - mode->CrtcHTotal = mode->CrtcHDisplay + info->HBlank; - mode->CrtcHSyncStart = mode->CrtcHDisplay + info->HOverPlus; - mode->CrtcHSyncEnd = mode->CrtcHSyncStart + info->HSyncWidth; - mode->CrtcVTotal = mode->CrtcVDisplay + info->VBlank; - mode->CrtcVSyncStart = mode->CrtcVDisplay + info->VOverPlus; - mode->CrtcVSyncEnd = mode->CrtcVSyncStart + info->VSyncWidth; + if(info->PanelXRes < mode->CrtcHDisplay) + mode->HDisplay = mode->CrtcHDisplay = info->PanelXRes; + if(info->PanelYRes < mode->CrtcVDisplay) + mode->VDisplay = mode->CrtcVDisplay = info->PanelYRes; + mode->CrtcHTotal = mode->CrtcHDisplay + info->HBlank; + mode->CrtcHSyncStart = mode->CrtcHDisplay + info->HOverPlus; + mode->CrtcHSyncEnd = mode->CrtcHSyncStart + info->HSyncWidth; + mode->CrtcVTotal = mode->CrtcVDisplay + info->VBlank; + mode->CrtcVSyncStart = mode->CrtcVDisplay + info->VOverPlus; + mode->CrtcVSyncEnd = mode->CrtcVSyncStart + info->VSyncWidth; } save->crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0xffff) @@ -3020,6 +3570,92 @@ return TRUE; } +/* Define CRTC2 registers for requested video mode. */ +static Bool R128InitCrtc2Registers(ScrnInfoPtr pScrn, R128SavePtr save, + DisplayModePtr mode, R128InfoPtr info) +{ + int format; + int hsync_start; + int hsync_wid; + int hsync_fudge; + int vsync_wid; + int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 }; + + switch (info->CurrentLayout.pixel_code) { + case 4: format = 1; break; + case 8: format = 2; break; + case 15: format = 3; break; /* 555 */ + case 16: format = 4; break; /* 565 */ + case 24: format = 5; break; /* RGB */ + case 32: format = 6; break; /* xRGB */ + default: + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Unsupported pixel depth (%d)\n", info->CurrentLayout.bitsPerPixel); + return FALSE; + } + R128TRACE(("Format = %d (%d bytes per pixel)\n", format, + (info->CurrentLayout.pixel_code + 1) / 8)); + + hsync_fudge = hsync_fudge_default[format-1]; + + save->crtc2_gen_cntl = (R128_CRTC2_EN + | (format << 8) + | ((mode->Flags & V_DBLSCAN) + ? R128_CRTC2_DBL_SCAN_EN + : 0)); +/* + save->crtc2_gen_cntl &= ~R128_CRTC_EXT_DISP_EN; + save->crtc2_gen_cntl |= (1 << 21); +*/ + save->crtc2_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0xffff) + | (((mode->CrtcHDisplay / 8) - 1) << 16)); + + hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; + if (!hsync_wid) hsync_wid = 1; + if (hsync_wid > 0x3f) hsync_wid = 0x3f; + + hsync_start = mode->CrtcHSyncStart - 8 + hsync_fudge; + + save->crtc2_h_sync_strt_wid = ((hsync_start & 0xfff) + | (hsync_wid << 16) + | ((mode->Flags & V_NHSYNC) + ? R128_CRTC2_H_SYNC_POL + : 0)); + +#if 1 + /* This works for double scan mode. */ + save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff) + | ((mode->CrtcVDisplay - 1) << 16)); +#else + /* This is what cce/nbmode.c example code + does -- is this correct? */ + save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff) + | ((mode->CrtcVDisplay + * ((mode->Flags & V_DBLSCAN) ? 2 : 1) - 1) + << 16)); +#endif + + vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; + if (!vsync_wid) vsync_wid = 1; + if (vsync_wid > 0x1f) vsync_wid = 0x1f; + + save->crtc2_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff) + | (vsync_wid << 16) + | ((mode->Flags & V_NVSYNC) + ? R128_CRTC2_V_SYNC_POL + : 0)); + + save->crtc2_offset = 0; + save->crtc2_offset_cntl = 0; + + save->crtc2_pitch = info->CurrentLayout.displayWidth / 8; + + R128TRACE(("Pitch = %d bytes (virtualX = %d, displayWidth = %d)\n", + save->crtc2_pitch, pScrn->virtualX, + info->CurrentLayout.displayWidth)); + return TRUE; +} + /* Define CRTC registers for requested video mode. */ static void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, DisplayModePtr mode, R128InfoPtr info) @@ -3029,20 +3665,20 @@ float Hratio, Vratio; if (info->BIOSDisplay == R128_BIOS_DISPLAY_CRT) { - save->crtc_ext_cntl |= R128_CRTC_CRT_ON; - save->crtc2_gen_cntl = 0; - save->fp_gen_cntl = orig->fp_gen_cntl; - save->fp_gen_cntl &= ~(R128_FP_FPON | - R128_FP_CRTC_USE_SHADOW_VEND | - R128_FP_CRTC_HORZ_DIV2_EN | - R128_FP_CRTC_HOR_CRT_DIV2_DIS | - R128_FP_USE_SHADOW_EN); - save->fp_gen_cntl |= (R128_FP_SEL_CRTC2 | - R128_FP_CRTC_DONT_SHADOW_VPAR); - save->fp_panel_cntl = orig->fp_panel_cntl & (CARD32)~R128_FP_DIGON; - save->lvds_gen_cntl = orig->lvds_gen_cntl & + save->crtc_ext_cntl |= R128_CRTC_CRT_ON; + save->crtc2_gen_cntl = 0; + save->fp_gen_cntl = orig->fp_gen_cntl; + save->fp_gen_cntl &= ~(R128_FP_FPON | + R128_FP_CRTC_USE_SHADOW_VEND | + R128_FP_CRTC_HORZ_DIV2_EN | + R128_FP_CRTC_HOR_CRT_DIV2_DIS | + R128_FP_USE_SHADOW_EN); + save->fp_gen_cntl |= (R128_FP_SEL_CRTC2 | + R128_FP_CRTC_DONT_SHADOW_VPAR); + save->fp_panel_cntl = orig->fp_panel_cntl & (CARD32)~R128_FP_DIGON; + save->lvds_gen_cntl = orig->lvds_gen_cntl & (CARD32)~(R128_LVDS_ON | R128_LVDS_BLON); - return; + return; } if (xres > info->PanelXRes) xres = info->PanelXRes; @@ -3055,14 +3691,14 @@ (((((int)(Hratio * R128_HORZ_STRETCH_RATIO_MAX + 0.5)) & R128_HORZ_STRETCH_RATIO_MASK) << R128_HORZ_STRETCH_RATIO_SHIFT) | (orig->fp_horz_stretch & (R128_HORZ_PANEL_SIZE | - R128_HORZ_FP_LOOP_STRETCH | - R128_HORZ_STRETCH_RESERVED))); + R128_HORZ_FP_LOOP_STRETCH | + R128_HORZ_STRETCH_RESERVED))); save->fp_horz_stretch &= ~R128_HORZ_AUTO_RATIO_FIX_EN; save->fp_horz_stretch &= ~R128_AUTO_HORZ_RATIO; if (xres == info->PanelXRes) - save->fp_horz_stretch &= ~(R128_HORZ_STRETCH_BLEND | R128_HORZ_STRETCH_ENABLE); + save->fp_horz_stretch &= ~(R128_HORZ_STRETCH_BLEND | R128_HORZ_STRETCH_ENABLE); else - save->fp_horz_stretch |= (R128_HORZ_STRETCH_BLEND | R128_HORZ_STRETCH_ENABLE); + save->fp_horz_stretch |= (R128_HORZ_STRETCH_BLEND | R128_HORZ_STRETCH_ENABLE); save->fp_vert_stretch = (((((int)(Vratio * R128_VERT_STRETCH_RATIO_MAX + 0.5)) @@ -3071,9 +3707,9 @@ R128_VERT_STRETCH_RESERVED))); save->fp_vert_stretch &= ~R128_VERT_AUTO_RATIO_EN; if (yres == info->PanelYRes) - save->fp_vert_stretch &= ~(R128_VERT_STRETCH_ENABLE | R128_VERT_STRETCH_BLEND); + save->fp_vert_stretch &= ~(R128_VERT_STRETCH_ENABLE | R128_VERT_STRETCH_BLEND); else - save->fp_vert_stretch |= (R128_VERT_STRETCH_ENABLE | R128_VERT_STRETCH_BLEND); + save->fp_vert_stretch |= (R128_VERT_STRETCH_ENABLE | R128_VERT_STRETCH_BLEND); save->fp_gen_cntl = (orig->fp_gen_cntl & (CARD32)~(R128_FP_SEL_CRTC2 | @@ -3092,35 +3728,40 @@ the flat panel and external CRT to either simultaneously display the same image or display two different images. */ + if(!info->isDFP){ - if (info->BIOSDisplay == R128_BIOS_DISPLAY_FP_CRT) { + if (info->BIOSDisplay == R128_BIOS_DISPLAY_FP_CRT) { + save->crtc_ext_cntl |= R128_CRTC_CRT_ON; + } else if (info->BIOSDisplay == R128_DUALHEAD) { save->crtc_ext_cntl |= R128_CRTC_CRT_ON; - } else { + save->dac_cntl |= R128_DAC_CRT_SEL_CRTC2; + save->dac_cntl |= R128_DAC_PALETTE2_SNOOP_EN; + } else { save->crtc_ext_cntl &= ~R128_CRTC_CRT_ON; save->dac_cntl |= R128_DAC_CRT_SEL_CRTC2; save->crtc2_gen_cntl = 0; - } + } } /* WARNING: Be careful about turning on the flat panel */ if(info->isDFP){ - save->fp_gen_cntl = orig->fp_gen_cntl; + save->fp_gen_cntl = orig->fp_gen_cntl; - save->fp_gen_cntl &= ~(R128_FP_CRTC_USE_SHADOW_VEND | - R128_FP_CRTC_USE_SHADOW_ROWCUR | - R128_FP_CRTC_HORZ_DIV2_EN | - R128_FP_CRTC_HOR_CRT_DIV2_DIS | - R128_FP_CRT_SYNC_SEL | - R128_FP_USE_SHADOW_EN); - - save->fp_panel_cntl |= (R128_FP_DIGON | R128_FP_BLON); - save->fp_gen_cntl |= (R128_FP_FPON | R128_FP_TDMS_EN | - R128_FP_CRTC_DONT_SHADOW_VPAR | R128_FP_CRTC_DONT_SHADOW_HEND); - save->tmds_transmitter_cntl = (orig->tmds_transmitter_cntl - & ~(CARD32)R128_TMDS_PLLRST) | R128_TMDS_PLLEN; + save->fp_gen_cntl &= ~(R128_FP_CRTC_USE_SHADOW_VEND | + R128_FP_CRTC_USE_SHADOW_ROWCUR | + R128_FP_CRTC_HORZ_DIV2_EN | + R128_FP_CRTC_HOR_CRT_DIV2_DIS | + R128_FP_CRT_SYNC_SEL | + R128_FP_USE_SHADOW_EN); + + save->fp_panel_cntl |= (R128_FP_DIGON | R128_FP_BLON); + save->fp_gen_cntl |= (R128_FP_FPON | R128_FP_TDMS_EN | + R128_FP_CRTC_DONT_SHADOW_VPAR | R128_FP_CRTC_DONT_SHADOW_HEND); + save->tmds_transmitter_cntl = (orig->tmds_transmitter_cntl + & ~(CARD32)R128_TMDS_PLLRST) | R128_TMDS_PLLEN; } else - save->lvds_gen_cntl |= (R128_LVDS_ON | R128_LVDS_BLON); + save->lvds_gen_cntl |= (R128_LVDS_ON | R128_LVDS_BLON); save->fp_crtc_h_total_disp = save->crtc_h_total_disp; save->fp_crtc_v_total_disp = save->crtc_v_total_disp; @@ -3180,10 +3821,62 @@ } +/* Define PLL2 registers for requested video mode. */ +static void R128InitPLL2Registers(R128SavePtr save, R128PLLPtr pll, + double dot_clock) +{ + unsigned long freq = dot_clock * 100; + struct { + int divider; + int bitvalue; + } *post_div, + post_divs[] = { + /* From RAGE 128 VR/RAGE 128 GL Register + Reference Manual (Technical Reference + Manual P/N RRG-G04100-C Rev. 0.04), page + 3-17 (PLL_DIV_[3:0]). */ + { 1, 0 }, /* VCLK_SRC */ + { 2, 1 }, /* VCLK_SRC/2 */ + { 4, 2 }, /* VCLK_SRC/4 */ + { 8, 3 }, /* VCLK_SRC/8 */ + + { 3, 4 }, /* VCLK_SRC/3 */ + /* bitvalue = 5 is reserved */ + { 6, 6 }, /* VCLK_SRC/6 */ + { 12, 7 }, /* VCLK_SRC/12 */ + { 0, 0 } + }; + + if (freq > pll->max_pll_freq) freq = pll->max_pll_freq; + if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12; + + for (post_div = &post_divs[0]; post_div->divider; ++post_div) { + save->pll_output_freq_2 = post_div->divider * freq; + if (save->pll_output_freq_2 >= pll->min_pll_freq + && save->pll_output_freq_2 <= pll->max_pll_freq) break; + } + + save->dot_clock_freq_2 = freq; + save->feedback_div_2 = R128Div(pll->reference_div + * save->pll_output_freq_2, + pll->reference_freq); + save->post_div_2 = post_div->divider; + + R128TRACE(("dc=%d, of=%d, fd=%d, pd=%d\n", + save->dot_clock_freq_2, + save->pll_output_freq_2, + save->feedback_div_2, + save->post_div_2)); + + save->p2pll_ref_div = pll->reference_div; + save->p2pll_div_0 = (save->feedback_div_2 | (post_div->bitvalue<<16)); + save->htotal_cntl2 = 0; +} + /* Define DDA registers for requested video mode. */ static Bool R128InitDDARegisters(ScrnInfoPtr pScrn, R128SavePtr save, R128PLLPtr pll, R128InfoPtr info, - DisplayModePtr mode) + DisplayModePtr mode) { int DisplayFifoWidth = 128; int DisplayFifoDepth = 32; @@ -3201,8 +3894,8 @@ pll->reference_div * save->post_div); if(info->isDFP && !info->isPro2){ - if(info->PanelXRes != mode->CrtcHDisplay) - VclkFreq = (VclkFreq * mode->CrtcHDisplay)/info->PanelXRes; + if(info->PanelXRes != mode->CrtcHDisplay) + VclkFreq = (VclkFreq * mode->CrtcHDisplay)/info->PanelXRes; } XclksPerTransfer = R128Div(XclkFreq * DisplayFifoWidth, @@ -3249,6 +3942,77 @@ return TRUE; } +/* Define DDA2 registers for requested video mode. */ +static Bool R128InitDDA2Registers(ScrnInfoPtr pScrn, R128SavePtr save, + R128PLLPtr pll, R128InfoPtr info, + DisplayModePtr mode) +{ + int DisplayFifoWidth = 128; + int DisplayFifoDepth = 32; + int XclkFreq; + int VclkFreq; + int XclksPerTransfer; + int XclksPerTransferPrecise; + int UseablePrecision; + int Roff; + int Ron; + + XclkFreq = pll->xclk; + + VclkFreq = R128Div(pll->reference_freq * save->feedback_div_2, + pll->reference_div * save->post_div_2); + + if(info->isDFP && !info->isPro2){ + if(info->PanelXRes != mode->CrtcHDisplay) + VclkFreq = (VclkFreq * mode->CrtcHDisplay)/info->PanelXRes; + } + + XclksPerTransfer = R128Div(XclkFreq * DisplayFifoWidth, + VclkFreq * (info->CurrentLayout.pixel_bytes * 8)); + + UseablePrecision = R128MinBits(XclksPerTransfer) + 1; + + XclksPerTransferPrecise = R128Div((XclkFreq * DisplayFifoWidth) + << (11 - UseablePrecision), + VclkFreq * (info->CurrentLayout.pixel_bytes * 8)); + + Roff = XclksPerTransferPrecise * (DisplayFifoDepth - 4); + + Ron = (4 * info->ram->MB + + 3 * MAX(info->ram->Trcd - 2, 0) + + 2 * info->ram->Trp + + info->ram->Twr + + info->ram->CL + + info->ram->Tr2w + + XclksPerTransfer) << (11 - UseablePrecision); + + + if (Ron + info->ram->Rloop >= Roff) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "(Ron = %d) + (Rloop = %d) >= (Roff = %d)\n", + Ron, info->ram->Rloop, Roff); + return FALSE; + } + + save->dda2_config = (XclksPerTransferPrecise + | (UseablePrecision << 16) + | (info->ram->Rloop << 20)); + + /*save->dda2_on_off = (Ron << 16) | Roff;*/ + /* shift most be 18 otherwise there's corruption on crtc2 */ + save->dda2_on_off = (Ron << 18) | Roff; + + R128TRACE(("XclkFreq = %d; VclkFreq = %d; per = %d, %d (useable = %d)\n", + XclkFreq, + VclkFreq, + XclksPerTransfer, + XclksPerTransferPrecise, + UseablePrecision)); + R128TRACE(("Roff = %d, Ron = %d, Rloop = %d\n", + Roff, Ron, info->ram->Rloop)); + + return TRUE; +} #if 0 /* Define initial palette for requested video mode. This doesn't do @@ -3316,21 +4080,42 @@ info->Flags = mode->Flags; - R128InitCommonRegisters(save, info); - if (!R128InitCrtcRegisters(pScrn, save, mode, info)) return FALSE; - if (info->HasPanelRegs || info->isDFP) - R128InitFPRegisters(&info->SavedReg, save, mode, info); - if(dot_clock > 0){ - R128InitPLLRegisters(pScrn, save, &info->pll, dot_clock); - if (!R128InitDDARegisters(pScrn, save, &info->pll, info, mode)) + if(info->IsSecondary) + { + if (!R128InitCrtc2Registers(pScrn, save, + pScrn->currentMode,info)) + return FALSE; + R128InitPLL2Registers(save, &info->pll, dot_clock); + if (!R128InitDDA2Registers(pScrn, save, &info->pll, info, mode)) + return FALSE; + } + else + { + R128InitCommonRegisters(save, info); + if(!R128InitCrtcRegisters(pScrn, save, mode, info)) + return FALSE; + if(dot_clock) + { + R128InitPLLRegisters(pScrn, save, &info->pll, dot_clock); + if (!R128InitDDARegisters(pScrn, save, &info->pll, info, mode)) return FALSE; + } + else + { + save->ppll_ref_div = info->SavedReg.ppll_ref_div; + save->ppll_div_3 = info->SavedReg.ppll_div_3; + save->htotal_cntl = info->SavedReg.htotal_cntl; + save->dda_config = info->SavedReg.dda_config; + save->dda_on_off = info->SavedReg.dda_on_off; + } + /* not used for now */ + /*if (!info->PaletteSavedOnVT) RADEONInitPalette(save);*/ } - else{ - save->ppll_ref_div = info->SavedReg.ppll_ref_div; - save->ppll_div_3 = info->SavedReg.ppll_div_3; - save->htotal_cntl = info->SavedReg.htotal_cntl; - save->dda_config = info->SavedReg.dda_config; - save->dda_on_off = info->SavedReg.dda_on_off; + + if (((info->DisplayType == MT_DFP) || + (info->DisplayType == MT_LCD))) + { + R128InitFPRegisters(&info->SavedReg, save, mode, info); } R128TRACE(("R128Init returns %p\n", save)); @@ -3372,9 +4157,21 @@ return TRUE; } +/* + * SwitchMode() doesn't work right on crtc2 on some laptops. + * The workaround is to switch the mode, then switch to another VT, then + * switch back. --AGD + */ Bool R128SwitchMode(int scrnIndex, DisplayModePtr mode, int flags) { - return R128ModeInit(xf86Screens[scrnIndex], mode); + ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; + R128InfoPtr info = R128PTR(pScrn); + Bool ret; + + info->SwitchingMode = TRUE; + ret = R128ModeInit(xf86Screens[scrnIndex], mode); + info->SwitchingMode = FALSE; + return ret; } /* Used to disallow modes that are not supported by the hardware. */ @@ -3385,20 +4182,19 @@ R128InfoPtr info = R128PTR(pScrn); if(info->isDFP) { - if(info->PanelXRes < mode->CrtcHDisplay || - info->PanelYRes < mode->CrtcVDisplay) - return MODE_NOMODE; - else - return MODE_OK; + if(info->PanelXRes < mode->CrtcHDisplay || + info->PanelYRes < mode->CrtcVDisplay) + return MODE_NOMODE; + else + return MODE_OK; } - if (info->HasPanelRegs) { + if (info->DisplayType == MT_LCD) { if (mode->Flags & V_INTERLACE) return MODE_NO_INTERLACE; if (mode->Flags & V_DBLSCAN) return MODE_NO_DBLESCAN; } - if (info->HasPanelRegs && - info->BIOSDisplay != R128_BIOS_DISPLAY_CRT && + if (info->DisplayType == MT_LCD && info->VBIOS) { int i; for (i = info->FPBIOSstart+64; R128_BIOS16(i) != 0; i += 2) { @@ -3463,7 +4259,7 @@ int Base; if(info->showCache && y && pScrn->vtSema) - y += pScrn->virtualY - 1; + y += pScrn->virtualY - 1; Base = y * info->CurrentLayout.displayWidth + x; @@ -3479,7 +4275,14 @@ if (info->CurrentLayout.pixel_code == 24) Base += 8 * (Base % 3); /* Must be multiple of 8 and 3 */ + if(info->IsSecondary) + { + Base += pScrn->fbOffset; + OUTREG(R128_CRTC2_OFFSET, Base); + } + else OUTREG(R128_CRTC_OFFSET, Base); + } /* Called when VT switching back to the X server. Reinitialize the video @@ -3491,9 +4294,9 @@ R128TRACE(("R128EnterVT\n")); if (info->FBDev) { - if (!fbdevHWEnterVT(scrnIndex,flags)) return FALSE; + if (!fbdevHWEnterVT(scrnIndex,flags)) return FALSE; } else - if (!R128ModeInit(pScrn, pScrn->currentMode)) return FALSE; + if (!R128ModeInit(pScrn, pScrn->currentMode)) return FALSE; if (info->accelOn) R128EngineInit(pScrn); @@ -3533,9 +4336,9 @@ R128SavePalette(pScrn, save); info->PaletteSavedOnVT = TRUE; if (info->FBDev) - fbdevHWLeaveVT(scrnIndex,flags); + fbdevHWLeaveVT(scrnIndex,flags); else - R128Restore(pScrn); + R128Restore(pScrn); } @@ -3575,7 +4378,7 @@ info->DGAModes = NULL; if (info->adaptor) { - xfree(info->adaptor->pPortPrivates[0].ptr); + xfree(info->adaptor->pPortPrivates[0].ptr); xf86XVFreeVideoAdaptorRec(info->adaptor); info->adaptor = NULL; } @@ -3590,9 +4393,10 @@ void R128FreeScreen(int scrnIndex, int flags) { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; + R128InfoPtr info = R128PTR(pScrn); R128TRACE(("R128FreeScreen\n")); - if (xf86LoaderCheckSymbol("vgaHWFreeHWRec")) + if (info->UseVGAHW) vgaHWFreeHWRec(pScrn); R128FreeRec(pScrn); } @@ -3606,27 +4410,52 @@ int mask = (R128_CRTC_DISPLAY_DIS | R128_CRTC_HSYNC_DIS | R128_CRTC_VSYNC_DIS); + int mask2 = R128_CRTC2_DISP_DIS; switch (PowerManagementMode) { case DPMSModeOn: /* Screen: On; HSync: On, VSync: On */ - OUTREGP(R128_CRTC_EXT_CNTL, 0, ~mask); + if (info->IsSecondary) + OUTREGP(R128_CRTC2_GEN_CNTL, 0, ~mask2); + else + OUTREGP(R128_CRTC_EXT_CNTL, 0, ~mask); break; case DPMSModeStandby: /* Screen: Off; HSync: Off, VSync: On */ - OUTREGP(R128_CRTC_EXT_CNTL, - R128_CRTC_DISPLAY_DIS | R128_CRTC_HSYNC_DIS, ~mask); + if (info->IsSecondary) + OUTREGP(R128_CRTC2_GEN_CNTL, R128_CRTC2_DISP_DIS, ~mask2); + else + OUTREGP(R128_CRTC_EXT_CNTL, + R128_CRTC_DISPLAY_DIS | R128_CRTC_HSYNC_DIS, ~mask); break; case DPMSModeSuspend: /* Screen: Off; HSync: On, VSync: Off */ - OUTREGP(R128_CRTC_EXT_CNTL, - R128_CRTC_DISPLAY_DIS | R128_CRTC_VSYNC_DIS, ~mask); + if (info->IsSecondary) + OUTREGP(R128_CRTC2_GEN_CNTL, R128_CRTC2_DISP_DIS, ~mask2); + else + OUTREGP(R128_CRTC_EXT_CNTL, + R128_CRTC_DISPLAY_DIS | R128_CRTC_VSYNC_DIS, ~mask); break; case DPMSModeOff: /* Screen: Off; HSync: Off, VSync: Off */ - OUTREGP(R128_CRTC_EXT_CNTL, mask, ~mask); + if (info->IsSecondary) + OUTREGP(R128_CRTC2_GEN_CNTL, mask2, ~mask2); + else + OUTREGP(R128_CRTC_EXT_CNTL, mask, ~mask); break; } + if(info->isDFP) { + switch (PowerManagementMode) { + case DPMSModeOn: + OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL) | (R128_FP_FPON | R128_FP_TDMS_EN)); + break; + case DPMSModeStandby: + case DPMSModeSuspend: + case DPMSModeOff: + OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL) & ~(R128_FP_FPON | R128_FP_TDMS_EN)); + break; + } + } } static int r128_set_backlight_enable(ScrnInfoPtr pScrn, int on); @@ -3642,7 +4471,7 @@ case DPMSModeOn: /* Screen: On; HSync: On, VSync: On */ OUTREGP(R128_LVDS_GEN_CNTL, 0, ~mask); - r128_set_backlight_enable(pScrn, 1); + r128_set_backlight_enable(pScrn, 1); break; case DPMSModeStandby: /* Fall through */ @@ -3652,21 +4481,21 @@ case DPMSModeOff: /* Screen: Off; HSync: Off, VSync: Off */ OUTREGP(R128_LVDS_GEN_CNTL, mask, ~mask); - r128_set_backlight_enable(pScrn, 0); + r128_set_backlight_enable(pScrn, 0); break; } } static int r128_set_backlight_enable(ScrnInfoPtr pScrn, int on) { - R128InfoPtr info = R128PTR(pScrn); - unsigned char *R128MMIO = info->MMIO; + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; unsigned int lvds_gen_cntl = INREG(R128_LVDS_GEN_CNTL); lvds_gen_cntl |= (/*R128_LVDS_BL_MOD_EN |*/ R128_LVDS_BLON); if (on) { lvds_gen_cntl |= R128_LVDS_DIGON; - if (!lvds_gen_cntl & R128_LVDS_ON) { + if (!(lvds_gen_cntl & R128_LVDS_ON)) { lvds_gen_cntl &= ~R128_LVDS_BLON; OUTREG(R128_LVDS_GEN_CNTL, lvds_gen_cntl); (void)INREG(R128_LVDS_GEN_CNTL); Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_misc.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/r128_misc.c:1.11 xc/programs/Xserver/hw/xfree86/drivers/ati/r128_misc.c:1.12 --- xc/programs/Xserver/hw/xfree86/drivers/ati/r128_misc.c:1.11 Mon Jan 1 08:08:18 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128_misc.c Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_misc.c,v 1.11 2007/01/01 16:08:18 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_misc.c,v 1.12 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.c:1.20 xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.c:1.21 --- xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.c:1.20 Thu Mar 16 08:49:59 2006 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.c Wed Apr 2 13:47:58 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.c,v 1.20 2006/03/16 16:49:59 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.c,v 1.21 2008/04/02 20:47:58 tsi Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and @@ -180,6 +180,8 @@ { -1, -1, RES_UNDEFINED } }; +int gR128EntityIndex = -1; + /* Return the options for supported chipset 'n'; NULL otherwise */ const OptionInfoRec * R128AvailableOptions(int chipid, int busid) @@ -216,7 +218,6 @@ int numDevSections, nATIGDev, nR128GDev; int *usedChips; GDevPtr *devSections, *ATIGDevs, *R128GDevs; - EntityInfoPtr pEnt; Bool foundScreen = FALSE; int i; @@ -262,10 +263,11 @@ if (flags & PROBE_DETECT) foundScreen = TRUE; else for (i = 0; i < numUsed; i++) { - pEnt = xf86GetEntityInfo(usedChips[i]); + ScrnInfoPtr pScrn; + EntityInfoPtr pEnt; - if (pEnt->active) { - ScrnInfoPtr pScrn = xf86AllocateScreen(drv, 0); + if ((pScrn = xf86ConfigPciEntity(NULL, 0, usedChips[i], + R128PciChipsets, 0, 0, 0, 0, 0))) { #ifdef XFree86LOADER ModuleDescPtr pModule; @@ -293,13 +295,47 @@ pScrn->LeaveVT = R128LeaveVT; pScrn->FreeScreen = R128FreeScreen; pScrn->ValidMode = R128ValidMode; + pScrn->Probe = R128Probe; foundScreen = TRUE; - xf86ConfigActivePciEntity(pScrn, usedChips[i], R128PciChipsets, - 0, 0, 0, 0, 0); + pEnt = xf86GetEntityInfo(usedChips[i]); + + /* mobility cards support Dual-Head, mark the entity as sharable */ + if (pEnt->chipset == PCI_CHIP_RAGE128LE || + pEnt->chipset == PCI_CHIP_RAGE128LF || + pEnt->chipset == PCI_CHIP_RAGE128MF || + pEnt->chipset == PCI_CHIP_RAGE128ML) { + static int instance = 0; + DevUnion* pPriv; + + xf86SetEntitySharable(usedChips[i]); + xf86SetEntityInstanceForScreen(pScrn, + pScrn->entityList[0], instance); + + if (gR128EntityIndex < 0) + { + gR128EntityIndex = xf86AllocateEntityPrivateIndex(); + pPriv = xf86GetEntityPrivate(pScrn->entityList[0], + gR128EntityIndex); + + if (!pPriv->ptr) + { + R128EntPtr pR128Ent; + pPriv->ptr = xnfcalloc(sizeof(R128EntRec), 1); + pR128Ent = pPriv->ptr; + pR128Ent->IsDRIEnabled = FALSE; + pR128Ent->BypassSecondary = FALSE; + pR128Ent->HasSecondary = FALSE; + pR128Ent->IsSecondaryRestored = FALSE; + } + } + + instance++; + } + + xfree(pEnt); } - xfree(pEnt); } xfree(usedChips); Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.h:1.11 xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.h:1.12 --- xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.h:1.11 Tue Jan 23 10:02:59 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.h Wed Apr 2 13:47:58 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.h,v 1.11 2007/01/23 18:02:59 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_probe.h,v 1.12 2008/04/02 20:47:58 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -41,6 +41,21 @@ #include "xf86str.h" +typedef struct +{ + Bool IsDRIEnabled; + + Bool HasSecondary; + Bool BypassSecondary; + /*These two registers are used to make sure the CRTC2 is + retored before CRTC_EXT, otherwise it could lead to blank screen.*/ + Bool IsSecondaryRestored; + Bool RestorePrimary; + + ScrnInfoPtr pSecondaryScrn; + ScrnInfoPtr pPrimaryScrn; +} R128EntRec, *R128EntPtr; + /* r128_probe.c */ extern const OptionInfoRec * R128AvailableOptions FunctionPrototype((int, int)); Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_reg.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/r128_reg.h:1.18 xc/programs/Xserver/hw/xfree86/drivers/ati/r128_reg.h:1.19 --- xc/programs/Xserver/hw/xfree86/drivers/ati/r128_reg.h:1.18 Fri Dec 10 08:07:01 2004 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128_reg.h Wed Apr 2 13:47:58 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_reg.h,v 1.18 2004/12/10 16:07:01 alanh Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_reg.h,v 1.19 2008/04/02 20:47:58 tsi Exp $ */ /* * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, * Precision Insight, Inc., Cedar Park, Texas, and @@ -68,7 +68,7 @@ do { \ CARD32 tmp = INREG(addr); \ tmp &= (mask); \ - tmp |= (val); \ + tmp |= ((val) & ~(mask)); \ OUTREG(addr, tmp); \ } while (0) @@ -76,7 +76,7 @@ #define OUTPLL(addr, val) \ do { \ - OUTREG8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x1f) | R128_PLL_WR_EN); \ + OUTREG8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x3f) | R128_PLL_WR_EN); \ OUTREG(R128_CLOCK_CNTL_DATA, val); \ } while (0) @@ -84,7 +84,7 @@ do { \ CARD32 tmp = INPLL(pScrn, addr); \ tmp &= (mask); \ - tmp |= (val); \ + tmp |= ((val) & ~(mask)); \ OUTPLL(addr, tmp); \ } while (0) @@ -151,9 +151,6 @@ #define R128_AMCGPIO_EN_REG 0x01a8 #define R128_AMCGPIO_MASK 0x0194 #define R128_AMCGPIO_Y_REG 0x01a4 -#define R128_ATTRDR 0x03c1 /* VGA */ -#define R128_ATTRDW 0x03c0 /* VGA */ -#define R128_ATTRX 0x03c0 /* VGA */ #define R128_AUX_SC_CNTL 0x1660 # define R128_AUX1_SC_EN (1 << 0) # define R128_AUX1_SC_MODE_OR (0 << 1) @@ -189,6 +186,9 @@ # define R128_BIOS_DISPLAY_FP (1 << 0) # define R128_BIOS_DISPLAY_CRT (2 << 0) # define R128_BIOS_DISPLAY_FP_CRT (3 << 0) +/* R128_DUALHEAD is just a flag for the driver; + it doesn't actually correspond to any bits */ +# define R128_DUALHEAD 4 #define R128_BIOS_6_SCRATCH 0x0028 #define R128_BIOS_7_SCRATCH 0x002c #define R128_BIOS_ROM 0x0f30 /* PCI */ @@ -284,6 +284,7 @@ #define R128_CLOCK_CNTL_INDEX 0x0008 # define R128_PLL_WR_EN (1 << 7) # define R128_PLL_DIV_SEL (3 << 8) +# define R128_PLL2_DIV_SEL_MASK ~(3 << 8) #define R128_CLR_CMP_CLR_3D 0x1a24 #define R128_CLR_CMP_CLR_DST 0x15c8 #define R128_CLR_CMP_CLR_SRC 0x15c4 @@ -374,45 +375,77 @@ #define R128_CRTC2_CRNT_FRAME 0x0314 #define R128_CRTC2_DEBUG 0x031c #define R128_CRTC2_GEN_CNTL 0x03f8 +# define R128_CRTC2_DBL_SCAN_EN (1 << 0) +# define R128_CRTC2_CUR_EN (1 << 16) +# define R128_CRTC2_ICON_EN (1 << 20) +# define R128_CRTC2_DISP_DIS (1 << 23) +# define R128_CRTC2_EN (1 << 25) +# define R128_CRTC2_DISP_REQ_EN_B (1 << 26) #define R128_CRTC2_GUI_TRIG_VLINE 0x0318 #define R128_CRTC2_H_SYNC_STRT_WID 0x0304 +# define R128_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +# define R128_CRTC2_H_SYNC_STRT_CHAR (0x1ff << 3) +# define R128_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +# define R128_CRTC2_H_SYNC_WID (0x3f << 16) +# define R128_CRTC2_H_SYNC_WID_SHIFT 16 +# define R128_CRTC2_H_SYNC_POL (1 << 23) #define R128_CRTC2_H_TOTAL_DISP 0x0300 +# define R128_CRTC2_H_TOTAL (0x01ff << 0) +# define R128_CRTC2_H_TOTAL_SHIFT 0 +# define R128_CRTC2_H_DISP (0x00ff << 16) +# define R128_CRTC2_H_DISP_SHIFT 16 #define R128_CRTC2_OFFSET 0x0324 #define R128_CRTC2_OFFSET_CNTL 0x0328 +# define R128_CRTC2_TILE_EN (1 << 15) #define R128_CRTC2_PITCH 0x032c #define R128_CRTC2_STATUS 0x03fc #define R128_CRTC2_V_SYNC_STRT_WID 0x030c +# define R128_CRTC2_V_SYNC_STRT (0x7ff << 0) +# define R128_CRTC2_V_SYNC_STRT_SHIFT 0 +# define R128_CRTC2_V_SYNC_WID (0x1f << 16) +# define R128_CRTC2_V_SYNC_WID_SHIFT 16 +# define R128_CRTC2_V_SYNC_POL (1 << 23) #define R128_CRTC2_V_TOTAL_DISP 0x0308 +# define R128_CRTC2_V_TOTAL (0x07ff << 0) +# define R128_CRTC2_V_TOTAL_SHIFT 0 +# define R128_CRTC2_V_DISP (0x07ff << 16) +# define R128_CRTC2_V_DISP_SHIFT 16 #define R128_CRTC2_VLINE_CRNT_VLINE 0x0310 -#define R128_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ -#define R128_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ #define R128_CUR_CLR0 0x026c #define R128_CUR_CLR1 0x0270 #define R128_CUR_HORZ_VERT_OFF 0x0268 #define R128_CUR_HORZ_VERT_POSN 0x0264 #define R128_CUR_OFFSET 0x0260 # define R128_CUR_LOCK (1 << 31) +#define R128_CUR2_CLR0 0x036c +#define R128_CUR2_CLR1 0x0370 +#define R128_CUR2_HORZ_VERT_OFF 0x0368 +#define R128_CUR2_HORZ_VERT_POSN 0x0364 +#define R128_CUR2_OFFSET 0x0360 +# define R128_CUR2_LOCK (1 << 31) #define R128_DAC_CNTL 0x0058 # define R128_DAC_RANGE_CNTL (3 << 0) # define R128_DAC_BLANKING (1 << 2) # define R128_DAC_CRT_SEL_CRTC2 (1 << 4) # define R128_DAC_PALETTE_ACC_CTL (1 << 5) +# define R128_DAC_PALETTE2_SNOOP_EN (1 << 6) # define R128_DAC_8BIT_EN (1 << 8) # define R128_DAC_VGA_ADR_EN (1 << 13) # define R128_DAC_MASK_ALL (0xff << 24) #define R128_DAC_CRC_SIG 0x02cc -#define R128_DAC_DATA 0x03c9 /* VGA */ -#define R128_DAC_MASK 0x03c6 /* VGA */ -#define R128_DAC_R_INDEX 0x03c7 /* VGA */ -#define R128_DAC_W_INDEX 0x03c8 /* VGA */ #define R128_DDA_CONFIG 0x02e0 #define R128_DDA_ON_OFF 0x02e4 +#define R128_DDA2_CONFIG 0x03e0 +#define R128_DDA2_ON_OFF 0x03e4 #define R128_DEFAULT_OFFSET 0x16e0 #define R128_DEFAULT_PITCH 0x16e4 #define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 # define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) # define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define R128_DEFAULT2_OFFSET 0x16f8 +#define R128_DEFAULT2_PITCH 0x16fc +#define R128_DEFAULT2_SC_BOTTOM_RIGHT 0x16dc #define R128_DESTINATION_3D_CLR_CMP_VAL 0x1820 #define R128_DESTINATION_3D_CLR_CMP_MSK 0x1824 #define R128_DEVICE_ID 0x0f02 /* PCI */ @@ -613,13 +646,6 @@ # define R128_SOFT_RESET_PCLK (1 << 9) # define R128_SOFT_RESET_DISPENG_XCLK (1 << 11) # define R128_SOFT_RESET_MEMCTLR_XCLK (1 << 12) -#define R128_GENENB 0x03c3 /* VGA */ -#define R128_GENFC_RD 0x03ca /* VGA */ -#define R128_GENFC_WT 0x03da /* VGA, 0x03ba */ -#define R128_GENMO_RD 0x03cc /* VGA */ -#define R128_GENMO_WT 0x03c2 /* VGA */ -#define R128_GENS0 0x03c2 /* VGA */ -#define R128_GENS1 0x03da /* VGA, 0x03ba */ #define R128_GPIO_MONID 0x0068 # define R128_GPIO_MONID_A_0 (1 << 0) # define R128_GPIO_MONID_A_1 (1 << 1) @@ -638,8 +664,6 @@ # define R128_GPIO_MONID_MASK_2 (1 << 26) # define R128_GPIO_MONID_MASK_3 (1 << 27) #define R128_GPIO_MONIDB 0x006c -#define R128_GRPH8_DATA 0x03cf /* VGA */ -#define R128_GRPH8_IDX 0x03ce /* VGA */ #define R128_GUI_DEBUG0 0x16a0 #define R128_GUI_DEBUG1 0x16a4 #define R128_GUI_DEBUG2 0x16a8 @@ -670,6 +694,7 @@ #define R128_HOST_DATA_LAST 0x17e0 #define R128_HOST_PATH_CNTL 0x0130 #define R128_HTOTAL_CNTL 0x0009 /* PLL */ +#define R128_HTOTAL2_CNTL 0x002e /* PLL */ #define R128_HW_DEBUG 0x0128 #define R128_HW_DEBUG2 0x011c @@ -875,6 +900,19 @@ # define R128_PPLL_REF_DIV_MASK 0x03ff # define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ # define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define R128_P2PLL_CNTL 0x002a /* P2PLL */ +# define R128_P2PLL_RESET (1 << 0) +# define R128_P2PLL_SLEEP (1 << 1) +# define R128_P2PLL_ATOMIC_UPDATE_EN (1 << 16) +# define R128_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define R128_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define R128_P2PLL_DIV_0 0x002c +# define R128_P2PLL_FB0_DIV_MASK 0x07ff +# define R128_P2PLL_POST0_DIV_MASK 0x00070000 +#define R128_P2PLL_REF_DIV 0x002B /* PLL */ +# define R128_P2PLL_REF_DIV_MASK 0x03ff +# define R128_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define R128_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ #define R128_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ #define R128_REG_BASE 0x0f18 /* PCI */ #define R128_REGPROG_INF 0x0f09 /* PCI */ @@ -888,8 +926,6 @@ #define R128_SC_TOP 0x1648 #define R128_SC_TOP_LEFT 0x16ec #define R128_SC_TOP_LEFT_C 0x1c88 -#define R128_SEQ8_DATA 0x03c5 /* VGA */ -#define R128_SEQ8_IDX 0x03c4 /* VGA */ #define R128_SNAPSHOT_F_COUNT 0x0244 #define R128_SNAPSHOT_VH_COUNTS 0x0240 #define R128_SNAPSHOT_VIF_COUNT 0x024c @@ -935,7 +971,14 @@ #define R128_TRAIL_X_SUB 0x1620 #define R128_VCLK_ECP_CNTL 0x0008 /* PLL */ +# define R128_VCLK_SRC_SEL_MASK 0x03 +# define R128_VCLK_SRC_SEL_CPUCLK 0x00 +# define R128_VCLK_SRC_SEL_PPLLCLK 0x03 # define R128_ECP_DIV_MASK (3 << 8) +#define R128_V2CLK_VCLKTV_CNTL 0x002d /* PLL */ +# define R128_V2CLK_SRC_SEL_MASK 0x03 +# define R128_V2CLK_SRC_SEL_CPUCLK 0x00 +# define R128_V2CLK_SRC_SEL_P2PLLCLK 0x03 #define R128_VENDOR_ID 0x0f00 /* PCI */ #define R128_VGA_DDA_CONFIG 0x02e8 #define R128_VGA_DDA_ON_OFF 0x02ec Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_version.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/r128_version.h:1.10 xc/programs/Xserver/hw/xfree86/drivers/ati/r128_version.h:1.12 --- xc/programs/Xserver/hw/xfree86/drivers/ati/r128_version.h:1.10 Mon Jan 1 08:08:18 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128_version.h Wed Apr 2 13:47:58 2008 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_version.h,v 1.10 2007/01/01 16:08:18 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_version.h,v 1.12 2008/04/02 20:47:58 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -38,8 +38,8 @@ #define R128_DRIVER_NAME "r128" #define R128_VERSION_MAJOR 4 -#define R128_VERSION_MINOR 0 -#define R128_VERSION_PATCH 1 +#define R128_VERSION_MINOR 1 +#define R128_VERSION_PATCH 0 #ifndef R128_VERSION_EXTRA #define R128_VERSION_EXTRA "" Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_video.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/r128_video.c:1.33 xc/programs/Xserver/hw/xfree86/drivers/ati/r128_video.c:1.34 --- xc/programs/Xserver/hw/xfree86/drivers/ati/r128_video.c:1.33 Fri Oct 14 08:16:37 2005 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128_video.c Wed Apr 2 13:47:58 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_video.c,v 1.33 2005/10/14 15:16:37 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_video.c,v 1.34 2008/04/02 20:47:58 tsi Exp $ */ #include "r128.h" #include "r128_reg.h" @@ -579,20 +579,20 @@ pScreen = screenInfo.screens[pScrn->scrnIndex]; - new_linear = xf86AllocateOffscreenLinear(pScreen, size, 16, + new_linear = xf86AllocateOffscreenLinear(pScreen, size, 8, NULL, NULL, NULL); if(!new_linear) { int max_size; - xf86QueryLargestOffscreenLinear(pScreen, &max_size, 16, + xf86QueryLargestOffscreenLinear(pScreen, &max_size, 8, PRIORITY_EXTREME); if(max_size < size) return NULL; xf86PurgeUnlockedOffscreenAreas(pScreen); - new_linear = xf86AllocateOffscreenLinear(pScreen, size, 16, + new_linear = xf86AllocateOffscreenLinear(pScreen, size, 8, NULL, NULL, NULL); } Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h:1.48 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h:1.50 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h:1.48 Tue Jan 9 09:04:45 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h Sun Apr 6 12:17:40 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.48 2007/01/09 17:04:45 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.50 2008/04/06 19:17:40 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -42,6 +42,7 @@ /* PCI support */ #include "xf86Pci.h" +#include "xf86int10.h" /* XAA and Cursor Support */ #include "xaa.h" @@ -53,6 +54,7 @@ /* Xv support */ #include "xf86xv.h" +#include "radeon_probe.h" /* DRI support */ #ifdef XF86DRI #define _XF86DRI_SERVER_ @@ -61,10 +63,40 @@ #include "GL/glxint.h" #endif + /* Render support */ +#include "picturestr.h" + +/* ------- mergedfb support ------------- */ + /* Pseudo Xinerama support */ +#define NEED_REPLIES /* ? */ +#define EXTENSION_PROC_ARGS void * +#include "extnsionst.h" /* required */ +#include <X11/extensions/panoramiXproto.h> /* required */ +#define RADEON_XINERAMA_MAJOR_VERSION 1 +#define RADEON_XINERAMA_MINOR_VERSION 1 + + +/* Relative merge position */ +typedef enum { + radeonLeftOf, + radeonRightOf, + radeonAbove, + radeonBelow, + radeonClone +} RADEONScrn2Rel; + +typedef struct _region { + int x0,x1,y0,y1; +} region; + +/* ------------------------------------- */ + #define RADEON_DEBUG 0 /* Turn off debugging output */ #define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ #define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ +/* Buffer are aligned on 4096 byte boundaries */ +#define RADEON_BUFFER_ALIGN 0x00000fff #define RADEON_VBIOS_SIZE 0x00010000 #define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX * Need to comfirm this is not used @@ -72,13 +104,13 @@ */ #if RADEON_DEBUG -#define RADEONTRACE(x) \ +#define RADEONTRACE(x) \ do { \ ErrorF("(**) %s(%d): ", RADEON_NAME, pScrn->scrnIndex); \ ErrorF x; \ -} while (0); +} while(0) #else -#define RADEONTRACE(x) +#define RADEONTRACE(x) do { } while(0) #endif @@ -87,6 +119,7 @@ #define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1)) #define RADEONPTR(pScrn) ((RADEONInfoPtr)(pScrn)->driverPrivate) + typedef struct { /* Common registers */ CARD32 ovr_clr; @@ -102,8 +135,17 @@ CARD32 cap0_trig_cntl; CARD32 cap1_trig_cntl; CARD32 bus_cntl; - CARD32 surface_cntl; + CARD32 bios_4_scratch; CARD32 bios_5_scratch; + CARD32 bios_6_scratch; + CARD32 surface_cntl; + CARD32 surfaces[8][3]; + unsigned mc_agp_location; + unsigned mc_fb_location; + CARD32 display_base_addr; + CARD32 display2_base_addr; + CARD32 ov0_base_addr; + /* Other registers to save for VT switches */ CARD32 dp_datatype; CARD32 rbbm_soft_reset; @@ -184,13 +226,16 @@ Bool palette_valid; CARD32 palette[256]; CARD32 palette2[256]; + + CARD32 tv_dac_cntl; + } RADEONSaveRec, *RADEONSavePtr; typedef struct { CARD16 reference_freq; CARD16 reference_div; - CARD32 min_pll_freq; - CARD32 max_pll_freq; + unsigned min_pll_freq; + unsigned max_pll_freq; CARD16 xclk; } RADEONPLLRec, *RADEONPLLPtr; @@ -198,37 +243,13 @@ int bitsPerPixel; int depth; int displayWidth; + int displayHeight; int pixel_code; int pixel_bytes; DisplayModePtr mode; } RADEONFBLayout; typedef enum { - MT_NONE, - MT_CRT, - MT_LCD, - MT_DFP, - MT_CTV, - MT_STV -} RADEONMonitorType; - -typedef enum { - DDC_NONE_DETECTED, - DDC_MONID, - DDC_DVI, - DDC_VGA, - DDC_CRT2 -} RADEONDDCType; - -typedef enum { - CONNECTOR_NONE, - CONNECTOR_PROPRIETARY, - CONNECTOR_CRT, - CONNECTOR_DVI_I, - CONNECTOR_DVI_D -} RADEONConnectorType; - -typedef enum { CHIP_FAMILY_UNKNOW, CHIP_FAMILY_LEGACY, CHIP_FAMILY_RADEON, @@ -238,17 +259,54 @@ CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ CHIP_FAMILY_R200, CHIP_FAMILY_RV250, - CHIP_FAMILY_RS300, /* Radeon 9000 IGP */ + CHIP_FAMILY_RS300, /* RS300/RS350 */ CHIP_FAMILY_RV280, CHIP_FAMILY_R300, CHIP_FAMILY_R350, CHIP_FAMILY_RV350, + CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ + CHIP_FAMILY_R420, /* R420/R423/M18 */ + CHIP_FAMILY_RV410, /* RV410, M26 */ + CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */ CHIP_FAMILY_LAST } RADEONChipFamily; +#define IS_RV100_VARIANT ((info->ChipFamily == CHIP_FAMILY_RV100) || \ + (info->ChipFamily == CHIP_FAMILY_RV200) || \ + (info->ChipFamily == CHIP_FAMILY_RS100) || \ + (info->ChipFamily == CHIP_FAMILY_RS200) || \ + (info->ChipFamily == CHIP_FAMILY_RV250) || \ + (info->ChipFamily == CHIP_FAMILY_RV280) || \ + (info->ChipFamily == CHIP_FAMILY_RS300)) + + +#define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300) || \ + (info->ChipFamily == CHIP_FAMILY_RV350) || \ + (info->ChipFamily == CHIP_FAMILY_R350) || \ + (info->ChipFamily == CHIP_FAMILY_RV380) || \ + (info->ChipFamily == CHIP_FAMILY_R420) || \ + (info->ChipFamily == CHIP_FAMILY_RV410) || \ + (info->ChipFamily == CHIP_FAMILY_RS400)) + +/* + * Errata workarounds + */ +typedef enum { + CHIP_ERRATA_NONE = 0, + CHIP_ERRATA_R300_CG = 0x00000001, + CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, + CHIP_ERRATA_PLL_DELAY = 0x00000004 +} RADEONErrata; + +typedef enum { + CARD_PCI, + CARD_AGP, + CARD_PCIE +} RADEONCardType; + typedef struct { - CARD32 freq; - CARD32 value; + unsigned freq; + unsigned value; }RADEONTMDSPll; typedef struct { @@ -257,20 +315,31 @@ PCITAG PciTag; int Chipset; RADEONChipFamily ChipFamily; + RADEONErrata ChipErrata; Bool FBDev; unsigned long LinearAddr; /* Frame buffer physical address */ unsigned long MMIOAddr; /* MMIO region physical address */ unsigned long BIOSAddr; /* BIOS physical address */ + CARD32 fbLocation; + CARD32 gartLocation; + CARD32 mc_fb_location; + CARD32 mc_agp_location; unsigned char *MMIO; /* Map of MMIO region */ unsigned char *FB; /* Map of frame buffer */ CARD8 *VBIOS; /* Video BIOS pointer */ + Bool IsAtomBios; /* New BIOS used in R420 etc. */ + int ROMHeaderStart; /* Start of the ROM Info Table */ + int MasterDataStart; /* Offset for Master Data Table for ATOM BIOS */ + CARD32 MemCntl; CARD32 BusCntl; unsigned long FbMapSize; /* Size of frame buffer, in bytes */ + unsigned long FbSecureSize; /* Size of secured fb area at end of + framebuffer */ int Flags; /* Saved copy of mode flags */ /* VE/M6 support */ @@ -280,18 +349,12 @@ Bool HasCRTC2; /* All cards except original Radeon */ Bool IsMobility; /* Mobile chips for laptops */ Bool IsIGP; /* IGP chips */ + Bool HasSingleDAC; /* only TVDAC on chip */ Bool IsSecondary; /* Second Screen */ + Bool IsPrimary; /* Primary Screen */ Bool IsSwitching; /* Flag for switching mode */ - Bool Clone; /* Force second head to clone primary*/ - RADEONMonitorType CloneType; - RADEONDDCType CloneDDCType; - DisplayModePtr CloneModes; - DisplayModePtr CurCloneMode; - int CloneFrameX0; - int CloneFrameY0; Bool OverlayOnCRTC2; Bool PanelOff; /* Force panel (LCD/DFP) off */ - int FPBIOSstart; /* Start of the flat panel info */ Bool ddc_mode; /* Validate mode by matching exactly * the modes supported in DDC data */ @@ -339,10 +402,12 @@ XAAInfoRecPtr accel; Bool accelOn; xf86CursorInfoPtr cursor; - unsigned long cursor_start; + unsigned cursor_offset; unsigned long cursor_end; + Bool allowColorTiling; + Bool tilingEnabled; /* mirror of sarea->tiling_enabled */ #ifdef ARGB_CURSOR - Bool cursor_argb; + Bool cursor_argb; #endif int cursor_fg; int cursor_bg; @@ -398,32 +463,37 @@ DGAFunctionRec DGAFuncs; RADEONFBLayout CurrentLayout; + CARD32 dst_pitch_offset; #ifdef XF86DRI Bool noBackBuffer; Bool directRenderingEnabled; + Bool directRenderingInited; + Bool newMemoryMap; + drmVersionPtr pLibDRMVersion; + drmVersionPtr pKernelDRMVersion; DRIInfoPtr pDRIInfo; int drmFD; int numVisualConfigs; __GLXvisualConfig *pVisualConfigs; RADEONConfigPrivPtr pVisualConfigsPriv; + Bool (*DRICloseScreen)(int, ScreenPtr); - drm_handle_t fbHandle; + drm_handle_t fbHandle; drmSize registerSize; - drm_handle_t registerHandle; + drm_handle_t registerHandle; - Bool IsPCI; /* Current card is a PCI card */ + RADEONCardType cardType; /* Current card is a PCI card */ drmSize pciSize; - drm_handle_t pciMemHandle; + drm_handle_t pciMemHandle; unsigned char *PCI; /* Map */ Bool depthMoves; /* Enable depth moves -- slow! */ Bool allowPageFlip; /* Enable 3d page flipping */ Bool have3DWindows; /* Are there any 3d clients? */ - int drmMinor; drmSize gartSize; - drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ + drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ unsigned long gartOffset; unsigned char *AGP; /* Map */ int agpMode; @@ -440,32 +510,32 @@ /* CP ring buffer data */ unsigned long ringStart; /* Offset into GART space */ - drm_handle_t ringHandle; /* Handle from drmAddMap */ + drm_handle_t ringHandle; /* Handle from drmAddMap */ drmSize ringMapSize; /* Size of map */ int ringSize; /* Size of ring (in MB) */ - unsigned char *ring; /* Map */ + drmAddress ring; /* Map */ int ringSizeLog2QW; unsigned long ringReadOffset; /* Offset into GART space */ - drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ + drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ drmSize ringReadMapSize; /* Size of map */ - unsigned char *ringReadPtr; /* Map */ + drmAddress ringReadPtr; /* Map */ /* CP vertex/indirect buffer data */ unsigned long bufStart; /* Offset into GART space */ - drm_handle_t bufHandle; /* Handle from drmAddMap */ + drm_handle_t bufHandle; /* Handle from drmAddMap */ drmSize bufMapSize; /* Size of map */ int bufSize; /* Size of buffers (in MB) */ - unsigned char *buf; /* Map */ + drmAddress buf; /* Map */ int bufNumBufs; /* Number of buffers */ drmBufMapPtr buffers; /* Buffer map */ /* CP GART Texture data */ unsigned long gartTexStart; /* Offset into GART space */ - drm_handle_t gartTexHandle; /* Handle from drmAddMap */ + drm_handle_t gartTexHandle; /* Handle from drmAddMap */ drmSize gartTexMapSize; /* Size of map */ int gartTexSize; /* Size of GART tex space (in MB) */ - unsigned char *gartTex; /* Map */ + drmAddress gartTex; /* Map */ int log2GARTTexGran; /* CP accleration */ @@ -486,16 +556,18 @@ int backPitch; int depthOffset; int depthPitch; + int depthBits; int textureOffset; int textureSize; int log2TexGran; + int pciGartSize; + unsigned pciGartOffset; + void *pciGartBackup; CARD32 frontPitchOffset; CARD32 backPitchOffset; CARD32 depthPitchOffset; - CARD32 dst_pitch_offset; - /* offscreen memory management */ int backLines; FBAreaPtr backArea; @@ -515,23 +587,97 @@ int irq; + Bool DMAForXv; + #ifdef PER_CONTEXT_SAREA int perctx_sarea_size; #endif -#endif + + /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */ + int dma_begin_count; + char *dma_debug_func; + int dma_debug_lineno; +#endif /* XF86DRI */ /* XVideo */ XF86VideoAdaptorPtr adaptor; void (*VideoTimerCallback)(ScrnInfoPtr, Time); FBLinearPtr videoLinear; int videoKey; + Bool MM_TABLE_valid; + struct { + CARD8 table_revision; + CARD8 table_size; + CARD8 tuner_type; + CARD8 audio_chip; + CARD8 product_id; + CARD8 tuner_voltage_teletext_fm; + CARD8 i2s_config; /* configuration of the sound chip */ + CARD8 video_decoder_type; + CARD8 video_decoder_host_config; + CARD8 input[5]; + } MM_TABLE; + CARD16 video_decoder_type; - /* general */ + /* general */ Bool showCache; OptionInfoPtr Options; + #ifdef XFree86LOADER XF86ModReqInfo xaaReq; #endif + + /* X itself has the 3D context */ + Bool XInited3D; + + /* merged fb stuff, also covers clone modes */ + Bool MergedFB; + RADEONScrn2Rel CRT2Position; + char * CRT2HSync; + char * CRT2VRefresh; + char * MetaModes; + ScrnInfoPtr CRT2pScrn; + DisplayModePtr CRT1Modes; + DisplayModePtr CRT1CurrentMode; + int CRT1frameX0; + int CRT1frameY0; + int CRT1frameX1; + int CRT1frameY1; + RADEONMonitorType MergeType; + RADEONDDCType MergeDDCType; + void (*PointerMoved)(int indx, int x, int y); + /* pseudo xinerama support for mergedfb */ + int maxCRT1_X1, maxCRT1_X2, maxCRT1_Y1, maxCRT1_Y2; + int maxCRT2_X1, maxCRT2_X2, maxCRT2_Y1, maxCRT2_Y2; + int maxClone_X1, maxClone_X2, maxClone_Y1, maxClone_Y2; + Bool UseRADEONXinerama; + Bool CRT2IsScrn0; + ExtensionEntry *XineramaExtEntry; + int RADEONXineramaVX, RADEONXineramaVY; + Bool AtLeastOneNonClone; + int MergedFBXDPI, MergedFBYDPI; + Bool NoVirtual; + int CRT1XOffs, CRT1YOffs, CRT2XOffs, CRT2YOffs; + int MBXNR1XMAX, MBXNR1YMAX, MBXNR2XMAX, MBXNR2YMAX; + Bool NonRect, HaveNonRect, HaveOffsRegions, MouseRestrictions; + region NonRectDead, OffDead1, OffDead2; + + int constantDPI; /* -1 = auto, 0 = off, 1 = on */ + int RADEONDPIVX, RADEONDPIVY; + RADEONScrn2Rel MergedDPISRel; + int RADEONMergedDPIVX, RADEONMergedDPIVY, RADEONMergedDPIRot; + + /* special handlings for DELL triple-head server */ + Bool IsDellServer; + + /* enable bios hotkey output switching */ + Bool BiosHotkeys; + + int MaxSurfaceWidth; + int MaxLines; + + Bool UseVGAHW; + } RADEONInfoRec, *RADEONInfoPtr; #define RADEONWaitForFifo(pScrn, entries) \ @@ -541,6 +687,7 @@ info->fifo_slots -= entries; \ } while (0) +extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries); extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn); #ifdef XF86DRI @@ -555,33 +702,68 @@ extern void RADEONEngineRestore(ScrnInfoPtr pScrn); extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); +extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data); + extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn); -extern void RADEONSelectBuffer(ScrnInfoPtr pScrn, int buffer); +extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn); extern Bool RADEONAccelInit(ScreenPtr pScreen); +extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a); extern void RADEONEngineInit(ScrnInfoPtr pScrn); extern Bool RADEONCursorInit(ScreenPtr pScreen); extern Bool RADEONDGAInit(ScreenPtr pScreen); +extern void RADEONInit3DEngine(ScrnInfoPtr pScrn); + extern int RADEONMinBits(int val); extern void RADEONInitVideo(ScreenPtr pScreen); extern void RADEONResetVideo(ScrnInfoPtr pScrn); extern void R300CGWorkaround(ScrnInfoPtr pScrn); +extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); +extern void RADEONPllErrataAfterData(RADEONInfoPtr info); + +extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10); +extern Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn); +extern Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn); +extern Bool RADEONGetLVDSInfoFromBIOS (ScrnInfoPtr pScrn); +extern Bool RADEONGetTMDSInfoFromBIOS (ScrnInfoPtr pScrn); +extern Bool RADEONGetHardCodedEDIDFromBIOS (ScrnInfoPtr pScrn); + #ifdef XF86DRI +extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a); +extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn); extern Bool RADEONDRIScreenInit(ScreenPtr pScreen); extern void RADEONDRICloseScreen(ScreenPtr pScreen); extern void RADEONDRIResume(ScreenPtr pScreen); extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen); +extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen); +extern void RADEONDRIInitPageFlip(ScreenPtr pScreen); +extern void RADEONDRIStop(ScreenPtr pScreen); extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn); extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard); extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn); extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info); +extern void RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, + CARD32 pitch, int cpp, + CARD32 *dstPitchOffset, int *x, int *y); +extern pointer RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp, + unsigned int w, CARD32 dstPitchOff, + CARD32 *bufPitch, int x, int *y, + unsigned int *h, unsigned int *hpass); +extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn, + unsigned int bpp, + CARD8 *dst, CARD8 *src, + unsigned int hpass, + unsigned int dstPitch, + unsigned int srcPitch); +extern void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size, + int swap); #define RADEONCP_START(pScrn, info) \ do { \ @@ -597,12 +779,12 @@ do { \ int _ret; \ if (info->CPStarted) { \ - _ret = RADEONCPStop(pScrn, info); \ - if (_ret) { \ + _ret = RADEONCPStop(pScrn, info); \ + if (_ret) { \ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ "%s: CP stop %d\n", __FUNCTION__, _ret); \ - } \ - info->CPStarted = FALSE; \ + } \ + info->CPStarted = FALSE; \ } \ RADEONEngineRestore(pScrn); \ info->CPRuns = FALSE; \ @@ -645,13 +827,21 @@ #define RADEON_VERBOSE 0 -#define RING_LOCALS CARD32 *__head = NULL; int __count = 0 +#define RING_LOCALS CARD32 *__head = NULL; int __expected; int __count = 0 #define BEGIN_RING(n) do { \ if (RADEON_VERBOSE) { \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ - "BEGIN_RING(%d) in %s\n", n, __FUNCTION__); \ + "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ } \ + if (++info->dma_begin_count != 1) { \ + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ + "BEGIN_RING without end at %s:%d\n", \ + info->dma_debug_func, info->dma_debug_lineno); \ + info->dma_begin_count = 1; \ + } \ + info->dma_debug_func = __FILE__; \ + info->dma_debug_lineno = __LINE__; \ if (!info->indirectBuffer) { \ info->indirectBuffer = RADEONCPGetBuffer(pScrn); \ info->indirectStart = 0; \ @@ -659,12 +849,24 @@ info->indirectBuffer->total) { \ RADEONCPFlushIndirect(pScrn, 1); \ } \ + __expected = n; \ __head = (pointer)((char *)info->indirectBuffer->address + \ info->indirectBuffer->used); \ __count = 0; \ } while (0) #define ADVANCE_RING() do { \ + if (info->dma_begin_count-- != 1) { \ + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ + "ADVANCE_RING without begin at %s:%d\n", \ + __FILE__, __LINE__); \ + info->dma_begin_count = 0; \ + } \ + if (__count != __expected) { \ + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ + "ADVANCE_RING count != expected (%d vs %d) at %s:%d\n", \ + __count, __expected, __FILE__, __LINE__); \ + } \ if (RADEON_VERBOSE) { \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ "ADVANCE_RING() start: %d used: %d count: %d\n", \ @@ -735,16 +937,16 @@ #define RADEON_FLUSH_CACHE() \ do { \ BEGIN_RING(2); \ - OUT_RING(CP_PACKET0(RADEON_RB2D_DSTCACHE_CTLSTAT, 0)); \ - OUT_RING(RADEON_RB2D_DC_FLUSH); \ + OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ + OUT_RING(RADEON_RB3D_DC_FLUSH); \ ADVANCE_RING(); \ } while (0) #define RADEON_PURGE_CACHE() \ do { \ BEGIN_RING(2); \ - OUT_RING(CP_PACKET0(RADEON_RB2D_DSTCACHE_CTLSTAT, 0)); \ - OUT_RING(RADEON_RB2D_DC_FLUSH_ALL); \ + OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ + OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ ADVANCE_RING(); \ } while (0) Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man:1.9 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man:1.10 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man:1.9 Mon Jan 26 13:05:43 2004 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man Wed Apr 2 14:02:31 2008 @@ -1,4 +1,4 @@ -.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man,v 1.9 2004/01/26 21:05:43 tsi Exp $ +.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man,v 1.10 2008/04/02 21:02:31 tsi Exp $ .ds q \N'34' .TH RADEON __drivermansuffix__ __vendorversion__ .SH NAME @@ -13,10 +13,11 @@ .fi .SH DESCRIPTION .B radeon -is a XFree86 driver for ATI RADEON based video cards. It contains +is an XFree86 driver for ATI RADEON based video cards. It contains full support for 8, 15, 16 and 24 bit pixel depths, dual-head setup, flat panel, hardware 2D acceleration, hardware 3D acceleration -(except R300 and IGP series cards), hardware cursor, XV extension, Xinerama extension. +(experimental on R300 and R400 series cards), hardware cursor, XV extension, +and the Xinerama extension. .SH SUPPORTED HARDWARE The .B radeon @@ -29,16 +30,16 @@ Radeon 7000(VE), M6 .TP 12 .B RS100 -Radeon IGP320(M) (2D only) +Radeon IGP320(M) .TP 12 .B RV200 Radeon 7500, M7, FireGL 7800 .TP 12 .B RS200 -Radeon IGP330(M)/IGP340(M) (2D only) +Radeon IGP330(M)/IGP340(M) .TP 12 .B RS250 -Radeon Mobility 7000 IGP (2D only) +Radeon Mobility 7000 IGP .TP 12 .B R200 Radeon 8500, 9100, FireGL 8800/8700 @@ -47,7 +48,13 @@ Radeon 9000PRO/9000, M9 .TP 12 .B RS300 -Radeon 9100 IGP (2D only) +Radeon 9100 IGP +.TP 12 +.B RS350 +Radeon 9200 IGP +.TP 12 +.B RS400 +Radeon XPRESS 200/200M IGP .TP 12 .B RV280 Radeon 9200PRO/9200/9200SE, M9+ @@ -64,8 +71,26 @@ .B RV350 Radeon 9600PRO/9600SE/9600, M10/M11, FireGL T2 (2D only) .TP 12 -.B RV360 +.B RV360 Radeon 9600XT (2d only) +.TP 12 +.B RV370 +Radeon X300, M22 (2d only) +.TP 12 +.B RV380 +Radeon X600, M24 (2d only) +.TP 12 +.B RV410 +Radeon X700, M26 PCIE (2d only) +.TP 12 +.B R420 +Radeon X800 AGP (2d only) +.TP 12 +.B R423/R430 +Radeon X800, M28 PCIE (2d only) +.TP 12 +.B R480/R481 +Radeon X850 PCIE/AGP (2d only) .SH CONFIGURATION DETAILS Please refer to XF86Config(__filemansuffix__) for general configuration @@ -117,8 +142,8 @@ .TP .BI "Option \*qUseFBDev\*q \*q" boolean \*q Enable or disable use of an OS\-specific framebuffer device interface -(which is not supported on all OSs). See fbdevhw(__drivermansuffix__) -for further information. +(which is not supported on all OSs). MergedFB does not work when this +option is in use. See fbdevhw(__drivermansuffix__) for further information. .br The default is .B off. @@ -133,12 +158,13 @@ .br 4 \-\- x4 .br +8 \-\- x8 +.br others \-\- invalid .TP .BI "Option \*qAGPFastWrite\*q \*q" boolean \*q -Enable AGP fast write. -.br -(used only when DRI is enabled) +Enable AGP fast write. Enabling this option is frequently the cause of +instability. Used only when the DRI is enabled. .br The default is .B off. @@ -159,12 +185,6 @@ .br The default is .B auto detect. -.TP -.BI "Option \*qForcePCIMode\*q \*q" boolean \*q -Force to use PCI GART for DRI acceleration. -This option is deprecated in favor of the -.BI BusType -option above and will be removed in the next release. .TP .BI "Option \*qDDCMode\*q \*q" boolean \*q Force to use the modes queried from the connected monitor. @@ -184,7 +204,7 @@ .br HIGH \-\- Force to the highest priority. Use this if you have problem with above options. - This may affect performence slightly. + This might affect performance slightly. .br The default value is .B AUTO. @@ -200,7 +220,7 @@ CRT \-\- Analog CRT monitor .br TMDS \-\- Desktop flat panel -.br +.br LVDS \-\- Laptop flat panel .br This option can be used in following format: @@ -218,9 +238,9 @@ DVI port on DVI+VGA cards .br LCD output on laptops -.br -Internal TMDS prot on DVI+DVI cards -.br +.br +Internal TMDS port on DVI+DVI cards +.br .B Secondary head: .br VGA port on DVI+VGA cards @@ -231,54 +251,212 @@ The default value is .B undefined. +.TP +.BI "Option \*qMergedFB\*q \*q" boolean \*q +This enables merged framebuffer mode. In this mode you have a single +shared framebuffer with two viewports looking into it. It is similar +to Xinerama, but has some advantages. It is faster than Xinerama, the +DRI works on both heads, and it supports clone modes. +.br +Merged framebuffer mode provides two linked viewports looking into a +single large shared framebuffer. The size of the framebuffer is +determined by the +.B Virtual +keyword defined on the +.B Screen +section of your XF86Config file. It works just like regular virtual +desktop except you have two viewports looking into it instead of one. +.br +For example, if you wanted a desktop composed of two 1024x768 viewports +looking into a single desktop you would create a virtual desktop of +2048x768 (left/right) or 1024x1536 (above/below), e.g., +.br +.B Virtual 2048 768 +or +.B Virtual 1024 1536 +.br +The virtual desktop can be larger than the size of the viewports +looking into it. In this case the linked viewports will scroll around in the +virtual desktop. Viewports with different sizes are also supported (e.g., one +that is 1024x768 and one that is 640x480). In this case the smaller viewport +will scroll relative to the larger one such that none of the virtual desktop +is inaccessible. If you do not define a virtual desktop the driver will create +one based on the orientation of the heads and size of the largest defined mode in +the display section that is supported on each head. +.br +The relation of the viewports in specified by the +.B CRT2Position +Option. The options are +.B Clone +, +.B LeftOf +, +.B RightOf +, +.B Above +, and +.B Below. +MergedFB is enabled by default if a monitor is detected on each output. If +no position is given it defaults to clone mode (the old clone options are now +deprecated, also, the option OverlayOnCRTC2 has been replaced by the Xv +attribute XV_SWITCHCRT; the overlay can be switched to CRT1 or CRT2 on the fly +in clone mode). +.br +The maximum framebuffer size that the 2D acceleration engine can handle is +8192x8192. The maximum framebuffer size that the 3D engine can handle is +2048x2048. +.br +.B Note: +Page flipping does not work well in certain configurations with MergedFB. If you +see rendering errors or other strange behavior, disable page flipping. Also MergedFB +is not compatible with the +.B UseFBDev +option. +.br +The default value is +.B undefined. +.TP +.BI "Option \*qCRT2HSync\*q \*q" "string" \*q +Set the horizontal sync range for the secondary monitor. +It is not required if a DDC\-capable monitor is connected. +.br +For example, Option "CRT2HSync" "30.0-86.0" +.br +The default value is +.B undefined. +.TP +.BI "Option \*qCRT2VRefresh\*q \*q" "string" \*q +Set the vertical refresh range for the secondary monitor. +It is not required if a DDC\-capable monitor is connected. +.br +For example, Option "CRT2VRefresh" "50.0-120.0" +.br +The default value is +.B undefined. .TP -.BI "Option \*qCloneMode\*q \*q" "string" \*q -Set the first mode for the secondary head. -It can be different from the modes used for the primary head. If you don't -have this line while clone is on, the modes specified for the primary head -will be used for the secondary head. +.BI "Option \*qCRT2Position\*q \*q" "string" \*q +Set the relationship of CRT2 relative to CRT1. Valid options are: +.B Clone +, +.B LeftOf +, +.B RightOf +, +.B Above +, and +.B Below +. +.br +For example, Option "CRT2Position" "RightOf" +.br +This option also supports an offset. This is most useful when +.B MergedNonRectangular +is enabled. For example if you want CRT2 to be offset 100 pixels down from +the start of CRT1, you'd type: +.br +Option "CRT2Position" "LeftOf 100" +.br +The offset is vertical for LeftOf and RightOf and horizontal for Above and +Below. Offsets can be positive or negative. +.br +The default value is +.B Clone. +.TP +.BI "Option \*qMetaModes\*q \*q" "string" \*q +MetaModes are mode combinations for CRT1 and CRT2. If you are using merged +frame buffer mode and want to change modes (CTRL-ALT-+/-), these define which +modes will be switched to on CRT1 and CRT2. The MetaModes are defined as +CRT1Mode-CRT2Mode (800x600-1024x768). Modes listed individually (800x600) +define clone modes, that way you can mix clone modes with non-clone modes. +Also some programs require "standard" modes. If you want to add clone modes +of different refreshes or sizes to the mix, they are defined as CRT1Mode+CRT2Mode +(800x600+1024x768). +.br +Note: Any mode you use in the MetaModes must be defined in the +.B Screen +section of your XF86Config file. Modes not defined there will be ignored when +the MetaModes are parsed since the driver uses them to make sure the monitors can +handle those modes. If you do not define a MetaMode the driver will create +one based on the orientation of the heads and size of the largest defined mode in +the display section that is supported on each head. +.br +.B Modes "1024x768" "800x600" "640x480" .br -For example, Option "CloneMode" "1024x768" +For example, Option "MetaModes" "1024x768-1024x768 800x600-1024x768 640x480-800x600 800x600" .br The default value is .B undefined. .TP -.BI "Option \*qCloneHSync\*q \*q" "string" \*q -Set the horizontal sync range for the secondary monitor. -It is not required if a DDC\-capable monitor is connected. +.BI "Option \*qMergedXinerama\*q \*q" boolean \*q +Since merged framebuffer mode does not use Xinerama, apps are not able to intelligently +place windows. Merged framebuffer mode provides its own pseudo-Xinerama. This allows +Xinerama compliant applications to place windows appropriately. There are some caveats. +Since merged framebuffer mode is able to change relative screen sizes and orientations on +the fly, as well has having overlapping viewports, pseudo-Xinerama, might not always +provide the right hints. Also many Xinerama compliant applications only query Xinerama +once at startup; if the information changes, they might not be aware of the change. If +you are already using Xinerama (e.g., a single head card and a dualhead card providing +three heads), pseudo-Xinerama will be disabled. .br -For example, Option "CloneHSync" "30.0-86.0" +This option allows you turn off the driver provided pseudo-Xinerama extension. +.br +The default value is +.B TRUE. +.TP +.BI "Option \*qMergedXineramaCRT2IsScreen0\*q \*q" boolean \*q +By default the pseudo-Xinerama provided by the driver makes the left-most or bottom +head Xinerama screen 0. Certain Xinerama-aware applications do special things with +screen 0. To change that behavior, use this option. .br The default value is .B undefined. .TP -.BI "Option \*qCloneVRefresh\*q \*q" "string" \*q -Set the vertical refresh range for the secondary monitor. -It is not required if a DDC\-capable monitor is connected. +.BI "Option \*qMergedDPI\*q \*q" "string" \*q +The driver will attempt to figure out an appropriate DPI based on the DDC information +and the orientation of the heads when in merged framebuffer mode. If this value does +not suit you, you can manually set the DPI using this option. .br -For example, Option "CloneVRefresh" "50.0-120.0" +For example, Option "MergedDPI" "100 100" .br The default value is .B undefined. .TP -.BI "Option \*qOverlayOnCRTC2\*q \*q" boolean \*q -Force hardware overlay to clone head. +.BI "Option \*qMergedNonRectangular\*q \*q" boolean \*q +If you are using MergedFB with two modes of different sizes, turn this option on to +keep the smaller head from scrolling within the larger virtual desktop and to keep +the mouse from moving into that area. Applications that are not Xinerama aware can +potentially end up stranded in this area. .br The default value is -.B off. +.B FALSE. .TP +.BI "Option \*qColorTiling\*q \*q" "boolean" \*q +Frame buffer can be addressed either in linear or tiled mode. Tiled mode can provide +significant performance benefits with 3D applications, for 2D it shouldn't matter +much. Tiling will be disabled if the virtual x resolution exceeds 2048 (3968 for R300 +and above), if option +.B UseFBDev +is used, or (if DRI is enabled) the drm module is too old. +.br +If this option is enabled, a new dri driver is required for direct rendering too. +.br +Color tiling will be automatically disabled in interlaced or doublescan screen modes. +.br +The default value is +.B on. +.TP .BI "Option \*qIgnoreEDID\*q \*q" boolean \*q Do not use EDID data for mode validation, but DDC is still used for monitor detection. This is different from NoDDC option. .br The default value is .B off. -.TP +.TP .BI "Option \*qPanelSize\*q \*q" "string" \*q Should only be used when driver cannot detect the correct panel size. Apply to both desktop (TMDS) and laptop (LVDS) digital panels. When a valid panel size is specified, the timings collected from -DDC and BIOS will not be used. If you have a panel with timings +DDC and BIOS will not be used. If you have a panel with timings different from that of a standard VESA mode, you have to provide this information through the Modeline. .br @@ -286,9 +464,9 @@ .br The default value is .B none. -.TP +.TP .BI "Option \*qPanelOff\*q \*q" boolean \*q -Disable panel output. Only used when clone is enabled. +Disable panel output. .br The default value is .B off. @@ -297,21 +475,103 @@ Enable page flipping for 3D acceleration. This will increase performance but not work correctly in some rare cases, hence the default is .B off. - .TP .BI "Option \*qForceMinDotClock\*q \*q" frequency \*q Override minimum dot clock. Some Radeon BIOSes report a minimum dot clock unsuitable (too high) for use with television sets even when they actually can produce lower dot clocks. If this is the case you can override the value here. -.B Note that using this option may damage your hardware. +.B Note that using this option might damage your hardware. You have been warned. The .B frequency parameter may be specified as a float value with standard suffixes like "k", "kHz", "M", "MHz". +.TP +.BI "Option \*qDepthBits\*q \*q" integer \*q +Precision in bits per pixel of the shared depth buffer used for 3D acceleration. +Valid values are 16 and 24. When this is 24, there will also be a hardware +accelerated stencil buffer, but the combined depth/stencil buffer will take up +twice as much video RAM as when it's 16. +Default: +.B The same as the screen depth. +.TP +.BI "Option \*qDMAForXv\*q \*q" boolean \*q +Try or don't try to use DMA for Xv image transfers. This will reduce CPU +usage when playing big videos like DVDs, but might cause instabilities. +Default: +.B on. +.TP +.BI "Option \*qSubPixelOrder\*q \*q" "string" \*q +Force subpixel order to specified order. +Subpixel order is used for subpixel decimation on flat panels. +.br +NONE \-\- No subpixel (CRT like displays) +.br +RGB \-\- in horizontal RGB order (most flat panels) +.br +BGR \-\- in horizontal BGR order (some flat panels) + +.br +This option is intended to be used in following cases: +.br +1. The default subpixel order is incorrect for your panel. +.br +2. Enable subpixel decimation on analog panels. +.br +3. Adjust to one display type in dual-head clone mode setup. +.br +4. Get better performance with Render acceleration on +digital panels (use NONE setting). +.br +The default is +.B NONE +for CRT, +.B RGB +for digital panels +.TP +.BI "Option \*qDynamicClocks\*q \*q" boolean \*q +Enable dynamic clock scaling. The on-chip clocks will scale dynamically +based on usage. This can help reduce heat and increase battery +life by reducing power usage. Some users report reduced 3D performance +with this enabled. The default is +.B off. +.TP +.BI "Option \*qBIOSHotkeys\*q \*q" boolean \*q +Enable BIOS hotkey output switching. This allows the BIOS to toggle outputs +using hotkeys (e.g., fn-f7, etc.). Since the driver does not support ACPI, +there is no way to validate modes on an output switch and the BIOS can +potentially change things behind the driver's back. The default is +.B off. +.TP +.BI "Option \*qReverseDDC\*q \*q" boolean \*q +When BIOS connector informations aren't available, use this option to +reverse the mapping of the 2 main DDC ports. Use this if the X serve +obviously detects the wrong display for each connector. This is +typically needed on the Radeon 9600 cards bundled with Apple G5s. The +default is +.B off. +.TP +.BI "Option \*qLVDSProbePLL\*q \*q" boolean \*q +When BIOS panel informations aren't available (like on PowerBooks), it +might still be necessary to use the firmware provided PLL values for the +panel or flickering will happen. This option will force probing of +the current value programmed in the chip when X is launched in that +case. This is only useful for LVDS panels (laptop internal panels). +The default is +.B on. +.TP .SH SEE ALSO XFree86(1), XF86Config(__filemansuffix__), xf86config(1), Xserver(1), X(__miscmansuffix__) .SH AUTHORS .nf -Authors include: ... +Authors include: +Rickard E. (Rik) Faith \fIfaith@precisioninsight.com\fP +Kevin E. Martin \fIkem@freedesktop.org\fP +Alan Hourihane \fIalanh@fairlite.demon.co.uk\fP +Marc Aurele La France \fItsi@xfree86.org\fP +Benjamin Herrenschmidt \fIbenh@kernel.crashing.org\fP +Michel DƤnzer \fImichel@tungstengraphics.com\fP +Alex Deucher \fIalexdeucher@gmail.com\fP +Bogdan D. \fIbogdand@users.sourceforge.net\fP +Eric Anholt \fIeric@anholt.net\fP Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c:1.40 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c:1.42 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c:1.40 Sat Jan 28 17:46:52 2006 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c Thu Apr 3 07:50:48 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c,v 1.40 2006/01/29 01:46:52 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c,v 1.42 2008/04/03 14:50:48 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -111,8 +111,6 @@ { RADEON_ROP3_ONE, RADEON_ROP3_ONE } /* GXset */ }; -extern int gRADEONEntityIndex; - /* The FIFO has 64 slots. This routines waits until at least `entries' * of these slots are empty. */ @@ -128,7 +126,7 @@ INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; if (info->fifo_slots >= entries) return; } - RADEONTRACE(("FIFO timed out: %d entries, stat=0x%08x\n", + RADEONTRACE(("FIFO timed out: %u entries, stat=0x%08x\n", INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, INREG(RADEON_RBBM_STATUS))); xf86DrvMsg(pScrn->scrnIndex, X_ERROR, @@ -151,13 +149,17 @@ unsigned char *RADEONMMIO = info->MMIO; int i; - OUTREGP(RADEON_RB2D_DSTCACHE_CTLSTAT, - RADEON_RB2D_DC_FLUSH_ALL, - ~RADEON_RB2D_DC_FLUSH_ALL); + OUTREGP(RADEON_RB3D_DSTCACHE_CTLSTAT, + RADEON_RB3D_DC_FLUSH_ALL, + ~RADEON_RB3D_DC_FLUSH_ALL); for (i = 0; i < RADEON_TIMEOUT; i++) { - if (!(INREG(RADEON_RB2D_DSTCACHE_CTLSTAT) & RADEON_RB2D_DC_BUSY)) + if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY)) break; } + if (i == RADEON_TIMEOUT) { + RADEONTRACE(("DC flush timeout: %x\n", + INREG(RADEON_RB3D_DSTCACHE_CTLSTAT))); + } } /* Reset graphics card to known state */ @@ -170,11 +172,37 @@ CARD32 rbbm_soft_reset; CARD32 host_path_cntl; + /* The following RBBM_SOFT_RESET sequence can help un-wedge + * an R300 after the command processor got stuck. + */ + rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); + OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | + RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_HI | + RADEON_SOFT_RESET_SE | + RADEON_SOFT_RESET_RE | + RADEON_SOFT_RESET_PP | + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB)); + INREG(RADEON_RBBM_SOFT_RESET); + OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (CARD32) + ~(RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_HI | + RADEON_SOFT_RESET_SE | + RADEON_SOFT_RESET_RE | + RADEON_SOFT_RESET_PP | + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB))); + INREG(RADEON_RBBM_SOFT_RESET); + OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); + INREG(RADEON_RBBM_SOFT_RESET); + RADEONEngineFlush(pScrn); clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); - if (info->R300CGWorkaround) R300CGWorkaround(pScrn); + RADEONPllErrataAfterIndex(info); +#if 0 /* taken care of by new PM code */ /* Some ASICs have bugs with dynamic-on feature, which are * ASIC-version dependent, so we force all blocks on for now */ @@ -191,8 +219,11 @@ OUTPLL(RADEON_SCLK_MORE_CNTL, tmp | RADEON_SCLK_MORE_FORCEON); } } +#endif /* new PM code */ mclk_cntl = INPLL(pScrn, RADEON_MCLK_CNTL); + +#if 0 /* handled by new PM code */ OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl | RADEON_FORCEON_MCLKA | RADEON_FORCEON_MCLKB | @@ -200,6 +231,7 @@ RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC | RADEON_FORCEON_AIC)); +#endif /* new PM code */ /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some * unexpected behaviour on some machines. Here we use @@ -208,9 +240,7 @@ host_path_cntl = INREG(RADEON_HOST_PATH_CNTL); rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350)) { + if (IS_R300_VARIANT) { CARD32 tmp; OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | @@ -219,12 +249,11 @@ RADEON_SOFT_RESET_E2)); INREG(RADEON_RBBM_SOFT_RESET); OUTREG(RADEON_RBBM_SOFT_RESET, 0); - tmp = INREG(RADEON_RB2D_DSTCACHE_MODE); - OUTREG(RADEON_RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */ + tmp = INREG(RADEON_RB3D_DSTCACHE_MODE); + OUTREG(RADEON_RB3D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */ } else { OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_HI | RADEON_SOFT_RESET_SE | RADEON_SOFT_RESET_RE | RADEON_SOFT_RESET_PP | @@ -233,7 +262,6 @@ INREG(RADEON_RBBM_SOFT_RESET); OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (CARD32) ~(RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_HI | RADEON_SOFT_RESET_SE | RADEON_SOFT_RESET_RE | RADEON_SOFT_RESET_PP | @@ -246,14 +274,12 @@ INREG(RADEON_HOST_PATH_CNTL); OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl); - if ((info->ChipFamily != CHIP_FAMILY_R300) && - (info->ChipFamily != CHIP_FAMILY_R350) && - (info->ChipFamily != CHIP_FAMILY_RV350)) + if (!IS_R300_VARIANT) OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); - OUTPLL(RADEON_MCLK_CNTL, mclk_cntl); - if (info->R300CGWorkaround) R300CGWorkaround(pScrn); + RADEONPllErrataAfterIndex(info); + OUTPLL(pScrn, RADEON_MCLK_CNTL, mclk_cntl); } /* Restore the acceleration hardware to its previous state */ @@ -261,31 +287,19 @@ { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - int pitch64; RADEONTRACE(("EngineRestore (%d/%d)\n", info->CurrentLayout.pixel_code, info->CurrentLayout.bitsPerPixel)); - RADEONWaitForFifo(pScrn, 1); - - /* NOTE: The following RB2D_DSTCACHE_MODE setting will cause the - * R300 to hang. ATI does not see a reason to change it from the - * default BIOS settings (even on non-R300 cards). This setting - * might be removed in future versions of the Radeon driver. + /* Setup engine location. This shouldn't be necessary since we + * set them appropriately before any accel ops, but let's avoid + * random bogus DMA in case we inadvertently trigger the engine + * in the wrong place (happened). */ - - /* Turn of all automatic flushing - we'll do it all */ - if ((info->ChipFamily != CHIP_FAMILY_R300) && - (info->ChipFamily != CHIP_FAMILY_R350) && - (info->ChipFamily != CHIP_FAMILY_RV350)) - OUTREG(RADEON_RB2D_DSTCACHE_MODE, 0); - - pitch64 = ((pScrn->displayWidth * (pScrn->bitsPerPixel / 8) + 0x3f)) >> 6; - - RADEONWaitForFifo(pScrn, 1); - OUTREG(RADEON_DEFAULT_OFFSET, ((INREG(RADEON_DISPLAY_BASE_ADDR) >> 10) - | (pitch64 << 22))); + RADEONWaitForFifo(pScrn, 2); + OUTREG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset); + OUTREG(RADEON_SRC_PITCH_OFFSET, info->dst_pitch_offset); RADEONWaitForFifo(pScrn, 1); #if X_BYTE_ORDER == X_BIG_ENDIAN @@ -296,10 +310,8 @@ OUTREGP(RADEON_DP_DATATYPE, 0, ~RADEON_HOST_BIG_ENDIAN_EN); #endif - /* Restore SURFACE_CNTL - only the first head contains valid data -ReneR */ - if (!info->IsSecondary) { - OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); - } + /* Restore SURFACE_CNTL */ + OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); RADEONWaitForFifo(pScrn, 1); OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX @@ -309,9 +321,7 @@ | RADEON_GMC_BRUSH_SOLID_COLOR | RADEON_GMC_SRC_DATATYPE_COLOR)); - RADEONWaitForFifo(pScrn, 7); - OUTREG(RADEON_DST_LINE_START, 0); - OUTREG(RADEON_DST_LINE_END, 0); + RADEONWaitForFifo(pScrn, 5); OUTREG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); OUTREG(RADEON_DP_BRUSH_BKGD_CLR, 0x00000000); OUTREG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff); @@ -319,6 +329,8 @@ OUTREG(RADEON_DP_WRITE_MASK, 0xffffffff); RADEONWaitForIdleMMIO(pScrn); + + info->XInited3D = FALSE; } /* Initialize the acceleration hardware */ @@ -332,15 +344,6 @@ info->CurrentLayout.bitsPerPixel)); OUTREG(RADEON_RB3D_CNTL, 0); -#ifdef __powerpc__ -#ifdef XF86DRI - if(!info->directRenderingEnabled) -#endif - { - OUTREG(RADEON_MC_FB_LOCATION, 0xffff0000); - OUTREG(RADEON_MC_AGP_LOCATION, 0xfffff000); - } -#endif RADEONEngineReset(pScrn); @@ -363,7 +366,8 @@ info->dp_gui_master_cntl = ((info->datatype << RADEON_GMC_DST_DATATYPE_SHIFT) - | RADEON_GMC_CLR_CMP_CNTL_DIS); + | RADEON_GMC_CLR_CMP_CNTL_DIS + | RADEON_GMC_DST_PITCH_OFFSET_CNTL); #ifdef XF86DRI info->sc_left = 0x00000000; @@ -381,12 +385,14 @@ RADEONEngineRestore(pScrn); } + #define ACCEL_MMIO #define ACCEL_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO #define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) #define FINISH_ACCEL() +#include "radeon_commonfuncs.c" #include "radeon_accelfuncs.c" #undef ACCEL_MMIO @@ -405,6 +411,8 @@ #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) #define FINISH_ACCEL() ADVANCE_RING() + +#include "radeon_commonfuncs.c" #include "radeon_accelfuncs.c" #undef ACCEL_CP @@ -582,11 +590,245 @@ drmCommandWriteRead(info->drmFD, DRM_RADEON_INDIRECT, &indirect, sizeof(drmRadeonIndirect)); } + +/** \brief Calculate HostDataBlit parameters from pointer and pitch + * + * This is a helper for the trivial HostDataBlit users that don't need to worry + * about tiling etc. + */ +void +RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, CARD32 pitch, int cpp, + CARD32 *dstPitchOff, int *x, int *y) +{ + RADEONInfoPtr info = RADEONPTR( pScrn ); + CARD32 dstOffs = dst - info->FB + info->fbLocation; + + *dstPitchOff = pitch << 16 | (dstOffs & ~RADEON_BUFFER_ALIGN) >> 10; + *y = ( dstOffs & RADEON_BUFFER_ALIGN ) / pitch; + *x = ( ( dstOffs & RADEON_BUFFER_ALIGN ) - ( *y * pitch ) ) / cpp; +} + +/* Set up a hostdata blit to transfer data from system memory to the + * framebuffer. Returns the address where the data can be written to and sets + * the dstPitch and hpass variables as required. + */ +pointer +RADEONHostDataBlit( + ScrnInfoPtr pScrn, + unsigned int cpp, + unsigned int w, + CARD32 dstPitchOff, + CARD32 *bufPitch, + int x, + int *y, + unsigned int *h, + unsigned int *hpass +){ + RADEONInfoPtr info = RADEONPTR( pScrn ); + CARD32 format; + int dwords; + CARD8 *ret; + RING_LOCALS; + + if ( *h == 0 ) + { + return NULL; + } + + switch ( cpp ) + { + case 4: + format = RADEON_GMC_DST_32BPP; + *bufPitch = 4 * w; + break; + case 2: + format = RADEON_GMC_DST_16BPP; + *bufPitch = 2 * ((w + 1) & ~1); + break; + case 1: + format = RADEON_GMC_DST_8BPP_CI; + *bufPitch = (w + 3) & ~3; + break; + default: + xf86DrvMsg( pScrn->scrnIndex, X_ERROR, + "RADEONHostDataBlit: Unsupported cpp %d!\n", cpp ); + return NULL; + } + +#if X_BYTE_ORDER == X_BIG_ENDIAN + /* Swap doesn't work on R300 and later, it's handled during the + * copy to ind. buffer pass + */ + if (info->ChipFamily < CHIP_FAMILY_R300) { + BEGIN_RING(2); + if (cpp == 2) + OUT_RING_REG(RADEON_RBBM_GUICNTL, + RADEON_HOST_DATA_SWAP_HDW); + else if (cpp == 1) + OUT_RING_REG(RADEON_RBBM_GUICNTL, + RADEON_HOST_DATA_SWAP_32BIT); + else + OUT_RING_REG(RADEON_RBBM_GUICNTL, + RADEON_HOST_DATA_SWAP_NONE); + ADVANCE_RING(); + } #endif -/* Initialize XAA for supported acceleration and also initialize the - * graphics hardware for acceleration + /*RADEON_PURGE_CACHE(); + RADEON_WAIT_UNTIL_IDLE();*/ + + *hpass = min( *h, ( ( RADEON_BUFFER_SIZE - 10 * 4 ) / *bufPitch ) ); + dwords = *hpass * *bufPitch / 4; + + BEGIN_RING( dwords + 10 ); + OUT_RING( CP_PACKET3( RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT, dwords + 10 - 2 ) ); + OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL + | RADEON_GMC_DST_CLIPPING + | RADEON_GMC_BRUSH_NONE + | format + | RADEON_GMC_SRC_DATATYPE_COLOR + | RADEON_ROP3_S + | RADEON_DP_SRC_SOURCE_HOST_DATA + | RADEON_GMC_CLR_CMP_CNTL_DIS + | RADEON_GMC_WR_MSK_DIS ); + OUT_RING( dstPitchOff ); + OUT_RING( (*y << 16) | x ); + OUT_RING( ((*y + *hpass) << 16) | (x + w) ); + OUT_RING( 0xffffffff ); + OUT_RING( 0xffffffff ); + OUT_RING( *y << 16 | x ); + OUT_RING( *hpass << 16 | (*bufPitch / cpp) ); + OUT_RING( dwords ); + + ret = ( CARD8* )&__head[__count]; + + __count += dwords; + ADVANCE_RING(); + + *y += *hpass; + *h -= *hpass; + + return ret; +} + +void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size, int swap) +{ + switch(swap) { + case RADEON_HOST_DATA_SWAP_HDW: + { + unsigned int *d = (unsigned int *)(pointer)dst; + unsigned int *s = (unsigned int *)(pointer)src; + unsigned int nwords = size >> 2; + + for (; nwords > 0; --nwords, ++d, ++s) + *d = ((*s & 0xffff) << 16) | ((*s >> 16) & 0xffff); + return; + } + case RADEON_HOST_DATA_SWAP_32BIT: + { + unsigned int *d = (unsigned int *)(pointer)dst; + unsigned int *s = (unsigned int *)(pointer)src; + unsigned int nwords = size >> 2; + + for (; nwords > 0; --nwords, ++d, ++s) +#ifdef __powerpc__ + asm volatile("stwbrx %0,0,%1" : : "r" (*s), "r" (d)); +#else + *d = ((*s >> 24) & 0xff) | ((*s >> 8) & 0xff00) + | ((*s & 0xff00) << 8) | ((*s & 0xff) << 24); +#endif + return; + } + case RADEON_HOST_DATA_SWAP_16BIT: + { + unsigned short *d = (unsigned short *)(pointer)dst; + unsigned short *s = (unsigned short *)(pointer)src; + unsigned int nwords = size >> 1; + + for (; nwords > 0; --nwords, ++d, ++s) +#ifdef __powerpc__ + asm volatile("stwbrx %0,0,%1" : : "r" (*s), "r" (d)); +#else + *d = ((*s >> 24) & 0xff) | ((*s >> 8) & 0xff00) + | ((*s & 0xff00) << 8) | ((*s & 0xff) << 24); +#endif + return; + } + } + if (src != dst) + memmove(dst, src, size); +} + +/* Copies a single pass worth of data for a hostdata blit set up by + * RADEONHostDataBlit(). */ +void +RADEONHostDataBlitCopyPass( + ScrnInfoPtr pScrn, + unsigned int cpp, + CARD8 *dst, + CARD8 *src, + unsigned int hpass, + unsigned int dstPitch, + unsigned int srcPitch +){ + +#if X_BYTE_ORDER == X_BIG_ENDIAN + RADEONInfoPtr info = RADEONPTR( pScrn ); +#endif + + /* RADEONHostDataBlitCopy can return NULL ! */ + if( (dst==NULL) || (src==NULL)) return; + + if ( dstPitch == srcPitch ) + { +#if X_BYTE_ORDER == X_BIG_ENDIAN + if (info->ChipFamily >= CHIP_FAMILY_R300) { + switch(cpp) { + case 1: + RADEONCopySwap(dst, src, hpass * dstPitch, + RADEON_HOST_DATA_SWAP_32BIT); + return; + case 2: + RADEONCopySwap(dst, src, hpass * dstPitch, + RADEON_HOST_DATA_SWAP_HDW); + return; + } + } +#endif + memcpy( dst, src, hpass * dstPitch ); + } + else + { + unsigned int minPitch = min( dstPitch, srcPitch ); + while ( hpass-- ) + { +#if X_BYTE_ORDER == X_BIG_ENDIAN + if (info->ChipFamily >= CHIP_FAMILY_R300) { + switch(cpp) { + case 1: + RADEONCopySwap(dst, src, minPitch, + RADEON_HOST_DATA_SWAP_32BIT); + goto next; + case 2: + RADEONCopySwap(dst, src, minPitch, + RADEON_HOST_DATA_SWAP_HDW); + goto next; + } + } +#endif + memcpy( dst, src, minPitch ); +#if X_BYTE_ORDER == X_BIG_ENDIAN + next: +#endif + src += srcPitch; + dst += dstPitch; + } + } +} + +#endif + Bool RADEONAccelInit(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; @@ -602,7 +844,7 @@ if (info->directRenderingEnabled) RADEONAccelInitCP(pScreen, a); else -#endif +#endif /* XF86DRI */ RADEONAccelInitMMIO(pScreen, a); RADEONEngineInit(pScrn); @@ -611,6 +853,24 @@ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "XAAInit Error\n"); return FALSE; } - return TRUE; } + +void RADEONInit3DEngine(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + +#ifdef XF86DRI + if (info->directRenderingEnabled) { + RADEONSAREAPrivPtr pSAREAPriv; + + pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); + pSAREAPriv->ctxOwner = DRIGetContext(pScrn->pScreen); + RADEONInit3DEngineCP(pScrn); + } else +#endif + RADEONInit3DEngineMMIO(pScrn); + + info->XInited3D = TRUE; +} + Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c:1.8 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c:1.9 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c:1.8 Sun Nov 2 21:11:05 2003 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c Wed Apr 2 14:02:31 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c,v 1.8 2003/11/03 05:11:05 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c,v 1.9 2008/04/02 21:02:31 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -91,107 +91,25 @@ #endif #endif -/* MMIO: - * - * Wait for the graphics engine to be completely idle: the FIFO has - * drained, the Pixel Cache is flushed, and the engine is idle. This is - * a standard "sync" function that will make the hardware "quiescent". - * - * CP: - * - * Wait until the CP is completely idle: the FIFO has drained and the CP - * is idle. - */ -void -FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i = 0; - -#ifdef ACCEL_CP - /* Make sure the CP is idle first */ - if (info->CPStarted) { - int ret; - FLUSH_RING(); - - for (;;) { - do { - ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_IDLE); - if (ret && ret != -EBUSY) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "%s: CP idle %d\n", __FUNCTION__, ret); - } - } while ((ret == -EBUSY) && (i++ < RADEON_TIMEOUT)); - - if (ret == 0) return; - - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Idle timed out, resetting engine...\n"); - RADEONEngineReset(pScrn); - RADEONEngineRestore(pScrn); - - /* Always restart the engine when doing CP 2D acceleration */ - RADEONCP_RESET(pScrn, info); - RADEONCP_START(pScrn, info); - } - } -#endif - - RADEONTRACE(("WaitForIdle (entering): %d entries, stat=0x%08x\n", - INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, - INREG(RADEON_RBBM_STATUS))); - - /* Wait for the engine to go idle */ - RADEONWaitForFifoFunction(pScrn, 64); - - for (;;) { - for (i = 0; i < RADEON_TIMEOUT; i++) { - if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) { - RADEONEngineFlush(pScrn); - return; - } - } - RADEONTRACE(("Idle timed out: %d entries, stat=0x%08x\n", - INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, - INREG(RADEON_RBBM_STATUS))); - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Idle timed out, resetting engine...\n"); - RADEONEngineReset(pScrn); - RADEONEngineRestore(pScrn); -#ifdef XF86DRI - if (info->directRenderingEnabled) { - RADEONCP_RESET(pScrn, info); - RADEONCP_START(pScrn, info); - } -#endif - } -} /* This callback is required for multiheader cards using XAA */ static void FUNC_NAME(RADEONRestoreAccelState)(ScrnInfoPtr pScrn) { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; + /*RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO;*/ #ifdef ACCEL_MMIO - CARD32 pitch64; - - pitch64 = ((pScrn->displayWidth * (pScrn->bitsPerPixel / 8) + 0x3f)) >> 6; - - OUTREG(RADEON_DEFAULT_OFFSET, (((INREG(RADEON_DISPLAY_BASE_ADDR) + pScrn->fbOffset) >> 10) | - (pitch64 << 22))); - +/* OUTREG(RADEON_DEFAULT_OFFSET, info->dst_pitch_offset);*/ /* FIXME: May need to restore other things, like BKGD_CLK FG_CLK... */ RADEONWaitForIdleMMIO(pScrn); #else /* ACCEL_CP */ - RADEONWaitForFifo(pScrn, 1); - OUTREG(RADEON_DEFAULT_OFFSET, info->frontPitchOffset); +/* RADEONWaitForFifo(pScrn, 1); + OUTREG(RADEON_DEFAULT_OFFSET, info->frontPitchOffset);*/ RADEONWaitForIdleMMIO(pScrn); @@ -243,8 +161,10 @@ RADEONInfoPtr info = RADEONPTR(pScrn); ACCEL_PREAMBLE(); - BEGIN_ACCEL(2); + BEGIN_ACCEL(3); + OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset | + ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x); OUT_ACCEL_REG(RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); @@ -271,6 +191,7 @@ BEGIN_ACCEL(1); OUT_ACCEL_REG(RADEON_DST_LINE_PATCOUNT, 0x55 << RADEON_BRES_CNTL_SHIFT); + FINISH_ACCEL(); } BEGIN_ACCEL(3); @@ -297,10 +218,12 @@ if (dir == DEGREES_0) w = len; else h = len; - BEGIN_ACCEL(3); + BEGIN_ACCEL(4); OUT_ACCEL_REG(RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM)); + OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset | + ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x); OUT_ACCEL_REG(RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); @@ -330,8 +253,10 @@ xb, yb, 1, DEGREES_0); - BEGIN_ACCEL(2); + BEGIN_ACCEL(3); + OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset | + ((info->tilingEnabled && (ya <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); OUT_ACCEL_REG(RADEON_DST_LINE_START, (ya << 16) | xa); OUT_ACCEL_REG(RADEON_DST_LINE_END, (yb << 16) | xb); @@ -413,12 +338,14 @@ dp_gui_master_cntl &= ~RADEON_GMC_SRC_DATATYPE_MASK; dp_gui_master_cntl |= RADEON_GMC_SRC_DATATYPE_COLOR; - BEGIN_ACCEL(7); + BEGIN_ACCEL(8); OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, dp_gui_master_cntl); - OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, fg); OUT_ACCEL_REG(RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM)); + OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset | + ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); + OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, fg); OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x); OUT_ACCEL_REG(RADEON_DST_WIDTH_HEIGHT, (1 << 16) | 1); @@ -459,8 +386,10 @@ FUNC_NAME(RADEONDashedLastPel)(pScrn, xb, yb, info->dash_bg); } - BEGIN_ACCEL(3); + BEGIN_ACCEL(4); + OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset | + ((info->tilingEnabled && (ya <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); OUT_ACCEL_REG(RADEON_DST_LINE_START, (ya << 16) | xa); OUT_ACCEL_REG(RADEON_DST_LINE_PATCOUNT, phase); OUT_ACCEL_REG(RADEON_DST_LINE_END, (yb << 16) | xb); @@ -516,7 +445,8 @@ | RADEON_GMC_BRUSH_NONE | RADEON_GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].rop - | RADEON_DP_SRC_SOURCE_MEMORY); + | RADEON_DP_SRC_SOURCE_MEMORY + | RADEON_GMC_SRC_PITCH_OFFSET_CNTL); BEGIN_ACCEL(3); @@ -545,8 +475,12 @@ if (info->xdir < 0) xa += w - 1, xb += w - 1; if (info->ydir < 0) ya += h - 1, yb += h - 1; - BEGIN_ACCEL(3); + BEGIN_ACCEL(5); + OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, info->dst_pitch_offset | + ((info->tilingEnabled && (ya <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); + OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset | + ((info->tilingEnabled && (yb <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); OUT_ACCEL_REG(RADEON_SRC_Y_X, (ya << 16) | xa); OUT_ACCEL_REG(RADEON_DST_Y_X, (yb << 16) | xb); OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); @@ -630,8 +564,10 @@ RADEONInfoPtr info = RADEONPTR(pScrn); ACCEL_PREAMBLE(); - BEGIN_ACCEL(3); + BEGIN_ACCEL(4); + OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset | + ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); OUT_ACCEL_REG(RADEON_BRUSH_Y_X, (patterny << 8) | patternx); OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x); OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); @@ -683,8 +619,10 @@ RADEONInfoPtr info = RADEONPTR(pScrn); ACCEL_PREAMBLE(); - BEGIN_ACCEL(3); + BEGIN_ACCEL(4); + OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset | + ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); OUT_ACCEL_REG(RADEON_BRUSH_Y_X, (paty << 16) | patx); OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x); OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); @@ -694,7 +632,7 @@ #endif #ifdef ACCEL_CP -#define CP_BUFSIZE (info->indirectBuffer->total/4-9) +#define CP_BUFSIZE (info->indirectBuffer->total/4-10) /* Helper function to write out a HOSTDATA_BLT packet into the indirect * buffer and set the XAA scratch buffer address appropriately. @@ -711,10 +649,12 @@ "CPScanline Packet h=%d hpass=%d chunkwords=%d\n", info->scanline_h, info->scanline_hpass, chunk_words); } - BEGIN_RING(chunk_words+9); + BEGIN_RING(chunk_words+10); - OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT,chunk_words+9-2)); + OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT,chunk_words+10-2)); OUT_RING(info->dp_gui_master_cntl_clip); + OUT_RING(info->dst_pitch_offset | + ((info->tilingEnabled && (info->scanline_y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); OUT_RING((info->scanline_y << 16) | (info->scanline_x1clip & 0xffff)); OUT_RING(((info->scanline_y+info->scanline_hpass) << 16) | @@ -755,6 +695,8 @@ RADEONInfoPtr info = RADEONPTR(pScrn); ACCEL_PREAMBLE(); + info->scanline_bpp = 0; + /* Save for later clipping */ info->dp_gui_master_cntl_clip = (info->dp_gui_master_cntl | RADEON_GMC_DST_CLIPPING @@ -792,9 +734,12 @@ #if X_BYTE_ORDER == X_LITTLE_ENDIAN BEGIN_ACCEL(1); #else - BEGIN_ACCEL(2); + if (info->ChipFamily < CHIP_FAMILY_R300) { + BEGIN_ACCEL(2); - OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT); + OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT); + } else + BEGIN_ACCEL(1); #endif OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); @@ -838,9 +783,11 @@ info->scanline_direct = 0; } - BEGIN_ACCEL(4 + (info->scanline_direct ? + BEGIN_ACCEL(5 + (info->scanline_direct ? (info->scanline_words * h) : 0)); + OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset | + ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, (y << 16) | ((x+skipleft) & 0xffff)); OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff)); @@ -917,6 +864,22 @@ #else /* ACCEL_CP */ +#if X_BYTE_ORDER == X_BIG_ENDIAN + if (info->ChipFamily >= CHIP_FAMILY_R300) { + if (info->scanline_bpp == 16) { + RADEONCopySwap(info->scratch_buffer[bufno], + info->scratch_buffer[bufno], + info->scanline_words << 2, + RADEON_HOST_DATA_SWAP_HDW); + } else if (info->scanline_bpp < 15) { + RADEONCopySwap(info->scratch_buffer[bufno], + info->scratch_buffer[bufno], + info->scanline_words << 2, + RADEON_HOST_DATA_SWAP_32BIT); + } + } +#endif + if (--info->scanline_hpass) { info->scratch_buffer[bufno] += 4 * info->scanline_words; } else if (info->scanline_h) { @@ -972,12 +935,15 @@ #if X_BYTE_ORDER == X_LITTLE_ENDIAN BEGIN_ACCEL(1); #else - BEGIN_ACCEL(2); + if (info->ChipFamily < CHIP_FAMILY_R300) { + BEGIN_ACCEL(2); - if (bpp == 16) - OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_HDW); - else - OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE); + if (bpp == 16) + OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_HDW); + else + OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE); + } else + BEGIN_ACCEL(1); #endif #endif OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); @@ -1028,9 +994,11 @@ info->scanline_direct = 0; } - BEGIN_ACCEL(4 + (info->scanline_direct ? + BEGIN_ACCEL(5 + (info->scanline_direct ? (info->scanline_words * h) : 0)); + OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset | + ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, (y << 16) | ((x+skipleft) & 0xffff)); OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff)); @@ -1137,39 +1105,7 @@ FUNC_NAME(RADEONSetTransparency)(pScrn, info->trans_color); } -#ifdef ACCEL_CP -/* Point the DST_PITCH_OFFSET register at the current buffer. This - * allows us to interact with the back and depth buffers. All CP 2D - * acceleration commands use the DST_PITCH_OFFSET register. - */ void -RADEONSelectBuffer(ScrnInfoPtr pScrn, int buffer) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - switch (buffer) { - case RADEON_BACK: - info->dst_pitch_offset = info->backPitchOffset; - break; - case RADEON_DEPTH: - info->dst_pitch_offset = info->depthPitchOffset; - break; - default: - case RADEON_FRONT: - info->dst_pitch_offset = info->frontPitchOffset; - break; - } - - BEGIN_ACCEL(1); - - OUT_ACCEL_REG(RADEON_DEFAULT_OFFSET, info->dst_pitch_offset); - - FINISH_ACCEL(); -} -#endif - -static void FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; @@ -1224,15 +1160,17 @@ | LEFT_EDGE_CLIPPING_NEGATIVE_X); a->NumScanlineColorExpandBuffers = 1; a->ScanlineColorExpandBuffers = info->scratch_buffer; - info->scratch_save - = xalloc(((pScrn->virtualX+31)/32*4) - + (pScrn->virtualX * info->CurrentLayout.pixel_bytes)); + if (!info->scratch_save) + info->scratch_save + = xalloc(((pScrn->virtualX+31)/32*4) + + (pScrn->virtualX * info->CurrentLayout.pixel_bytes)); info->scratch_buffer[0] = info->scratch_save; a->SetupForScanlineCPUToScreenColorExpandFill = FUNC_NAME(RADEONSetupForScanlineCPUToScreenColorExpandFill); a->SubsequentScanlineCPUToScreenColorExpandFill = FUNC_NAME(RADEONSubsequentScanlineCPUToScreenColorExpandFill); - a->SubsequentColorExpandScanline = FUNC_NAME(RADEONSubsequentScanline); + a->SubsequentColorExpandScanline + = FUNC_NAME(RADEONSubsequentScanline); /* Solid Lines */ a->SetupForSolidLine @@ -1258,7 +1196,7 @@ a->SolidLineLimits.x2 = pScrn->virtualX-1; a->SolidLineLimits.y2 = pScrn->virtualY-1; - /* Call miSetZeroLineBias() to have mi/mfb/cfb/fb routines match + /* Call miSetZeroLineBias() to have mi/mfb/fb routines match hardware accel two point lines */ miSetZeroLineBias(pScreen, (OCTANT5 | OCTANT6 | OCTANT7 | OCTANT8)); Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_bios.c diff -u /dev/null xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_bios.c:1.1 --- /dev/null Mon Dec 15 09:54:56 2008 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_bios.c Wed Apr 2 14:02:31 2008 @@ -0,0 +1,609 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_bios.c,v 1.1 2008/04/02 21:02:31 tsi Exp $ */ +/* + * Copyright 2004 ATI Technologies Inc., Markham, Ontario + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "xf86.h" +#include "xf86_OSproc.h" + +#include "radeon.h" +#include "radeon_reg.h" +#include "radeon_macros.h" +#include "radeon_probe.h" +#include "vbe.h" + +/* Read the Video BIOS block and the FP registers (if applicable). */ +Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + int tmp; + unsigned short dptr; + + if (!(info->VBIOS = xalloc(RADEON_VBIOS_SIZE))) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Cannot allocate space for hold Video BIOS!\n"); + return FALSE; + } + + if (pInt10) { + info->BIOSAddr = pInt10->BIOSseg << 4; + (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr), + RADEON_VBIOS_SIZE); + } else { + xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); + if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { + if (!xf86DomainHasBIOSSegments(xf86GetPciDomain(info->PciTag))) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "x86 video BIOS not available\n"); + xfree(info->VBIOS); + info->VBIOS = NULL; + return FALSE; + } + + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Video BIOS not detected in PCI space!\n"); + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Attempting to read Video BIOS from ISA space!\n"); + info->BIOSAddr = 0x000c0000; + xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, + RADEON_VBIOS_SIZE, info->VBIOS); + } + } + + if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Unrecognized BIOS signature, BIOS data will not be used\n"); + xfree(info->VBIOS); + info->VBIOS = NULL; + return FALSE; + } + + /* Verify it's an x86 BIOS not OF firmware, copied from radeonfb */ + dptr = RADEON_BIOS16(0x18); + /* If PCI data signature is wrong assume x86 video BIOS anyway */ + if (RADEON_BIOS32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "ROM PCI data signature incorrect, ignoring\n"); + } + else if (info->VBIOS[dptr + 0x14] != 0x0) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Not an x86 BIOS ROM image, BIOS data will not be used\n"); + xfree(info->VBIOS); + info->VBIOS = NULL; + return FALSE; + } + + if (info->VBIOS) info->ROMHeaderStart = RADEON_BIOS16(0x48); + + if(!info->ROMHeaderStart) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Invalid ROM pointer, BIOS data will not be used\n"); + xfree(info->VBIOS); + info->VBIOS = NULL; + return FALSE; + } + + tmp = info->ROMHeaderStart + 4; + if ((RADEON_BIOS8(tmp) == 'A' && + RADEON_BIOS8(tmp+1) == 'T' && + RADEON_BIOS8(tmp+2) == 'O' && + RADEON_BIOS8(tmp+3) == 'M') || + (RADEON_BIOS8(tmp) == 'M' && + RADEON_BIOS8(tmp+1) == 'O' && + RADEON_BIOS8(tmp+2) == 'T' && + RADEON_BIOS8(tmp+3) == 'A')) + info->IsAtomBios = TRUE; + else + info->IsAtomBios = FALSE; + + if (info->IsAtomBios) + info->MasterDataStart = RADEON_BIOS16(info->ROMHeaderStart + 32); + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s BIOS detected\n", + info->IsAtomBios ? "ATOM":"Legacy"); + + return TRUE; +} + +Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + int i = 0, j, tmp, tmp0=0, tmp1=0; + + if(!info->VBIOS) return FALSE; + + if (info->IsAtomBios) { + if((tmp = RADEON_BIOS16(info->MasterDataStart + 22))) { + int crtc = 0, id[2]; + tmp1 = RADEON_BIOS16(tmp + 4); + for (i=0; i<8; i++) { + if(tmp1 & (1<<i)) { + CARD16 portinfo = RADEON_BIOS16(tmp+6+i*2); + if (crtc < 2) { + if ((i==2) || (i==6)) continue; /* ignore TV here */ + + if (crtc == 1) { + /* sharing same port with id[0] */ + if (((portinfo>>8) & 0xf) == id[0]) { + if (i == 3) + pRADEONEnt->PortInfo[0].TMDSType = TMDS_INT; + else if (i == 7) + pRADEONEnt->PortInfo[0].TMDSType = TMDS_EXT; + + if (pRADEONEnt->PortInfo[0].DACType == DAC_UNKNOWN) + pRADEONEnt->PortInfo[0].DACType = (portinfo & 0xf) - 1; + continue; + } + } + + id[crtc] = (portinfo>>8) & 0xf; + pRADEONEnt->PortInfo[crtc].DACType = (portinfo & 0xf) - 1; + pRADEONEnt->PortInfo[crtc].ConnectorType = (portinfo>>4) & 0xf; + if (i == 3) + pRADEONEnt->PortInfo[crtc].TMDSType = TMDS_INT; + else if (i == 7) + pRADEONEnt->PortInfo[crtc].TMDSType = TMDS_EXT; + + if((tmp0 = RADEON_BIOS16(info->MasterDataStart + 24)) && id[crtc]) { + switch (RADEON_BIOS16(tmp0 + 4 + 27 * id[crtc]) * 4) + { + case RADEON_GPIO_MONID: + pRADEONEnt->PortInfo[crtc].DDCType = DDC_MONID; + break; + case RADEON_GPIO_DVI_DDC: + pRADEONEnt->PortInfo[crtc].DDCType = DDC_DVI; + break; + case RADEON_GPIO_VGA_DDC: + pRADEONEnt->PortInfo[crtc].DDCType = DDC_VGA; + break; + case RADEON_GPIO_CRT2_DDC: + pRADEONEnt->PortInfo[crtc].DDCType = DDC_CRT2; + break; + default: + pRADEONEnt->PortInfo[crtc].DDCType = DDC_NONE_DETECTED; + break; + } + + } else { + pRADEONEnt->PortInfo[crtc].DDCType = DDC_NONE_DETECTED; + } + crtc++; + } else { + /* we have already had two CRTCs assigned. the rest may share the same + * port with the existing connector, fill in them accordingly. + */ + for (j=0; j<2; j++) { + if (((portinfo>>8) & 0xf) == id[j]) { + if (i == 3) + pRADEONEnt->PortInfo[j].TMDSType = TMDS_INT; + else if (i == 7) + pRADEONEnt->PortInfo[j].TMDSType = TMDS_EXT; + + if (pRADEONEnt->PortInfo[j].DACType == DAC_UNKNOWN) + pRADEONEnt->PortInfo[j].DACType = (portinfo & 0xf) - 1; + } + } + } + } + } + + for (i=0; i<2; i++) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-%d, DACType-%d, TMDSType-%d, ConnectorType-%d\n", + i, pRADEONEnt->PortInfo[i].DDCType, pRADEONEnt->PortInfo[i].DACType, + pRADEONEnt->PortInfo[i].TMDSType, pRADEONEnt->PortInfo[i].ConnectorType); + } + } else { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Device Info Table found!\n"); + return FALSE; + } + } else { + /* Some laptops only have one connector (VGA) listed in the connector table, + * we need to add LVDS in as a non-DDC display. + * Note, we can't assume the listed VGA will be filled in PortInfo[0], + * when walking through connector table. connector_found has following meaning: + * 0 -- nothing found, + * 1 -- only PortInfo[0] filled, + * 2 -- only PortInfo[1] filled, + * 3 -- both are filled. + */ + int connector_found = 0; + + if ((tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x50))) { + for (i = 1; i < 4; i++) { + + if (!RADEON_BIOS16(tmp + i*2)) + break; /* end of table */ + + tmp0 = RADEON_BIOS16(tmp + i*2); + if (((tmp0 >> 12) & 0x0f) == 0) continue; /* no connector */ + if (connector_found > 0) { + if (pRADEONEnt->PortInfo[tmp1].DDCType == + (RADEONDDCType)((tmp0 >> 8) & 0x0f)) + continue; /* same connector */ + } + + /* internal DDC_DVI port will get assigned to PortInfo[0], or if there is no DDC_DVI (like in some IGPs). */ + tmp1 = ((((tmp0 >> 8) & 0xf) == DDC_DVI) || (tmp1 == 1)) ? 0 : 1; /* determine port info index */ + + pRADEONEnt->PortInfo[tmp1].DDCType = (tmp0 >> 8) & 0x0f; + if (pRADEONEnt->PortInfo[tmp1].DDCType > DDC_CRT2) pRADEONEnt->PortInfo[tmp1].DDCType = DDC_NONE_DETECTED; + pRADEONEnt->PortInfo[tmp1].DACType = (tmp0 & 0x01) ? DAC_TVDAC : DAC_PRIMARY; + pRADEONEnt->PortInfo[tmp1].ConnectorType = (tmp0 >> 12) & 0x0f; + if (pRADEONEnt->PortInfo[tmp1].ConnectorType > CONNECTOR_UNSUPPORTED) pRADEONEnt->PortInfo[tmp1].ConnectorType = CONNECTOR_UNSUPPORTED; + pRADEONEnt->PortInfo[tmp1].TMDSType = ((tmp0 >> 4) & 0x01) ? TMDS_EXT : TMDS_INT; + + /* some sanity checks */ + if (((pRADEONEnt->PortInfo[tmp1].ConnectorType != CONNECTOR_DVI_D) && + (pRADEONEnt->PortInfo[tmp1].ConnectorType != CONNECTOR_DVI_I)) && + pRADEONEnt->PortInfo[tmp1].TMDSType == TMDS_INT) + pRADEONEnt->PortInfo[tmp1].TMDSType = TMDS_UNKNOWN; + + connector_found += (tmp1 + 1); + } + } else { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n"); + return FALSE; + } + + if (info->IsMobility) { + /* For the cases where only one VGA connector is found, + we assume LVDS is not listed in the connector table, + add it in here as the first port. + */ + if ((connector_found < 3) && (pRADEONEnt->PortInfo[tmp1].ConnectorType == CONNECTOR_CRT)) { + if (connector_found == 1) { + memcpy (&pRADEONEnt->PortInfo[1], &pRADEONEnt->PortInfo[0], + sizeof (pRADEONEnt->PortInfo[0])); + } + pRADEONEnt->PortInfo[0].DACType = DAC_TVDAC; + pRADEONEnt->PortInfo[0].TMDSType = TMDS_UNKNOWN; + pRADEONEnt->PortInfo[0].DDCType = DDC_NONE_DETECTED; + pRADEONEnt->PortInfo[0].ConnectorType = CONNECTOR_PROPRIETARY; + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "LVDS port is not in connector table, added in.\n"); + if (connector_found == 0) connector_found = 1; + else connector_found = 3; + } + + if ((tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x42))) { + if ((tmp0 = RADEON_BIOS16(tmp + 0x15))) { + if ((tmp1 = RADEON_BIOS8(tmp0+2) & 0x07)) { + pRADEONEnt->PortInfo[0].DDCType = tmp1; + if (pRADEONEnt->PortInfo[0].DDCType > DDC_CRT2) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Unknown DDCType %d found\n", + pRADEONEnt->PortInfo[0].DDCType); + pRADEONEnt->PortInfo[0].DDCType = DDC_NONE_DETECTED; + } + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "LCD DDC Info Table found!\n"); + } + } + } + } else if (connector_found == 2) { + memcpy (&pRADEONEnt->PortInfo[0], &pRADEONEnt->PortInfo[1], + sizeof (pRADEONEnt->PortInfo[0])); + pRADEONEnt->PortInfo[1].DACType = DAC_UNKNOWN; + pRADEONEnt->PortInfo[1].TMDSType = TMDS_UNKNOWN; + pRADEONEnt->PortInfo[1].DDCType = DDC_NONE_DETECTED; + pRADEONEnt->PortInfo[1].ConnectorType = CONNECTOR_NONE; + connector_found = 1; + } + + if (connector_found == 0) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No connector found in Connector Info Table.\n"); + } else { + xf86DrvMsg(0, X_INFO, "Connector0: DDCType-%d, DACType-%d, TMDSType-%d, ConnectorType-%d\n", + pRADEONEnt->PortInfo[0].DDCType, pRADEONEnt->PortInfo[0].DACType, + pRADEONEnt->PortInfo[0].TMDSType, pRADEONEnt->PortInfo[0].ConnectorType); + } + if (connector_found == 3) { + xf86DrvMsg(0, X_INFO, "Connector1: DDCType-%d, DACType-%d, TMDSType-%d, ConnectorType-%d\n", + pRADEONEnt->PortInfo[1].DDCType, pRADEONEnt->PortInfo[1].DACType, + pRADEONEnt->PortInfo[1].TMDSType, pRADEONEnt->PortInfo[1].ConnectorType); + } + +#if 0 +/* External TMDS Table, not used now */ + if ((tmp0 = RADEON_BIOS16(info->ROMHeaderStart + 0x58))) { + + pRADEONEnt->PortInfo[1].DDCType = (RADEON_BIOS8(tmp0 + 7) & 0x07); + pRADEONEnt->PortInfo[1].ConnectorType = CONNECTOR_DVI_I; + pRADEONEnt->PortInfo[1].TMDSType = TMDS_EXT; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "External TMDS found.\n"); + + } else { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NO External TMDS Info found\n"); + + } +#endif + + } + return TRUE; +} + +/* Read PLL parameters from BIOS block. Default to typical values if there + is no BIOS. */ +Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONPLLPtr pll = &info->pll; + CARD16 pll_info_block; + + if (!info->VBIOS) { + return FALSE; + } else { + if (info->IsAtomBios) { + pll_info_block = RADEON_BIOS16(info->MasterDataStart + 12); + + pll->reference_freq = RADEON_BIOS16(pll_info_block + 82); + pll->reference_div = 0; /* Need to derive from existing setting + or use a new algorithm to calculate + from min_input and max_input + */ + pll->min_pll_freq = RADEON_BIOS16(pll_info_block + 78); + pll->max_pll_freq = RADEON_BIOS32(pll_info_block + 32); + pll->xclk = RADEON_BIOS16(pll_info_block + 72); + + info->sclk = RADEON_BIOS32(pll_info_block + 8) / 100.0; + info->mclk = RADEON_BIOS32(pll_info_block + 12) / 100.0; + if (info->sclk == 0) info->sclk = 200; + if (info->mclk == 0) info->mclk = 200; + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %d, max_pll: %d, xclk: %d, sclk: %f, mclk: %f\n", + pll->reference_freq, pll->min_pll_freq, pll->max_pll_freq, pll->xclk, info->sclk, info->mclk); + + } else { + pll_info_block = RADEON_BIOS16(info->ROMHeaderStart + 0x30); + + pll->reference_freq = RADEON_BIOS16(pll_info_block + 0x0e); + pll->reference_div = RADEON_BIOS16(pll_info_block + 0x10); + pll->min_pll_freq = RADEON_BIOS32(pll_info_block + 0x12); + pll->max_pll_freq = RADEON_BIOS32(pll_info_block + 0x16); + pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); + + info->sclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; + info->mclk = RADEON_BIOS16(pll_info_block + 10) / 100.0; + } + } + + return TRUE; +} + +Bool RADEONGetLVDSInfoFromBIOS (ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned long tmp, i; + + if (!info->VBIOS) return FALSE; + + if (info->IsAtomBios) { + if((tmp = RADEON_BIOS16(info->MasterDataStart + 16))) { + + info->PanelXRes = RADEON_BIOS16(tmp+6); + info->PanelYRes = RADEON_BIOS16(tmp+10); + info->DotClock = RADEON_BIOS16(tmp+4)*10; + info->HBlank = RADEON_BIOS16(tmp+8); + info->HOverPlus = RADEON_BIOS16(tmp+14); + info->HSyncWidth = RADEON_BIOS16(tmp+16); + info->VBlank = RADEON_BIOS16(tmp+12); + info->VOverPlus = RADEON_BIOS16(tmp+18); + info->VSyncWidth = RADEON_BIOS16(tmp+20); + info->PanelPwrDly = RADEON_BIOS16(tmp+40); + + info->Flags = 0; + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "LVDS Info:\n" + "XRes: %d, YRes: %d, DotClock: %d\n" + "HBlank: %d, HOverPlus: %d, HSyncWidth: %d\n" + "VBlank: %d, VOverPlus: %d, VSyncWidth: %d\n", + info->PanelXRes, info->PanelYRes, info->DotClock, + info->HBlank,info->HOverPlus, info->HSyncWidth, + info->VBlank, info->VOverPlus, info->VSyncWidth); + } else { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "No LVDS Info Table found in BIOS!\n"); + return FALSE; + } + } else { + + tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x40); + + if (!tmp) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "No Panel Info Table found in BIOS!\n"); + return FALSE; + } else { + char stmp[30]; + int tmp0; + + for (i = 0; i < 24; i++) + stmp[i] = RADEON_BIOS8(tmp+i+1); + stmp[24] = 0; + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Panel ID string: %s\n", stmp); + + info->PanelXRes = RADEON_BIOS16(tmp+25); + info->PanelYRes = RADEON_BIOS16(tmp+27); + xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n", + info->PanelXRes, info->PanelYRes); + + info->PanelPwrDly = RADEON_BIOS16(tmp+44); + if (info->PanelPwrDly > 2000 || info->PanelPwrDly < 0) + info->PanelPwrDly = 2000; + + /* some panels only work well with certain divider combinations. + */ + info->RefDivider = RADEON_BIOS16(tmp+46); + info->PostDivider = RADEON_BIOS8(tmp+48); + info->FeedbackDivider = RADEON_BIOS16(tmp+49); + if ((info->RefDivider != 0) && + (info->FeedbackDivider > 3)) { + info->UseBiosDividers = TRUE; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "BIOS provided dividers will be used.\n"); + } + + /* We don't use a while loop here just in case we have a corrupted BIOS image. + The max number of table entries is 23 at present, but may grow in future. + To ensure it works with future revisions we loop it to 32. + */ + for (i = 0; i < 32; i++) { + tmp0 = RADEON_BIOS16(tmp+64+i*2); + if (tmp0 == 0) break; + if ((RADEON_BIOS16(tmp0) == info->PanelXRes) && + (RADEON_BIOS16(tmp0+2) == info->PanelYRes)) { + info->HBlank = (RADEON_BIOS16(tmp0+17) - + RADEON_BIOS16(tmp0+19)) * 8; + info->HOverPlus = (RADEON_BIOS16(tmp0+21) - + RADEON_BIOS16(tmp0+19) - 1) * 8; + info->HSyncWidth = RADEON_BIOS8(tmp0+23) * 8; + info->VBlank = (RADEON_BIOS16(tmp0+24) - + RADEON_BIOS16(tmp0+26)); + info->VOverPlus = ((RADEON_BIOS16(tmp0+28) & 0x7ff) - + RADEON_BIOS16(tmp0+26)); + info->VSyncWidth = ((RADEON_BIOS16(tmp0+28) & 0xf800) >> 11); + info->DotClock = RADEON_BIOS16(tmp0+9) * 10; + info->Flags = 0; + } + } + } + } + return TRUE; +} + +Bool RADEONGetHardCodedEDIDFromBIOS (ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned long tmp; + char EDID[256]; + + if (!info->VBIOS) return FALSE; + + if (info->IsAtomBios) { + /* Not yet */ + return FALSE; + } else { + if (!(tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x4c))) { + return FALSE; + } + + memcpy(EDID, (char*)(info->VBIOS + tmp), 256); + + info->DotClock = ((*(CARD8*)(EDID+54)) + ((*(CARD8*)(EDID+55))*256)) * 10; + info->PanelXRes = (*(CARD8*)(EDID+56)) + ((*(CARD8*)(EDID+58))>>4)*256; + info->HBlank = (*(CARD8*)(EDID+57)) + ((*(CARD8*)(EDID+58)) & 0xf)*256; + info->HOverPlus = (*(CARD8*)(EDID+62)) + ((*(CARD8*)(EDID+65)>>6)*256); + info->HSyncWidth = (*(CARD8*)(EDID+63)) + (((*(CARD8*)(EDID+65)>>4) & 3)*256); + info->PanelYRes = (*(CARD8*)(EDID+59)) + ((*(CARD8*)(EDID+61))>>4)*256; + info->VBlank = ((*(CARD8*)(EDID+60)) + ((*(CARD8*)(EDID+61)) & 0xf)*256); + info->VOverPlus = (((*(CARD8*)(EDID+64))>>4) + (((*(CARD8*)(EDID+65)>>2) & 3)*16)); + info->VSyncWidth = (((*(CARD8*)(EDID+64)) & 0xf) + ((*(CARD8*)(EDID+65)) & 3)*256); + info->Flags = V_NHSYNC | V_NVSYNC; /**(CARD8*)(EDID+71);*/ + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Hardcoded EDID data will be used for TMDS panel\n"); + } + return TRUE; +} + +Bool RADEONGetTMDSInfoFromBIOS (ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + CARD32 tmp, maxfreq; + int i, n; + + if (!info->VBIOS) return FALSE; + + if (info->IsAtomBios) { + if((tmp = RADEON_BIOS16(info->MasterDataStart + 18))) { + + maxfreq = RADEON_BIOS16(tmp+4); + + for (i=0; i<4; i++) { + info->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*6+6); + /* This assumes each field in TMDS_PLL has 6 bit as in R300/R420 */ + info->tmds_pll[i].value = ((RADEON_BIOS8(tmp+i*6+8) & 0x3f) | + ((RADEON_BIOS8(tmp+i*6+10) & 0x3f)<<6) | + ((RADEON_BIOS8(tmp+i*6+9) & 0xf)<<12) | + ((RADEON_BIOS8(tmp+i*6+11) & 0xf)<<16)); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "TMDS PLL from BIOS: %d %x\n", + info->tmds_pll[i].freq, info->tmds_pll[i].value); + + if (maxfreq == info->tmds_pll[i].freq) { + info->tmds_pll[i].freq = 0xffffffff; + break; + } + } + return TRUE; + } + } else { + + tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x34); + if (tmp) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "DFP table revision: %d\n", RADEON_BIOS8(tmp)); + if (RADEON_BIOS8(tmp) == 3) { + n = RADEON_BIOS8(tmp + 5) + 1; + if (n > 4) n = 4; + for (i=0; i<n; i++) { + info->tmds_pll[i].value = RADEON_BIOS32(tmp+i*10+0x08); + info->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*10+0x10); + } + return TRUE; + } else if (RADEON_BIOS8(tmp) == 4) { + int stride = 0; + n = RADEON_BIOS8(tmp + 5) + 1; + if (n > 4) n = 4; + for (i=0; i<n; i++) { + info->tmds_pll[i].value = RADEON_BIOS32(tmp+stride+0x08); + info->tmds_pll[i].freq = RADEON_BIOS16(tmp+stride+0x10); + if (i == 0) stride += 10; + else stride += 6; + } + return TRUE; + } + + /* revision 4 has some problem as it appears in RV280, + comment it off for now, use default instead */ + /* + else if (RADEON_BIOS8(tmp) == 4) { + int stride = 0; + n = RADEON_BIOS8(tmp + 5) + 1; + if (n > 4) n = 4; + for (i=0; i<n; i++) { + info->tmds_pll[i].value = RADEON_BIOS32(tmp+stride+0x08); + info->tmds_pll[i].freq = RADEON_BIOS16(tmp+stride+0x10); + if (i == 0) stride += 10; + else stride += 6; + } + return TRUE; + } + */ + } + } + return FALSE; +} Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h:1.11 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h:1.12 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h:1.11 Mon Dec 13 14:40:55 2004 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h Wed Apr 2 14:02:31 2008 @@ -1,3 +1,4 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v 1.12 2008/04/02 21:02:31 tsi Exp $ */ /* radeon_common.h -- common header definitions for Radeon 2D/3D/DRM suite * * Copyright 2000 VA Linux Systems, Inc., Fremont, California. @@ -30,9 +31,6 @@ * * Converted to common header format: * Jens Owen <jens@tungstengraphics.com> - * - * $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v 1.11 2004/12/13 22:40:55 tsi Exp $ - * */ #ifndef _RADEON_COMMON_H_ @@ -72,6 +70,8 @@ #define DRM_RADEON_IRQ_WAIT 0x17 #define DRM_RADEON_CP_RESUME 0x18 #define DRM_RADEON_SETPARAM 0x19 +#define DRM_RADEON_SURF_ALLOC 0x1a +#define DRM_RADEON_SURF_FREE 0x1b #define DRM_RADEON_MAX_DRM_COMMAND_INDEX 0x39 @@ -91,7 +91,8 @@ enum { DRM_RADEON_INIT_CP = 0x01, DRM_RADEON_CLEANUP_CP = 0x02, - DRM_RADEON_INIT_R200_CP = 0x03 + DRM_RADEON_INIT_R200_CP = 0x03, + DRM_RADEON_INIT_R300_CP = 0x04 } func; unsigned long sarea_priv_offset; int is_pci; @@ -467,6 +468,20 @@ } drmRadeonSetParam; #define RADEON_SETPARAM_FB_LOCATION 1 - +#define RADEON_SETPARAM_SWITCH_TILING 2 +#define RADEON_SETPARAM_PCIGART_LOCATION 3 +#define RADEON_SETPARAM_NEW_MEMMAP 4 + +/* 1.14: Clients can allocate/free a surface + */ +typedef struct drm_radeon_surface_alloc { + unsigned int address; + unsigned int size; + unsigned int flags; +} drmRadeonSurfaceAlloc; + +typedef struct drm_radeon_surface_free { + unsigned int address; +} drmRadeonSurfaceFree; #endif Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_commonfuncs.c diff -u /dev/null xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_commonfuncs.c:1.1 --- /dev/null Mon Dec 15 09:54:56 2008 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_commonfuncs.c Wed Apr 2 14:02:31 2008 @@ -0,0 +1,184 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_commonfuncs.c,v 1.1 2008/04/02 21:02:31 tsi Exp $ */ +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#if defined(ACCEL_MMIO) && defined(ACCEL_CP) +#error Cannot define both MMIO and CP acceleration! +#endif + +#if !defined(UNIXCPP) || defined(ANSICPP) +#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix +#else +#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix +#endif + +#ifdef ACCEL_MMIO +#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO) +#else +#ifdef ACCEL_CP +#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP) +#else +#error No accel type defined! +#endif +#endif + +static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + ACCEL_PREAMBLE(); + + if (info->ChipFamily >= CHIP_FAMILY_R300) { + /* Unimplemented */ + } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || + (info->ChipFamily == CHIP_FAMILY_RV280) || + (info->ChipFamily == CHIP_FAMILY_RS300) || + (info->ChipFamily == CHIP_FAMILY_R200)) { + + BEGIN_ACCEL(7); + if (info->ChipFamily == CHIP_FAMILY_RS300) { + OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); + } else { + OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); + } + OUT_ACCEL_REG(R200_PP_CNTL_X, 0); + OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); + OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); + OUT_ACCEL_REG(R200_RE_CNTL, 0x0); + /* XXX: correct? Want it to be like RADEON_VTX_ST?_NONPARAMETRIC */ + OUT_ACCEL_REG(R200_SE_VTE_CNTL, R200_VTX_ST_DENORMALIZED); + OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | + R200_VAP_VF_MAX_VTX_NUM); + FINISH_ACCEL(); + } else { + BEGIN_ACCEL(2); + if ((info->ChipFamily == CHIP_FAMILY_RADEON) || + (info->ChipFamily == CHIP_FAMILY_RV200)) + OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); + else + OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); + OUT_ACCEL_REG(RADEON_SE_COORD_FMT, + RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | + RADEON_VTX_ST0_NONPARAMETRIC | + RADEON_VTX_ST1_NONPARAMETRIC | + RADEON_TEX1_W_ROUTING_USE_W0); + FINISH_ACCEL(); + } + + BEGIN_ACCEL(5); + OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); + OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); + OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); + OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); + OUT_ACCEL_REG(RADEON_SE_CNTL, RADEON_DIFFUSE_SHADE_GOURAUD | + RADEON_BFACE_SOLID | + RADEON_FFACE_SOLID | + RADEON_VTX_PIX_CENTER_OGL | + RADEON_ROUND_MODE_ROUND | + RADEON_ROUND_PREC_4TH_PIX); + FINISH_ACCEL(); +} + + +/* MMIO: + * + * Wait for the graphics engine to be completely idle: the FIFO has + * drained, the Pixel Cache is flushed, and the engine is idle. This is + * a standard "sync" function that will make the hardware "quiescent". + * + * CP: + * + * Wait until the CP is completely idle: the FIFO has drained and the CP + * is idle. + */ +void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + int i = 0; + +#ifdef ACCEL_CP + /* Make sure the CP is idle first */ + if (info->CPStarted) { + int ret; + + FLUSH_RING(); + + for (;;) { + do { + ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_IDLE); + if (ret && ret != -EBUSY) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "%s: CP idle %d\n", __FUNCTION__, ret); + } + } while ((ret == -EBUSY) && (i++ < RADEON_TIMEOUT)); + + if (ret == 0) return; + + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Idle timed out, resetting engine...\n"); + RADEONEngineReset(pScrn); + RADEONEngineRestore(pScrn); + + /* Always restart the engine when doing CP 2D acceleration */ + RADEONCP_RESET(pScrn, info); + RADEONCP_START(pScrn, info); + } + } +#endif + +#if 0 + RADEONTRACE(("WaitForIdle (entering): %d entries, stat=0x%08x\n", + INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, + INREG(RADEON_RBBM_STATUS))); +#endif + + /* Wait for the engine to go idle */ + RADEONWaitForFifoFunction(pScrn, 64); + + for (;;) { + for (i = 0; i < RADEON_TIMEOUT; i++) { + if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) { + RADEONEngineFlush(pScrn); + return; + } + } + RADEONTRACE(("Idle timed out: %u entries, stat=0x%08x\n", + INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, + INREG(RADEON_RBBM_STATUS))); + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Idle timed out, resetting engine...\n"); + RADEONEngineReset(pScrn); + RADEONEngineRestore(pScrn); +#ifdef XF86DRI + if (info->directRenderingEnabled) { + RADEONCP_RESET(pScrn, info); + RADEONCP_START(pScrn, info); + } +#endif + } +} Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_cursor.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_cursor.c:1.26 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_cursor.c:1.27 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_cursor.c:1.26 Mon Nov 10 10:41:22 2003 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_cursor.c Wed Apr 2 14:02:31 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_cursor.c,v 1.26 2003/11/10 18:41:22 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_cursor.c,v 1.27 2008/04/02 21:02:31 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -46,8 +46,10 @@ /* Driver data structures */ #include "radeon.h" -#include "radeon_macros.h" +#include "radeon_version.h" #include "radeon_reg.h" +#include "radeon_macros.h" +#include "radeon_mergedfb.h" /* X and server generic header files */ #include "xf86.h" @@ -72,31 +74,40 @@ #if X_BYTE_ORDER == X_BIG_ENDIAN #define CURSOR_SWAPPING_DECL_MMIO unsigned char *RADEONMMIO = info->MMIO; -#define CURSOR_SWAPPING_DECL CARD32 __surface_cntl; #define CURSOR_SWAPPING_START() \ + do { \ + if (info->accel) \ + (*info->accel->Sync)(pScrn); \ OUTREG(RADEON_SURFACE_CNTL, \ - ((__surface_cntl = INREG(RADEON_SURFACE_CNTL)) | \ - RADEON_NONSURF_AP0_SWP_32BPP) & \ - ~RADEON_NONSURF_AP0_SWP_16BPP) -#define CURSOR_SWAPPING_END() (OUTREG(RADEON_SURFACE_CNTL, __surface_cntl)) + (info->ModeReg.surface_cntl | \ + RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \ + ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP)); \ + } while (0) +#define CURSOR_SWAPPING_END() (OUTREG(RADEON_SURFACE_CNTL, \ + info->ModeReg.surface_cntl)) #else #define CURSOR_SWAPPING_DECL_MMIO -#define CURSOR_SWAPPING_DECL -#define CURSOR_SWAPPING_START() +#define CURSOR_SWAPPING_START() \ + do { \ + if (info->accel) \ + (*info->accel->Sync)(pScrn); \ + } while (0) #define CURSOR_SWAPPING_END() #endif + /* Set cursor foreground and background colors */ static void RADEONSetCursorColors(ScrnInfoPtr pScrn, int bg, int fg) { RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 *pixels = (CARD32 *)(pointer)(info->FB + info->cursor_start); + CARD32 *pixels = (CARD32 *)(pointer)(info->FB + info->cursor_offset); int pixel, i; CURSOR_SWAPPING_DECL_MMIO - CURSOR_SWAPPING_DECL + + RADEONTRACE(("RADEONSetCursorColors\n")); #ifdef ARGB_CURSOR /* Don't recolour cursors set with SetCursorARGB. */ @@ -119,7 +130,7 @@ */ for (i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++) if ((pixel = *pixels)) - *pixels = (pixel == info->cursor_fg) ? fg : bg; + *pixels = (pixel == info->cursor_fg) ? fg : bg; CURSOR_SWAPPING_END(); info->cursor_fg = fg; @@ -138,10 +149,16 @@ int xorigin = 0; int yorigin = 0; int total_y = pScrn->frameY1 - pScrn->frameY0; - int X2 = pScrn->frameX0 + x; - int Y2 = pScrn->frameY0 + y; int stride = 256; + if(info->MergedFB) { + RADEONTRACE(("RADEONSetCursorPositionMerged\n")); + RADEONSetCursorPositionMerged(pScrn, x, y); + return; + } + + RADEONTRACE(("RADEONSetCursorPosition\n")); + if (x < 0) xorigin = -x+1; if (y < 0) yorigin = -y+1; if (y > total_y) y = total_y; @@ -149,57 +166,6 @@ if (xorigin >= cursor->MaxWidth) xorigin = cursor->MaxWidth - 1; if (yorigin >= cursor->MaxHeight) yorigin = cursor->MaxHeight - 1; - if (info->Clone) { - int X0 = 0; - int Y0 = 0; - - if ((info->CurCloneMode->VDisplay == pScrn->currentMode->VDisplay) && - (info->CurCloneMode->HDisplay == pScrn->currentMode->HDisplay)) { - Y2 = y; - X2 = x; - X0 = pScrn->frameX0; - Y0 = pScrn->frameY0; - } else { - if (y < 0) - Y2 = pScrn->frameY0; - - if (x < 0) - X2 = pScrn->frameX0; - - if (Y2 >= info->CurCloneMode->VDisplay + info->CloneFrameY0) { - Y0 = Y2 - info->CurCloneMode->VDisplay; - Y2 = info->CurCloneMode->VDisplay - 1; - } else if (Y2 < info->CloneFrameY0) { - Y0 = Y2; - Y2 = 0; - } else { - Y2 -= info->CloneFrameY0; - Y0 = info->CloneFrameY0; - } - - if (X2 >= info->CurCloneMode->HDisplay + info->CloneFrameX0) { - X0 = X2 - info->CurCloneMode->HDisplay; - X2 = info->CurCloneMode->HDisplay - 1; - } else if (X2 < info->CloneFrameX0) { - X0 = X2; - X2 = 0; - } else { - X2 -= info->CloneFrameX0; - X0 = info->CloneFrameX0; - } - - if (info->CurCloneMode->Flags & V_DBLSCAN) - Y2 *= 2; - } - - if ((X0 >= 0 || Y0 >= 0) && - ((info->CloneFrameX0 != X0) || (info->CloneFrameY0 != Y0))) { - RADEONDoAdjustFrame(pScrn, X0, Y0, TRUE); - info->CloneFrameX0 = X0; - info->CloneFrameY0 = Y0; - } - } - if (!info->IsSecondary) { OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK | (xorigin << 16) @@ -207,7 +173,9 @@ OUTREG(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y))); - OUTREG(RADEON_CUR_OFFSET, info->cursor_start + yorigin * stride); + RADEONTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d\n", + info->cursor_offset, yorigin, stride)); + OUTREG(RADEON_CUR_OFFSET, info->cursor_offset + yorigin * stride); } else { OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK | (xorigin << 16) @@ -216,26 +184,9 @@ | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y))); OUTREG(RADEON_CUR2_OFFSET, - info->cursor_start + pScrn->fbOffset + yorigin * stride); + info->cursor_offset + pScrn->fbOffset + yorigin * stride); } - if (info->Clone) { - xorigin = 0; - yorigin = 0; - if (X2 < 0) xorigin = -X2 + 1; - if (Y2 < 0) yorigin = -Y2 + 1; - if (xorigin >= cursor->MaxWidth) xorigin = cursor->MaxWidth - 1; - if (yorigin >= cursor->MaxHeight) yorigin = cursor->MaxHeight - 1; - - OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK - | (xorigin << 16) - | yorigin)); - OUTREG(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK - | ((xorigin ? 0 : X2) << 16) - | (yorigin ? 0 : Y2))); - OUTREG(RADEON_CUR2_OFFSET, - info->cursor_start + pScrn->fbOffset + yorigin * stride); - } } /* Copy cursor image from `image' to video memory. RADEONSetCursorPosition @@ -246,12 +197,13 @@ RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; CARD8 *s = (CARD8 *)(pointer)image; - CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_start); + CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset); CARD32 save1 = 0; CARD32 save2 = 0; CARD8 chunk; CARD32 i, j; - CURSOR_SWAPPING_DECL + + RADEONTRACE(("RADEONLoadCursorImage (at %x)\n", info->cursor_offset)); if (!info->IsSecondary) { save1 = INREG(RADEON_CRTC_GEN_CNTL) & ~(CARD32) (3 << 20); @@ -259,7 +211,7 @@ OUTREG(RADEON_CRTC_GEN_CNTL, save1 & (CARD32)~RADEON_CRTC_CUR_EN); } - if (info->IsSecondary || info->Clone) { + if (info->IsSecondary || info->MergedFB) { save2 = INREG(RADEON_CRTC2_GEN_CNTL) & ~(CARD32) (3 << 20); save2 |= (CARD32) (2 << 20); OUTREG(RADEON_CRTC2_GEN_CNTL, save2 & (CARD32)~RADEON_CRTC2_CUR_EN); @@ -279,8 +231,8 @@ */ CURSOR_SWAPPING_START(); #define ARGB_PER_CHUNK (8 * sizeof (chunk) / 2) - for (i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT / ARGB_PER_CHUNK; i++) { - chunk = *s++; + for (i = 0; i < (CURSOR_WIDTH * CURSOR_HEIGHT / ARGB_PER_CHUNK); i++) { + chunk = *s++; for (j = 0; j < ARGB_PER_CHUNK; j++, chunk >>= 2) *d++ = mono_cursor_color[chunk & 3]; } @@ -292,7 +244,7 @@ if (!info->IsSecondary) OUTREG(RADEON_CRTC_GEN_CNTL, save1); - if (info->IsSecondary || info->Clone) + if (info->IsSecondary || info->MergedFB) OUTREG(RADEON_CRTC2_GEN_CNTL, save2); } @@ -303,7 +255,9 @@ RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - if (info->IsSecondary || info->Clone) + RADEONTRACE(("RADEONHideCursor\n")); + + if (info->IsSecondary || info->MergedFB) OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_CUR_EN); if (!info->IsSecondary) @@ -316,7 +270,9 @@ RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - if (info->IsSecondary || info->Clone) + RADEONTRACE(("RADEONShowCursor\n")); + + if (info->IsSecondary || info->MergedFB) OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN, ~RADEON_CRTC2_CUR_EN); @@ -331,7 +287,7 @@ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); - return info->cursor_start ? TRUE : FALSE; + return info->cursor ? TRUE : FALSE; } #ifdef ARGB_CURSOR @@ -339,10 +295,7 @@ static Bool RADEONUseHWCursorARGB (ScreenPtr pScreen, CursorPtr pCurs) { - ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (info->cursor_start && + if (RADEONUseHWCursor(pScreen, pCurs) && pCurs->bits->height <= CURSOR_HEIGHT && pCurs->bits->width <= CURSOR_WIDTH) return TRUE; return FALSE; @@ -352,16 +305,14 @@ { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_start); + CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset); int x, y, w, h; CARD32 save1 = 0; CARD32 save2 = 0; CARD32 *image = pCurs->bits->argb; CARD32 *i; - CURSOR_SWAPPING_DECL - if (!image) - return; /* XXX can't happen */ + RADEONTRACE(("RADEONLoadCursorARGB\n")); if (!info->IsSecondary) { save1 = INREG(RADEON_CRTC_GEN_CNTL) & ~(CARD32) (3 << 20); @@ -369,7 +320,7 @@ OUTREG(RADEON_CRTC_GEN_CNTL, save1 & (CARD32)~RADEON_CRTC_CUR_EN); } - if (info->IsSecondary || info->Clone) { + if (info->IsSecondary || info->MergedFB) { save2 = INREG(RADEON_CRTC2_GEN_CNTL) & ~(CARD32) (3 << 20); save2 |= (CARD32) (2 << 20); OUTREG(RADEON_CRTC2_GEN_CNTL, save2 & (CARD32)~RADEON_CRTC2_CUR_EN); @@ -402,12 +353,12 @@ for (x = 0; x < CURSOR_WIDTH; x++) *d++ = 0; - CURSOR_SWAPPING_END (); + CURSOR_SWAPPING_END(); if (!info->IsSecondary) OUTREG(RADEON_CRTC_GEN_CNTL, save1); - if (info->IsSecondary || info->Clone) + if (info->IsSecondary || info->MergedFB) OUTREG(RADEON_CRTC2_GEN_CNTL, save2); } @@ -458,29 +409,24 @@ width = pScrn->displayWidth; width_bytes = width * (pScrn->bitsPerPixel / 8); height = (size_bytes + width_bytes - 1) / width_bytes; - fbarea = xf86AllocateOffscreenArea(pScreen, - width, - height, - 256, - NULL, - NULL, - NULL); + + fbarea = xf86AllocateOffscreenArea(pScreen, width, height, + 256, NULL, NULL, NULL); if (!fbarea) { - info->cursor_start = 0; + info->cursor_offset = 0; xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Hardware cursor disabled" " due to insufficient offscreen memory\n"); } else { - info->cursor_start = RADEON_ALIGN((fbarea->box.x1 + - fbarea->box.y1 * width) * - info->CurrentLayout.pixel_bytes, - 256); - info->cursor_end = info->cursor_start + size_bytes; + info->cursor_offset = RADEON_ALIGN((fbarea->box.x1 + + fbarea->box.y1 * width) * + info->CurrentLayout.pixel_bytes, + 256); + info->cursor_end = info->cursor_offset + size_bytes; } - RADEONTRACE(("RADEONCursorInit (0x%08x-0x%08x)\n", - info->cursor_start, info->cursor_end)); + info->cursor_offset, info->cursor_end)); return xf86InitCursor(pScreen, cursor); } Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c:1.42 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c:1.43 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c:1.42 Tue Jan 9 09:04:45 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c Wed Apr 2 14:02:31 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c,v 1.42 2007/01/09 17:04:45 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c,v 1.43 2008/04/02 21:02:31 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, * VA Linux Systems Inc., Fremont, California. @@ -59,8 +59,6 @@ static size_t radeon_drm_page_size; -static Bool RADEONDRICloseFullScreen(ScreenPtr pScreen); -static Bool RADEONDRIOpenFullScreen(ScreenPtr pScreen); static void RADEONDRITransitionTo2d(ScreenPtr pScreen); static void RADEONDRITransitionTo3d(ScreenPtr pScreen); static void RADEONDRITransitionMultiToSingle3d(ScreenPtr pScreen); @@ -124,7 +122,7 @@ } i = 0; - for (db = 0; db <= use_db; db++) { + for (db = use_db; db >= 0; db--) { for (accum = 0; accum <= RADEON_USE_ACCUM; accum++) { for (stencil = 0; stencil <= RADEON_USE_STENCIL; stencil++) { pRADEONConfigPtrs[i] = &pRADEONConfigs[i]; @@ -157,14 +155,17 @@ pConfigs[i].doubleBuffer = FALSE; pConfigs[i].stereo = FALSE; pConfigs[i].bufferSize = 16; - pConfigs[i].depthSize = 16; - if (stencil) + pConfigs[i].depthSize = info->depthBits; + if (pConfigs[i].depthSize == 24 ? (RADEON_USE_STENCIL - stencil) + : stencil) { pConfigs[i].stencilSize = 8; - else + } else { pConfigs[i].stencilSize = 0; + } pConfigs[i].auxBuffers = 0; pConfigs[i].level = 0; - if (accum || stencil) { + if (accum || + (pConfigs[i].stencilSize && pConfigs[i].depthSize == 16)) { pConfigs[i].visualRating = GLX_SLOW_CONFIG; } else { pConfigs[i].visualRating = GLX_NONE; @@ -207,7 +208,7 @@ } i = 0; - for (db = 0; db <= use_db; db++) { + for (db = use_db; db >= 0; db--) { for (accum = 0; accum <= RADEON_USE_ACCUM; accum++) { for (stencil = 0; stencil <= RADEON_USE_STENCIL; stencil++) { pRADEONConfigPtrs[i] = &pRADEONConfigs[i]; @@ -240,16 +241,17 @@ pConfigs[i].doubleBuffer = FALSE; pConfigs[i].stereo = FALSE; pConfigs[i].bufferSize = 32; - if (stencil) { - pConfigs[i].depthSize = 24; + pConfigs[i].depthSize = info->depthBits; + if (pConfigs[i].depthSize == 24 ? (RADEON_USE_STENCIL - stencil) + : stencil) { pConfigs[i].stencilSize = 8; } else { - pConfigs[i].depthSize = 24; pConfigs[i].stencilSize = 0; } pConfigs[i].auxBuffers = 0; pConfigs[i].level = 0; - if (accum) { + if (accum || + (pConfigs[i].stencilSize && pConfigs[i].depthSize == 16)) { pConfigs[i].visualRating = GLX_SLOW_CONFIG; } else { pConfigs[i].visualRating = GLX_NONE; @@ -343,8 +345,57 @@ { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONSAREAPrivPtr pSAREAPriv; + + SET_SYNC_FLAG(info->accel); + + pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); + if (pSAREAPriv->ctxOwner != DRIGetContext(pScrn->pScreen)) + info->XInited3D = FALSE; + + + /* TODO: Fix this more elegantly. + * Sometimes (especially with multiple DRI clients), this code + * runs immediately after a DRI client issues a rendering command. + * + * The accel code regularly inserts WAIT_UNTIL_IDLE into the + * command buffer that is sent with the indirect buffer below. + * The accel code fails to set the 3D cache flush registers for + * the R300 before sending WAIT_UNTIL_IDLE. Sending a cache flush + * on these new registers is not necessary for pure 2D functionality, + * but it *is* necessary after 3D operations. + * Without the cache flushes before WAIT_UNTIL_IDLE, the R300 locks up. + * + * The CP_IDLE call into the DRM indirectly flushes all caches and + * thus avoids the lockup problem, but the solution is far from ideal. + * Better solutions could be: + * - always flush caches when entering the X server + * - track the type of rendering commands somewhere and issue + * cache flushes when they change + * However, I don't feel confident enough with the control flow + * inside the X server to implement either fix. -- nh + */ + + /* On my computer (Radeon Mobility M10) + The fix below results in x11perf -shmput500 rate of 245.0/sec + which is lower than 264.0/sec I get without it. + + Doing the same each time before indirect buffer is submitted + results in x11perf -shmput500 rate of 225.0/sec. + + On the other hand, not using CP acceleration at all benchmarks + at 144.0/sec. + + For now let us accept this as a lesser evil, especially as the + DRM driver for R300 is still in flux. + + Once the code is more stable this should probably be moved into DRM driver. + */ + + if (info->ChipFamily>=CHIP_FAMILY_R300) + drmCommandNone(info->drmFD, DRM_RADEON_CP_IDLE); + - if (info->accel) info->accel->NeedToSync = TRUE; } /* Called when the X server goes to sleep to allow the X server's @@ -394,73 +445,23 @@ } } -/* The Radeon has depth tiling on all the time, so we have to convert - * the x,y coordinates into the memory bus address (mba) in the same - * manner as the engine. In each case, the linear block address (ba) - * is calculated, and then wired with x and y to produce the final - * memory address. +/* The Radeon has depth tiling on all the time. Rely on surface regs to + * translate the addresses (only works if allowColorTiling is true). */ -static CARD32 radeon_mba_z16(RADEONInfoPtr info, int x, int y) -{ - CARD32 pitch = info->frontPitch; - CARD32 address = 0; /* a[0] = 0 */ - CARD32 ba; - - ba = (y / 16) * (pitch / 32) + (x / 32); - - address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */ - address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */ - address |= (x & 0x8) << 4; /* a[7] = x[3] */ - address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */ - address |= (y & 0x8) << 7; /* a[10] = y[3] */ - address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */ - address |= (ba & ~0x3u) << 10; /* a[12..] = ba[2..] */ - - return address; -} - -static CARD32 radeon_mba_z32(RADEONInfoPtr info, int x, int y) -{ - CARD32 pitch = info->frontPitch; - CARD32 address = 0; /* a[0..1] = 0 */ - CARD32 ba; - - ba = (y / 16) * (pitch / 16) + (x / 16); - - address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */ - address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */ - address |= - (((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */ - address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */ - - address |= (y & 0x8) << 7; /* a[10] = y[3] */ - address |= - (((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */ - address |= (ba & ~0x3u) << 10; /* a[12..] = ba[2..] */ - - return address; -} /* 16-bit depth buffer functions */ #define WRITE_DEPTH16(_x, _y, d) \ - *(CARD16 *)(pointer)(buf + radeon_mba_z16(info, (_x), (_y))) = (d) + *(CARD16 *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) = (d) #define READ_DEPTH16(d, _x, _y) \ - (d) = *(CARD16 *)(pointer)(buf + radeon_mba_z16(info, (_x), (_y))) + (d) = *(CARD16 *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) + +/* 32-bit depth buffer (stencil and depth simultaneously) functions */ +#define WRITE_DEPTHSTENCIL32(_x, _y, d) \ + *(CARD32 *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) = (d) -/* 24 bit depth, 8 bit stencil depthbuffer functions */ -#define WRITE_DEPTH32(_x, _y, d) \ -do { \ - CARD32 tmp = \ - *(CARD32 *)(pointer)(buf + radeon_mba_z32(info, (_x), (_y))); \ - tmp &= 0xff000000; \ - tmp |= ((d) & 0x00ffffff); \ - *(CARD32 *)(pointer)(buf + radeon_mba_z32(info, (_x), (_y))) = tmp; \ -} while (0) - -#define READ_DEPTH32(d, _x, _y) \ - d = (*(CARD32 *)(pointer)(buf + radeon_mba_z32(info, (_x), (_y))) \ - & 0x00ffffff) +#define READ_DEPTHSTENCIL32(d, _x, _y) \ + (d) = *(CARD32 *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) /* Screen to screen copy of data in the depth buffer */ static void RADEONScreenToScreenCopyDepth(ScrnInfoPtr pScrn, @@ -493,8 +494,8 @@ case 32: for (x = xstart; x != xend; x += xdir) { for (y = ystart; y != yend; y += ydir) { - READ_DEPTH32(d, xa+x, ya+y); - WRITE_DEPTH32(xb+x, yb+y, d); + READ_DEPTHSTENCIL32(d, xa+x, ya+y); + WRITE_DEPTHSTENCIL32(xb+x, yb+y, d); } } break; @@ -632,6 +633,11 @@ xdir = 1; } + /* pretty much a hack. */ + info->dst_pitch_offset = info->backPitchOffset; + if (info->tilingEnabled) + info->dst_pitch_offset |= RADEON_DST_TILE_MACRO; + (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, GXcopy, (CARD32)(-1), -1); @@ -651,14 +657,12 @@ if (w <= 0) continue; if (h <= 0) continue; - RADEONSelectBuffer(pScrn, RADEON_BACK); (*info->accel->SubsequentScreenToScreenCopy)(pScrn, xa, ya, destx, desty, w, h); if (info->depthMoves) { - RADEONSelectBuffer(pScrn, RADEON_DEPTH); RADEONScreenToScreenCopyDepth(pScrn, xa, ya, destx, desty, @@ -666,7 +670,7 @@ } } - RADEONSelectBuffer(pScrn, RADEON_FRONT); + info->dst_pitch_offset = info->frontPitchOffset;; DEALLOCATE_LOCAL(pptNew2); DEALLOCATE_LOCAL(pboxNew2); @@ -712,23 +716,39 @@ unsigned int device = drmAgpDeviceId(info->drmFD); mode &= ~RADEON_AGP_MODE_MASK; - switch (info->agpMode) { - case 4: mode |= RADEON_AGP_4X_MODE; - case 2: mode |= RADEON_AGP_2X_MODE; - case 1: default: mode |= RADEON_AGP_1X_MODE; + if ((mode & RADEON_AGPv3_MODE) && + (INREG(RADEON_AGP_STATUS) & RADEON_AGPv3_MODE)) { + /* only set one mode bit for AGPv3 */ + switch (info->agpMode) { + case 8: mode |= RADEON_AGPv3_8X_MODE; break; + case 4: default: mode |= RADEON_AGPv3_4X_MODE; + } + /*TODO: need to take care of other bits valid for v3 mode + * currently these bits are not used in all tested cards. + */ + } else { + switch (info->agpMode) { + case 4: mode |= RADEON_AGP_4X_MODE; + case 2: mode |= RADEON_AGP_2X_MODE; + case 1: default: mode |= RADEON_AGP_1X_MODE; + } } - if (info->agpFastWrite) mode |= RADEON_AGP_FW_MODE; - - if ((vendor == PCI_VENDOR_AMD) && + if (info->agpFastWrite && + (vendor == PCI_VENDOR_AMD) && (device == PCI_CHIP_AMD761)) { /* Disable fast write for AMD 761 chipset, since they cause * lockups when enabled. */ - mode &= ~0x10; /* FIXME: Magic number */ + info->agpFastWrite = FALSE; + xf86DrvMsg(pScreen->myNum, X_WARNING, + "[agp] Not enabling Fast Writes on AMD 761 chipset to avoid " + "lockups"); } + if (info->agpFastWrite) mode |= RADEON_AGP_FW_MODE; + xf86DrvMsg(pScreen->myNum, X_INFO, "[agp] Mode 0x%08lx [AGP 0x%04x/0x%04x; Card 0x%04x/0x%04x]\n", mode, vendor, device, @@ -807,7 +827,7 @@ "[agp] ring handle = 0x%08lx\n", info->ringHandle); if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize, - (drmAddressPtr)&info->ring) < 0) { + &info->ring) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n"); return FALSE; } @@ -826,7 +846,7 @@ info->ringReadPtrHandle); if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize, - (drmAddressPtr)&info->ringReadPtr) < 0) { + &info->ringReadPtr) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring read ptr\n"); return FALSE; @@ -846,7 +866,7 @@ info->bufHandle); if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize, - (drmAddressPtr)&info->buf) < 0) { + &info->buf) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map vertex/indirect buffers\n"); return FALSE; @@ -866,7 +886,7 @@ info->gartTexHandle); if (drmMap(info->drmFD, info->gartTexHandle, info->gartTexMapSize, - (drmAddressPtr)&info->gartTex) < 0) { + &info->gartTex) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map GART texture map\n"); return FALSE; @@ -910,7 +930,7 @@ "[pci] ring handle = 0x%08lx\n", info->ringHandle); if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize, - (drmAddressPtr)&info->ring) < 0) { + &info->ring) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n"); return FALSE; } @@ -932,7 +952,7 @@ info->ringReadPtrHandle); if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize, - (drmAddressPtr)&info->ringReadPtr) < 0) { + &info->ringReadPtr) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring read ptr\n"); return FALSE; @@ -955,7 +975,7 @@ info->bufHandle); if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize, - (drmAddressPtr)&info->buf) < 0) { + &info->buf) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map vertex/indirect buffers\n"); return FALSE; @@ -978,7 +998,7 @@ info->gartTexHandle); if (drmMap(info->drmFD, info->gartTexHandle, info->gartTexMapSize, - (drmAddressPtr)&info->gartTex) < 0) { + &info->gartTex) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map GART texture map\n"); return FALSE; @@ -1015,28 +1035,30 @@ drmRadeonInit drmInfo; memset(&drmInfo, 0, sizeof(drmRadeonInit)); - + if ( info->ChipFamily >= CHIP_FAMILY_R300 ) + drmInfo.func = DRM_RADEON_INIT_R300_CP; + else if ( info->ChipFamily >= CHIP_FAMILY_R200 ) drmInfo.func = DRM_RADEON_INIT_R200_CP; else drmInfo.func = DRM_RADEON_INIT_CP; drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec); - drmInfo.is_pci = info->IsPCI; + drmInfo.is_pci = (info->cardType!=CARD_AGP); drmInfo.cp_mode = info->CPMode; drmInfo.gart_size = info->gartSize*1024*1024; drmInfo.ring_size = info->ringSize*1024*1024; drmInfo.usec_timeout = info->CPusecTimeout; drmInfo.fb_bpp = info->CurrentLayout.pixel_code; - drmInfo.depth_bpp = info->CurrentLayout.pixel_code; + drmInfo.depth_bpp = (info->depthBits - 8) * 2; drmInfo.front_offset = info->frontOffset; drmInfo.front_pitch = info->frontPitch * cpp; drmInfo.back_offset = info->backOffset; drmInfo.back_pitch = info->backPitch * cpp; drmInfo.depth_offset = info->depthOffset; - drmInfo.depth_pitch = info->depthPitch * cpp; + drmInfo.depth_pitch = info->depthPitch * drmInfo.depth_bpp / 8; drmInfo.fb_offset = info->fbHandle; drmInfo.mmio_offset = info->registerHandle; @@ -1063,24 +1085,18 @@ drmRadeonMemInitHeap drmHeap; /* Start up the simple memory manager for GART space */ - if (info->drmMinor >= 6) { - drmHeap.region = RADEON_MEM_REGION_GART; - drmHeap.start = 0; - drmHeap.size = info->gartTexMapSize; - - if (drmCommandWrite(info->drmFD, DRM_RADEON_INIT_HEAP, - &drmHeap, sizeof(drmHeap))) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[drm] Failed to initialize GART heap manager\n"); - } else { - xf86DrvMsg(pScreen->myNum, X_INFO, - "[drm] Initialized kernel GART heap manager, %d\n", - info->gartTexMapSize); - } + drmHeap.region = RADEON_MEM_REGION_GART; + drmHeap.start = 0; + drmHeap.size = info->gartTexMapSize; + + if (drmCommandWrite(info->drmFD, DRM_RADEON_INIT_HEAP, + &drmHeap, sizeof(drmHeap))) { + xf86DrvMsg(pScreen->myNum, X_ERROR, + "[drm] Failed to initialize GART heap manager\n"); } else { xf86DrvMsg(pScreen->myNum, X_INFO, - "[drm] Kernel module too old (1.%d) for GART heap manager\n", - info->drmMinor); + "[drm] Initialized kernel GART heap manager, %d\n", + info->gartTexMapSize); } } @@ -1093,7 +1109,7 @@ info->bufNumBufs = drmAddBufs(info->drmFD, info->bufMapSize / RADEON_BUFFER_SIZE, RADEON_BUFFER_SIZE, - info->IsPCI ? DRM_SG_BUFFER : DRM_AGP_BUFFER, + (info->cardType!=CARD_AGP) ? DRM_SG_BUFFER : DRM_AGP_BUFFER, info->bufStart); if (info->bufNumBufs <= 0) { @@ -1157,23 +1173,17 @@ /* Make sure the CP is on for the X server */ RADEONCP_START(pScrn, info); - RADEONSelectBuffer(pScrn, RADEON_FRONT); + info->dst_pitch_offset = info->frontPitchOffset; } -/* Initialize the screen-specific data structures for the DRI and the - * Radeon. This is the main entry point to the device-specific - * initialization code. It calls device-independent DRI functions to - * create the DRI data structures and initialize the DRI state. - */ -Bool RADEONDRIScreenInit(ScreenPtr pScreen) +/* Get the DRM version and do some basic useability checks of DRI */ +Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) { - ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); - DRIInfoPtr pDRIInfo; - RADEONDRIPtr pRADEONDRI; - int major, minor, patch; - drmVersionPtr version; + int major, minor, patch, fd; + int req_minor, req_patch; + char *busId; /* Check that the GLX, DRI, and DRM modules have been loaded by testing * for known symbols in each module. @@ -1182,24 +1192,135 @@ if (!xf86LoaderCheckSymbol("DRIScreenInit")) return FALSE; if (!xf86LoaderCheckSymbol("drmAvailable")) return FALSE; if (!xf86LoaderCheckSymbol("DRIQueryVersion")) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[dri] RADEONDRIScreenInit failed (libdri.a too old)\n"); + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "[dri] RADEONDRIGetVersion failed (libdri.a too old)\n" + "[dri] Disabling DRI.\n"); return FALSE; } /* Check the DRI version */ DRIQueryVersion(&major, &minor, &patch); if (major != 4 || minor < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[dri] RADEONDRIScreenInit failed because of a version " + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "[dri] RADEONDRIGetVersion failed because of a version " "mismatch.\n" - "[dri] libDRI version is %d.%d.%d but version 4.0.x is " + "[dri] libdri version is %d.%d.%d but version 4.0.x is " "needed.\n" "[dri] Disabling DRI.\n", major, minor, patch); return FALSE; } + /* Check the lib version */ + if (xf86LoaderCheckSymbol("drmGetLibVersion")) + info->pLibDRMVersion = drmGetLibVersion(info->drmFD); + if (info->pLibDRMVersion == NULL) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "[dri] RADEONDRIGetVersion failed because libDRM is really " + "way to old to even get a version number out of it.\n" + "[dri] Disabling DRI.\n"); + return FALSE; + } + if (info->pLibDRMVersion->version_major != 1 || + info->pLibDRMVersion->version_minor < 2) { + /* incompatible drm library version */ + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "[dri] RADEONDRIGetVersion failed because of a " + "version mismatch.\n" + "[dri] libdrm.a module version is %d.%d.%d but " + "version 1.2.x is needed.\n" + "[dri] Disabling DRI.\n", + info->pLibDRMVersion->version_major, + info->pLibDRMVersion->version_minor, + info->pLibDRMVersion->version_patchlevel); + drmFreeVersion(info->pLibDRMVersion); + info->pLibDRMVersion = NULL; + return FALSE; + } + + /* Create a bus Id */ + if (xf86LoaderCheckSymbol("DRICreatePCIBusID")) { + busId = DRICreatePCIBusID(info->PciInfo); + } else { + busId = xalloc(64); + sprintf(busId, + "PCI:%d:%d:%d", + info->PciInfo->bus, + info->PciInfo->device, + info->PciInfo->func); + } + + /* Low level DRM open */ + fd = drmOpen(RADEON_DRIVER_NAME, busId); + xfree(busId); + if (fd < 0) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "[dri] RADEONDRIGetVersion failed to open the DRM\n" + "[dri] Disabling DRI.\n"); + return FALSE; + } + + /* Get DRM version & close DRM */ + info->pKernelDRMVersion = drmGetVersion(fd); + drmClose(fd); + if (info->pKernelDRMVersion == NULL) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "[dri] RADEONDRIGetVersion failed to get the DRM version\n" + "[dri] Disabling DRI.\n"); + return FALSE; + } + + /* Now check if we qualify */ + if (info->ChipFamily >= CHIP_FAMILY_R300) { + req_minor = 17; + req_patch = 0; + } else if (info->IsIGP) { + req_minor = 10; + req_patch = 0; + } else { /* Many problems have been reported with 1.7 in the 2.4 kernel */ + req_minor = 8; + req_patch = 0; + } + + /* We don't, bummer ! */ + if (info->pKernelDRMVersion->version_major != 1 || + info->pKernelDRMVersion->version_minor < req_minor || + (info->pKernelDRMVersion->version_minor == req_minor && + info->pKernelDRMVersion->version_patchlevel < req_patch)) { + /* Incompatible drm version */ + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "[dri] RADEONDRIGetVersion failed because of a version " + "mismatch.\n" + "[dri] radeon.o kernel module version is %d.%d.%d " + "but version 1.%d.%d or newer is needed.\n" + "[dri] Disabling DRI.\n", + info->pKernelDRMVersion->version_major, + info->pKernelDRMVersion->version_minor, + info->pKernelDRMVersion->version_patchlevel, + req_minor, + req_patch); + drmFreeVersion(info->pKernelDRMVersion); + info->pKernelDRMVersion = NULL; + return FALSE; + } + + return TRUE; +} + +/* Initialize the screen-specific data structures for the DRI and the + * Radeon. This is the main entry point to the device-specific + * initialization code. It calls device-independent DRI functions to + * create the DRI data structures and initialize the DRI state. + */ +Bool RADEONDRIScreenInit(ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); + DRIInfoPtr pDRIInfo; + RADEONDRIPtr pRADEONDRI; + + info->DRICloseScreen = NULL; + switch (info->CurrentLayout.pixel_code) { case 8: case 15: @@ -1227,6 +1348,9 @@ info->pDRIInfo = pDRIInfo; pDRIInfo->drmDriverName = RADEON_DRIVER_NAME; + if ( (info->ChipFamily >= CHIP_FAMILY_R300) ) { + pDRIInfo->clientDriverName = R300_DRIVER_NAME; + } else if ( info->ChipFamily >= CHIP_FAMILY_R200 ) pDRIInfo->clientDriverName = R200_DRIVER_NAME; else @@ -1242,11 +1366,12 @@ info->PciInfo->device, info->PciInfo->func); } - pDRIInfo->ddxDriverMajorVersion = RADEON_VERSION_MAJOR; + pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? + RADEON_VERSION_MAJOR_TILED : RADEON_VERSION_MAJOR; pDRIInfo->ddxDriverMinorVersion = RADEON_VERSION_MINOR; pDRIInfo->ddxDriverPatchVersion = RADEON_VERSION_PATCH; pDRIInfo->frameBufferPhysicalAddress = info->LinearAddr; - pDRIInfo->frameBufferSize = info->FbMapSize; + pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize; pDRIInfo->frameBufferStride = (pScrn->displayWidth * info->CurrentLayout.pixel_bytes); pDRIInfo->ddxDrawableTableEntry = RADEON_MAX_DRAWABLES; @@ -1254,6 +1379,9 @@ < RADEON_MAX_DRAWABLES ? SAREA_MAX_DRAWABLES : RADEON_MAX_DRAWABLES); + /* kill DRIAdjustFrame. We adjust sarea frame info ourselves to work + correctly with pageflip + mergedfb/color tiling */ + pDRIInfo->wrap.AdjustFrame = NULL; #ifdef PER_CONTEXT_SAREA /* This is only here for testing per-context SAREAs. When used, the @@ -1294,8 +1422,6 @@ pDRIInfo->InitBuffers = RADEONDRIInitBuffers; pDRIInfo->MoveBuffers = RADEONDRIMoveBuffers; pDRIInfo->bufferRequests = DRI_ALL_WINDOWS; - pDRIInfo->OpenFullScreen = RADEONDRIOpenFullScreen; - pDRIInfo->CloseFullScreen = RADEONDRICloseFullScreen; pDRIInfo->TransitionTo2d = RADEONDRITransitionTo2d; pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d; pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d; @@ -1313,102 +1439,8 @@ pDRIInfo = NULL; return FALSE; } - - /* Check the DRM lib version. - * drmGetLibVersion was not supported in version 1.0, so check for - * symbol first to avoid possible crash or hang. - */ - if (xf86LoaderCheckSymbol("drmGetLibVersion")) { - version = drmGetLibVersion(info->drmFD); - } else { - /* drmlib version 1.0.0 didn't have the drmGetLibVersion - * entry point. Fake it by allocating a version record - * via drmGetVersion and changing it to version 1.0.0. - */ - version = drmGetVersion(info->drmFD); - version->version_major = 1; - version->version_minor = 0; - version->version_patchlevel = 0; - } - - if (version) { - if (version->version_major != 1 || - version->version_minor < 1) { - /* incompatible drm library version */ - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[dri] RADEONDRIScreenInit failed because of a " - "version mismatch.\n" - "[dri] libdrm.a module version is %d.%d.%d but " - "version 1.1.x is needed.\n" - "[dri] Disabling DRI.\n", - version->version_major, - version->version_minor, - version->version_patchlevel); - drmFreeVersion(version); - RADEONDRICloseScreen(pScreen); - return FALSE; - } - drmFreeVersion(version); - } - - /* Check the radeon DRM version */ - version = drmGetVersion(info->drmFD); - if (version) { - int req_minor, req_patch; - - if (info->IsIGP) { - req_minor = 10; - req_patch = 0; - } else if (info->ChipFamily >= CHIP_FAMILY_R200) { - req_minor = 5; - req_patch = 0; - } else { -#if X_BYTE_ORDER == X_LITTLE_ENDIAN - req_minor = 1; - req_patch = 0; -#else - req_minor = 2; - req_patch = 1; -#endif - } - - if (version->version_major != 1 || - version->version_minor < req_minor || - (version->version_minor == req_minor && - version->version_patchlevel < req_patch)) { - /* Incompatible drm version */ - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[dri] RADEONDRIScreenInit failed because of a version " - "mismatch.\n" - "[dri] radeon.o kernel module version is %d.%d.%d " - "but version 1.%d.%d or newer is needed.\n" - "[dri] Disabling DRI.\n", - version->version_major, - version->version_minor, - version->version_patchlevel, - req_minor, - req_patch); - drmFreeVersion(version); - RADEONDRICloseScreen(pScreen); - return FALSE; - } - - if (version->version_minor < 3) { - xf86DrvMsg(pScreen->myNum, X_WARNING, - "[dri] Some DRI features disabled because of version " - "mismatch.\n" - "[dri] radeon.o kernel module version is %d.%d.%d but " - "1.3.1 or later is preferred.\n", - version->version_major, - version->version_minor, - version->version_patchlevel); - } - info->drmMinor = version->version_minor; - drmFreeVersion(version); - } - /* Initialize AGP */ - if (!info->IsPCI && !RADEONDRIAgpInit(info, pScreen)) { + if (info->cardType==CARD_AGP && !RADEONDRIAgpInit(info, pScreen)) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] AGP failed to initialize. Disabling the DRI.\n" ); xf86DrvMsg(pScreen->myNum, X_INFO, @@ -1419,7 +1451,7 @@ } /* Initialize PCI */ - if (info->IsPCI && !RADEONDRIPciInit(info, pScreen)) { + if ((info->cardType!=CARD_AGP) && !RADEONDRIPciInit(info, pScreen)) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] PCI failed to initialize. Disabling the DRI.\n" ); RADEONDRICloseScreen(pScreen); @@ -1439,12 +1471,12 @@ map, but we need it as well */ { void *scratch_ptr; - int scratch_int; + int scratch_int; DRIGetDeviceInfo(pScreen, &info->fbHandle, - &scratch_int, &scratch_int, - &scratch_int, &scratch_int, - &scratch_ptr); + &scratch_int, &scratch_int, + &scratch_int, &scratch_int, + &scratch_ptr); } /* FIXME: When are these mappings unmapped? */ @@ -1458,6 +1490,17 @@ return TRUE; } +static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); + + RADEONDRICloseScreen(pScreen); + + pScreen->CloseScreen = info->DRICloseScreen; + return (*pScreen->CloseScreen)(scrnIndex, pScreen); +} + /* Finish initializing the device-dependent DRI state, and call * DRIFinishScreenInit() to complete the device-independent DRI * initialization. @@ -1515,7 +1558,7 @@ pRADEONDRI->depth = pScrn->depth; pRADEONDRI->bpp = pScrn->bitsPerPixel; - pRADEONDRI->IsPCI = info->IsPCI; + pRADEONDRI->IsPCI = (info->cardType!=CARD_AGP); pRADEONDRI->AGPMode = info->agpMode; pRADEONDRI->frontOffset = info->frontOffset; @@ -1546,16 +1589,32 @@ pRADEONDRI->perctx_sarea_size = info->perctx_sarea_size; #endif - /* Have shadowfb run only while there is 3d active. */ - if (info->allowPageFlip /* && info->drmMinor >= 3 */) { - ShadowFBInit( pScreen, RADEONDRIRefreshArea ); - } else { - info->allowPageFlip = 0; - } + info->directRenderingInited = TRUE; + + /* Wrap CloseScreen */ + info->DRICloseScreen = pScreen->CloseScreen; + pScreen->CloseScreen = RADEONDRIDoCloseScreen; return TRUE; } +void RADEONDRIInitPageFlip(ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); + + /* Have shadowfb run only while there is 3d active. This must happen late, + * after XAAInit has been called + */ + if (!ShadowFBInit( pScreen, RADEONDRIRefreshArea )) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "ShadowFB init failed, Page Flipping disabled\n"); + info->allowPageFlip = 0; + } else + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "ShadowFB initialized for Page Flipping\n"); +} + /** * This function will attempt to get the Radeon hardware back into shape * after a resume from disc. @@ -1568,7 +1627,7 @@ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); - if (info->drmMinor >= 9) { + if (info->pKernelDRMVersion->version_minor >= 9) { xf86DrvMsg(pScreen->myNum, X_INFO, "[RESUME] Attempting to re-init Radeon hardware.\n"); } else { @@ -1578,7 +1637,7 @@ return; } - if (!info->IsPCI) { + if (info->cardType==CARD_AGP) { if (!RADEONSetAgpMode(info, pScreen)) return; @@ -1597,18 +1656,16 @@ RADEONDRICPInit(pScrn); } -/* The screen is being closed, so clean up any state and free any - * resources used by the DRI. - */ -void RADEONDRICloseScreen(ScreenPtr pScreen) +void RADEONDRIStop(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); - drmRadeonInit drmInfo; RING_LOCALS; - /* Stop the CP */ - if (info->directRenderingEnabled) { + RADEONTRACE(("RADEONDRIStop\n")); + + /* Stop the CP */ + if (info->directRenderingInited) { /* If we've generated any CP commands, we must flush them to the * kernel module now. */ @@ -1621,26 +1678,39 @@ } RADEONCP_STOP(pScrn, info); } + info->directRenderingInited = FALSE; +} + +/* The screen is being closed, so clean up any state and free any + * resources used by the DRI. + */ +void RADEONDRICloseScreen(ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); + drmRadeonInit drmInfo; + + RADEONTRACE(("RADEONDRICloseScreen\n")); - if (info->irq) { + if (info->irq) { drmCtlUninstHandler(info->drmFD); info->irq = 0; info->ModeReg.gen_int_cntl = 0; } - /* De-allocate vertex buffers */ + /* De-allocate vertex buffers */ if (info->buffers) { drmUnmapBufs(info->buffers); info->buffers = NULL; } - /* De-allocate all kernel resources */ + /* De-allocate all kernel resources */ memset(&drmInfo, 0, sizeof(drmRadeonInit)); drmInfo.func = DRM_RADEON_CLEANUP_CP; drmCommandWrite(info->drmFD, DRM_RADEON_CP_INIT, &drmInfo, sizeof(drmRadeonInit)); - /* De-allocate all GART resources */ + /* De-allocate all GART resources */ if (info->gartTex) { drmUnmap(info->gartTex, info->gartTexMapSize); info->gartTex = NULL; @@ -1668,10 +1738,15 @@ info->pciMemHandle = 0; } - /* De-allocate all DRI resources */ + if (info->pciGartBackup) { + xfree(info->pciGartBackup); + info->pciGartBackup = NULL; + } + + /* De-allocate all DRI resources */ DRICloseScreen(pScreen); - /* De-allocate all DRI data structures */ + /* De-allocate all DRI data structures */ if (info->pDRIInfo) { if (info->pDRIInfo->devPrivate) { xfree(info->pDRIInfo->devPrivate); @@ -1690,24 +1765,6 @@ } } - - -/* Fullscreen hooks. The DRI fullscreen mode can probably be removed as - * it adds little or nothing above the mechanism below (and isn't widely - * used). - */ -static Bool RADEONDRIOpenFullScreen(ScreenPtr pScreen) -{ - return TRUE; -} - -static Bool RADEONDRICloseFullScreen(ScreenPtr pScreen) -{ - return TRUE; -} - - - /* Use callbacks from dri.c to support pageflipping mode for a single * 3d context without need for any specific full-screen extension. * @@ -1734,12 +1791,20 @@ int i; RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); + if (!info->directRenderingInited) + return; + /* Don't want to do this when no 3d is active and pages are * right-way-round */ if (!pSAREAPriv->pfAllowPageFlip && pSAREAPriv->pfCurrentPage == 0) return; + /* Make sure accel has been properly inited */ + if (info->accel == NULL || info->accel->SetupForScreenToScreenCopy == NULL) + return; + if (info->tilingEnabled) + info->dst_pitch_offset |= RADEON_DST_TILE_MACRO; (*info->accel->SetupForScreenToScreenCopy)(pScrn, 1, 1, GXcopy, (CARD32)(-1), -1); @@ -1756,6 +1821,7 @@ yb - ya + 1); } } + info->dst_pitch_offset &= ~RADEON_DST_TILE_MACRO; } static void RADEONEnablePageFlip(ScreenPtr pScreen) @@ -1765,6 +1831,9 @@ RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen); if (info->allowPageFlip) { + /* pretty much a hack. */ + if (info->tilingEnabled) + info->dst_pitch_offset |= RADEON_DST_TILE_MACRO; /* Duplicate the frontbuffer to the backbuffer */ (*info->accel->SetupForScreenToScreenCopy)(pScrn, 1, 1, GXcopy, @@ -1778,6 +1847,7 @@ pScrn->virtualX, pScrn->virtualY); + info->dst_pitch_offset &= ~RADEON_DST_TILE_MACRO; pSAREAPriv->pfAllowPageFlip = 1; } } @@ -1827,7 +1897,7 @@ xf86QueryLargestOffscreenArea(pScreen, &width, &height, 0, 0, 0); /* Free Xv linear offscreen memory if necessary */ - if (height < (info->depthTexLines + info->backLines)) { + if (info->videoLinear && height < (info->depthTexLines + info->backLines)) { xf86FreeOffscreenLinear(info->videoLinear); info->videoLinear = NULL; xf86QueryLargestOffscreenArea(pScreen, &width, &height, 0, 0, 0); @@ -1835,6 +1905,8 @@ /* Reserve placeholder area so the other areas will match the * pre-calculated offsets + * FIXME: We may have other locked allocations and thus this would allocate + * in the wrong place. The XV surface allocations seem likely. -- anholt */ fbarea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth, height @@ -1851,9 +1923,8 @@ pScrn->displayWidth, NULL, NULL, NULL); if (!info->backArea) - xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve offscreen " - "area for back buffer, you might experience screen " - "corruption\n"); + xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve offscreen area " + "for back buffer, you might experience screen corruption\n"); info->depthTexArea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth, @@ -1867,11 +1938,12 @@ xf86FreeOffscreenArea(fbarea); - RADEONEnablePageFlip(pScreen); - info->have3DWindows = 1; - if (info->cursor_start) + RADEONChangeSurfaces(pScrn); + RADEONEnablePageFlip(pScreen); + + if (info->cursor) xf86ForceHWCursor (pScreen, TRUE); } @@ -1900,6 +1972,32 @@ info->have3DWindows = 0; - if (info->cursor_start) - xf86ForceHWCursor (pScreen, FALSE); + RADEONChangeSurfaces(pScrn); + + if (info->cursor) + xf86ForceHWCursor (pScreen, FALSE); +} + +void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); + + if (info->cardType != CARD_PCIE || + info->pKernelDRMVersion->version_minor < 19) + return; + + if (info->FbSecureSize==0) + return; + + info->pciGartSize = RADEON_PCIGART_TABLE_SIZE; + + /* allocate space to back up PCIEGART table */ + info->pciGartBackup = xnfcalloc(1, info->pciGartSize); + if (info->pciGartBackup == NULL) + return; + + info->pciGartOffset = (info->FbMapSize - info->FbSecureSize); + + } Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h:1.6 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h:1.7 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h:1.6 Fri Dec 10 08:07:01 2004 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h Wed Apr 2 14:02:31 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h,v 1.6 2004/12/10 16:07:01 alanh Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h,v 1.7 2008/04/02 21:02:31 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, * VA Linux Systems Inc., Fremont, California. @@ -54,12 +54,11 @@ #define RADEON_DEFAULT_CP_TIMEOUT 10000 /* usecs */ -#define RADEON_AGP_MAX_MODE 4 +#define RADEON_PCIGART_TABLE_SIZE 32768 -#define RADEON_CARD_TYPE_RADEON 1 +#define RADEON_AGP_MAX_MODE 8 -/* Buffer are aligned on 4096 byte boundaries */ -#define RADEON_BUFFER_ALIGN 0x00000fff +#define RADEON_CARD_TYPE_RADEON 1 #define RADEONCP_USE_RING_BUFFER(m) \ (((m) == RADEON_CSQ_PRIBM_INDDIS) || \ Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c:1.136 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c:1.143 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c:1.136 Fri Mar 23 19:29:44 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c Wed Nov 12 08:34:57 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v 1.136 2007/03/24 02:29:44 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v 1.143 2008/11/12 16:34:57 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -56,11 +56,15 @@ * overlay planes * * Modified by Marc Aurele La France (tsi@xfree86.org) for ATI driver merge. + * + * Mergedfb and pseudo xinerama support added by Alex Deucher (agd5f@yahoo.com) + * based on the sis driver by Thomas Winischhofer. */ /* Driver data structures */ #include "radeon.h" #include "radeon_macros.h" +#include "radeon_mergedfb.h" #include "radeon_probe.h" #include "radeon_reg.h" #include "radeon_version.h" @@ -69,6 +73,7 @@ #define _XF86DRI_SERVER_ #include "radeon_dri.h" #include "radeon_sarea.h" +#include "sarea.h" #endif #include "fb.h" @@ -108,41 +113,75 @@ int flags); static void RADEONInitDispBandwidth(ScrnInfoPtr pScrn); +static void RADEONGetMergedFBOptions(ScrnInfoPtr pScrn); +static int RADEONValidateMergeModes(ScrnInfoPtr pScrn); +static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode); +static void RADEONForceSomeClocks(ScrnInfoPtr pScrn); +static void RADEONUpdatePanelSize(ScrnInfoPtr pScrn); +static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); + +#ifdef XF86DRI +static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); +#endif + +/* pseudo xinerama support */ + +extern Bool RADEONnoPanoramiXExtension; + typedef enum { OPTION_NOACCEL, OPTION_SW_CURSOR, OPTION_DAC_6BIT, OPTION_DAC_8BIT, #ifdef XF86DRI - OPTION_IS_PCI, OPTION_BUS_TYPE, OPTION_CP_PIO, OPTION_USEC_TIMEOUT, OPTION_AGP_MODE, OPTION_AGP_FW, OPTION_GART_SIZE, + OPTION_GART_SIZE_OLD, OPTION_RING_SIZE, OPTION_BUFFER_SIZE, OPTION_DEPTH_MOVE, OPTION_PAGE_FLIP, OPTION_NO_BACKBUFFER, + OPTION_XV_DMA, + OPTION_FBTEX_PERCENT, + OPTION_DEPTH_BITS, #endif OPTION_PANEL_OFF, OPTION_DDC_MODE, OPTION_MONITOR_LAYOUT, OPTION_IGNORE_EDID, - OPTION_CRTC2_OVERLAY, - OPTION_CLONE_MODE, - OPTION_CLONE_HSYNC, - OPTION_CLONE_VREFRESH, OPTION_FBDEV, - OPTION_VIDEO_KEY, + OPTION_MERGEDFB, + OPTION_CRT2HSYNC, + OPTION_CRT2VREFRESH, + OPTION_CRT2POS, + OPTION_METAMODES, + OPTION_MERGEDDPI, + OPTION_RADEONXINERAMA, + OPTION_CRT2ISSCRN0, + OPTION_MERGEDFBNONRECT, + OPTION_MERGEDFBMOUSER, OPTION_DISP_PRIORITY, OPTION_PANEL_SIZE, + OPTION_MIN_DOTCLOCK, + OPTION_COLOR_TILING, + OPTION_VIDEO_KEY, + OPTION_SUBPIXEL_ORDER, + OPTION_SHOWCACHE, + OPTION_DYNAMIC_CLOCKS, + OPTION_BIOS_HOTKEYS, + OPTION_VGA_ACCESS, + OPTION_REVERSE_DDC, + OPTION_LVDS_PROBE_PLL, + OPTION_CONSTANTDPI, #ifdef __powerpc__ OPTION_IBOOKHACKS, #endif - OPTION_MIN_DOTCLOCK + OPTION_LAST } RADEONOpts; const OptionInfoRec RADEONOptions[] = { @@ -151,33 +190,48 @@ { OPTION_DAC_6BIT, "Dac6Bit", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_DAC_8BIT, "Dac8Bit", OPTV_BOOLEAN, {0}, TRUE }, #ifdef XF86DRI - { OPTION_IS_PCI, "ForcePCIMode", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_BUS_TYPE, "BusType", OPTV_ANYSTR, {0}, FALSE }, { OPTION_CP_PIO, "CPPIOMode", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_USEC_TIMEOUT, "CPusecTimeout", OPTV_INTEGER, {0}, FALSE }, { OPTION_AGP_MODE, "AGPMode", OPTV_INTEGER, {0}, FALSE }, { OPTION_AGP_FW, "AGPFastWrite", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_GART_SIZE, "AGPSize", OPTV_INTEGER, {0}, FALSE }, + { OPTION_GART_SIZE_OLD, "AGPSize", OPTV_INTEGER, {0}, FALSE }, { OPTION_GART_SIZE, "GARTSize", OPTV_INTEGER, {0}, FALSE }, { OPTION_RING_SIZE, "RingSize", OPTV_INTEGER, {0}, FALSE }, { OPTION_BUFFER_SIZE, "BufferSize", OPTV_INTEGER, {0}, FALSE }, { OPTION_DEPTH_MOVE, "EnableDepthMoves", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_NO_BACKBUFFER, "NoBackBuffer", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_XV_DMA, "DMAForXv", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_DEPTH_BITS, "DepthBits", OPTV_INTEGER, {0}, FALSE }, #endif { OPTION_PANEL_OFF, "PanelOff", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_DDC_MODE, "DDCMode", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_MONITOR_LAYOUT, "MonitorLayout", OPTV_ANYSTR, {0}, FALSE }, { OPTION_IGNORE_EDID, "IgnoreEDID", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_CRTC2_OVERLAY , "OverlayOnCRTC2", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_CLONE_MODE, "CloneMode", OPTV_ANYSTR, {0}, FALSE }, - { OPTION_CLONE_HSYNC, "CloneHSync", OPTV_ANYSTR, {0}, FALSE }, - { OPTION_CLONE_VREFRESH, "CloneVRefresh", OPTV_ANYSTR, {0}, FALSE }, { OPTION_FBDEV, "UseFBDev", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE }, + { OPTION_MERGEDFB, "MergedFB", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_CRT2HSYNC, "CRT2HSync", OPTV_ANYSTR, {0}, FALSE }, + { OPTION_CRT2VREFRESH, "CRT2VRefresh", OPTV_ANYSTR, {0}, FALSE }, + { OPTION_CRT2POS, "CRT2Position", OPTV_ANYSTR, {0}, FALSE }, + { OPTION_METAMODES, "MetaModes", OPTV_ANYSTR, {0}, FALSE }, + { OPTION_MERGEDDPI, "MergedDPI", OPTV_ANYSTR, {0}, FALSE }, + { OPTION_RADEONXINERAMA, "MergedXinerama", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_CRT2ISSCRN0, "MergedXineramaCRT2IsScreen0", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_MERGEDFBNONRECT, "MergedNonRectangular", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_MERGEDFBMOUSER, "MergedMouseRestriction", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE }, { OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE }, { OPTION_MIN_DOTCLOCK, "ForceMinDotClock", OPTV_FREQ, {0}, FALSE }, + { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE }, + { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, + { OPTION_SHOWCACHE, "ShowCache", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_DYNAMIC_CLOCKS, "DynamicClocks", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_BIOS_HOTKEYS, "BIOSHotkeys", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_REVERSE_DDC, "ReverseDDC", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_LVDS_PROBE_PLL, "LVDSProbePLL", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_CONSTANTDPI, "ConstantDPI", OPTV_BOOLEAN, {0}, FALSE }, #ifdef __powerpc__ { OPTION_IBOOKHACKS, "iBookHacks", OPTV_BOOLEAN, {0}, FALSE }, #endif @@ -200,12 +254,14 @@ "fbdevHWInit", "fbdevHWUseBuildinMode", + "fbdevHWGetLineLength", "fbdevHWGetVidmem", "fbdevHWDPMSSet", /* colormap */ "fbdevHWLoadPalette", + /* ScrnInfo hooks */ "fbdevHWAdjustFrame", "fbdevHWEnterVT", @@ -226,7 +282,6 @@ static const char *ddcSymbols[] = { "xf86PrintEDID", - "xf86DoEDID_DDC1", "xf86DoEDID_DDC2", NULL }; @@ -329,6 +384,7 @@ static const char *int10Symbols[] = { "xf86InitInt10", + "xf86ExecX86int10", "xf86FreeInt10", "xf86int10Addr", NULL @@ -401,10 +457,14 @@ {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R200*/ {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV250*/ {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS300*/ - {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x400f7/*0x40111*/}, {0, 0}}, /*CHIP_FAMILY_RV280*/ + {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /*CHIP_FAMILY_RV280*/ {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R300*/ {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R350*/ {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV350*/ + {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV380*/ + {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R420*/ + {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV410*/ /* FIXME: just values from r420 used... */ + {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS400*/ /* FIXME: just values from rv380 used... */ }; extern int gRADEONEntityIndex; @@ -418,12 +478,11 @@ static Bool RADEONMapMMIO(ScrnInfoPtr pScrn); static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn); -static RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) +RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) { DevUnion *pPriv; RADEONInfoPtr info = RADEONPTR(pScrn); - pPriv = xf86GetEntityPrivate(info->pEnt->index, - gRADEONEntityIndex); + pPriv = xf86GetEntityPrivate(info->pEnt->index, gRADEONEntityIndex); return pPriv->ptr; } @@ -511,6 +570,48 @@ /* Free our private RADEONInfoRec */ static void RADEONFreeRec(ScrnInfoPtr pScrn) { + RADEONInfoPtr info = RADEONPTR(pScrn); + if(info->CRT2HSync) xfree(info->CRT2HSync); + info->CRT2HSync = NULL; + if(info->CRT2VRefresh) xfree(info->CRT2VRefresh); + info->CRT2VRefresh = NULL; + if(info->MetaModes) xfree(info->MetaModes); + info->MetaModes = NULL; + if(info->CRT2pScrn) { + if(info->CRT2pScrn->modes) { + while(info->CRT2pScrn->modes) + xf86DeleteMode(&info->CRT2pScrn->modes, info->CRT2pScrn->modes); + } + if(info->CRT2pScrn->monitor) { + if(info->CRT2pScrn->monitor->Modes) { + while(info->CRT2pScrn->monitor->Modes) + xf86DeleteMode(&info->CRT2pScrn->monitor->Modes, info->CRT2pScrn->monitor->Modes); + } + if(info->CRT2pScrn->monitor->DDC) xfree(info->CRT2pScrn->monitor->DDC); + xfree(info->CRT2pScrn->monitor); + } + xfree(info->CRT2pScrn); + info->CRT2pScrn = NULL; + } + if(info->CRT1Modes) { + if(info->CRT1Modes != pScrn->modes) { + if(pScrn->modes) { + pScrn->currentMode = pScrn->modes; + do { + DisplayModePtr p = pScrn->currentMode->next; + if(pScrn->currentMode->Private) + xfree(pScrn->currentMode->Private); + xfree(pScrn->currentMode); + pScrn->currentMode = p; + } while(pScrn->currentMode != pScrn->modes); + } + pScrn->currentMode = info->CRT1CurrentMode; + pScrn->modes = info->CRT1Modes; + info->CRT1CurrentMode = NULL; + info->CRT1Modes = NULL; + } + } + if (!pScrn || !pScrn->driverPrivate) return; xfree(pScrn->driverPrivate); pScrn->driverPrivate = NULL; @@ -562,6 +663,7 @@ if (info->FBDev) { info->FB = fbdevHWMapVidmem(pScrn); } else { + RADEONTRACE(("Map: 0x%08lx, 0x%08lx\n", info->LinearAddr, info->FbMapSize)); info->FB = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_FRAMEBUFFER, info->PciTag, @@ -604,24 +706,49 @@ return TRUE; } -/* This function is required to workaround a hardware bug in some (all?) - * revisions of the R300. This workaround should be called after every - * CLOCK_CNTL_INDEX register access. If not, register reads afterward - * may not be correct. - */ -void R300CGWorkaround(ScrnInfoPtr pScrn) { - RADEONInfoPtr info = RADEONPTR(pScrn); +void RADEONPllErrataAfterIndex(RADEONInfoPtr info) +{ + unsigned char *RADEONMMIO = info->MMIO; + + if (!(info->ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS)) + return; + + /* This workaround is necessary on rv200 and RS200 or PLL + * reads may return garbage (among others...) + */ + (void)INREG(RADEON_CLOCK_CNTL_DATA); + (void)INREG(RADEON_CRTC_GEN_CNTL); +} + +void RADEONPllErrataAfterData(RADEONInfoPtr info) +{ unsigned char *RADEONMMIO = info->MMIO; - CARD32 save, tmp; - save = INREG(RADEON_CLOCK_CNTL_INDEX); - tmp = save & ~(0x3f | RADEON_PLL_WR_EN); - OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); - tmp = INREG(RADEON_CLOCK_CNTL_DATA); - OUTREG(RADEON_CLOCK_CNTL_INDEX, save); + /* This workarounds is necessary on RV100, RS100 and RS200 chips + * or the chip could hang on a subsequent access + */ + if (info->ChipErrata & CHIP_ERRATA_PLL_DELAY) { + /* we can't deal with posted writes here ... */ + usleep(5000); + } + + /* This function is required to workaround a hardware bug in some (all?) + * revisions of the R300. This workaround should be called after every + * CLOCK_CNTL_INDEX register access. If not, register reads afterward + * may not be correct. + */ + if (info->ChipErrata & CHIP_ERRATA_R300_CG) { + CARD32 save, tmp; + + save = INREG(RADEON_CLOCK_CNTL_INDEX); + tmp = save & ~(0x3f | RADEON_PLL_WR_EN); + OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); + tmp = INREG(RADEON_CLOCK_CNTL_DATA); + OUTREG(RADEON_CLOCK_CNTL_INDEX, save); + } } -/* Read PLL information */ +/* Read PLL register */ unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -629,12 +756,27 @@ CARD32 data; OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); + RADEONPllErrataAfterIndex(info); data = INREG(RADEON_CLOCK_CNTL_DATA); - if (info->R300CGWorkaround) R300CGWorkaround(pScrn); + RADEONPllErrataAfterData(info); return data; } +/* Write PLL information */ +void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | + RADEON_PLL_WR_EN)); + RADEONPllErrataAfterIndex(info); + OUTREG(RADEON_CLOCK_CNTL_DATA, data); + RADEONPllErrataAfterData(info); +} + + #if 0 /* Read PAL information (only used for debugging) */ static int RADEONINPAL(int idx) @@ -652,8 +794,14 @@ { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; + CARD32 crtc_gen_cntl; int i; + crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); + if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || + !(crtc_gen_cntl & RADEON_CRTC_EN)) + return; + /* Clear the CRTC_VBLANK_SAVE bit */ OUTREG(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); @@ -669,8 +817,14 @@ { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; + CARD32 crtc2_gen_cntl; int i; + crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); + if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || + !(crtc2_gen_cntl & RADEON_CRTC2_EN)) + return; + /* Clear the CRTC2_VBLANK_SAVE bit */ OUTREG(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); @@ -701,7 +855,7 @@ default: break; } - if (info->Clone) + if (info->MergedFB) OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS, ~(RADEON_CRTC2_DISP_DIS)); @@ -732,7 +886,7 @@ default: break; } - if (info->Clone) + if (info->MergedFB) OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~(RADEON_CRTC2_DISP_DIS)); @@ -769,12 +923,13 @@ return (n + (d / 2)) / d; } -static RADEONMonitorType RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, RADEONDDCType DDCType, xf86MonPtr* MonInfo) +static RADEONMonitorType RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, RADEONDDCType DDCType, RADEONConnector* port) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; unsigned long DDCReg; RADEONMonitorType MonType = MT_NONE; + xf86MonPtr* MonInfo = &port->MonInfo; int i, j; DDCReg = info->DDCReg; @@ -857,10 +1012,25 @@ MonType = MT_NONE; } + OUTREG(info->DDCReg, INREG(info->DDCReg) & + ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1)); + if (*MonInfo) { if ((*MonInfo)->rawData[0x14] & 0x80) { - if (INREG(RADEON_LVDS_GEN_CNTL) & RADEON_LVDS_ON) MonType = MT_LCD; - else MonType = MT_DFP; + /* Note some laptops have a DVI output that uses internal TMDS, + * when its DVI is enabled by hotkey, LVDS panel is not used. + * In this case, the laptop is configured as DVI+VGA as a normal + * desktop card. + * Also for laptop, when X starts with lid closed (no DVI connection) + * both LDVS and TMDS are disable, we still need to treat it as a LVDS panel. + */ + if (port->TMDSType == TMDS_EXT) MonType = MT_DFP; + else { + if ((INREG(RADEON_FP_GEN_CNTL) & (1<<7)) || !info->IsMobility) + MonType = MT_DFP; + else + MonType = MT_LCD; + } } else MonType = MT_CRT; } else MonType = MT_NONE; @@ -885,6 +1055,7 @@ if(IsCrtDac) { unsigned long ulOrigVCLK_ECP_CNTL; unsigned long ulOrigDAC_CNTL; + unsigned long ulOrigDAC_MACRO_CNTL; unsigned long ulOrigDAC_EXT_CNTL; unsigned long ulOrigCRTC_EXT_CNTL; unsigned long ulData; @@ -919,6 +1090,15 @@ OUTREG(RADEON_DAC_EXT_CNTL, ulData); ulOrigDAC_CNTL = INREG(RADEON_DAC_CNTL); + + if (ulOrigDAC_CNTL & RADEON_DAC_PDWN) { + /* turn on power so testing can go through */ + ulOrigDAC_MACRO_CNTL = INREG(RADEON_DAC_MACRO_CNTL); + ulOrigDAC_MACRO_CNTL &= ~(RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | + RADEON_DAC_PDWN_B); + OUTREG(RADEON_DAC_MACRO_CNTL, ulOrigDAC_MACRO_CNTL); + } + ulData = ulOrigDAC_CNTL; ulData |= RADEON_DAC_CMP_EN; ulData &= ~(RADEON_DAC_RANGE_CNTL_MASK @@ -926,7 +1106,7 @@ ulData |= 0x2; OUTREG(RADEON_DAC_CNTL, ulData); - usleep(1000); + usleep(10000); ulData = INREG(RADEON_DAC_CNTL); bConnected = (RADEON_DAC_CMP_OUTPUT & ulData)?1:0; @@ -938,19 +1118,30 @@ OUTREG(RADEON_DAC_CNTL, ulOrigDAC_CNTL ); OUTREG(RADEON_DAC_EXT_CNTL, ulOrigDAC_EXT_CNTL ); OUTREG(RADEON_CRTC_EXT_CNTL, ulOrigCRTC_EXT_CNTL); + + if (!bConnected) { + /* Power DAC down if CRT is not connected */ + ulOrigDAC_MACRO_CNTL = INREG(RADEON_DAC_MACRO_CNTL); + ulOrigDAC_MACRO_CNTL |= (RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | + RADEON_DAC_PDWN_B); + OUTREG(RADEON_DAC_MACRO_CNTL, ulOrigDAC_MACRO_CNTL); + + ulData = INREG(RADEON_DAC_CNTL); + ulData |= RADEON_DAC_PDWN ; + OUTREG(RADEON_DAC_CNTL, ulData); + } } else { /* TV DAC */ - /* This doesn't seem to work reliably (maybe worse on some OEM cards), - for now we always return false. If one wants to connected a - non-DDC monitor on the DVI port when CRT port is also connected, - he will need to explicitly tell the driver in the config file - with Option MonitorLayout. - */ - bConnected = FALSE; + /* This doesn't seem to work reliably (maybe worse on some OEM cards), + for now we always return false. If one wants to connected a + non-DDC monitor on the DVI port when CRT port is also connected, + he will need to explicitly tell the driver in the config file + with Option MonitorLayout. + */ + bConnected = FALSE; #if 0 if (info->ChipFamily == CHIP_FAMILY_R200) { - unsigned long ulOrigGPIO_MONID; unsigned long ulOrigFP2_GEN_CNTL; unsigned long ulOrigDISP_OUTPUT_CNTL; @@ -1025,7 +1216,7 @@ OUTREG(RADEON_DISP_OUTPUT_CNTL, ulOrigDISP_OUTPUT_CNTL); OUTREG(RADEON_FP2_GEN_CNTL, ulOrigFP2_GEN_CNTL); OUTREG(RADEON_GPIO_MONID, ulOrigGPIO_MONID); - } else { + } else { unsigned long ulOrigPIXCLKSDATA; unsigned long ulOrigTV_MASTER_CNTL; unsigned long ulOrigTV_DAC_CNTL; @@ -1066,15 +1257,13 @@ | RADEON_RED_MX_FORCE_DAC_DATA | RADEON_GRN_MX_FORCE_DAC_DATA | RADEON_BLU_MX_FORCE_DAC_DATA); - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350)) + if (IS_R300_VARIANT) ulData |= 0x180 << RADEON_TV_FORCE_DAC_DATA_SHIFT; else ulData |= 0x1f5 << RADEON_TV_FORCE_DAC_DATA_SHIFT; OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, ulData); - usleep(1000); + usleep(10000); ulData = INREG(RADEON_TV_DAC_CNTL); bConnected = (ulData & RADEON_TV_DAC_CMPOUT)?1:0; @@ -1094,774 +1283,865 @@ return(bConnected ? MT_CRT : MT_NONE); } -static void RADEONQueryConnectedDisplays(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) +static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) { - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONPLLPtr pll = &info->pll; unsigned char *RADEONMMIO = info->MMIO; - const char *s; - Bool ignore_edid = FALSE, ddc_crt2_used = FALSE; - -#define RADEON_BIOS8(v) (info->VBIOS[v]) -#define RADEON_BIOS16(v) (info->VBIOS[v] | \ - (info->VBIOS[(v) + 1] << 8)) -#define RADEON_BIOS32(v) (info->VBIOS[v] | \ - (info->VBIOS[(v) + 1] << 8) | \ - (info->VBIOS[(v) + 2] << 16) | \ - (info->VBIOS[(v) + 3] << 24)) - - pRADEONEnt->MonType1 = MT_NONE; - pRADEONEnt->MonType2 = MT_NONE; - pRADEONEnt->MonInfo1 = NULL; - pRADEONEnt->MonInfo2 = NULL; - pRADEONEnt->ReversedDAC = FALSE; - pRADEONEnt->ReversedTMDS = FALSE; - - /* IgnoreEDID option is different from NoDDC options used by DDC module - * When IgnoreEDID is used, monitor detection will still use DDC - * detection, but all EDID data will not be used in mode validation. - */ - if (xf86GetOptValBool(info->Options, OPTION_IGNORE_EDID, &ignore_edid)) { - if (ignore_edid) - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, - "IgnoreEDID is specified, EDID data will be ignored\n"); + unsigned char ppll_div_sel; + unsigned mpll_fb_div, spll_fb_div, M; + unsigned xclk, tmp, ref_div; + int hTotal, vTotal, num, denom, m, n; + float hz, prev_xtal, vclk, xtal, mpll, spll; + long start_secs, start_usecs, stop_secs, stop_usecs, total_usecs; + long to1_secs, to1_usecs, to2_secs, to2_usecs; + unsigned int f1, f2, f3; + int tries = 0; + + prev_xtal = 0; + again: + xtal = 0; + if (++tries > 10) + goto failed; + + xf86getsecs(&to1_secs, &to1_usecs); + f1 = INREG(RADEON_CRTC_CRNT_FRAME); + for (;;) { + f2 = INREG(RADEON_CRTC_CRNT_FRAME); + if (f1 != f2) + break; + xf86getsecs(&to2_secs, &to2_usecs); + if ((to2_secs - to1_secs) > 1) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n"); + goto failed; + } } + xf86getsecs(&start_secs, &start_usecs); + for(;;) { + f3 = INREG(RADEON_CRTC_CRNT_FRAME); + if (f3 != f2) + break; + xf86getsecs(&to2_secs, &to2_usecs); + if ((to2_secs - start_secs) > 1) + goto failed; + } + xf86getsecs(&stop_secs, &stop_usecs); - /* - * MonitorLayout option takes a string for two monitors connected in following format: - * Option "MonitorLayout" "primary-port-display, secondary-port-display" - * primary and secondary port displays can have one of following: - * NONE, CRT, LVDS, TMDS - * With this option, driver will bring up monitors as specified, - * not using auto-detection routines to probe monitors. - */ - - /* current monitor mapping scheme: - * Two displays connected: - * Primary Port: - * CRTC1 -> FP/TMDS -> DVI port -> TMDS panel --> Primary or - * CRTC1 -> FP/LVDS -> Int. LCD -> LVDS panel --> Primary or - * CRTC1 -> TV DAC -> DVI port -> CRT monitor --> Primary - * - * Secondary Port - * CRTC2 -> CRT DAC -> VGA port -> CRT monitor --> Secondary or - * CRTC2 -> FP2/Ext. -> DVI port -> TMDS panel --> Secondary - * - * Only DVI (or Int. LDC) conneced: - * CRTC1 -> FP/TMDS -> DVI port -> TMDS panel --> Primary or - * CRTC1 -> FP/LVDS -> Int. LCD -> LVDS panel --> Primary or - * CRTC1 -> TV DAC -> DVI port -> CRT monitor --> Primary - * - * Only VGA (can be DVI on some dual-DVI boards) connected: - * CRTC1 -> CRT DAC -> VGA port -> CRT monitor --> Primary or - * CRTC1 -> FP2/Ext. -> DVI port -> TMDS panel --> Primary (not supported) - * - * Note, this is different from Windows scheme where - * if a digital panel is connected to DVI port, DVI will be the 1st port - * otherwise, VGA port will be treated as 1st port - * - * Here we always treat DVI port as primary if both ports are connected. - * When only one port is connected, it will be treated as - * primary regardless which port or what type of display is involved. - */ + if ((stop_secs - start_secs) != 0) + goto again; + total_usecs = abs(stop_usecs - start_usecs); + if (total_usecs == 0) + goto again; + hz = 1000000.0/(float)total_usecs; - if ((s = xf86GetOptValString(info->Options, OPTION_MONITOR_LAYOUT))) { - char s1[5], s2[5]; - int i = 0, second = 0; + hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x3ff) + 1) * 8; + vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0xfff) + 1); + vclk = (float)(hTotal * (float)(vTotal * hz)); - /* When using user specified monitor types, we will not do DDC detection - * - */ - do { - switch(*s) - { - case ',': - s1[i] = '\0'; - i = 0; - second = 1; - break; - case ' ': - case '\t': - case '\n': - case '\r': - break; - default: - if (second) - s2[i] = *s; - else - s1[i] = *s; - i++; - if (i == 4) break; - } - } while(*s++); - s2[i] = '\0'; + switch((INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x30000) >> 16) { + case 0: + default: + num = 1; + denom = 1; + break; + case 1: + n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 16) & 0xff); + m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); + num = 2*n; + denom = 2*m; + break; + case 2: + n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 8) & 0xff); + m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); + num = 2*n; + denom = 2*m; + break; + } - if (strcmp(s1, "NONE") == 0) - pRADEONEnt->MonType1 = MT_NONE; - else if (strcmp(s1, "CRT") == 0) - pRADEONEnt->MonType1 = MT_CRT; - else if (strcmp(s1, "TMDS") == 0) - pRADEONEnt->MonType1 = MT_DFP; - else if (strcmp(s1, "LVDS") == 0) - pRADEONEnt->MonType1 = MT_LCD; - else - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Invalid Monitor type specified for 1st port \n"); - if (strcmp(s2, "NONE") == 0) - pRADEONEnt->MonType2 = MT_NONE; - else if (strcmp(s2, "CRT") == 0) - pRADEONEnt->MonType2 = MT_CRT; - else if (strcmp(s2, "TMDS") == 0) - pRADEONEnt->MonType2 = MT_DFP; - else if (strcmp(s2, "LVDS") == 0) - pRADEONEnt->MonType2 = MT_LCD; - else - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Invalid Monitor type specified for 2nd port \n"); + ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; + RADEONPllErrataAfterIndex(info); - if (!ignore_edid) { - if (pRADEONEnt->MonType1) /* assuming the first port using DDC_DVI */ - if(!RADEONDisplayDDCConnected(pScrn, DDC_DVI, &pRADEONEnt->MonInfo1)) { - RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo1); - ddc_crt2_used = TRUE; - } - if (pRADEONEnt->MonType2) { /* assuming the second port using DDC_VGA/DDC_CRT2 */ - if(!RADEONDisplayDDCConnected(pScrn, DDC_VGA, &pRADEONEnt->MonInfo2)) - if (!ddc_crt2_used) - RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo2); - } - } + n = (INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) & 0x7ff); + m = (INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff); - if (!pRADEONEnt->MonType1) { - if (pRADEONEnt->MonType2) { - pRADEONEnt->MonType1 = pRADEONEnt->MonType2; - pRADEONEnt->MonInfo1 = pRADEONEnt->MonInfo2; - } else { - pRADEONEnt->MonType1 = MT_CRT; - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "No valid monitor specified, force to CRT on 1st port\n"); - } - pRADEONEnt->MonType2 = MT_NONE; - pRADEONEnt->MonInfo2 = NULL; - } - } else { - /* Auto detection */ - int i; - CARD32 tmp; - - /* Old single head radeon cards */ - if(!info->HasCRTC2) { - if((pRADEONEnt->MonType1 = RADEONDisplayDDCConnected(pScrn, DDC_DVI, &pRADEONEnt->MonInfo1))); - else if((pRADEONEnt->MonType1 = RADEONDisplayDDCConnected(pScrn, DDC_VGA, &pRADEONEnt->MonInfo1))); - else if((pRADEONEnt->MonType1 = RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo1))); - else if (pInt10) { - pointer pVBEModule; - if ((pVBEModule = xf86LoadVBEModule(pScrn))) { - vbeInfoPtr pVbe; - pVbe = VBEInit(pInt10, info->pEnt->index); - if (pVbe) { - for (i = 0; i < 5; i++) { - pRADEONEnt->MonInfo1 = - vbeDoEDID(pVbe, info->pDDCModule); - } - if (pRADEONEnt->MonInfo1->rawData[0x14] & 0x80) - pRADEONEnt->MonType1 = MT_DFP; - else pRADEONEnt->MonType1 = MT_CRT; - vbeFree(pVbe); - } - xf86UnloadSubModule(pVBEModule); - } - } else - pRADEONEnt->MonType1 = MT_CRT; + num *= n; + denom *= m; - pRADEONEnt->HasSecondary = FALSE; - if (!ignore_edid) { - if (pRADEONEnt->MonInfo1) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Monitor1 EDID data ---------------------------\n"); - xf86PrintEDID( pRADEONEnt->MonInfo1 ); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "End of Monitor1 EDID data --------------------\n"); - } - } - return; - } + switch ((INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { + case 1: + denom *= 2; + break; + case 2: + denom *= 4; + break; + case 3: + denom *= 8; + break; + case 4: + denom *= 3; + break; + case 6: + denom *= 6; + break; + case 7: + denom *= 12; + break; + } - /* Normally the port uses DDC_DVI connected with TVDAC, - * But this is not true for OEM cards which have TVDAC and CRT DAC reversed. - * If that's the case, we need also reverse the port arrangement. - * BIOS settings are supposed report this correctly, work fine for all cards tested. - * But there may be some exceptions, in that case, user can reverse their monitor - * definition in config file to correct the problem. - */ - if (info->VBIOS && (tmp = RADEON_BIOS16(info->FPBIOSstart + 0x50))) { - for (i = 1; i < 4; i++) { - unsigned int tmp0; - if (!RADEON_BIOS8(tmp + i*2) && i > 1) break; - tmp0 = RADEON_BIOS16(tmp + i*2); - if ((!(tmp0 & 0x01)) && (((tmp0 >> 8) & 0xf) == DDC_DVI)) { - pRADEONEnt->ReversedDAC = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Reversed DACs detected\n"); - } - if ((((tmp0 >> 8) & 0x0f) == DDC_DVI ) && ((tmp0 >> 4) & 0x1)) { - pRADEONEnt->ReversedTMDS = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Reversed TMDS detected\n"); - } - } - } + xtal = (int)(vclk *(float)denom/(float)num); - /* Primary Head (DVI or Laptop Int. panel)*/ - /* A ddc capable display connected on DVI port */ - if((pRADEONEnt->MonType1 = RADEONDisplayDDCConnected(pScrn, DDC_DVI, &pRADEONEnt->MonInfo1))); - else if((pRADEONEnt->MonType1 = - RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo1))) { - ddc_crt2_used = TRUE; - } else if ((info->IsMobility) && - (info->VBIOS && (INREG(RADEON_BIOS_4_SCRATCH) & 4))) { - /* non-DDC laptop panel connected on primary */ - pRADEONEnt->MonType1 = MT_LCD; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Non-DDC laptop panel detected\n"); - } else { - /* CRT on DVI, TODO: not reliable, make it always return false for now*/ - pRADEONEnt->MonType1 = RADEONCrtIsPhysicallyConnected(pScrn, pRADEONEnt->ReversedDAC); - } + if ((xtal > 26900000) && (xtal < 27100000)) + xtal = 2700; + else if ((xtal > 14200000) && (xtal < 14400000)) + xtal = 1432; + else if ((xtal > 29400000) && (xtal < 29600000)) + xtal = 2950; + else + goto again; + failed: + if (xtal == 0) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Failed to probe xtal value ! " + "Using default 27Mhz\n"); + xtal = 2700; + } else { + if (prev_xtal == 0) { + prev_xtal = xtal; + tries = 0; + goto again; + } else if (prev_xtal != xtal) { + prev_xtal = 0; + goto again; + } + } - /* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/ - if((pRADEONEnt->MonType2 = - RADEONDisplayDDCConnected(pScrn, DDC_VGA, &pRADEONEnt->MonInfo2))); - else if(!ddc_crt2_used) - pRADEONEnt->MonType2 = - RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->MonInfo2); - if (!pRADEONEnt->MonType2) - pRADEONEnt->MonType2 = RADEONCrtIsPhysicallyConnected(pScrn, !pRADEONEnt->ReversedDAC); - - if(pRADEONEnt->ReversedTMDS) { - /* always keep internal TMDS as primary head */ - if (pRADEONEnt->MonType1 == MT_DFP || - pRADEONEnt->MonType2 == MT_DFP) { - int tmp1 = pRADEONEnt->MonType1; - xf86MonPtr MonInfo = pRADEONEnt->MonInfo1; - pRADEONEnt->MonInfo1 = pRADEONEnt->MonInfo2; - pRADEONEnt->MonInfo2 = MonInfo; - pRADEONEnt->MonType1 = pRADEONEnt->MonType2; - pRADEONEnt->MonType2 = tmp1; - if ((pRADEONEnt->MonType1 == MT_CRT) || - (pRADEONEnt->MonType2 == MT_CRT)) { - pRADEONEnt->ReversedDAC ^= 1; - } - } - } + tmp = INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV); + ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff; - /* no display detected on DVI port*/ - if (pRADEONEnt->MonType1 == MT_NONE) { - if (pRADEONEnt->MonType2 != MT_NONE) { - /* Only one detected on VGA, let it to be primary */ - pRADEONEnt->MonType1 = pRADEONEnt->MonType2; - pRADEONEnt->MonInfo1 = pRADEONEnt->MonInfo2; - pRADEONEnt->MonType2 = MT_NONE; - pRADEONEnt->MonInfo2 = NULL; - } else { - /* Non detected, Default to a CRT connected */ - pRADEONEnt->MonType1 = MT_CRT; - } - } - } + /* Some sanity check based on the BIOS code .... */ + if (ref_div < 2) { + CARD32 tmp2; + tmp2 = INPLL(pScrn, RADEON_PPLL_REF_DIV); + if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS300)) + ref_div = (tmp2 & R300_PPLL_REF_DIV_ACC_MASK) >> + R300_PPLL_REF_DIV_ACC_SHIFT; + else + ref_div = tmp2 & RADEON_PPLL_REF_DIV_MASK; + if (ref_div < 2) + ref_div = 12; + } + + /* Calculate "base" xclk straight from MPLL, though that isn't + * really useful (hopefully). This isn't called XCLK anymore on + * radeon's... + */ + mpll_fb_div = (tmp & 0xff00) >> 8; + spll_fb_div = (tmp & 0xff0000) >> 16; + M = (tmp & 0xff); + xclk = RADEONDiv((2 * mpll_fb_div * xtal), (M)); - if(s) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Displays Configured by MonitorLayout: \n\tMonitor1--Type %d, Monitor2--Type %d\n\n", - pRADEONEnt->MonType1, pRADEONEnt->MonType2); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Displays Detected: Monitor1--Type %d, Monitor2--Type %d\n\n", - pRADEONEnt->MonType1, pRADEONEnt->MonType2); - } + /* + * Calculate MCLK based on MCLK-A + */ + mpll = (2.0 * (float)mpll_fb_div * (xtal / 100.0)) / (float)M; + spll = (2.0 * (float)spll_fb_div * (xtal / 100.0)) / (float)M; - if(ignore_edid) { - pRADEONEnt->MonInfo1 = NULL; - pRADEONEnt->MonInfo2 = NULL; + tmp = INPLL(pScrn, RADEON_MCLK_CNTL) & 0x7; + switch(tmp) { + case 1: info->mclk = mpll; break; + case 2: info->mclk = mpll / 2.0; break; + case 3: info->mclk = mpll / 4.0; break; + case 4: info->mclk = mpll / 8.0; break; + case 7: info->mclk = spll; break; + default: + info->mclk = 200.00; + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported MCLKA source" + " setting %d, can't probe MCLK value !\n", tmp); } - if (!ignore_edid) { - if (pRADEONEnt->MonInfo1) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Monitor1 EDID data ---------------------------\n"); - xf86PrintEDID( pRADEONEnt->MonInfo1 ); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "End of Monitor1 EDID data --------------------\n"); - } - if (pRADEONEnt->MonInfo2) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Monitor2 EDID data ---------------------------\n"); - xf86PrintEDID( pRADEONEnt->MonInfo2 ); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "End of Monitor2 EDID data --------------------\n"); - } + /* + * Calculate SCLK + */ + tmp = INPLL(pScrn, RADEON_SCLK_CNTL) & 0x7; + switch(tmp) { + case 1: info->sclk = spll; break; + case 2: info->sclk = spll / 2.0; break; + case 3: info->sclk = spll / 4.0; break; + case 4: info->sclk = spll / 8.0; break; + case 7: info->sclk = mpll; + default: + info->sclk = 200.00; + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported SCLK source" + " setting %d, can't probe SCLK value !\n", tmp); } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "\n"); + /* we're done, hopefully these are sane values */ + pll->reference_div = ref_div; + pll->xclk = xclk; + pll->reference_freq = xtal; - info->OverlayOnCRTC2 = FALSE; - if (xf86ReturnOptValBool(info->Options, OPTION_CRTC2_OVERLAY, FALSE)) { - info->OverlayOnCRTC2 = TRUE; - } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probed PLL values: xtal: %f Mhz, " + "sclk: %f Mhz, mclk: %f Mhz\n", xtal/100.0, info->sclk, info->mclk); - if (pRADEONEnt->MonType2 == MT_NONE) - pRADEONEnt->HasSecondary = FALSE; + return TRUE; } - -/* Read the Video BIOS block and the FP registers (if applicable). */ -static Bool RADEONGetBIOSParameters(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) +static void RADEONGetPanelInfoFromReg (ScrnInfoPtr pScrn) { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned long tmp, i; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + CARD32 fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH); + CARD32 fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH); - if (!(info->VBIOS = xalloc(RADEON_VBIOS_SIZE))) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Cannot allocate space for hold Video BIOS!\n"); - return FALSE; + info->PanelPwrDly = 200; + if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) { + info->PanelYRes = (fp_vert_stretch>>12) + 1; + } else { + info->PanelYRes = (INREG(RADEON_CRTC_V_TOTAL_DISP)>>16) + 1; } - - if (pInt10) { - info->BIOSAddr = pInt10->BIOSseg << 4; - (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr), - RADEON_VBIOS_SIZE); + if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) { + info->PanelXRes = ((fp_horz_stretch>>16) + 1) * 8; } else { - xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); - if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Video BIOS not detected in PCI space!\n"); - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Attempting to read Video BIOS from " - "legacy ISA space!\n"); - info->BIOSAddr = 0x000c0000; - xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, - RADEON_VBIOS_SIZE, info->VBIOS); - } + info->PanelXRes = ((INREG(RADEON_CRTC_H_TOTAL_DISP)>>16) + 1) * 8; } - if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { - xfree(info->VBIOS); - info->FPBIOSstart = 0; - info->VBIOS = NULL; - info->BIOSAddr = 0x00000000; - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Video BIOS not found!\n"); - } else - info->FPBIOSstart = RADEON_BIOS16(0x48); - info->OverlayOnCRTC2 = FALSE; - - if (!info->IsSecondary) - RADEONQueryConnectedDisplays(pScrn, pInt10); + if ((info->PanelXRes < 640) || (info->PanelYRes < 480)) { + info->PanelXRes = 640; + info->PanelYRes = 480; + } - { - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + if (xf86ReturnOptValBool(info->Options, OPTION_LVDS_PROBE_PLL, TRUE)) { + CARD32 ppll_div_sel, ppll_val; - info->Clone = FALSE; - info->CloneType = MT_NONE; + ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; + RADEONPllErrataAfterIndex(info); + ppll_val = INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel); + if ((ppll_val & 0x000707ff) == 0x1bb) + goto noprobe; + info->FeedbackDivider = ppll_val & 0x7ff; + info->PostDivider = (ppll_val >> 16) & 0x7; + info->RefDivider = info->pll.reference_div; + info->UseBiosDividers = TRUE; - if(info->HasCRTC2) { - if(info->IsSecondary) { - info->DisplayType = (RADEONMonitorType)pRADEONEnt->MonType2; - if(info->DisplayType == MT_NONE) return FALSE; - } else { - info->DisplayType = (RADEONMonitorType)pRADEONEnt->MonType1; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Existing panel PLL dividers will be used.\n"); + } + noprobe: - if(!pRADEONEnt->HasSecondary) { - info->CloneType = (RADEONMonitorType)pRADEONEnt->MonType2; - if (info->CloneType != MT_NONE) - info->Clone = TRUE; - } - } - } else { - info->DisplayType = (RADEONMonitorType)pRADEONEnt->MonType1; - } + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Panel size %dx%d is derived, this may not be correct.\n" + "If not, use PanelSize option to overwrite this setting\n", + info->PanelXRes, info->PanelYRes); +} - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s Display == Type %d\n", - (info->IsSecondary ? "Secondary" : "Primary"), - info->DisplayType); - - if (info->Clone) - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Clone Display == Type %d\n", - info->CloneType); - - info->HBlank = 0; - info->HOverPlus = 0; - info->HSyncWidth = 0; - info->VBlank = 0; - info->VOverPlus = 0; - info->VSyncWidth = 0; - info->DotClock = 0; - info->UseBiosDividers = FALSE; - - if (info->DisplayType == MT_LCD && info->VBIOS && - !(xf86GetOptValString(info->Options, OPTION_PANEL_SIZE))) { - tmp = RADEON_BIOS16(info->FPBIOSstart + 0x40); - if (!tmp) { - info->PanelPwrDly = 200; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "No Panel Info Table found in BIOS!\n"); - } else { - char stmp[30]; - int tmp0; - - for (i = 0; i < 24; i++) - stmp[i] = RADEON_BIOS8(tmp+i+1); - stmp[24] = 0; +static Bool RADEONGetLVDSInfo (ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Panel ID string: %s\n", stmp); + if (!RADEONGetLVDSInfoFromBIOS(pScrn)) + RADEONGetPanelInfoFromReg(pScrn); - info->PanelXRes = RADEON_BIOS16(tmp+25); - info->PanelYRes = RADEON_BIOS16(tmp+27); - xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n", - info->PanelXRes, info->PanelYRes); + /* The panel size we collected from BIOS may not be the + * maximum size supported by the panel. If not, we update + * it now. These will be used if no matching mode can be + * found from EDID data. + */ + RADEONUpdatePanelSize(pScrn); - info->PanelPwrDly = RADEON_BIOS16(tmp+44); - if (info->PanelPwrDly > 2000 || info->PanelPwrDly < 0) - info->PanelPwrDly = 2000; + /* No timing information for the native mode, + * use whatever specified in the Modeline. + * If no Modeline specified, we'll just pick + * the VESA mode at 60Hz refresh rate which + * is likely to be the best for a flat panel. + */ + if (info->DotClock == 0) { + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + DisplayModePtr tmp_mode = NULL; + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "No valid timing info from BIOS.\n"); + tmp_mode = pScrn->monitor->Modes; + while(tmp_mode) { + if ((tmp_mode->HDisplay == info->PanelXRes) && + (tmp_mode->VDisplay == info->PanelYRes)) { - /* some panels only work well with certain divider combinations. - */ - info->RefDivider = RADEON_BIOS16(tmp+46); - info->PostDivider = RADEON_BIOS8(tmp+48); - info->FeedbackDivider = RADEON_BIOS16(tmp+49); - if ((info->RefDivider != 0) && - (info->FeedbackDivider > 3)) { - info->UseBiosDividers = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "BIOS provided dividers will be used.\n"); + float refresh = + (float)tmp_mode->Clock * 1000.0 / tmp_mode->HTotal / tmp_mode->VTotal; + if ((abs(60.0 - refresh) < 1.0) || + (tmp_mode->type == 0)) { + info->HBlank = tmp_mode->HTotal - tmp_mode->HDisplay; + info->HOverPlus = tmp_mode->HSyncStart - tmp_mode->HDisplay; + info->HSyncWidth = tmp_mode->HSyncEnd - tmp_mode->HSyncStart; + info->VBlank = tmp_mode->VTotal - tmp_mode->VDisplay; + info->VOverPlus = tmp_mode->VSyncStart - tmp_mode->VDisplay; + info->VSyncWidth = tmp_mode->VSyncEnd - tmp_mode->VSyncStart; + info->DotClock = tmp_mode->Clock; + info->Flags = 0; + break; } + } + tmp_mode = tmp_mode->next; + } + if ((info->DotClock == 0) && !pRADEONEnt->PortInfo[0].MonInfo) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Panel size is not correctly detected.\n" + "Please try to use PanelSize option for correct settings.\n"); + return FALSE; + } + } - /* We don't use a while loop here just in case we have a corrupted BIOS image. - The max number of table entries is 23 at present, but may grow in future. - To ensure it works with future revisions we loop it to 32. - */ - for (i = 0; i < 32; i++) { - tmp0 = RADEON_BIOS16(tmp+64+i*2); - if (tmp0 == 0) break; - if ((RADEON_BIOS16(tmp0) == info->PanelXRes) && - (RADEON_BIOS16(tmp0+2) == info->PanelYRes)) { - info->HBlank = (RADEON_BIOS16(tmp0+17) - - RADEON_BIOS16(tmp0+19)) * 8; - info->HOverPlus = (RADEON_BIOS16(tmp0+21) - - RADEON_BIOS16(tmp0+19) - 1) * 8; - info->HSyncWidth = RADEON_BIOS8(tmp0+23) * 8; - info->VBlank = (RADEON_BIOS16(tmp0+24) - - RADEON_BIOS16(tmp0+26)); - info->VOverPlus = ((RADEON_BIOS16(tmp0+28) & 0x7ff) - - RADEON_BIOS16(tmp0+26)); - info->VSyncWidth = ((RADEON_BIOS16(tmp0+28) & 0xf800) >> 11); - info->DotClock = RADEON_BIOS16(tmp0+9) * 10; - info->Flags = 0; - } - } + return TRUE; +} - if (info->DotClock == 0) { - DisplayModePtr tmp_mode = NULL; - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "No valid timing info from BIOS.\n"); - /* No timing information for the native mode, - use whatever specified in the Modeline. - If no Modeline specified, we'll just pick - the VESA mode at 60Hz refresh rate which - is likely to be the best for a flat panel. - */ - tmp_mode = pScrn->monitor->Modes; - while(tmp_mode) { - if ((tmp_mode->HDisplay == info->PanelXRes) && - (tmp_mode->VDisplay == info->PanelYRes)) { - - float refresh = - (float)tmp_mode->Clock * 1000.0 / tmp_mode->HTotal / tmp_mode->VTotal; - if ((abs(60.0 - refresh) < 1.0) || - (tmp_mode->type == 0)) { - info->HBlank = tmp_mode->HTotal - tmp_mode->HDisplay; - info->HOverPlus = tmp_mode->HSyncStart - tmp_mode->HDisplay; - info->HSyncWidth = tmp_mode->HSyncEnd - tmp_mode->HSyncStart; - info->VBlank = tmp_mode->VTotal - tmp_mode->VDisplay; - info->VOverPlus = tmp_mode->VSyncStart - tmp_mode->VDisplay; - info->VSyncWidth = tmp_mode->VSyncEnd - tmp_mode->VSyncStart; - info->DotClock = tmp_mode->Clock; - info->Flags = 0; - break; - } - tmp_mode = tmp_mode->next; - } - } - if ((info->DotClock == 0) && !pRADEONEnt->MonInfo1) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Panel size is not correctly detected.\n" - "Please try to use PanelSize option for correct settings.\n"); - return FALSE; - } - } - } +static void RADEONGetTMDSInfo(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + int i; + + for (i=0; i<4; i++) { + info->tmds_pll[i].value = 0; + info->tmds_pll[i].freq = 0; + } + + if (RADEONGetTMDSInfoFromBIOS(pScrn)) return; + + for (i=0; i<4; i++) { + info->tmds_pll[i].value = default_tmds_pll[info->ChipFamily][i].value; + info->tmds_pll[i].freq = default_tmds_pll[info->ChipFamily][i].freq; + } +} + +static void RADEONGetPanelInfo (ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + char* s; + + if((s = xf86GetOptValString(info->Options, OPTION_PANEL_SIZE))) { + info->PanelPwrDly = 200; + if (sscanf (s, "%dx%d", &info->PanelXRes, &info->PanelYRes) != 2) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Invalid PanelSize option: %s\n", s); + RADEONGetPanelInfoFromReg(pScrn); + } + } else { + + if(info->DisplayType == MT_LCD) { + RADEONGetLVDSInfo(pScrn); + } else if ((info->DisplayType == MT_DFP) || (info->MergeType == MT_DFP)) { + RADEONGetTMDSInfo(pScrn); + if (!pScrn->monitor->DDC) + RADEONGetHardCodedEDIDFromBIOS(pScrn); + else if (!info->IsSecondary) + RADEONUpdatePanelSize(pScrn); } } +} + +static void RADEONGetClockInfo(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONPLLPtr pll = &info->pll; + double min_dotclock; + + if (RADEONGetClockInfoFromBIOS(pScrn)) { + if (pll->reference_div < 2) { + /* retrive it from register setting for fitting into current PLL algorithm. + We'll probably need a new routine to calculate the best ref_div from BIOS + provided min_input_pll and max_input_pll + */ + CARD32 tmp; + tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); + if (IS_R300_VARIANT || + (info->ChipFamily == CHIP_FAMILY_RS300)) { + pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; + } else { + pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; + } + + if (pll->reference_div < 2) pll->reference_div = 12; + } - if (info->VBIOS) { - tmp = RADEON_BIOS16(info->FPBIOSstart + 0x30); - info->sclk = RADEON_BIOS16(tmp + 8) / 100.0; - info->mclk = RADEON_BIOS16(tmp + 10) / 100.0; } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No valid info for SCLK/MCLK for display bandwidth calculation.\n"); + xf86DrvMsg (pScrn->scrnIndex, X_WARNING, + "Video BIOS not detected, using default clock settings!\n"); + + /* Default min/max PLL values */ + if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) { + pll->min_pll_freq = 20000; + pll->max_pll_freq = 50000; + } else { + pll->min_pll_freq = 12500; + pll->max_pll_freq = 35000; + } + + if (RADEONProbePLLParameters(pScrn)) + return; + + if (info->IsIGP) + pll->reference_freq = 1432; + else + pll->reference_freq = 2700; + + pll->reference_div = 12; + pll->xclk = 10300; + info->sclk = 200.00; info->mclk = 200.00; } - return TRUE; + if (info->ChipFamily == CHIP_FAMILY_RV100 && !info->HasCRTC2) { + /* Avoid RN50 corruption due to memory bandwidth starvation. + * 18 is an empirical value based on the databook and Windows driver. + * + * Empirical value changed to 24 to raise pixel clock limit and + * allow higher resolution modes on capable monitors + */ + pll->max_pll_freq = min(pll->max_pll_freq, + 24 * info->mclk * 100 / pScrn->bitsPerPixel * + info->RamWidth / 16); + } + + xf86DrvMsg (pScrn->scrnIndex, X_INFO, + "PLL parameters: rf=%d rd=%d min=%d max=%d; xclk=%d\n", + pll->reference_freq, + pll->reference_div, + pll->min_pll_freq, pll->max_pll_freq, pll->xclk); + + /* (Some?) Radeon BIOSes seem too lie about their minimum dot + * clocks. Allow users to override the detected minimum dot clock + * value (e.g., and allow it to be suitable for TV sets). + */ + if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK, + OPTUNITS_MHZ, &min_dotclock)) { + if (min_dotclock < 12 || min_dotclock*100 >= pll->max_pll_freq) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Illegal minimum dotclock specified %.2f MHz " + "(option ignored)\n", + min_dotclock); + } else { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Forced minimum dotclock to %.2f MHz " + "(instead of detected %.2f MHz)\n", + min_dotclock, ((double)pll->min_pll_freq/1000)); + pll->min_pll_freq = min_dotclock * 1000; + } + } } -static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) +static Bool RADEONQueryConnectedMonitors(ScrnInfoPtr pScrn) { - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPLLPtr pll = &info->pll; + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; - unsigned char ppll_div_sel; - unsigned Nx, M; - unsigned xclk, tmp, ref_div; - int hTotal, vTotal, num, denom, m, n; - float hz, vclk, xtal; - long start_secs, start_usecs, stop_secs, stop_usecs, total_usecs; - int i; + const char *s; + Bool ignore_edid = FALSE; + int i = 0, second = 0, max_mt; - for(i=0; i<1000000; i++) - if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) - break; + const char *MonTypeName[7] = + { + "AUTO", + "NONE", + "CRT", + "LVDS", + "TMDS", + "CTV", + "STV" + }; - xf86getsecs(&start_secs, &start_usecs); + const RADEONMonitorType MonTypeID[7] = + { + MT_UNKNOWN, /* this is just a dummy value for AUTO DETECTION */ + MT_NONE, /* NONE -> NONE */ + MT_CRT, /* CRT -> CRT */ + MT_LCD, /* Laptop LCDs are driven via LVDS port */ + MT_DFP, /* DFPs are driven via TMDS */ + MT_CTV, /* CTV -> CTV */ + MT_STV, /* STV -> STV */ + }; - for(i=0; i<1000000; i++) - if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0) - break; + const char *TMDSTypeName[3] = + { + "NONE", + "Internal", + "External" + }; - for(i=0; i<1000000; i++) - if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) - break; + const char *DDCTypeName[5] = + { + "NONE", + "MONID", + "DVI_DDC", + "VGA_DDC", + "CRT2_DDC" + }; - xf86getsecs(&stop_secs, &stop_usecs); + const char *DACTypeName[3] = + { + "Unknown", + "Primary", + "TVDAC/ExtDAC", + }; - total_usecs = abs(stop_usecs - start_usecs); - hz = 1000000/total_usecs; + const char *ConnectorTypeName[8] = + { + "None", + "Proprietary", + "VGA", + "DVI-I", + "DVI-D", + "CTV", + "STV", + "Unsupported" + }; - hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8; - vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0x3ff) + 1); - vclk = (float)(hTotal * (float)(vTotal * hz)); + const char *ConnectorTypeNameATOM[10] = + { + "None", + "VGA", + "DVI-I", + "DVI-D", + "DVI-A", + "STV", + "CTV", + "LVDS", + "Digital", + "Unsupported" + }; - switch((INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x30000) >> 16) { - case 0: - default: - num = 1; - denom = 1; - break; - case 1: - n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 16) & 0xff); - m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); - num = 2*n; - denom = 2*m; - break; - case 2: - n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 8) & 0xff); - m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); - num = 2*n; - denom = 2*m; - break; - } + max_mt = 5; - OUTREG(RADEON_CLOCK_CNTL_INDEX, 1); - ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_DATA + 1) & 0x3; + if(info->IsSecondary) { + info->DisplayType = (RADEONMonitorType)pRADEONEnt->MonType2; + if(info->DisplayType == MT_NONE) return FALSE; + return TRUE; + } - n = (INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) & 0x7ff); - m = (INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff); - num *= n; - denom *= m; + /* We first get the information about all connectors from BIOS. + * This is how the card is phyiscally wired up. + * The information should be correct even on a OEM card. + * If not, we may have problem -- need to use MonitorLayout option. + */ + for (i = 0; i < 2; i++) { + pRADEONEnt->PortInfo[i].MonType = MT_UNKNOWN; + pRADEONEnt->PortInfo[i].MonInfo = NULL; + pRADEONEnt->PortInfo[i].DDCType = DDC_NONE_DETECTED; + pRADEONEnt->PortInfo[i].DACType = DAC_UNKNOWN; + pRADEONEnt->PortInfo[i].TMDSType = TMDS_UNKNOWN; + pRADEONEnt->PortInfo[i].ConnectorType = CONNECTOR_NONE; + } + + if (!RADEONGetConnectorInfoFromBIOS(pScrn)) { + /* Below is the most common setting, but may not be true */ + pRADEONEnt->PortInfo[0].MonType = MT_UNKNOWN; + pRADEONEnt->PortInfo[0].MonInfo = NULL; + pRADEONEnt->PortInfo[0].DDCType = DDC_DVI; + pRADEONEnt->PortInfo[0].DACType = DAC_TVDAC; + pRADEONEnt->PortInfo[0].TMDSType = TMDS_INT; + pRADEONEnt->PortInfo[0].ConnectorType = CONNECTOR_DVI_D; + + pRADEONEnt->PortInfo[1].MonType = MT_UNKNOWN; + pRADEONEnt->PortInfo[1].MonInfo = NULL; + pRADEONEnt->PortInfo[1].DDCType = DDC_VGA; + pRADEONEnt->PortInfo[1].DACType = DAC_PRIMARY; + pRADEONEnt->PortInfo[1].TMDSType = TMDS_EXT; + pRADEONEnt->PortInfo[1].ConnectorType = CONNECTOR_CRT; - switch ((INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { - case 1: - denom *= 2; - break; - case 2: - denom *= 4; - break; - case 3: - denom *= 8; - break; - case 4: - denom *= 3; - break; - case 6: - denom *= 6; - break; - case 7: - denom *= 12; - break; + /* Some cards have the DDC lines swapped and we have no way to + * detect it yet (Mac cards) + */ + if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) { + pRADEONEnt->PortInfo[0].DDCType = DDC_VGA; + pRADEONEnt->PortInfo[1].DDCType = DDC_DVI; + } } - xtal = (int)(vclk *(float)denom/(float)num); + /* always make TMDS_INT port first*/ + if (pRADEONEnt->PortInfo[1].TMDSType == TMDS_INT) { + RADEONConnector connector; + connector = pRADEONEnt->PortInfo[0]; + pRADEONEnt->PortInfo[0] = pRADEONEnt->PortInfo[1]; + pRADEONEnt->PortInfo[1] = connector; + } else if ((pRADEONEnt->PortInfo[0].TMDSType != TMDS_INT && + pRADEONEnt->PortInfo[1].TMDSType != TMDS_INT)) { + /* no TMDS_INT port, make primary DAC port first */ + /* On my Inspiron 8600 both internal and external ports are + marked DAC_PRIMARY in BIOS. So be extra careful - only + swap when the first port is not DAC_PRIMARY */ + if ( (pRADEONEnt->PortInfo[1].DACType == DAC_PRIMARY) && + (pRADEONEnt->PortInfo[0].DACType != DAC_PRIMARY)) { + RADEONConnector connector; + connector = pRADEONEnt->PortInfo[0]; + pRADEONEnt->PortInfo[0] = pRADEONEnt->PortInfo[1]; + pRADEONEnt->PortInfo[1] = connector; + } + } - if ((xtal > 26900000) && (xtal < 27100000)) - xtal = 2700; - else if ((xtal > 14200000) && (xtal < 14400000)) - xtal = 1432; - else if ((xtal > 29400000) && (xtal < 29600000)) - xtal = 2950; - else - return FALSE; + if (info->HasSingleDAC) { + /* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC*/ + if (pRADEONEnt->PortInfo[0].ConnectorType == CONNECTOR_CRT) { + pRADEONEnt->PortInfo[0].DACType = DAC_TVDAC; + pRADEONEnt->PortInfo[1].DACType = DAC_PRIMARY; + } else { + pRADEONEnt->PortInfo[1].DACType = DAC_TVDAC; + pRADEONEnt->PortInfo[0].DACType = DAC_PRIMARY; + } + } else if (!info->HasCRTC2) { + pRADEONEnt->PortInfo[0].DACType = DAC_PRIMARY; + } - tmp = INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV); - ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff; + /* IgnoreEDID option is different from the NoDDCxx options used by DDC module + * When IgnoreEDID is used, monitor detection will still use DDC + * detection, but all EDID data will not be used in mode validation. + * You can use this option when you have a DDC monitor but want specify your own + * monitor timing parameters by using HSync, VRefresh and Modeline, + */ + if (xf86GetOptValBool(info->Options, OPTION_IGNORE_EDID, &ignore_edid)) { + if (ignore_edid) + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, + "IgnoreEDID is specified, EDID data will be ignored\n"); + } - Nx = (tmp & 0xff00) >> 8; - M = (tmp & 0xff); - xclk = RADEONDiv((2 * Nx * xtal), (2 * M)); + /* + * MonitorLayout option takes a string for two monitors connected in following format: + * Option "MonitorLayout" "primary-port-display, secondary-port-display" + * primary and secondary port displays can have one of following: + * NONE, CRT, LVDS, TMDS + * With this option, driver will bring up monitors as specified, + * not using auto-detection routines to probe monitors. + * + * This option can be used when the false monitor detection occurs. + * + * This option can also be used to disable one connected display. + * For example, if you have a laptop connected to an external CRT + * and you want to disable the internal LCD panel, you can specify + * Option "MonitorLayout" "NONE, CRT" + * + * This option can also used to disable Clone mode. One there is only + * one monitor is specified, clone mode will be turned off automatically + * even you have two monitors connected. + * + * Another usage of this option is you want to config the server + * to start up with a certain monitor arrangement even one monitor + * is not plugged in when server starts. + */ + if ((s = xf86GetOptValString(info->Options, OPTION_MONITOR_LAYOUT))) { + char s1[5], s2[5]; + i = 0; + /* When using user specified monitor types, we will not do DDC detection + * + */ + do { + switch(*s) { + case ',': + s1[i] = '\0'; + i = 0; + second = 1; + break; + case ' ': + case '\t': + case '\n': + case '\r': + break; + default: + if (second) + s2[i] = *s; + else + s1[i] = *s; + i++; + break; + } + if (i > 4) i = 4; + } while(*s++); + s2[i] = '\0'; - /* we're done, hopefully these are sane values */ - pll->reference_div = ref_div; - pll->xclk = xclk; - pll->reference_freq = xtal; + for (i = 0; i < max_mt; i++) { + if (strcmp(s1, MonTypeName[i]) == 0) { + pRADEONEnt->PortInfo[0].MonType = MonTypeID[i]; + break; + } + } + for (i = 0; i < max_mt; i++) { + if (strcmp(s2, MonTypeName[i]) == 0) { + pRADEONEnt->PortInfo[1].MonType = MonTypeID[i]; + break; + } + } - return TRUE; -} + if (i == max_mt) + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Invalid Monitor type specified for 2nd port \n"); -static void RADEONGetTMDSInfo(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - CARD32 tmp; - int i, n; + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, + "MonitorLayout Option: \n\tMonitor1--Type %s, Monitor2--Type %s\n\n", s1, s2); +#if 0 + if (pRADEONEnt->PortInfo[1].MonType == MT_CRT) { + pRADEONEnt->PortInfo[1].DACType = DAC_PRIMARY; + pRADEONEnt->PortInfo[1].TMDSType = TMDS_UNKNOWN; + pRADEONEnt->PortInfo[1].DDCType = DDC_VGA; + pRADEONEnt->PortInfo[1].ConnectorType = CONNECTOR_CRT; + pRADEONEnt->PortInfo[0].DACType = DAC_TVDAC; + pRADEONEnt->PortInfo[0].TMDSType = TMDS_UNKNOWN; + pRADEONEnt->PortInfo[0].DDCType = DDC_NONE_DETECTED; + pRADEONEnt->PortInfo[0].ConnectorType = pRADEONEnt->PortInfo[0].MonType+1; + pRADEONEnt->PortInfo[0].MonInfo = NULL; + } +#endif + + if (!ignore_edid) { + if ((pRADEONEnt->PortInfo[0].MonType > MT_NONE) && + (pRADEONEnt->PortInfo[0].MonType < MT_STV)) + RADEONDisplayDDCConnected(pScrn, pRADEONEnt->PortInfo[0].DDCType, + &pRADEONEnt->PortInfo[0]); + if ((pRADEONEnt->PortInfo[1].MonType > MT_NONE) && + (pRADEONEnt->PortInfo[1].MonType < MT_STV)) + RADEONDisplayDDCConnected(pScrn, pRADEONEnt->PortInfo[1].DDCType, + &pRADEONEnt->PortInfo[1]); + } - for (i=0; i<4; i++) { - info->tmds_pll[i].value = 0; - info->tmds_pll[i].freq = 0; } - if (info->VBIOS) { - tmp = RADEON_BIOS16(info->FPBIOSstart + 0x34); - if (tmp) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "DFP table revision: %d\n", RADEON_BIOS8(tmp)); - if (RADEON_BIOS8(tmp) == 3) { - n = RADEON_BIOS8(tmp + 5) + 1; - if (n > 4) n = 4; - for (i=0; i<n; i++) { - info->tmds_pll[i].value = RADEON_BIOS32(tmp+i*10+0x08); - info->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*10+0x10); - } - return; - } + if(((!info->HasCRTC2) || info->IsDellServer)) { + if (pRADEONEnt->PortInfo[0].MonType == MT_UNKNOWN) { + if((pRADEONEnt->PortInfo[0].MonType = RADEONDisplayDDCConnected(pScrn, DDC_DVI, &pRADEONEnt->PortInfo[0]))); + else if((pRADEONEnt->PortInfo[0].MonType = RADEONDisplayDDCConnected(pScrn, DDC_VGA, &pRADEONEnt->PortInfo[0]))); + else if((pRADEONEnt->PortInfo[0].MonType = RADEONDisplayDDCConnected(pScrn, DDC_CRT2, &pRADEONEnt->PortInfo[0]))); + else + pRADEONEnt->PortInfo[0].MonType = MT_CRT; + } - /* revision 4 has some problem as it appears in RV280, - comment it off for new, use default instead */ - /* - else if (RADEON_BIOS8(tmp) == 4) { - int stride = 0; - n = RADEON_BIOS8(tmp + 5) + 1; - if (n > 4) n = 4; - for (i=0; i<n; i++) { - info->tmds_pll[i].value = RADEON_BIOS32(tmp+stride+0x08); - info->tmds_pll[i].freq = RADEON_BIOS16(tmp+stride+0x10); - if (i == 0) stride += 10; - else stride += 6; - } - return; + if (!ignore_edid) { + if (pRADEONEnt->PortInfo[0].MonInfo) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Monitor1 EDID data ---------------------------\n"); + xf86PrintEDID(pRADEONEnt->PortInfo[0].MonInfo ); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "End of Monitor1 EDID data --------------------\n"); } - */ } - } - for (i=0; i<4; i++) { - info->tmds_pll[i].value = default_tmds_pll[info->ChipFamily][i].value; - info->tmds_pll[i].freq = default_tmds_pll[info->ChipFamily][i].freq; - } -} + pRADEONEnt->MonType1 = pRADEONEnt->PortInfo[0].MonType; + pRADEONEnt->MonInfo1 = pRADEONEnt->PortInfo[0].MonInfo; + pRADEONEnt->MonType2 = MT_NONE; + pRADEONEnt->MonInfo2 = NULL; + info->MergeType = MT_NONE; + info->DisplayType = pRADEONEnt->MonType1; -/* Read PLL parameters from BIOS block. Default to typical values if - * there is no BIOS. - */ -static Bool RADEONGetPLLParameters(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPLLPtr pll = &info->pll; - CARD16 bios_header; - CARD16 pll_info_block; - double min_dotclock; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Primary:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- %s\n", + MonTypeName[pRADEONEnt->PortInfo[0].MonType+1], + info->IsAtomBios ? + ConnectorTypeNameATOM[pRADEONEnt->PortInfo[0].ConnectorType]: + ConnectorTypeName[pRADEONEnt->PortInfo[0].ConnectorType], + DACTypeName[pRADEONEnt->PortInfo[0].DACType+1], + TMDSTypeName[pRADEONEnt->PortInfo[0].TMDSType+1], + DDCTypeName[pRADEONEnt->PortInfo[0].DDCType]); - if (!info->VBIOS) { + return TRUE; + } - pll->min_pll_freq = 12500; - pll->max_pll_freq = 35000; + if (pRADEONEnt->PortInfo[0].MonType == MT_UNKNOWN || pRADEONEnt->PortInfo[1].MonType == MT_UNKNOWN) { + /* Primary Head (DVI or Laptop Int. panel)*/ + /* A ddc capable display connected on DVI port */ + if (pRADEONEnt->PortInfo[0].MonType == MT_UNKNOWN) { + if((pRADEONEnt->PortInfo[0].MonType = RADEONDisplayDDCConnected(pScrn, pRADEONEnt->PortInfo[0].DDCType, &pRADEONEnt->PortInfo[0]))); + else if (info->IsMobility && + (INREG(RADEON_BIOS_4_SCRATCH) & 4)) { + /* non-DDC laptop panel connected on primary */ + pRADEONEnt->PortInfo[0].MonType = MT_LCD; + } else { + /* CRT on DVI, TODO: not reliable, make it always return false for now*/ + pRADEONEnt->PortInfo[0].MonType = RADEONCrtIsPhysicallyConnected(pScrn, !(pRADEONEnt->PortInfo[0].DACType)); + } + } - if (!RADEONProbePLLParameters(pScrn)) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Video BIOS not detected, using default PLL parameters!\n"); + /* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/ + if (pRADEONEnt->PortInfo[1].MonType == MT_UNKNOWN) { + if((pRADEONEnt->PortInfo[1].MonType = + RADEONDisplayDDCConnected(pScrn, pRADEONEnt->PortInfo[1].DDCType, &pRADEONEnt->PortInfo[1]))); + else if (info->IsMobility && + (INREG(RADEON_FP2_GEN_CNTL) & RADEON_FP2_ON)) { + /* non-DDC TMDS panel connected through DVO */ + pRADEONEnt->PortInfo[1].MonType = MT_DFP; + } else + pRADEONEnt->PortInfo[1].MonType = RADEONCrtIsPhysicallyConnected(pScrn, !(pRADEONEnt->PortInfo[1].DACType)); + } + } - switch (info->Chipset) { - case PCI_CHIP_R200_QL: - case PCI_CHIP_R200_QN: - case PCI_CHIP_R200_QO: - case PCI_CHIP_R200_BB: - pll->reference_freq = 2700; - pll->reference_div = 12; - pll->xclk = 27500; - break; - case PCI_CHIP_RV250_Id: - case PCI_CHIP_RV250_Ie: - case PCI_CHIP_RV250_If: - case PCI_CHIP_RV250_Ig: - pll->reference_freq = 2700; - pll->reference_div = 12; - pll->xclk = 24975; - break; - case PCI_CHIP_RV200_QW: - pll->reference_freq = 2700; - pll->reference_div = 12; - pll->xclk = 23000; - break; - case PCI_CHIP_RADEON_LW: /* Guess based on iBook OpenFirmware */ - pll->reference_freq = 2700; - pll->reference_div = 12; - pll->xclk = 36000; - break; - default: - pll->reference_freq = 2700; - pll->reference_div = 67; - pll->xclk = 16615; - break; - } - } + if(ignore_edid) { + pRADEONEnt->PortInfo[0].MonInfo = NULL; + pRADEONEnt->PortInfo[1].MonInfo = NULL; } else { - bios_header = RADEON_BIOS16(0x48); - pll_info_block = RADEON_BIOS16(bios_header + 0x30); - RADEONTRACE(("Header at 0x%04x; PLL Information at 0x%04x\n", - bios_header, pll_info_block)); - - pll->reference_freq = RADEON_BIOS16(pll_info_block + 0x0e); - pll->reference_div = RADEON_BIOS16(pll_info_block + 0x10); - pll->min_pll_freq = RADEON_BIOS32(pll_info_block + 0x12); - pll->max_pll_freq = RADEON_BIOS32(pll_info_block + 0x16); - pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); + if (pRADEONEnt->PortInfo[0].MonInfo) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on port 1 ----------------------\n"); + xf86PrintEDID(pRADEONEnt->PortInfo[0].MonInfo ); + } + + if (pRADEONEnt->PortInfo[1].MonInfo) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on port 2-----------------------\n"); + xf86PrintEDID(pRADEONEnt->PortInfo[1].MonInfo ); + } } - /* (Some?) Radeon BIOSes seem too lie about their minimum dot - * clocks. Allow users to override the detected minimum dot clock - * value (e.g., and allow it to be suitable for TV sets). - */ - if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK, - OPTUNITS_MHZ, &min_dotclock)) { - if (min_dotclock < 12 || min_dotclock*100 >= pll->max_pll_freq) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Illegal minimum dotclock specified %.2f MHz " - "(option ignored)\n", - min_dotclock); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "\n"); + + pRADEONEnt->MonType1 = pRADEONEnt->PortInfo[0].MonType; + pRADEONEnt->MonInfo1 = pRADEONEnt->PortInfo[0].MonInfo; + pRADEONEnt->MonType2 = pRADEONEnt->PortInfo[1].MonType; + pRADEONEnt->MonInfo2 = pRADEONEnt->PortInfo[1].MonInfo; + if (pRADEONEnt->PortInfo[0].MonType == MT_NONE) { + if (pRADEONEnt->PortInfo[1].MonType == MT_NONE) { + pRADEONEnt->MonType1 = MT_CRT; + pRADEONEnt->MonInfo1 = NULL; } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Forced minimum dotclock to %.2f MHz " - "(instead of detected %.2f MHz)\n", - min_dotclock, ((double)pll->min_pll_freq/1000)); - pll->min_pll_freq = min_dotclock * 1000; + RADEONConnector tmp; + pRADEONEnt->MonType1 = pRADEONEnt->PortInfo[1].MonType; + pRADEONEnt->MonInfo1 = pRADEONEnt->PortInfo[1].MonInfo; + tmp = pRADEONEnt->PortInfo[0]; + pRADEONEnt->PortInfo[0] = pRADEONEnt->PortInfo[1]; + pRADEONEnt->PortInfo[1] = tmp; + } + pRADEONEnt->MonType2 = MT_NONE; + pRADEONEnt->MonInfo2 = NULL; + } + + info->DisplayType = pRADEONEnt->MonType1; + pRADEONEnt->ReversedDAC = FALSE; + info->OverlayOnCRTC2 = FALSE; + info->MergeType = MT_NONE; + if (pRADEONEnt->MonType2 != MT_NONE) { + if(!pRADEONEnt->HasSecondary) { + info->MergeType = pRADEONEnt->MonType2; } + + if (pRADEONEnt->PortInfo[1].DACType == DAC_TVDAC) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Reversed DAC decteced\n"); + pRADEONEnt->ReversedDAC = TRUE; + } + } else { + pRADEONEnt->HasSecondary = FALSE; } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Primary:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- %s\n", + MonTypeName[pRADEONEnt->PortInfo[0].MonType+1], + info->IsAtomBios ? + ConnectorTypeNameATOM[pRADEONEnt->PortInfo[0].ConnectorType]: + ConnectorTypeName[pRADEONEnt->PortInfo[0].ConnectorType], + DACTypeName[pRADEONEnt->PortInfo[0].DACType+1], + TMDSTypeName[pRADEONEnt->PortInfo[0].TMDSType+1], + DDCTypeName[pRADEONEnt->PortInfo[0].DDCType]); + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Secondary:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- %s\n", + MonTypeName[pRADEONEnt->PortInfo[1].MonType+1], + info->IsAtomBios ? + ConnectorTypeNameATOM[pRADEONEnt->PortInfo[1].ConnectorType]: + ConnectorTypeName[pRADEONEnt->PortInfo[1].ConnectorType], + DACTypeName[pRADEONEnt->PortInfo[1].DACType+1], + TMDSTypeName[pRADEONEnt->PortInfo[1].TMDSType+1], + DDCTypeName[pRADEONEnt->PortInfo[1].DDCType]); + return TRUE; } + /* This is called by RADEONPreInit to set up the default visual */ static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn) { @@ -1951,6 +2231,97 @@ return TRUE; } +static void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, + RADEONInfoPtr info) +{ + save->mc_fb_location = info->mc_fb_location; + save->mc_agp_location = info->mc_agp_location; + save->display_base_addr = info->fbLocation; + save->display2_base_addr = info->fbLocation; + save->ov0_base_addr = info->fbLocation; +} + +static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + unsigned long mem_size; + CARD32 aper_size; + + /* Default to existing values */ + info->mc_fb_location = INREG(RADEON_MC_FB_LOCATION); + info->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION); + + /* We shouldn't use info->videoRam here which might have been clipped + * but the real video RAM instead + */ + mem_size = INREG(RADEON_CONFIG_MEMSIZE); + aper_size = INREG(RADEON_CONFIG_APER_SIZE); + if (mem_size == 0) + mem_size = 0x800000; + + /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - + Novell bug 204882 + along with lots of ubuntu ones */ + if (aper_size > mem_size) + mem_size = aper_size; + +#ifdef XF86DRI + /* Apply memory map limitation if using an old DRI */ + if (info->directRenderingEnabled && !info->newMemoryMap) { + if (aper_size < mem_size) + mem_size = aper_size; + } +#endif + + /* We won't try to change MC_FB_LOCATION when using fbdev */ + if (!info->FBDev) { + if (info->IsIGP) + info->mc_fb_location = INREG(RADEON_NB_TOM); +#ifdef XF86DRI + else + /* Old DRI has restrictions on the memory map */ + if ( info->directRenderingEnabled && + info->pKernelDRMVersion->version_minor < 10 ) + info->mc_fb_location = (mem_size - 1) & 0xffff0000U; + else + { + CARD32 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); + + /* Recent chips have an "issue" with the memory controller, the + * location must be aligned to the size. We just align it down, + * too bad if we walk over the top of system memory, we don't + * use DMA without a remapped anyway. + * Affected chips are rv280, all r3xx, and all r4xx, but not IGP + */ + if (info->ChipFamily == CHIP_FAMILY_RV280 || + info->ChipFamily == CHIP_FAMILY_R300 || + info->ChipFamily == CHIP_FAMILY_R350 || + info->ChipFamily == CHIP_FAMILY_RV350 || + info->ChipFamily == CHIP_FAMILY_RV380 || + info->ChipFamily == CHIP_FAMILY_R420 || + info->ChipFamily == CHIP_FAMILY_RV410) + aper0_base &= ~(mem_size - 1); + + info->mc_fb_location = (aper0_base >> 16) | + ((aper0_base + mem_size - 1) & 0xffff0000U); + } +#endif + } + info->fbLocation = (info->mc_fb_location & 0xffff) << 16; + +#ifdef XF86DRI + /* Just disable the damn AGP apertures for now, it may be + * re-enabled later by the DRM + */ + info->mc_agp_location = 0xffffffc0; +#endif + + RADEONTRACE(("RADEONInitMemoryMap() : \n")); + RADEONTRACE((" mem_size : 0x%08lx\n", mem_size)); + RADEONTRACE((" MC_FB_LOCATION : 0x%08lx\n", info->mc_fb_location)); + RADEONTRACE((" MC_AGP_LOCATION : 0x%08lx\n", info->mc_agp_location)); +} + static void RADEONGetVRamType(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -1964,9 +2335,7 @@ info->IsDDR = FALSE; tmp = INREG(RADEON_MEM_CNTL); - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350)) { + if (IS_R300_VARIANT) { tmp &= R300_MEM_NUM_CHANNELS_MASK; switch (tmp) { case 0: info->RamWidth = 64; break; @@ -1979,6 +2348,10 @@ (info->ChipFamily == CHIP_FAMILY_RS200)){ if (tmp & RV100_HALF_MODE) info->RamWidth = 32; else info->RamWidth = 64; + if (!info->HasCRTC2) { + info->RamWidth /= 4; + info->IsDDR = TRUE; + } } else { if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) info->RamWidth = 128; else info->RamWidth = 64; @@ -1989,24 +2362,189 @@ */ } +/* + * Depending on card genertation, chipset bugs, etc... the amount of vram + * accessible to the CPU can vary. This function is our best shot at figuring + * it out. Returns a value in KB. + */ +static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + unsigned long aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024; + +#ifdef XF86DRI + /* If we use the DRI, we need to check if it's a version that has the + * bug of always cropping MC_FB_LOCATION to one aperture, in which case + * we need to limit the amount of accessible video memory + */ + if (info->directRenderingEnabled && + info->pKernelDRMVersion->version_minor < 23) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "[dri] limiting video memory to one aperture of %ldK\n", + aper_size); + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "[dri] detected radeon kernel module version 1.%d but" + " 1.23 or newer is required for full memory mapping.\n", + info->pKernelDRMVersion->version_minor); + info->newMemoryMap = FALSE; + return aper_size; + } + info->newMemoryMap = TRUE; +#endif /* XF86DRI */ + + /* Set HDP_APER_CNTL only on cards that are known not to be broken, + * that is has the 2nd generation multifunction PCI interface + */ + if (info->ChipFamily == CHIP_FAMILY_RV280 || + info->ChipFamily == CHIP_FAMILY_RV350 || + info->ChipFamily == CHIP_FAMILY_RV380 || + info->ChipFamily == CHIP_FAMILY_R420 || + info->ChipFamily == CHIP_FAMILY_RV410) { + OUTREGP(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, + ~RADEON_HDP_APER_CNTL); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Generation 2 PCI interface, using max accessible memory\n"); + return aper_size * 2; + } + + /* Older cards have all sorts of funny issues to deal with. First + * check if it's a multifunction card by reading the PCI config + * header type... Limit those to one aperture size + */ + if (pciReadByte(info->PciTag, 0xe) & 0x80) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Generation 1 PCI interface in multifunction mode" + ", accessible memory limited to one aperture\n"); + return aper_size; + } + + /* Single function older card. We read HDP_APER_CNTL to see how the BIOS + * have set it up. We don't write this as it's broken on some ASICs but + * we expect the BIOS to have done the right thing (might be too optimistic...) + */ + if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) + return aper_size * 2; + + return aper_size; +} + +static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + EntityInfoPtr pEnt = info->pEnt; + GDevPtr dev = pEnt->device; + unsigned char *RADEONMMIO = info->MMIO; + MessageType from = X_PROBED; + + if (info->FBDev) + pScrn->videoRam = fbdevHWGetVidmem(pScrn) / 1024; + else if ((info->ChipFamily == CHIP_FAMILY_RS100) || + (info->ChipFamily == CHIP_FAMILY_RS200) || + (info->ChipFamily == CHIP_FAMILY_RS300)) { + CARD32 tom = INREG(RADEON_NB_TOM); + + pScrn->videoRam = (((tom >> 16) - + (tom & 0xffff) + 1) << 6); + + OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024); + } else { + int accessible; + int bar_size; + + /* Read VRAM size from card */ + pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; + + /* Some production boards of m6 will return 0 if it's 8 MB */ + if (pScrn->videoRam == 0) { + pScrn->videoRam = 8192; + OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000); + } + + /* Get accessible memory */ + accessible = RADEONGetAccessibleVRAM(pScrn); + + /* Crop it to the size of the PCI BAR */ + bar_size = (1u << info->PciInfo->size[0]) / 1024; + if (bar_size == 0) + bar_size = 0x20000; + if (accessible > bar_size) + accessible = bar_size; + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Detected total video RAM=%dK, accessible=%dK (PCI BAR=%dK)\n", + pScrn->videoRam, accessible, bar_size); + if (pScrn->videoRam > accessible) + pScrn->videoRam = accessible; + } + + info->MemCntl = INREG(RADEON_SDRAM_MODE_REG); + info->BusCntl = INREG(RADEON_BUS_CNTL); + + RADEONGetVRamType(pScrn); + + if (dev->videoRam) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Video RAM override, using %d kB instead of %d kB\n", + dev->videoRam, + pScrn->videoRam); + from = X_CONFIG; + pScrn->videoRam = dev->videoRam; + } + + xf86DrvMsg(pScrn->scrnIndex, from, + "Mapped VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR"); + + /* FIXME: For now, split FB into two equal sections. This should + * be able to be adjusted by user with a config option. */ + if (info->IsPrimary) { + pScrn->videoRam /= 2; + info->MergedFB = FALSE; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Using %dk of videoram for primary head\n", + pScrn->videoRam); + } + + if (info->IsSecondary) { + pScrn->videoRam /= 2; + info->LinearAddr += pScrn->videoRam * 1024; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Using %dk of videoram for secondary head\n", + pScrn->videoRam); + } + + pScrn->videoRam &= ~1023; + info->FbMapSize = pScrn->videoRam * 1024; + + /* if the card is PCI Express reserve the last 32k for the gart table */ +#ifdef XF86DRI + if (info->cardType == CARD_PCIE && info->directRenderingEnabled) + info->FbSecureSize = RADEON_PCIGART_TABLE_SIZE; + else +#endif + info->FbSecureSize = 0; + + return TRUE; +} + + /* This is called by RADEONPreInit to handle config file overrides for * things like chipset and memory regions. Also determine memory size * and type. If memory type ever needs an override, put it in this * routine. */ -static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn) +static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); EntityInfoPtr pEnt = info->pEnt; GDevPtr dev = pEnt->device; - MessageType from; unsigned char *RADEONMMIO = info->MMIO; + MessageType from = X_PROBED; #ifdef XF86DRI - const char *s; - CARD32 agpCommand; + const char *s; #endif - /* Chipset */ + /* Chipset */ from = X_PROBED; if (dev->chipset && *dev->chipset) { info->Chipset = xf86StringToToken(RADEONChipsets, dev->chipset); @@ -2037,6 +2575,8 @@ info->HasCRTC2 = TRUE; info->IsMobility = FALSE; info->IsIGP = FALSE; + info->IsDellServer = FALSE; + info->HasSingleDAC = FALSE; switch (info->Chipset) { case PCI_CHIP_RADEON_LY: case PCI_CHIP_RADEON_LZ: @@ -2044,9 +2584,29 @@ info->ChipFamily = CHIP_FAMILY_RV100; break; + case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ + case PCI_CHIP_RN50_5969: + info->HasCRTC2 = FALSE; case PCI_CHIP_RV100_QY: case PCI_CHIP_RV100_QZ: info->ChipFamily = CHIP_FAMILY_RV100; + + /* DELL triple-head configuration. */ + if ((info->PciInfo->subsysVendor == PCI_VENDOR_DELL) && + ((info->PciInfo->subsysCard == 0x016c) || + (info->PciInfo->subsysCard == 0x016d) || + (info->PciInfo->subsysCard == 0x016e) || + (info->PciInfo->subsysCard == 0x016f) || + (info->PciInfo->subsysCard == 0x0170) || + (info->PciInfo->subsysCard == 0x017d) || + (info->PciInfo->subsysCard == 0x017e) || + (info->PciInfo->subsysCard == 0x0183) || + (info->PciInfo->subsysCard == 0x018a) || + (info->PciInfo->subsysCard == 0x019a))) { + info->IsDellServer = TRUE; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL server detected, force to special setup\n"); + } + break; case PCI_CHIP_RS100_4336: @@ -2073,8 +2633,18 @@ case PCI_CHIP_R200_BB: case PCI_CHIP_R200_BC: case PCI_CHIP_R200_QH: + case PCI_CHIP_R200_QI: + case PCI_CHIP_R200_QJ: + case PCI_CHIP_R200_QK: case PCI_CHIP_R200_QL: case PCI_CHIP_R200_QM: + case PCI_CHIP_R200_QN: + case PCI_CHIP_R200_QO: + case PCI_CHIP_R200_Qh: + case PCI_CHIP_R200_Qi: + case PCI_CHIP_R200_Qj: + case PCI_CHIP_R200_Qk: + case PCI_CHIP_R200_Ql: info->ChipFamily = CHIP_FAMILY_R200; break; @@ -2087,19 +2657,25 @@ break; case PCI_CHIP_RV250_Ld: + case PCI_CHIP_RV250_Le: case PCI_CHIP_RV250_Lf: case PCI_CHIP_RV250_Lg: info->IsMobility = TRUE; + case PCI_CHIP_RV250_Id: + case PCI_CHIP_RV250_Ie: case PCI_CHIP_RV250_If: case PCI_CHIP_RV250_Ig: info->ChipFamily = CHIP_FAMILY_RV250; break; case PCI_CHIP_RS300_5835: + case PCI_CHIP_RS350_7835: info->IsMobility = TRUE; case PCI_CHIP_RS300_5834: + case PCI_CHIP_RS350_7834: info->ChipFamily = CHIP_FAMILY_RS300; info->IsIGP = TRUE; + info->HasSingleDAC = TRUE; break; case PCI_CHIP_RV280_5C61: @@ -2109,6 +2685,7 @@ case PCI_CHIP_RV280_5961: case PCI_CHIP_RV280_5962: case PCI_CHIP_RV280_5964: + case PCI_CHIP_RV280_5965: info->ChipFamily = CHIP_FAMILY_RV280; break; @@ -2121,7 +2698,7 @@ case PCI_CHIP_R300_NF: case PCI_CHIP_R300_NG: info->ChipFamily = CHIP_FAMILY_R300; - break; + break; case PCI_CHIP_RV350_NP: case PCI_CHIP_RV350_NQ: @@ -2135,9 +2712,11 @@ case PCI_CHIP_RV360_AR: case PCI_CHIP_RV350_AS: case PCI_CHIP_RV350_AT: + case PCI_CHIP_RV350_4155: case PCI_CHIP_RV350_AV: + case PCI_CHIP_RV350_AW: info->ChipFamily = CHIP_FAMILY_RV350; - break; + break; case PCI_CHIP_R350_AH: case PCI_CHIP_R350_AI: @@ -2148,14 +2727,113 @@ case PCI_CHIP_R350_NK: case PCI_CHIP_R360_NJ: info->ChipFamily = CHIP_FAMILY_R350; - break; + break; + + case PCI_CHIP_RV380_3150: + case PCI_CHIP_RV380_3152: + case PCI_CHIP_RV380_3154: + info->IsMobility = TRUE; + case PCI_CHIP_RV380_3E50: + case PCI_CHIP_RV380_3E54: + info->ChipFamily = CHIP_FAMILY_RV380; + break; + + case PCI_CHIP_RV370_5460: + case PCI_CHIP_RV370_5462: + case PCI_CHIP_RV370_5464: + info->IsMobility = TRUE; + case PCI_CHIP_RV370_5B60: + case PCI_CHIP_RV370_5B62: + case PCI_CHIP_RV370_5B63: + case PCI_CHIP_RV370_5B64: + case PCI_CHIP_RV370_5B65: + info->ChipFamily = CHIP_FAMILY_RV380; + break; + + case PCI_CHIP_RS400_5A42: + case PCI_CHIP_RC410_5A62: + case PCI_CHIP_RS480_5955: + case PCI_CHIP_RS482_5975: + info->IsMobility = TRUE; + case PCI_CHIP_RS400_5A41: + case PCI_CHIP_RC410_5A61: + case PCI_CHIP_RS480_5954: + case PCI_CHIP_RS482_5974: + info->ChipFamily = CHIP_FAMILY_RS400; + info->IsIGP = TRUE; + /*info->HasSingleDAC = TRUE;*/ /* ??? */ + break; + + case PCI_CHIP_RV410_564A: + case PCI_CHIP_RV410_564B: + case PCI_CHIP_RV410_564F: + case PCI_CHIP_RV410_5652: + case PCI_CHIP_RV410_5653: + info->IsMobility = TRUE; + case PCI_CHIP_RV410_5E48: + case PCI_CHIP_RV410_5E4B: + case PCI_CHIP_RV410_5E4A: + case PCI_CHIP_RV410_5E4D: + case PCI_CHIP_RV410_5E4C: + case PCI_CHIP_RV410_5E4F: + info->ChipFamily = CHIP_FAMILY_RV410; + break; + + case PCI_CHIP_R420_JN: + info->IsMobility = TRUE; + case PCI_CHIP_R420_JH: + case PCI_CHIP_R420_JI: + case PCI_CHIP_R420_JJ: + case PCI_CHIP_R420_JK: + case PCI_CHIP_R420_JL: + case PCI_CHIP_R420_JM: + case PCI_CHIP_R420_JP: + case PCI_CHIP_R420_4A4F: + info->ChipFamily = CHIP_FAMILY_R420; + break; + + case PCI_CHIP_R423_UH: + case PCI_CHIP_R423_UI: + case PCI_CHIP_R423_UJ: + case PCI_CHIP_R423_UK: + case PCI_CHIP_R423_UQ: + case PCI_CHIP_R423_UR: + case PCI_CHIP_R423_UT: + case PCI_CHIP_R423_5D57: + case PCI_CHIP_R423_5550: + info->ChipFamily = CHIP_FAMILY_R420; + break; + + case PCI_CHIP_R430_5D49: + case PCI_CHIP_R430_5D4A: + case PCI_CHIP_R430_5D48: + info->IsMobility = TRUE; + case PCI_CHIP_R430_554F: + case PCI_CHIP_R430_554D: + case PCI_CHIP_R430_554E: + case PCI_CHIP_R430_554C: + info->ChipFamily = CHIP_FAMILY_R420; /*CHIP_FAMILY_R430*/ + break; + + case PCI_CHIP_R480_5D4C: + case PCI_CHIP_R480_5D50: + case PCI_CHIP_R480_5D4E: + case PCI_CHIP_R480_5D4F: + case PCI_CHIP_R480_5D52: + case PCI_CHIP_R480_5D4D: + case PCI_CHIP_R481_4B4B: + case PCI_CHIP_R481_4B4A: + case PCI_CHIP_R481_4B49: + case PCI_CHIP_R481_4B4C: + info->ChipFamily = CHIP_FAMILY_R420; /*CHIP_FAMILY_R480*/ + break; default: /* Original Radeon/7200 */ info->ChipFamily = CHIP_FAMILY_RADEON; info->HasCRTC2 = FALSE; } - /* Framebuffer */ + from = X_PROBED; info->LinearAddr = info->PciInfo->memBase[0] & 0xfe000000; @@ -2192,127 +2870,116 @@ } /* Read registers used to determine options */ - from = X_PROBED; - if (info->FBDev) - pScrn->videoRam = fbdevHWGetVidmem(pScrn) / 1024; - else if ((info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200) || - (info->ChipFamily == CHIP_FAMILY_RS300)) { - CARD32 tom = INREG(RADEON_NB_TOM); - pScrn->videoRam = (((tom >> 16) - - (tom & 0xffff) + 1) << 6); - OUTREG(RADEON_MC_FB_LOCATION, tom); - OUTREG(RADEON_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); - OUTREG(RADEON_DISPLAY2_BASE_ADDR, (tom & 0xffff) << 16); - OUTREG(RADEON_OV0_BASE_ADDR, (tom & 0xffff) << 16); - - /* This is supposed to fix the crtc2 noise problem. - */ - OUTREG(RADEON_GRPH2_BUFFER_CNTL, - INREG(RADEON_GRPH2_BUFFER_CNTL) & ~0x7f0000); - - if ((info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200)) { - /* This is to workaround the asic bug for RMX, some versions - of BIOS dosen't have this register initialized correctly. - */ - OUTREGP(RADEON_CRTC_MORE_CNTL, RADEON_CRTC_H_CUTOFF_ACTIVE_EN, - ~RADEON_CRTC_H_CUTOFF_ACTIVE_EN); - } - - } - else - pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; - - /* Some production boards of m6 will return 0 if it's 8 MB */ - if (pScrn->videoRam == 0) pScrn->videoRam = 8192; - - if (info->IsSecondary) { - /* FIXME: For now, split FB into two equal sections. This should - * be able to be adjusted by user with a config option. */ - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - RADEONInfoPtr info1; - - pScrn->videoRam /= 2; - pRADEONEnt->pPrimaryScrn->videoRam = pScrn->videoRam; + /* Check chip errata */ + info->ChipErrata = CHIP_ERRATA_NONE; - info1 = RADEONPTR(pRADEONEnt->pPrimaryScrn); - info1->FbMapSize = pScrn->videoRam * 1024; - info->LinearAddr += pScrn->videoRam * 1024; - info1->Clone = FALSE; - info1->CurCloneMode = NULL; - } + if (info->ChipFamily == CHIP_FAMILY_R300 && + (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) + == RADEON_CFG_ATI_REV_A11) + info->ChipErrata |= CHIP_ERRATA_R300_CG; + + if (info->ChipFamily == CHIP_FAMILY_RV200 || + info->ChipFamily == CHIP_FAMILY_RS200) + info->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS; + + if (info->ChipFamily == CHIP_FAMILY_RV100 || + info->ChipFamily == CHIP_FAMILY_RS100 || + info->ChipFamily == CHIP_FAMILY_RS200) + info->ChipErrata |= CHIP_ERRATA_PLL_DELAY; + + /* Clear bit for M6 Chipsets */ + if (info->Chipset == PCI_CHIP_RADEON_LY || + info->Chipset == PCI_CHIP_RADEON_LZ) + info->ChipErrata &= ~CHIP_ERRATA_PLL_DELAY; - info->R300CGWorkaround = - (info->ChipFamily == CHIP_FAMILY_R300 && - (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) - == RADEON_CFG_ATI_REV_A11); +#ifdef XF86DRI + /* AGP/PCI */ + /* Proper autodetection of an AGP capable device requires examining + * PCI config registers to determine if the device implements extended + * PCI capabilities, and then walking the capability list as indicated + * in the PCI 2.2 and AGP 2.0 specifications, to determine if AGP + * capability is present. The procedure is outlined as follows: + * + * 1) Test bit 4 (CAP_LIST) of the PCI status register of the device + * to determine wether or not this device implements any extended + * capabilities. If this bit is zero, then the device is a PCI 2.1 + * or earlier device and is not AGP capable, and we can conclude it + * to be a PCI device. + * + * 2) If bit 4 of the status register is set, then the device implements + * extended capabilities. There is an 8 bit wide capabilities pointer + * register located at offset 0x34 in PCI config space which points to + * the first capability in a linked list of extended capabilities that + * this device implements. The lower two bits of this register are + * reserved and MBZ so must be masked out. + * + * 3) The extended capabilities list is formed by one or more extended + * capabilities structures which are aligned on DWORD boundaries. + * The first byte of the structure is the capability ID (CAP_ID) + * indicating what extended capability this structure refers to. The + * second byte of the structure is an offset from the beginning of + * PCI config space pointing to the next capability in the linked + * list (NEXT_PTR) or NULL (0x00) at the end of the list. The lower + * two bits of this pointer are reserved and MBZ. By examining the + * CAP_ID of each capability and walking through the list, we will + * either find the AGP_CAP_ID (0x02) indicating this device is an + * AGP device, or we'll reach the end of the list, indicating it is + * a PCI device. + * + * Mike A. Harris <mharris@redhat.com> + * + * References: + * - PCI Local Bus Specification Revision 2.2, Chapter 6 + * - AGP Interface Specification Revision 2.0, Section 6.1.5 + */ - info->MemCntl = INREG(RADEON_SDRAM_MODE_REG); - info->BusCntl = INREG(RADEON_BUS_CNTL); + info->cardType = CARD_PCI; - RADEONGetVRamType(pScrn); + if (pciReadLong(info->PciTag, PCI_CMD_STAT_REG) & RADEON_CAP_LIST) { + CARD32 cap_ptr, cap_id; - if (dev->videoRam) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Video RAM override, using %d kB instead of %d kB\n", - dev->videoRam, - pScrn->videoRam); - from = X_CONFIG; - pScrn->videoRam = dev->videoRam; + cap_ptr = pciReadLong(info->PciTag, + RADEON_CAPABILITIES_PTR_PCI_CONFIG) + & RADEON_CAP_PTR_MASK; + + while(cap_ptr != RADEON_CAP_ID_NULL) { + cap_id = pciReadLong(info->PciTag, cap_ptr); + if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { + info->cardType = CARD_AGP; + break; + } + if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { + info->cardType = CARD_PCIE; + break; + } + cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; + } } - pScrn->videoRam &= ~1023; - info->FbMapSize = pScrn->videoRam * 1024; - xf86DrvMsg(pScrn->scrnIndex, from, - "VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR"); - -#ifdef XF86DRI - /* AGP/PCI */ - /* There are signatures in BIOS and PCI-SSID for a PCI card, but - * they are not very reliable. Following detection method works for - * all cards tested so far. Note, checking AGP_ENABLE bit after - * drmAgpEnable call can also give the correct result. However, - * calling drmAgpEnable on a PCI card can cause some strange lockup - * when the server restarts next time. - */ - - agpCommand = pciReadLong(info->PciTag, RADEON_AGP_COMMAND_PCI_CONFIG); - pciWriteLong(info->PciTag, RADEON_AGP_COMMAND_PCI_CONFIG, - agpCommand | RADEON_AGP_ENABLE); - if (pciReadLong(info->PciTag, RADEON_AGP_COMMAND_PCI_CONFIG) - & RADEON_AGP_ENABLE) { - info->IsPCI = FALSE; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "AGP card detected\n"); - } else { - info->IsPCI = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PCI card detected\n"); - } - pciWriteLong(info->PciTag, RADEON_AGP_COMMAND_PCI_CONFIG, agpCommand); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n", + (info->cardType==CARD_PCI) ? "PCI" : + (info->cardType==CARD_PCIE) ? "PCIE" : "AGP"); if ((s = xf86GetOptValString(info->Options, OPTION_BUS_TYPE))) { if (strcmp(s, "AGP") == 0) { - info->IsPCI = FALSE; + info->cardType = CARD_AGP; xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into AGP mode\n"); } else if (strcmp(s, "PCI") == 0) { - info->IsPCI = TRUE; + info->cardType = CARD_PCI; xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); } else if (strcmp(s, "PCIE") == 0) { - info->IsPCI = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, - "PCI Express not supported yet, using PCI mode\n"); + info->cardType = CARD_PCIE; + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI Express mode\n"); } else { xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Invalid BusType option, using detected type\n"); } - } else if (xf86ReturnOptValBool(info->Options, OPTION_IS_PCI, FALSE)) { - info->IsPCI = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "ForcePCIMode is deprecated -- " - "use BusType option instead\n"); } #endif + xf86GetOptValBool(info->Options, OPTION_SHOWCACHE, &info->showCache); + if (info->showCache) + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, + "Option ShowCache enabled\n"); return TRUE; } @@ -2366,7 +3033,7 @@ static void RADEONPreInitDDC(ScrnInfoPtr pScrn) { - RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); ModuleDescPtr pModule; info->ddc1 = FALSE; @@ -2382,7 +3049,7 @@ /* Load I2C if we have the code to use it */ if (info->ddc2) { if ((pModule = xf86LoadSubModule(pScrn, "i2c"))) { - xf86LoaderModReqSymLists(pModule, i2cSymbols,NULL); + xf86LoaderModReqSymLists(pModule, i2cSymbols, NULL); info->ddc2 = RADEONI2cInit(pScrn); } else info->ddc2 = FALSE; @@ -2396,18 +3063,39 @@ static void RADEONUpdatePanelSize(ScrnInfoPtr pScrn) { int j; - RADEONInfoPtr info = RADEONPTR (pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); xf86MonPtr ddc = pScrn->monitor->DDC; DisplayModePtr p; + if ((info->UseBiosDividers && info->DotClock != 0) || (ddc == NULL)) + return; + /* Go thru detailed timing table first */ for (j = 0; j < 4; j++) { if (ddc->det_mon[j].type == 0) { struct detailed_timings *d_timings = &ddc->det_mon[j].section.d_timings; + int match = 0; + + /* If we didn't get a panel clock or guessed one, try to match the + * mode with the panel size. We do that because we _need_ a panel + * clock, or ValidateFPModes will fail, even when UseBiosDividers + * is set. + */ + if (info->DotClock == 0 && + info->PanelXRes == d_timings->h_active && + info->PanelYRes == d_timings->v_active) + match = 1; + + /* If we don't have a BIOS provided panel data with fixed dividers, + * check for a larger panel size + */ if (info->PanelXRes < d_timings->h_active && - info->PanelYRes < d_timings->v_active) { + info->PanelYRes < d_timings->v_active && + !info->UseBiosDividers) + match = 1; + if (match) { info->PanelXRes = d_timings->h_active; info->PanelYRes = d_timings->v_active; info->DotClock = d_timings->clock / 1000; @@ -2417,10 +3105,24 @@ info->VOverPlus = d_timings->v_sync_off; info->VSyncWidth = d_timings->v_sync_width; info->VBlank = d_timings->v_blanking; + info->Flags = (d_timings->interlaced ? V_INTERLACE : 0); + if (d_timings->sync == 3) { + switch (d_timings->misc) { + case 0: info->Flags |= V_NHSYNC | V_NVSYNC; break; + case 1: info->Flags |= V_PHSYNC | V_NVSYNC; break; + case 2: info->Flags |= V_NHSYNC | V_PVSYNC; break; + case 3: info->Flags |= V_PHSYNC | V_PVSYNC; break; + } + } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC detailed: %dx%d\n", + info->PanelXRes, info->PanelYRes); } } } + if (info->UseBiosDividers && info->DotClock != 0) + return; + /* Search thru standard VESA modes from EDID */ for (j = 0; j < 8; j++) { if ((info->PanelXRes < ddc->timings2[j].hsize) && @@ -2442,26 +3144,14 @@ info->VOverPlus = p->VSyncStart - p->VDisplay; info->VSyncWidth = p->VSyncEnd - p->VSyncStart; info->DotClock = p->Clock; - info->Flags = - (ddc->det_mon[j].section.d_timings.interlaced - ? V_INTERLACE - : 0); - if (ddc->det_mon[j].section.d_timings.sync == 3) { - switch (ddc->det_mon[j].section.d_timings.misc) { - case 0: info->Flags |= V_NHSYNC | V_NVSYNC; break; - case 1: info->Flags |= V_PHSYNC | V_NVSYNC; break; - case 2: info->Flags |= V_NHSYNC | V_PVSYNC; break; - case 3: info->Flags |= V_PHSYNC | V_PVSYNC; break; - } - } + info->Flags = p->Flags; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC VESA/EDID: %dx%d\n", + info->PanelXRes, info->PanelYRes); } } } } } - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel size found from DDC: %dx%d\n", - info->PanelXRes, info->PanelYRes); } /* This function will sort all modes according to their resolution. @@ -2508,13 +3198,20 @@ static void RADEONSetPitch (ScrnInfoPtr pScrn) { int dummy = pScrn->virtualX; + RADEONInfoPtr info = RADEONPTR(pScrn); /* FIXME: May need to validate line pitch here */ switch (pScrn->depth / 8) { - case 1: dummy = (pScrn->virtualX + 127) & ~127; break; - case 2: dummy = (pScrn->virtualX + 31) & ~31; break; + case 1: if (info->allowColorTiling) dummy = (pScrn->virtualX + 255) & ~255; + else dummy = (pScrn->virtualX + 127) & ~127; + break; + case 2: if (info->allowColorTiling) dummy = (pScrn->virtualX + 127) & ~127; + else dummy = (pScrn->virtualX + 31) & ~31; + break; case 3: - case 4: dummy = (pScrn->virtualX + 15) & ~15; break; + case 4: if (info->allowColorTiling) dummy = (pScrn->virtualX + 63) & ~63; + else dummy = (pScrn->virtualX + 15) & ~15; + break; } pScrn->displayWidth = dummy; } @@ -2582,6 +3279,8 @@ /* Search thru standard VESA modes from EDID */ for (j = 0; j < 8; j++) { + if (ddc->timings2[j].hsize == 0 || ddc->timings2[j].vsize == 0) + continue; for (p = pScrn->monitor->Modes; p && p->next; p = p->next->next) { /* Ignore all double scan modes */ if ((ddc->timings2[j].hsize == p->HDisplay) && @@ -2653,33 +3352,28 @@ /* XFree86's xf86ValidateModes routine doesn't work well with DDC modes, * so here is our own validation routine. */ -static int RADEONValidateDDCModes(ScrnInfoPtr pScrn, char **ppModeName, - RADEONMonitorType DisplayType) +static int RADEONValidateDDCModes(ScrnInfoPtr pScrn1, char **ppModeName, + RADEONMonitorType DisplayType, int crtc2) { - RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn1); DisplayModePtr p; DisplayModePtr last = NULL; DisplayModePtr first = NULL; DisplayModePtr ddcModes = NULL; int count = 0; int i, width, height; + ScrnInfoPtr pScrn = pScrn1; - pScrn->virtualX = pScrn->display->virtualX; - pScrn->virtualY = pScrn->display->virtualY; + if (crtc2) + pScrn = info->CRT2pScrn; - if (pScrn->monitor->DDC && !info->UseBiosDividers) { + pScrn->virtualX = pScrn1->display->virtualX; + pScrn->virtualY = pScrn1->display->virtualY; + + if (pScrn->monitor->DDC) { int maxVirtX = pScrn->virtualX; int maxVirtY = pScrn->virtualY; - if ((DisplayType != MT_CRT) && !info->IsSecondary) { - /* The panel size we collected from BIOS may not be the - * maximum size supported by the panel. If not, we update - * it now. These will be used if no matching mode can be - * found from EDID data. - */ - RADEONUpdatePanelSize(pScrn); - } - /* Collect all of the DDC modes */ first = last = ddcModes = RADEONDDCModes(pScrn); @@ -2687,7 +3381,7 @@ /* If primary head is a flat panel, use RMX by default */ if ((!info->IsSecondary && DisplayType != MT_CRT) && - !info->ddc_mode) { + (!info->ddc_mode) && (!crtc2)) { /* These values are effective values after expansion. * They are not really used to set CRTC registers. */ @@ -2728,7 +3422,7 @@ if (p->HDisplay == width && p->VDisplay == height) { /* We found a DDC mode that matches the one - requested in the XF86Config file */ + requested in the XF86Config file */ p->type |= M_T_USERDEF; /* Update the max virtual setttings */ @@ -2794,8 +3488,13 @@ p->type |= M_T_USERDEF; } - pScrn->virtualX = pScrn->display->virtualX = maxVirtX; - pScrn->virtualY = pScrn->display->virtualY = maxVirtY; + if (crtc2) { + pScrn->virtualX = maxVirtX; + pScrn->virtualY = maxVirtY; + } else { + pScrn->virtualX = pScrn->display->virtualX = maxVirtX; + pScrn->virtualY = pScrn->display->virtualY = maxVirtY; + } } /* Close the doubly-linked mode list, if we found any usable modes */ @@ -2853,7 +3552,7 @@ pScrn->virtualY = MAX(pScrn->virtualY, info->PanelYRes); xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "No valid mode specified, force to native mdoe\n"); + "No valid mode specified, force to native mode\n"); } return new; @@ -2970,8 +3669,9 @@ new->next = NULL; new->prev = last; - last->next = new; + if (last) last->next = new; last = new; + if (!first) first = new; } } } @@ -3087,253 +3787,178 @@ } } -static int RADEONValidateCloneModes(ScrnInfoPtr pScrn) +static int RADEONValidateMergeModes(ScrnInfoPtr pScrn1) { - RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn1); ClockRangePtr clockRanges; - DisplayModePtr tmp_mode = NULL; - DisplayModePtr clone_mode, save_mode; - int modesFound = 0; - int count = 0; - int tmp_hdisplay = 0; - int tmp_vdisplay = 0; - int i, save_n_hsync, save_n_vrefresh; - range save_hsync, save_vrefresh; - char *s; - char **clone_mode_names = NULL; - Bool ddc_mode = info->ddc_mode; - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + int modesFound; + ScrnInfoPtr pScrn = info->CRT2pScrn; - /* Save all infomations that will be changed by clone mode validateion */ - save_mode = pScrn->modes; - pScrn->modes = NULL; - - /* Clone display mode names, duplicate all mode names for primary - * head. Allocate one more, in case pScrn->display->modes[0] == - * NULL */ - while (pScrn->display->modes[count]) count++; - clone_mode_names = xnfalloc((count+2) * sizeof(char*)); - for (i = 0; i < count; i++) { - clone_mode_names[i] = xnfalloc(strlen(pScrn->display->modes[i]) + 1); - strcpy(clone_mode_names[i], pScrn->display->modes[i]); + /* fill in pScrn2 */ + pScrn->videoRam = pScrn1->videoRam; + pScrn->depth = pScrn1->depth; + pScrn->numClocks = pScrn1->numClocks; + pScrn->progClock = pScrn1->progClock; + pScrn->fbFormat = pScrn1->fbFormat; + pScrn->videoRam = pScrn1->videoRam; + pScrn->maxHValue = pScrn1->maxHValue; + pScrn->maxVValue = pScrn1->maxVValue; + pScrn->xInc = pScrn1->xInc; + + if (info->NoVirtual) { + pScrn1->display->virtualX = 0; + pScrn1->display->virtualY = 0; } - clone_mode_names[count] = NULL; - clone_mode_names[count+1] = NULL; - pScrn->progClock = TRUE; + if (pScrn->monitor->DDC) { + /* If we still don't know sync range yet, let's try EDID. + * + * Note that, since we can have dual heads, Xconfigurator + * may not be able to probe both monitors correctly through + * vbe probe function (RADEONProbeDDC). Here we provide an + * additional way to auto-detect sync ranges if they haven't + * been added to XF86Config manually. + */ + if (pScrn->monitor->nHsync <= 0) + RADEONSetSyncRangeFromEdid(pScrn, 1); + if (pScrn->monitor->nVrefresh <= 0) + RADEONSetSyncRangeFromEdid(pScrn, 0); + } + /* Get mode information */ + pScrn->progClock = TRUE; clockRanges = xnfcalloc(sizeof(*clockRanges), 1); clockRanges->next = NULL; clockRanges->minClock = info->pll.min_pll_freq; clockRanges->maxClock = info->pll.max_pll_freq * 10; clockRanges->clockIndex = -1; - clockRanges->interlaceAllowed = (info->CloneType == MT_CRT); - clockRanges->doubleScanAllowed = (info->CloneType == MT_CRT); + clockRanges->interlaceAllowed = (info->MergeType == MT_CRT); + clockRanges->doubleScanAllowed = (info->MergeType == MT_CRT); - /* Only take one clone mode from config file for now, rest of clone - * modes will copy from primary head. + /* We'll use our own mode validation routine for DFP/LCD, since + * xf86ValidateModes does not work correctly with the DFP/LCD modes + * 'stretched' from their native mode. */ - if ((s = xf86GetOptValString(info->Options, OPTION_CLONE_MODE))) { - if (sscanf(s, "%dx%d", &tmp_hdisplay, &tmp_vdisplay) == 2) { - if(count > 0) free(clone_mode_names[0]); - else count++; - clone_mode_names[0] = xnfalloc(strlen(s)+1); - sprintf(clone_mode_names[0], "%dx%d", tmp_hdisplay, tmp_vdisplay); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Clone mode %s in config file is used\n", clone_mode_names[0]); - } - } - - for (i = 0; i < count; i++) { - if (sscanf(clone_mode_names[i], "%dx%d", - &tmp_hdisplay, &tmp_vdisplay) == 2) { - if (pScrn->display->virtualX < tmp_hdisplay) - pScrn->display->virtualX = tmp_hdisplay; - if (pScrn->display->virtualY < tmp_vdisplay) - pScrn->display->virtualY = tmp_vdisplay; - } - } - - save_hsync = pScrn->monitor->hsync[0]; - save_vrefresh = pScrn->monitor->vrefresh[0]; - save_n_hsync = pScrn->monitor->nHsync; - save_n_vrefresh = pScrn->monitor->nVrefresh; - - pScrn->monitor->DDC = NULL; - pScrn->monitor->nHsync = 0; - pScrn->monitor->nVrefresh = 0; - - if ((s = xf86GetOptValString(info->Options, OPTION_CLONE_HSYNC))) { - if (sscanf(s, "%f-%f", &pScrn->monitor->hsync[0].lo, - &pScrn->monitor->hsync[0].hi) == 2) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "HSync for CloneMode from config file: %s\n", s); - pScrn->monitor->nHsync = 1; - } else { - pScrn->monitor->nHsync = 0; - } - } - - if ((s = xf86GetOptValString(info->Options, OPTION_CLONE_VREFRESH))) { - if (sscanf(s, "%f-%f", &pScrn->monitor->vrefresh[0].lo, - &pScrn->monitor->vrefresh[0].hi) == 2) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "VRefresh for CloneMode from config file: %s\n", s); - pScrn->monitor->nVrefresh = 1; - } else { - pScrn->monitor->nVrefresh = 0; - } - } - - pScrn->monitor->DDC = pRADEONEnt->MonInfo2; - if (pScrn->monitor->DDC) { - if ((pScrn->monitor->nVrefresh == 0) || (pScrn->monitor->nHsync == 0)) { - if (pScrn->monitor->nHsync == 0) - RADEONSetSyncRangeFromEdid(pScrn, 1); - if (pScrn->monitor->nVrefresh == 0) - RADEONSetSyncRangeFromEdid(pScrn, 0); - } - } else if (info->ddc_mode) { - ddc_mode = FALSE; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "No DDC data available for clone mode, " - "DDCMode option is dismissed\n"); - } + if (info->MergeType == MT_CRT && !info->ddc_mode) { - if (info->CloneType == MT_CRT && !ddc_mode) { modesFound = - xf86ValidateModes(pScrn, pScrn->monitor->Modes, - clone_mode_names, + xf86ValidateModes(pScrn, + pScrn->monitor->Modes, + pScrn1->display->modes, clockRanges, - NULL, /* linePitches */ - 8 * 64, /* minPitch */ - 8 * 1024, /* maxPitch */ - 64 * pScrn->bitsPerPixel, /* pitchInc */ - 128, /* minHeight */ - 2048, /* maxHeight */ - pScrn->display->virtualX, - pScrn->display->virtualY, + NULL, /* linePitches */ + 8 * 64, /* minPitch */ + 8 * 1024, /* maxPitch */ + info->allowColorTiling ? 2048 : + 64 * pScrn1->bitsPerPixel, /* pitchInc */ + 128, /* minHeight */ + info->MaxLines, /* maxHeight */ + pScrn1->display->virtualX ? pScrn1->virtualX : 0, + pScrn1->display->virtualY ? pScrn1->virtualY : 0, info->FbMapSize, LOOKUP_BEST_REFRESH); - } else { - /* Try to add DDC modes */ - info->IsSecondary = TRUE; /*fake secondary head*/ - modesFound = RADEONValidateDDCModes(pScrn, clone_mode_names, - info->CloneType); - info->IsSecondary = FALSE; - /* If that fails and we're connect to a flat panel, then try to - * add the flat panel modes - */ - if (modesFound < 1 && info->CloneType != MT_CRT) { - modesFound = - xf86ValidateModes(pScrn, pScrn->monitor->Modes, - clone_mode_names, - clockRanges, - NULL, /* linePitches */ - 8 * 64, /* minPitch */ - 8 * 1024, /* maxPitch */ - 64 * pScrn->bitsPerPixel, /* pitchInc */ - 128, /* minHeight */ - 2048, /* maxHeight */ - pScrn->display->virtualX, - pScrn->display->virtualY, - info->FbMapSize, - LOOKUP_BEST_REFRESH); - } - } - - if (modesFound > 0) { - int valid = 0; - save_mode = pScrn->modes; - xf86SetCrtcForModes(pScrn, 0); - xf86PrintModes(pScrn); - for (i = 0; i < modesFound; i++) { - - while (pScrn->modes->status != MODE_OK) { - pScrn->modes = pScrn->modes->next; - } - if (!pScrn->modes) break; - - if (pScrn->modes->Clock != 0.0) { - - clone_mode = xnfcalloc (1, sizeof (DisplayModeRec)); - if (!clone_mode) break; - memcpy(clone_mode, pScrn->modes, sizeof(DisplayModeRec)); - clone_mode->name = xnfalloc(strlen(pScrn->modes->name) + 1); - strcpy(clone_mode->name, pScrn->modes->name); - - if (!info->CurCloneMode) { - info->CloneModes = clone_mode; - info->CurCloneMode = clone_mode; - clone_mode->prev = NULL; - } else { - clone_mode->prev = tmp_mode; - clone_mode->prev->next = clone_mode; - } - valid++; + if (modesFound == -1) return 0; - tmp_mode = clone_mode; - clone_mode->next = NULL; - } - pScrn->modes = pScrn->modes->next; + xf86PruneDriverModes(pScrn); + if (!modesFound || !pScrn->modes) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes found\n"); + return 0; } - /* no longer needed, free it */ - pScrn->modes = save_mode; + } else { + /* First, free any allocated modes during configuration, since + * we don't need them + */ while (pScrn->modes) - xf86DeleteMode(&pScrn->modes, pScrn->modes); - pScrn->modes = NULL; - - /* modepool is no longer needed, free it */ + xf86DeleteMode(&pScrn->modes, pScrn->modes); while (pScrn->modePool) - xf86DeleteMode(&pScrn->modePool, pScrn->modePool); - pScrn->modePool = NULL; - - modesFound = valid; - } + xf86DeleteMode(&pScrn->modePool, pScrn->modePool); - /* Clone_mode_names list is no longer needed, free it. */ - if (clone_mode_names) { - for (i = 0; clone_mode_names[i]; i++) { - free(clone_mode_names[i]); - clone_mode_names[i] = NULL; - } + /* Next try to add DDC modes */ + modesFound = RADEONValidateDDCModes(pScrn, pScrn1->display->modes, + info->MergeType, 1); - free(clone_mode_names); - clone_mode_names = NULL; - } + /* If that fails and we're connect to a flat panel, then try to + * add the flat panel modes + */ + if (info->MergeType != MT_CRT) { - /* We need to restore all changed info for the primary head */ + /* some panels have DDC, but don't have internal scaler. + * in this case, we need to validate additional modes + * by using on-chip RMX. + */ + int user_modes_asked = 0, user_modes_found = 0, i; + DisplayModePtr tmp_mode = pScrn->modes; + while (pScrn1->display->modes[user_modes_asked]) user_modes_asked++; + if (tmp_mode) { + for (i = 0; i < modesFound; i++) { + if (tmp_mode->type & M_T_USERDEF) user_modes_found++; + tmp_mode = tmp_mode->next; + } + } - pScrn->monitor->hsync[0] = save_hsync; - pScrn->monitor->vrefresh[0] = save_vrefresh; - pScrn->monitor->nHsync = save_n_hsync; - pScrn->monitor->nVrefresh = save_n_vrefresh; + if ((modesFound <= 1) || (user_modes_found < user_modes_asked)) { + /* when panel size is not valid, try to validate + * mode using xf86ValidateModes routine + * This can happen when DDC is disabled. + */ + /* if (info->PanelXRes < 320 || info->PanelYRes < 200) */ + modesFound = + xf86ValidateModes(pScrn, + pScrn->monitor->Modes, + pScrn1->display->modes, + clockRanges, + NULL, /* linePitches */ + 8 * 64, /* minPitch */ + 8 * 1024, /* maxPitch */ + info->allowColorTiling ? 2048 : + 64 * pScrn1->bitsPerPixel, /* pitchInc */ + 128, /* minHeight */ + info->MaxLines, /* maxHeight */ + pScrn1->display->virtualX, + pScrn1->display->virtualY, + info->FbMapSize, + LOOKUP_BEST_REFRESH); - /* - * Also delete the clockRanges (if it was setup) since it will be - * set up during the primary head initialization. - */ - while (pScrn->clockRanges) { - ClockRangesPtr CRtmp = pScrn->clockRanges; - pScrn->clockRanges = pScrn->clockRanges->next; - xfree(CRtmp); - } + } + } + /* Setup the screen's clockRanges for the VidMode extension */ + if (!pScrn->clockRanges) { + pScrn->clockRanges = xnfcalloc(sizeof(*(pScrn->clockRanges)), 1); + memcpy(pScrn->clockRanges, clockRanges, sizeof(*clockRanges)); + pScrn->clockRanges->strategy = LOOKUP_BEST_REFRESH; + } + /* Fail if we still don't have any valid modes */ + if (modesFound < 1) { + if (info->MergeType == MT_CRT) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "No valid DDC modes found for this CRT\n"); + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Try turning off the \"DDCMode\" option\n"); + } else { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "No valid mode found for this DFP/LCD\n"); + } + return 0; + } + } return modesFound; } + /* This is called by RADEONPreInit to validate modes and compute * parameters for all of the valid modes. */ static Bool RADEONPreInitModes(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) { - RADEONInfoPtr info = RADEONPTR(pScrn); - ClockRangePtr clockRanges; - int modesFound; - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - char *s; + RADEONInfoPtr info = RADEONPTR(pScrn); + ClockRangePtr clockRanges; + int modesFound; + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + char *s; ModuleDescPtr pModule; /* This option has two purposes: @@ -3363,56 +3988,33 @@ * * Note: This option will be dismissed if no DDC data is available. */ + + if (info->MergedFB) { + if (!(pScrn->display->virtualX)) + info->NoVirtual = TRUE; + else + info->NoVirtual = FALSE; + } + info->ddc_mode = xf86ReturnOptValBool(info->Options, OPTION_DDC_MODE, FALSE); - /* don't use RMX if we have a dual-tdms panels */ + /* don't use RMX if we have a dual-tmds panels */ if (pRADEONEnt->MonType2 == MT_DFP) info->ddc_mode = TRUE; - - /* Here is a hack for cloning first display on the second head. If - * we don't do this, when both heads are connected, the same CRTC - * will be used to drive them according to the capability of the - * primary head. This can cause an unstable or blank screen, or - * even worse it can damage a monitor. This feature is also - * important for laptops (using M6, M7), where the panel can't be - * disconnect when one wants to use the CRT port. Although 2 - * Screens can be set up in the config file for displaying same - * content on two monitors, it has problems with cursor, overlay, - * DRI. - */ - if (info->HasCRTC2) { - if (info->Clone) { - - /* If we have 2 screens from the config file, we don't need - * to do clone thing, let each screen handles one head. - */ - if (!pRADEONEnt->HasSecondary) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Clone modes validation ------------ \n"); - - modesFound = RADEONValidateCloneModes(pScrn); - if (modesFound < 1) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "No valid mode found for CRTC2 clone\n"); - info->Clone = FALSE; - info->CurCloneMode = NULL; - } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Total of %d clone modes found ------------ \n\n", - modesFound); - } - } - } - + /* don't use RMX if we are Dell Server */ + if (info->IsDellServer) + { + info->ddc_mode = TRUE; + } xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Validating modes on %s head ---------\n", info->IsSecondary ? "Secondary" : "Primary"); if (info->IsSecondary) - pScrn->monitor->DDC = pRADEONEnt->MonInfo2; + pScrn->monitor->DDC = pRADEONEnt->MonInfo2; else - pScrn->monitor->DDC = pRADEONEnt->MonInfo1; + pScrn->monitor->DDC = pRADEONEnt->MonInfo1; if (!pScrn->monitor->DDC && info->ddc_mode) { info->ddc_mode = FALSE; @@ -3470,22 +4072,23 @@ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Invalid PanelSize value: %s\n", s); } - } + } else + RADEONGetPanelInfo(pScrn); } if (pScrn->monitor->DDC) { - /* If we still don't know sync range yet, let's try EDID. - * - * Note that, since we can have dual heads, Xconfigurator - * may not be able to probe both monitors correctly through - * vbe probe function (RADEONProbeDDC). Here we provide an - * additional way to auto-detect sync ranges if they haven't - * been added to XF86Config manually. - */ - if (pScrn->monitor->nHsync <= 0) - RADEONSetSyncRangeFromEdid(pScrn, 1); - if (pScrn->monitor->nVrefresh <= 0) - RADEONSetSyncRangeFromEdid(pScrn, 0); + /* If we still don't know sync range yet, let's try EDID. + * + * Note that, since we can have dual heads, Xconfigurator + * may not be able to probe both monitors correctly through + * vbe probe function (RADEONProbeDDC). Here we provide an + * additional way to auto-detect sync ranges if they haven't + * been added to XF86Config manually. + */ + if (pScrn->monitor->nHsync <= 0) + RADEONSetSyncRangeFromEdid(pScrn, 1); + if (pScrn->monitor->nVrefresh <= 0) + RADEONSetSyncRangeFromEdid(pScrn, 0); } /* Get mode information */ @@ -3512,9 +4115,10 @@ NULL, /* linePitches */ 8 * 64, /* minPitch */ 8 * 1024, /* maxPitch */ - 64 * pScrn->bitsPerPixel, /* pitchInc */ + info->allowColorTiling ? 2048 : + 64 * pScrn->bitsPerPixel, /* pitchInc */ 128, /* minHeight */ - 2048, /* maxHeight */ + info->MaxLines, /* maxHeight */ pScrn->display->virtualX, pScrn->display->virtualY, info->FbMapSize, @@ -3522,7 +4126,8 @@ if (modesFound < 1 && info->FBDev) { fbdevHWUseBuildinMode(pScrn); - pScrn->displayWidth = pScrn->virtualX; /* FIXME: might be wrong */ + pScrn->displayWidth = fbdevHWGetLineLength(pScrn) + / info->CurrentLayout.pixel_bytes; modesFound = 1; } @@ -3545,10 +4150,10 @@ /* Next try to add DDC modes */ modesFound = RADEONValidateDDCModes(pScrn, pScrn->display->modes, - info->DisplayType); + info->DisplayType, 0); /* If that fails and we're connect to a flat panel, then try to - * add the flat panel modes + * add the flat panel modes */ if (info->DisplayType != MT_CRT) { @@ -3580,9 +4185,10 @@ NULL, /* linePitches */ 8 * 64, /* minPitch */ 8 * 1024, /* maxPitch */ - 64 * pScrn->bitsPerPixel, /* pitchInc */ + info->allowColorTiling ? 2048 : + 64 * pScrn->bitsPerPixel, /* pitchInc */ 128, /* minHeight */ - 2048, /* maxHeight */ + info->MaxLines, /* maxHeight */ pScrn->display->virtualX, pScrn->display->virtualY, info->FbMapSize, @@ -3590,7 +4196,7 @@ else if (!info->IsSecondary) modesFound = RADEONValidateFPModes(pScrn, pScrn->display->modes); } - } + } /* Setup the screen's clockRanges for the VidMode extension */ if (!pScrn->clockRanges) { @@ -3616,30 +4222,114 @@ xf86SetCrtcForModes(pScrn, 0); - /* We need to adjust virtual size if the clone modes have larger - * display size. - */ - if (info->Clone && info->CloneModes) { - DisplayModePtr clone_mode = info->CloneModes; - while (1) { - if ((clone_mode->HDisplay > pScrn->virtualX) || - (clone_mode->VDisplay > pScrn->virtualY)) { - pScrn->virtualX = - pScrn->display->virtualX = clone_mode->HDisplay; - pScrn->virtualY = - pScrn->display->virtualY = clone_mode->VDisplay; - RADEONSetPitch(pScrn); + if (info->HasCRTC2) { + if (info->MergedFB) { + + /* If we have 2 screens from the config file, we don't need + * to do clone thing, let each screen handles one head. + */ + if (!pRADEONEnt->HasSecondary) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Validating CRTC2 modes for MergedFB ------------ \n"); + + modesFound = RADEONValidateMergeModes(pScrn); + if (modesFound < 1) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "No valid mode found for CRTC2, disabling MergedFB\n"); + info->MergedFB = FALSE; + } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Total of %d CRTC2 modes found for MergedFB------------ \n", + modesFound); } - if (!clone_mode->next) break; - clone_mode = clone_mode->next; } } pScrn->currentMode = pScrn->modes; + if(info->MergedFB) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Modes for CRT1: ********************\n"); + } xf86PrintModes(pScrn); + if(info->MergedFB) { + + xf86SetCrtcForModes(info->CRT2pScrn, INTERLACE_HALVE_V); + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Modes for CRT2: ********************\n"); + + xf86PrintModes(info->CRT2pScrn); + + info->CRT1Modes = pScrn->modes; + info->CRT1CurrentMode = pScrn->currentMode; + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Generating MergedFB mode list\n"); + + if (info->NoVirtual) { + pScrn->display->virtualX = 0; + pScrn->display->virtualY = 0; + } + pScrn->modes = RADEONGenerateModeList(pScrn, info->MetaModes, + info->CRT1Modes, info->CRT2pScrn->modes, + info->CRT2Position); + + if(!pScrn->modes) { + + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Failed to parse MetaModes or no modes found. MergeFB mode disabled.\n"); + if(info->CRT2pScrn) { + if(info->CRT2pScrn->modes) { + while(info->CRT2pScrn->modes) + xf86DeleteMode(&info->CRT2pScrn->modes, info->CRT2pScrn->modes); + } + if(info->CRT2pScrn->monitor) { + if(info->CRT2pScrn->monitor->Modes) { + while(info->CRT2pScrn->monitor->Modes) + xf86DeleteMode(&info->CRT2pScrn->monitor->Modes, info->CRT2pScrn->monitor->Modes); + } + if(info->CRT2pScrn->monitor->DDC) xfree(info->CRT2pScrn->monitor->DDC); + xfree(info->CRT2pScrn->monitor); + } + xfree(info->CRT2pScrn); + info->CRT2pScrn = NULL; + } + pScrn->modes = info->CRT1Modes; + info->CRT1Modes = NULL; + info->MergedFB = FALSE; + + } + } + + if (info->MergedFB) { + /* If no virtual dimension was given by the user, + * calculate a sane one now. Adapts pScrn->virtualX, + * pScrn->virtualY and pScrn->displayWidth. + */ + RADEONRecalcDefaultVirtualSize(pScrn); + info->CRT2pScrn->virtualX = pScrn->virtualX; + info->CRT2pScrn->virtualY = pScrn->virtualY; + RADEONSetPitch(pScrn); + RADEONSetPitch(info->CRT2pScrn); + + pScrn->modes = pScrn->modes->next; /* We get the last from GenerateModeList() */ + pScrn->currentMode = pScrn->modes; + + /* Update CurrentLayout */ + info->CurrentLayout.mode = pScrn->currentMode; + info->CurrentLayout.displayWidth = pScrn->displayWidth; + } + /* Set DPI */ - xf86SetDpi(pScrn, 0, 0); + /* xf86SetDpi(pScrn, 0, 0); */ + + if (info->MergedFB) { + RADEONMergedFBSetDpi(pScrn, info->CRT2pScrn, info->CRT2Position); + } else { + xf86SetDpi(pScrn, 0, 0); + info->RADEONDPIVX = pScrn->virtualX; + info->RADEONDPIVY = pScrn->virtualY; + } /* Get ScreenInit function */ if (!(pModule = xf86LoadSubModule(pScrn, "fb"))) return FALSE; @@ -3655,7 +4345,7 @@ /* This is called by RADEONPreInit to initialize the hardware cursor */ static Bool RADEONPreInitCursor(ScrnInfoPtr pScrn) { - RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); ModuleDescPtr pModule; if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { @@ -3669,12 +4359,15 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) { #ifdef XFree86LOADER - RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); ModuleDescPtr pModule; if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { int errmaj = 0, errmin = 0; + xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, + "Using XAA acceleration architecture\n"); + info->xaaReq.majorversion = 1; info->xaaReq.minorversion = 1; @@ -3691,7 +4384,7 @@ } xf86LoaderModReqSymLists(pModule, xaaSymbols, NULL); } -#endif +#endif /* XFree86Loader */ return TRUE; } @@ -3700,12 +4393,31 @@ { #if !defined(__powerpc__) RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + CARD32 fp2_gen_ctl_save = 0; ModuleDescPtr pModule; if ((pModule = xf86LoadSubModule(pScrn, "int10"))) { xf86LoaderModReqSymLists(pModule, int10Symbols, NULL); + + /* The VGA BIOS on the RV100/QY cannot be read when the digital output + * is enabled. Clear and restore FP2_ON around int10 to avoid this. + */ + if (info->PciInfo->chipType == PCI_CHIP_RV100_QY) { + fp2_gen_ctl_save = INREG(RADEON_FP2_GEN_CNTL); + if (fp2_gen_ctl_save & RADEON_FP2_ON) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "disabling digital out\n"); + OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save & ~RADEON_FP2_ON); + } + } + xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n"); *ppInt10 = xf86InitInt10(info->pEnt->index); + + if (fp2_gen_ctl_save & RADEON_FP2_ON) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n"); + OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save); + } } #endif return TRUE; @@ -3714,8 +4426,67 @@ #ifdef XF86DRI static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) { - RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); ModuleDescPtr pModule; + MessageType from; + + info->directRenderingEnabled = FALSE; + info->directRenderingInited = FALSE; + info->CPInUse = FALSE; + info->CPStarted = FALSE; + info->pLibDRMVersion = NULL; + info->pKernelDRMVersion = NULL; + + if (xf86IsEntityShared(info->pEnt->index)) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Direct Rendering Disabled -- " + "Dual-head configuration is not working with " + "DRI at present.\n" + "Please use the radeon MergedFB option if you " + "want Dual-head with DRI.\n"); + return FALSE; + } + if (info->IsSecondary) + return FALSE; + + if (info->Chipset == PCI_CHIP_RN50_515E || + info->Chipset == PCI_CHIP_RN50_5969) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Direct rendering not supported on RN50\n"); + return FALSE; + } + + if (info->Chipset == PCI_CHIP_RS400_5A41 || + info->Chipset == PCI_CHIP_RS400_5A42 || + info->Chipset == PCI_CHIP_RC410_5A61 || + info->Chipset == PCI_CHIP_RC410_5A62 || + info->Chipset == PCI_CHIP_RS480_5954 || + info->Chipset == PCI_CHIP_RS480_5955 || + info->Chipset == PCI_CHIP_RS482_5974 || + info->Chipset == PCI_CHIP_RS482_5975) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Direct rendering broken on XPRESS 200 and 200M\n"); + return FALSE; + } + + if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "[dri] Acceleration disabled, not initializing the DRI\n"); + return FALSE; + } + + if (!RADEONDRIGetVersion(pScrn)) + return FALSE; + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "[dri] Found DRI library version %d.%d.%d and kernel" + " module version %d.%d.%d\n", + info->pLibDRMVersion->version_major, + info->pLibDRMVersion->version_minor, + info->pLibDRMVersion->version_patchlevel, + info->pKernelDRMVersion->version_major, + info->pKernelDRMVersion->version_minor, + info->pKernelDRMVersion->version_patchlevel); if (xf86ReturnOptValBool(info->Options, OPTION_CP_PIO, FALSE)) { xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forcing CP into PIO mode\n"); @@ -3733,16 +4504,23 @@ info->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; - if (!info->IsPCI) { + if (info->cardType==CARD_AGP) { if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &(info->agpMode))) { if (info->agpMode < 1 || info->agpMode > RADEON_AGP_MAX_MODE) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Illegal AGP Mode: %d\n", info->agpMode); - return FALSE; + "Illegal AGP Mode: %dx, set to default %dx mode\n", + info->agpMode, RADEON_DEFAULT_AGP_MODE); + info->agpMode = RADEON_DEFAULT_AGP_MODE; } + + /* AGP_MAX_MODE is changed to allow v3 8x mode. + * At this time we don't know if the AGP bridge supports + * 8x mode. This will later be verified on both + * AGP master and target sides. + */ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, - "Using AGP %dx mode\n", info->agpMode); + "AGP %dx mode is configured\n", info->agpMode); } if ((info->agpFastWrite = xf86ReturnOptValBool(info->Options, @@ -3756,8 +4534,10 @@ } } - if (xf86GetOptValInteger(info->Options, - OPTION_GART_SIZE, (int *)&(info->gartSize))) { + if ((xf86GetOptValInteger(info->Options, + OPTION_GART_SIZE, (int *)&(info->gartSize))) || + (xf86GetOptValInteger(info->Options, + OPTION_GART_SIZE_OLD, (int *)&(info->gartSize)))) { switch (info->gartSize) { case 4: case 8: @@ -3817,15 +4597,6 @@ /* This option checked by the RADEON DRM kernel module */ } - /* Depth moves are disabled by default since they are extremely slow */ - if ((info->depthMoves = xf86ReturnOptValBool(info->Options, - OPTION_DEPTH_MOVE, FALSE))) { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling depth moves\n"); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Depth moves disabled by default\n"); - } - /* Two options to try and squeeze as much texture memory as possible * for dedicated 3d rendering boxes */ @@ -3850,33 +4621,161 @@ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Page flipping %sabled\n", info->allowPageFlip ? "en" : "dis"); + info->DMAForXv = TRUE; + from = xf86GetOptValBool(info->Options, OPTION_XV_DMA, &info->DMAForXv) + ? X_CONFIG : X_INFO; + xf86DrvMsg(pScrn->scrnIndex, from, + "Will %stry to use DMA for Xv image transfers\n", + info->DMAForXv ? "" : "not "); + + return TRUE; +} +#endif /* XF86DRI */ + +static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + + info->allowColorTiling = xf86ReturnOptValBool(info->Options, + OPTION_COLOR_TILING, TRUE); + if (IS_R300_VARIANT) { + info->MaxSurfaceWidth = 3968; /* one would have thought 4096...*/ + info->MaxLines = 4096; + } else { + info->MaxSurfaceWidth = 2048; + info->MaxLines = 2048; + } + + if (!info->allowColorTiling) + return; + +#ifdef XF86DRI + if (info->directRenderingEnabled && + info->pKernelDRMVersion->version_minor < 14) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "[dri] color tiling disabled because of version " + "mismatch.\n" + "[dri] radeon.o kernel module version is %d.%d.%d but " + "1.14.0 or later is required for color tiling.\n", + info->pKernelDRMVersion->version_major, + info->pKernelDRMVersion->version_minor, + info->pKernelDRMVersion->version_patchlevel); + info->allowColorTiling = FALSE; + return; + } +#endif /* XF86DRI */ + + if ((info->allowColorTiling) && (info->IsSecondary)) { + /* can't have tiling on the 2nd head (as long as it can't use drm). + * We'd never get the surface save/restore (vt switching) right... + */ + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling disabled for 2nd head\n"); + info->allowColorTiling = FALSE; + } + else if ((info->allowColorTiling) && (info->FBDev)) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Color tiling not supported with UseFBDev option\n"); + info->allowColorTiling = FALSE; + } + else if (info->allowColorTiling) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling enabled by default\n"); + } else { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling disabled\n"); + } +} + + +static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + CARD16 mm_table; + CARD16 bios_header; + CARD16 pll_info_block; + + /* Rescue MM_TABLE before VBIOS is freed */ + info->MM_TABLE_valid = FALSE; + + if((info->VBIOS==NULL)||(info->VBIOS[0]!=0x55)||(info->VBIOS[1]!=0xaa)){ + info->MM_TABLE_valid = FALSE; + return TRUE; + } + + bios_header=info->VBIOS[0x48]; + bios_header+=(((int)info->VBIOS[0x49]+0)<<8); + + mm_table=info->VBIOS[bios_header+0x38]; + if(mm_table==0) + { + xf86DrvMsg(pScrn->scrnIndex,X_INFO,"No MM_TABLE found - assuming CARD is not TV-in capable.\n"); + info->MM_TABLE_valid = FALSE; + return TRUE; + } + mm_table+=(((int)info->VBIOS[bios_header+0x39]+0)<<8)-2; + + if(mm_table>0) + { + memcpy(&(info->MM_TABLE), &(info->VBIOS[mm_table]), sizeof(info->MM_TABLE)); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "MM_TABLE: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", + info->MM_TABLE.table_revision, + info->MM_TABLE.table_size, + info->MM_TABLE.tuner_type, + info->MM_TABLE.audio_chip, + info->MM_TABLE.product_id, + info->MM_TABLE.tuner_voltage_teletext_fm, + info->MM_TABLE.i2s_config, + info->MM_TABLE.video_decoder_type, + info->MM_TABLE.video_decoder_host_config, + info->MM_TABLE.input[0], + info->MM_TABLE.input[1], + info->MM_TABLE.input[2], + info->MM_TABLE.input[3], + info->MM_TABLE.input[4]); + + /* Is it an MM_TABLE we know about ? */ + if(info->MM_TABLE.table_size != 0xc){ + info->MM_TABLE_valid = FALSE; + return TRUE; + } + info->MM_TABLE_valid = TRUE; + } else { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No MM_TABLE found - assuming card is not TV-in capable (mm_table=%d).\n", mm_table); + info->MM_TABLE_valid = FALSE; + } + + pll_info_block=info->VBIOS[bios_header+0x30]; + pll_info_block+=(((int)info->VBIOS[bios_header+0x31]+0)<<8); + + info->video_decoder_type=info->VBIOS[pll_info_block+0x08]; + info->video_decoder_type+=(((int)info->VBIOS[pll_info_block+0x09]+0)<<8); + return TRUE; } -#endif static void RADEONProbeDDC(ScrnInfoPtr pScrn, int indx) { - vbeInfoPtr pVbe; - ModuleDescPtr pModule; + vbeInfoPtr pVbe; + pointer pModule; if ((pModule = xf86LoadVBEModule(pScrn))) { xf86LoaderModReqSymLists(pModule, vbeSymbols, NULL); - pVbe = VBEInit(NULL,indx); - ConfiguredMonitor = vbeDoEDID(pVbe, NULL); - vbeFree(pVbe); + if ((pVbe = VBEInit(NULL, indx))) { + ConfiguredMonitor = vbeDoEDID(pVbe, NULL); + vbeFree(pVbe); + } xf86UnloadSubModule(pModule); } } -/* RADEONPreInit is called once at server startup */ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) { RADEONInfoPtr info; xf86Int10InfoPtr pInt10 = NULL; void *int10_save = NULL; const char *s; + unsigned char *RADEONMMIO; ModuleDescPtr pModule; + MessageType from; RADEONTRACE(("RADEONPreInit\n")); if (pScrn->numEntities != 1) return FALSE; @@ -3885,9 +4784,8 @@ info = RADEONPTR(pScrn); info->IsSecondary = FALSE; - info->Clone = FALSE; - info->CurCloneMode = NULL; - info->CloneModes = NULL; + info->IsPrimary = FALSE; + info->MergedFB = FALSE; info->IsSwitching = FALSE; info->MMIO = NULL; @@ -3914,7 +4812,7 @@ if(!RADEONMapMMIO(pScrn)) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Memory map the MMIO region failed\n"); + "Memory map of MMIO region failed\n"); goto fail1; } @@ -3947,6 +4845,8 @@ } else { RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + info->IsPrimary = TRUE; + xf86SetPrimInitDone(info->pEnt->index); pRADEONEnt->pPrimaryScrn = pScrn; @@ -3962,15 +4862,6 @@ return TRUE; } - if (!(pModule = xf86LoadSubModule(pScrn, "vgahw"))) return FALSE; - xf86LoaderModReqSymLists(pModule, vgahwSymbols, NULL); - if (!vgaHWGetHWRec(pScrn)) { - RADEONFreeRec(pScrn); - goto fail2; - } - - vgaHWGetIOBase(VGAHWPTR(pScrn)); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PCI bus %d card %d func %d\n", info->PciInfo->bus, @@ -4021,6 +4912,25 @@ info->DispPriority = 1; } + info->constantDPI = -1; + from = X_DEFAULT; + if (xf86GetOptValBool(info->Options, OPTION_CONSTANTDPI, &info->constantDPI)) { + from = X_CONFIG; + } else { + if (monitorResolution > 0) { + info->constantDPI = TRUE; + from = X_CMDLINE; + xf86DrvMsg(pScrn->scrnIndex, from, + "\"-dpi %d\" given in command line, assuming \"ConstantDPI\" set\n", + monitorResolution); + } else { + info->constantDPI = FALSE; + } + } + xf86DrvMsg(pScrn->scrnIndex, from, + "X server will %skeep DPI constant for all screen sizes\n", + info->constantDPI ? "" : "not "); + if (xf86ReturnOptValBool(info->Options, OPTION_FBDEV, FALSE)) { /* check for Linux framebuffer device */ @@ -4048,18 +4958,50 @@ RADEONPostInt10Check(pScrn, int10_save); - if (!RADEONPreInitConfig(pScrn)) + RADEONMMIO = info->MMIO; + + /* + * Don't use vgaHW if the adapter is found to be in an accelerator video + * mode on entry, as some Radeons do not respond to VGA accesses when in + * such a mode. This means that saving & restoring video memory contents + * is left up to the background system. + */ + info->UseVGAHW = !(INREG(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EXT_DISP_EN); + if (info->UseVGAHW) { + if (!(pModule = xf86LoadSubModule(pScrn, "vgahw"))) goto fail2; + xf86LoaderModReqSymLists(pModule, vgahwSymbols, NULL); + if (!vgaHWGetHWRec(pScrn)) goto fail2; + + vgaHWGetIOBase(VGAHWPTR(pScrn)); + } + + if (!RADEONPreInitChipType(pScrn)) goto fail; - RADEONPreInitDDC(pScrn); +#ifdef XF86DRI + /* PreInit DRI first of all since we need that for getting a proper + * memory map + */ + info->directRenderingEnabled = RADEONPreInitDRI(pScrn); +#endif - if (!RADEONGetBIOSParameters(pScrn, pInt10)) + if (!RADEONPreInitVRAM(pScrn)) goto fail; - if (info->DisplayType == MT_DFP) - RADEONGetTMDSInfo(pScrn); + RADEONPreInitColorTiling(pScrn); + + RADEONPreInitDDC(pScrn); - if (!RADEONGetPLLParameters(pScrn)) goto fail; + RADEONGetBIOSInfo(pScrn, pInt10); + if (!RADEONQueryConnectedMonitors(pScrn)) goto fail; + RADEONGetClockInfo(pScrn); + + /* collect MergedFB options */ + /* only parse mergedfb options on the primary head. + Mergedfb is already disabled in xinerama/screen based + multihead */ + if (!info->IsSecondary) + RADEONGetMergedFBOptions(pScrn); if (!RADEONPreInitGamma(pScrn)) goto fail; @@ -4069,11 +5011,9 @@ if (!RADEONPreInitAccel(pScrn)) goto fail; -#ifdef XF86DRI - if (!RADEONPreInitDRI(pScrn)) goto fail; -#endif + if (!RADEONPreInitXv(pScrn)) goto fail; - /* Free the video bios (if applicable) */ + /* Free the video bios (if applicable) */ if (info->VBIOS) { xfree(info->VBIOS); info->VBIOS = NULL; @@ -4086,16 +5026,12 @@ if(info->MMIO) RADEONUnmapMMIO(pScrn); info->MMIO = NULL; - xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, - "For information on using the multimedia capabilities\n of this" - " adapter, please see http://gatos.sf.net.\n"); - return TRUE; fail: /* Pre-init failed. */ if (info->IsSecondary) { - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); pRADEONEnt->HasSecondary = FALSE; } /* Free the video bios (if applicable) */ @@ -4104,15 +5040,17 @@ info->VBIOS = NULL; } + if (info->UseVGAHW) + vgaHWFreeHWRec(pScrn); + +fail2: /* Free int10 info */ if (pInt10) xf86FreeInt10(pInt10); - vgaHWFreeHWRec(pScrn); - - fail2: if(info->MMIO) RADEONUnmapMMIO(pScrn); info->MMIO = NULL; + fail1: RADEONFreeRec(pScrn); @@ -4130,10 +5068,11 @@ unsigned char r, g, b; #ifdef XF86DRI - if (info->CPStarted) DRILock(pScrn->pScreen, 0); + if (info->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); #endif - if (info->accelOn) info->accel->Sync(pScrn); + if (info->accelOn && pScrn->pScreen && info->accel) + (*info->accel->Sync)(pScrn); if (info->FBDev) { fbdevHWLoadPalette(pScrn, numColors, indices, colors, pVisual); @@ -4194,7 +5133,7 @@ } } - if (info->Clone) { + if (info->MergedFB) { PAL_SELECT(1); if (info->CurrentLayout.depth == 15) { /* 15bpp mode. This sends 32 values. */ @@ -4244,7 +5183,7 @@ } #ifdef XF86DRI - if (info->CPStarted) DRIUnlock(pScrn->pScreen); + if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); #endif } @@ -4256,10 +5195,10 @@ RADEONInfoPtr info = RADEONPTR(pScrn); #ifdef XF86DRI - if (info->directRenderingEnabled) + if (info->directRenderingInited) { FLUSH_RING(); + } #endif - pScreen->BlockHandler = info->BlockHandler; (*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask); pScreen->BlockHandler = RADEONBlockHandler; @@ -4268,25 +5207,348 @@ (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); } + +#ifdef XF86DRI +static Bool RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); + int cpp = info->CurrentLayout.pixel_bytes; + int depthCpp = (info->depthBits - 8) / 4; + int width_bytes = pScrn->displayWidth * cpp; + int bufferSize; + int depthSize; + int l; + int scanlines; + int texsizerequest; + BoxRec MemBox; + FBAreaPtr fbarea; + + info->frontOffset = 0; + info->frontPitch = pScrn->displayWidth; + info->backPitch = pScrn->displayWidth; + + /* make sure we use 16 line alignment for tiling (8 might be enough). + * Might need that for non-XF86DRI too? + */ + if (info->allowColorTiling) { + bufferSize = (((pScrn->virtualY + 15) & ~15) * width_bytes + + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN; + } else { + bufferSize = (pScrn->virtualY * width_bytes + + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN; + } + + /* Due to tiling, the Z buffer pitch must be a multiple of 32 pixels, + * which is always the case if color tiling is used due to color pitch + * but not necessarily otherwise, and its height a multiple of 16 lines. + */ + info->depthPitch = (pScrn->displayWidth + 31) & ~31; + depthSize = ((((pScrn->virtualY + 15) & ~15) * info->depthPitch + * depthCpp + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); + + switch (info->CPMode) { + case RADEON_DEFAULT_CP_PIO_MODE: + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in PIO mode\n"); + break; + case RADEON_DEFAULT_CP_BM_MODE: + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in BM mode\n"); + break; + default: + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in UNKNOWN mode\n"); + break; + } + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Using %d MB GART aperture\n", info->gartSize); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Using %d MB for the ring buffer\n", info->ringSize); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Using %d MB for vertex/indirect buffers\n", info->bufSize); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Using %d MB for GART textures\n", info->gartTexSize); + + /* Try for front, back, depth, and three framebuffers worth of + * pixmap cache. Should be enough for a fullscreen background + * image plus some leftovers. + */ + if (info->textureSize >= 0) { + texsizerequest = ((int)info->FbMapSize - 2 * bufferSize - depthSize + - 2 * width_bytes - 16384 - info->FbSecureSize) + /* first divide, then multiply or we'll get an overflow (been there...) */ + / 100 * info->textureSize; + } + else { + texsizerequest = (int)info->FbMapSize / 2; + } + info->textureSize = info->FbMapSize - info->FbSecureSize - 5 * bufferSize - depthSize; + + /* If that gives us less than the requested memory, let's + * be greedy and grab some more. Sorry, I care more about 3D + * performance than playing nicely, and you'll get around a full + * framebuffer's worth of pixmap cache anyway. + */ + if (info->textureSize < texsizerequest) { + info->textureSize = info->FbMapSize - 4 * bufferSize - depthSize; + } + if (info->textureSize < texsizerequest) { + info->textureSize = info->FbMapSize - 3 * bufferSize - depthSize; + } + + /* If there's still no space for textures, try without pixmap cache, but + * never use the reserved space, the space hw cursor and PCIGART table might + * use. + */ + if (info->textureSize < 0) { + info->textureSize = info->FbMapSize - 2 * bufferSize - depthSize + - 2 * width_bytes - 16384 - info->FbSecureSize; + } + + /* Check to see if there is more room available after the 8192nd + * scanline for textures + */ + /* FIXME: what's this good for? condition is pretty much impossible to meet */ + if ((int)info->FbMapSize - 8192*width_bytes - bufferSize - depthSize + > info->textureSize) { + info->textureSize = + info->FbMapSize - 8192*width_bytes - bufferSize - depthSize; + } + + /* If backbuffer is disabled, don't allocate memory for it */ + if (info->noBackBuffer) { + info->textureSize += bufferSize; + } + + /* RADEON_BUFFER_ALIGN is not sufficient for backbuffer! + At least for pageflip + color tiling, need to make sure it's 16 scanlines aligned, + otherwise the copy-from-front-to-back will fail (width_bytes * 16 will also guarantee + it's still 4kb aligned for tiled case). Need to round up offset (might get into cursor + area otherwise). + This might cause some space at the end of the video memory to be unused, since it + can't be used (?) due to that log_tex_granularity thing??? + Could use different copyscreentoscreen function for the pageflip copies + (which would use different src and dst offsets) to avoid this. */ + if (info->allowColorTiling && !info->noBackBuffer) { + info->textureSize = info->FbMapSize - ((info->FbMapSize - info->textureSize + + width_bytes * 16 - 1) / (width_bytes * 16)) * (width_bytes * 16); + } + if (info->textureSize > 0) { + l = RADEONMinBits((info->textureSize-1) / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) + l = RADEON_LOG_TEX_GRANULARITY; + /* Round the texture size up to the nearest whole number of + * texture regions. Again, be greedy about this, don't + * round down. + */ + info->log2TexGran = l; + info->textureSize = (info->textureSize >> l) << l; + } else { + info->textureSize = 0; + } + + /* Set a minimum usable local texture heap size. This will fit + * two 256x256x32bpp textures. + */ + if (info->textureSize < 512 * 1024) { + info->textureOffset = 0; + info->textureSize = 0; + } + + if (info->allowColorTiling && !info->noBackBuffer) { + info->textureOffset = ((info->FbMapSize - info->textureSize) / + (width_bytes * 16)) * (width_bytes * 16); + } + else { + /* Reserve space for textures */ + info->textureOffset = ((info->FbMapSize - info->textureSize + + RADEON_BUFFER_ALIGN) & + ~(CARD32)RADEON_BUFFER_ALIGN); + } + + /* Reserve space for the shared depth + * buffer. + */ + info->depthOffset = ((info->textureOffset - depthSize + + RADEON_BUFFER_ALIGN) & + ~(CARD32)RADEON_BUFFER_ALIGN); + + /* Reserve space for the shared back buffer */ + if (info->noBackBuffer) { + info->backOffset = info->depthOffset; + } else { + info->backOffset = ((info->depthOffset - bufferSize + + RADEON_BUFFER_ALIGN) & + ~(CARD32)RADEON_BUFFER_ALIGN); + } + + info->backY = info->backOffset / width_bytes; + info->backX = (info->backOffset - (info->backY * width_bytes)) / cpp; + + scanlines = (info->FbMapSize-info->FbSecureSize) / width_bytes; + if (scanlines > 8191) + scanlines = 8191; + + MemBox.x1 = 0; + MemBox.y1 = 0; + MemBox.x2 = pScrn->displayWidth; + MemBox.y2 = scanlines; + + if (!xf86InitFBManager(pScreen, &MemBox)) { + xf86DrvMsg(scrnIndex, X_ERROR, + "Memory manager initialization to " + "(%d,%d) (%d,%d) failed\n", + MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2); + return FALSE; + } else { + int width, height; + + xf86DrvMsg(scrnIndex, X_INFO, + "Memory manager initialized to (%d,%d) (%d,%d)\n", + MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2); + /* why oh why can't we just request modes which are guaranteed to be 16 lines + aligned... sigh */ + if ((fbarea = xf86AllocateOffscreenArea(pScreen, + pScrn->displayWidth, + info->allowColorTiling ? + ((pScrn->virtualY + 15) & ~15) + - pScrn->virtualY + 2 : 2, + 0, NULL, NULL, + NULL))) { + xf86DrvMsg(scrnIndex, X_INFO, + "Reserved area from (%d,%d) to (%d,%d)\n", + fbarea->box.x1, fbarea->box.y1, + fbarea->box.x2, fbarea->box.y2); + } else { + xf86DrvMsg(scrnIndex, X_ERROR, "Unable to reserve area\n"); + } + + RADEONDRIAllocatePCIGARTTable(pScreen); + + if (xf86QueryLargestOffscreenArea(pScreen, &width, + &height, 0, 0, 0)) { + xf86DrvMsg(scrnIndex, X_INFO, + "Largest offscreen area available: %d x %d\n", + width, height); + + /* Lines in offscreen area needed for depth buffer and + * textures + */ + info->depthTexLines = (scanlines + - info->depthOffset / width_bytes); + info->backLines = (scanlines + - info->backOffset / width_bytes + - info->depthTexLines); + info->backArea = NULL; + } else { + xf86DrvMsg(scrnIndex, X_ERROR, + "Unable to determine largest offscreen area " + "available\n"); + return FALSE; + } + } + + xf86DrvMsg(scrnIndex, X_INFO, + "Will use back buffer at offset 0x%x\n", + info->backOffset); + xf86DrvMsg(scrnIndex, X_INFO, + "Will use depth buffer at offset 0x%x\n", + info->depthOffset); + if (info->cardType==CARD_PCIE) + xf86DrvMsg(scrnIndex, X_INFO, + "Will use %d kb for PCI GART table at offset 0x%x\n", + info->pciGartSize/1024, info->pciGartOffset); + xf86DrvMsg(scrnIndex, X_INFO, + "Will use %d kb for textures at offset 0x%x\n", + info->textureSize/1024, info->textureOffset); + + info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) | + ((info->frontOffset + info->fbLocation) >> 10)); + + info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) | + ((info->backOffset + info->fbLocation) >> 10)); + + info->depthPitchOffset = (((info->depthPitch * depthCpp / 64) << 22) | + ((info->depthOffset + info->fbLocation) >> 10)); + return TRUE; +} +#endif /* XF86DRI */ + +static Bool RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); + BoxRec MemBox; + int y2; + + int width_bytes = pScrn->displayWidth * info->CurrentLayout.pixel_bytes; + + MemBox.x1 = 0; + MemBox.y1 = 0; + MemBox.x2 = pScrn->displayWidth; + y2 = info->FbMapSize / width_bytes; + if (y2 >= 32768) + y2 = 32767; /* because MemBox.y2 is signed short */ + MemBox.y2 = y2; + + /* The acceleration engine uses 14 bit + * signed coordinates, so we can't have any + * drawable caches beyond this region. + */ + if (MemBox.y2 > 8191) + MemBox.y2 = 8191; + + if (!xf86InitFBManager(pScreen, &MemBox)) { + xf86DrvMsg(scrnIndex, X_ERROR, + "Memory manager initialization to " + "(%d,%d) (%d,%d) failed\n", + MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2); + return FALSE; + } else { + int width, height; + FBAreaPtr fbarea; + + xf86DrvMsg(scrnIndex, X_INFO, + "Memory manager initialized to (%d,%d) (%d,%d)\n", + MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2); + if ((fbarea = xf86AllocateOffscreenArea(pScreen, + pScrn->displayWidth, + info->allowColorTiling ? + ((pScrn->virtualY + 15) & ~15) + - pScrn->virtualY + 2 : 2, + 0, NULL, NULL, + NULL))) { + xf86DrvMsg(scrnIndex, X_INFO, + "Reserved area from (%d,%d) to (%d,%d)\n", + fbarea->box.x1, fbarea->box.y1, + fbarea->box.x2, fbarea->box.y2); + } else { + xf86DrvMsg(scrnIndex, X_ERROR, "Unable to reserve area\n"); + } + if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, + 0, 0, 0)) { + xf86DrvMsg(scrnIndex, X_INFO, + "Largest offscreen area available: %d x %d\n", + width, height); + } + return TRUE; + } +} + /* Called at the start of each server generation. */ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, const int argc, const char **argv) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); - BoxRec MemBox; - int y2; + int hasDRI = 0; + int subPixelOrder = SubPixelUnknown; + char* s; - RADEONTRACE(("RADEONScreenInit %x %d\n", + RADEONTRACE(("RADEONScreenInit %lx %ld\n", pScrn->memPhysBase, pScrn->fbOffset)); -#ifdef XF86DRI - /* Turn off the CP for now. */ - info->CPInUse = FALSE; - info->CPStarted = FALSE; - info->directRenderingEnabled = FALSE; -#endif info->accelOn = FALSE; + info->accel = NULL; pScrn->fbOffset = 0; if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024; if (!RADEONMapMem(pScrn)) return FALSE; @@ -4299,28 +5561,39 @@ info->PaletteSavedOnVT = FALSE; RADEONSave(pScrn); - if (info->FBDev) { - unsigned char *RADEONMMIO = info->MMIO; - - if (!fbdevHWModeInit(pScrn, pScrn->currentMode)) return FALSE; - info->ModeReg.surface_cntl = INREG(RADEON_SURFACE_CNTL); - } else { - if (!RADEONModeInit(pScrn, pScrn->currentMode)) return FALSE; - } - RADEONSaveScreen(pScreen, SCREEN_SAVER_ON); + if ((!info->IsSecondary) && info->IsMobility) { + if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { + RADEONSetDynamicClock(pScrn, 1); + } else { + RADEONSetDynamicClock(pScrn, 0); + } + } - pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); + if ((!info->IsSecondary) && (IS_R300_VARIANT || IS_RV100_VARIANT)) + RADEONForceSomeClocks(pScrn); - if (info->CurCloneMode) { - info->CloneFrameX0 = - (pScrn->virtualX - info->CurCloneMode->HDisplay) / 2; - info->CloneFrameY0 = - (pScrn->virtualY - info->CurCloneMode->VDisplay) / 2; - RADEONDoAdjustFrame(pScrn, info->CloneFrameX0, info->CloneFrameY0, TRUE); + if (info->allowColorTiling && (pScrn->virtualX > info->MaxSurfaceWidth)) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Color tiling not supported with virtual x resolutions larger than %d, disabling\n", + info->MaxSurfaceWidth); + info->allowColorTiling = FALSE; + } + if (info->allowColorTiling) { + if (info->MergedFB) { + if ((((RADEONMergedDisplayModePtr)(pointer)pScrn->currentMode->Private)->CRT1->Flags & + (V_DBLSCAN | V_INTERLACE)) || + (((RADEONMergedDisplayModePtr)(pointer)pScrn->currentMode->Private)->CRT2->Flags & + (V_DBLSCAN | V_INTERLACE))) + info->tilingEnabled = FALSE; + else info->tilingEnabled = TRUE; + } + else { + info->tilingEnabled = (pScrn->currentMode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; + } } - /* Visual setup */ + /* Visual setup */ miClearVisualTypes(); if (!miSetVisualTypes(pScrn->depth, miGetDefaultVisualMask(pScrn->depth), @@ -4329,12 +5602,30 @@ miSetPixmapDepths (); #ifdef XF86DRI - /* Setup DRI after visuals have been - established, but before fbScreenInit is - called. fbScreenInit will eventually - call the driver's InitGLXVisuals call - back. */ - { + if (info->directRenderingEnabled) { + MessageType from; + + info->depthBits = pScrn->depth; + + from = xf86GetOptValInteger(info->Options, OPTION_DEPTH_BITS, + &info->depthBits) + ? X_CONFIG : X_DEFAULT; + + if (info->depthBits != 16 && info->depthBits != 24) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Value for Option \"DepthBits\" must be 16 or 24\n"); + info->depthBits = pScrn->depth; + from = X_DEFAULT; + } + + xf86DrvMsg(pScrn->scrnIndex, from, + "Using %d bit depth buffer\n", info->depthBits); + } + + /* Setup DRI after visuals have been established, but before fbScreenInit is + * called. fbScreenInit will eventually call the driver's InitGLXVisuals + * call back. */ + if (info->directRenderingEnabled) { /* FIXME: When we move to dynamic allocation of back and depth * buffers, we will want to revisit the following check for 3 * times the virtual size of the screen below. @@ -4343,53 +5634,98 @@ info->CurrentLayout.pixel_bytes); int maxy = info->FbMapSize / width_bytes; - if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { - xf86DrvMsg(scrnIndex, X_WARNING, - "Acceleration disabled, not initializing the DRI\n"); - info->directRenderingEnabled = FALSE; - } else if (maxy <= pScrn->virtualY * 3) { - xf86DrvMsg(scrnIndex, X_WARNING, - "Static buffer allocation failed -- " - "need at least %d kB video memory\n", + if (maxy <= pScrn->virtualY * 3) { + xf86DrvMsg(scrnIndex, X_ERROR, + "Static buffer allocation failed. Disabling DRI.\n"); + xf86DrvMsg(scrnIndex, X_ERROR, + "At least %d kB of video memory needed at this " + "resolution and depth.\n", (pScrn->displayWidth * pScrn->virtualY * info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024); info->directRenderingEnabled = FALSE; - } else if ((info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200) || - (info->ChipFamily == CHIP_FAMILY_RS300)) { - info->directRenderingEnabled = FALSE; - xf86DrvMsg(scrnIndex, X_WARNING, - "Direct rendering not yet supported on " - "IGP320/330/340/350, 7000, 9000 integrated chips\n"); - } else if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350)) { - info->directRenderingEnabled = FALSE; - xf86DrvMsg(scrnIndex, X_WARNING, - "Direct rendering not yet supported on " - "Radeon 9500/9700 and newer cards\n"); } else { - if (info->IsSecondary) + info->directRenderingEnabled = RADEONDRIScreenInit(pScreen); + } + } + + /* Tell DRI about new memory map */ + if (info->directRenderingEnabled && info->newMemoryMap) { + drmRadeonSetParam radeonsetparam; + RADEONTRACE(("DRI New memory map param\n")); + memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam)); + radeonsetparam.param = RADEON_SETPARAM_NEW_MEMMAP; + radeonsetparam.value = 1; + if (drmCommandWrite(info->drmFD, DRM_RADEON_SETPARAM, + &radeonsetparam, sizeof(drmRadeonSetParam)) < 0) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "[drm] failed to enable new memory map\n"); + RADEONDRICloseScreen(pScreen); info->directRenderingEnabled = FALSE; - else { - /* Xinerama has sync problem with DRI, disable it for now */ - if (xf86IsEntityShared(info->pEnt->index)) { - info->directRenderingEnabled = FALSE; - xf86DrvMsg(scrnIndex, X_WARNING, - "Direct Rendering Disabled -- " - "Dual-head configuration is not working with " - "DRI at present.\n" - "Please use only one Device/Screen " - "section in your XFConfig file.\n"); - } else { - info->directRenderingEnabled = - RADEONDRIScreenInit(pScreen); - } - } } } + + hasDRI = info->directRenderingEnabled; +#endif /* XF86DRI */ + + /* Initialize the memory map, this basically calculates the values + * we'll use later on for MC_FB_LOCATION & MC_AGP_LOCATION + */ + RADEONInitMemoryMap(pScrn); + + if (!info->IsSecondary) { + /* empty the surfaces */ + unsigned char *RADEONMMIO = info->MMIO; + unsigned int i; + for (i = 0; i < 8; i++) { + OUTREG(RADEON_SURFACE0_INFO + 16 * i, 0); + OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * i, 0); + OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * i, 0); + } + } + + if (info->FBDev) { + unsigned char *RADEONMMIO = info->MMIO; + + if (!fbdevHWModeInit(pScrn, pScrn->currentMode)) return FALSE; + pScrn->displayWidth = fbdevHWGetLineLength(pScrn) + / info->CurrentLayout.pixel_bytes; + RADEONSaveMemMapRegisters(pScrn, &info->ModeReg); + info->fbLocation = (info->ModeReg.mc_fb_location & 0xffff) << 16; + info->ModeReg.surface_cntl = INREG(RADEON_SURFACE_CNTL); + info->ModeReg.surface_cntl &= ~RADEON_SURF_TRANSLATION_DIS; + } else { + if (!RADEONModeInit(pScrn, pScrn->currentMode)) return FALSE; + } + + RADEONSaveScreen(pScreen, SCREEN_SAVER_ON); + + pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); + +#ifdef XF86DRI + /* Depth moves are disabled by default since they are extremely slow */ + info->depthMoves = xf86ReturnOptValBool(info->Options, + OPTION_DEPTH_MOVE, FALSE); + if (info->depthMoves && info->allowColorTiling) { + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling depth moves\n"); + } else if (info->depthMoves) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Depth moves don't work without color tiling, disabled\n"); + info->depthMoves = FALSE; + } else { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Depth moves disabled by default\n"); + } #endif + /* Initial setup of surfaces */ + if (!info->IsSecondary) { + RADEONTRACE(("Setting up initial surfaces\n")); + RADEONChangeSurfaces(pScrn); + } + + RADEONTRACE(("Initializing fb layer\n")); + + /* Init fb layer */ if (!fbScreenInit(pScreen, info->FB, pScrn->virtualX, pScrn->virtualY, pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, @@ -4417,10 +5753,14 @@ /* Must be after RGB order fixed */ fbPictureInit (pScreen, 0, 0); - if (fbPictureGetSubpixelOrder (pScreen) == SubPixelUnknown) - { - int subPixelOrder; + if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { + if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; + else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; + else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; + fbPictureSetSubpixelOrder (pScreen, subPixelOrder); + } + if (fbPictureGetSubpixelOrder (pScreen) == SubPixelUnknown) { switch (info->DisplayType) { case MT_NONE: subPixelOrder = SubPixelUnknown; break; case MT_LCD: subPixelOrder = SubPixelHorizontalRGB; break; @@ -4429,364 +5769,397 @@ } fbPictureSetSubpixelOrder (pScreen, subPixelOrder); } - /* Memory manager setup */ + + RADEONTRACE(("Setting up accel memmap\n")); + #ifdef XF86DRI - if (info->directRenderingEnabled) { - FBAreaPtr fbarea; - int width_bytes = (pScrn->displayWidth * - info->CurrentLayout.pixel_bytes); - int cpp = info->CurrentLayout.pixel_bytes; - int bufferSize = ((pScrn->virtualY * width_bytes - + RADEON_BUFFER_ALIGN) - & ~RADEON_BUFFER_ALIGN); - int depthSize = ((((pScrn->virtualY+15) & ~15) * width_bytes - + RADEON_BUFFER_ALIGN) - & ~RADEON_BUFFER_ALIGN); - int l; - int scanlines; - - info->frontOffset = 0; - info->frontPitch = pScrn->displayWidth; - - switch (info->CPMode) { - case RADEON_DEFAULT_CP_PIO_MODE: - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in PIO mode\n"); - break; - case RADEON_DEFAULT_CP_BM_MODE: - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in BM mode\n"); - break; - default: - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in UNKNOWN mode\n"); - break; + if (hasDRI) { + info->textureSize = -1; + if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, + &(info->textureSize))) { + if (info->textureSize < 0 || info->textureSize > 100) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Illegal texture memory percentage: %dx, using default behaviour\n", + info->textureSize); + info->textureSize = -1; + } } + if (!RADEONSetupMemXAA_DRI(scrnIndex, pScreen)) + return FALSE; + } +#endif - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using %d MB GART aperture\n", info->gartSize); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using %d MB for the ring buffer\n", info->ringSize); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using %d MB for vertex/indirect buffers\n", info->bufSize); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using %d MB for GART textures\n", info->gartTexSize); + if (!hasDRI && !RADEONSetupMemXAA(scrnIndex, pScreen)) + return FALSE; - /* Try for front, back, depth, and three framebuffers worth of - * pixmap cache. Should be enough for a fullscreen background - * image plus some leftovers. - */ - info->textureSize = info->FbMapSize - 5 * bufferSize - depthSize; + info->dst_pitch_offset = (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) + << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); - /* If that gives us less than half the available memory, let's - * be greedy and grab some more. Sorry, I care more about 3D - * performance than playing nicely, and you'll get around a full - * framebuffer's worth of pixmap cache anyway. + /* Backing store setup */ + RADEONTRACE(("Initializing backing store\n")); + miInitializeBackingStore(pScreen); + xf86SetBackingStore(pScreen); + + /* DRI finalisation */ +#ifdef XF86DRI + if (info->directRenderingEnabled && info->cardType==CARD_PCIE && + info->pciGartOffset && info->pKernelDRMVersion->version_minor >= 19) + { + drmRadeonSetParam radeonsetparam; + RADEONTRACE(("DRI PCIGART param\n")); + memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam)); + radeonsetparam.param = RADEON_SETPARAM_PCIGART_LOCATION; + radeonsetparam.value = info->pciGartOffset; + if (drmCommandWrite(info->drmFD, DRM_RADEON_SETPARAM, + &radeonsetparam, sizeof(drmRadeonSetParam)) < 0) + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "[drm] failed set pci gart location\n"); + } + if (info->directRenderingEnabled) { + RADEONTRACE(("DRI Finishing init !\n")); + info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); + } + if (info->directRenderingEnabled) { + /* DRI final init might have changed the memory map, we need to adjust + * our local image to make sure we restore them properly on mode + * changes or VT switches */ - if (info->textureSize < (int)info->FbMapSize / 2) { - info->textureSize = info->FbMapSize - 4 * bufferSize - depthSize; - } - if (info->textureSize < (int)info->FbMapSize / 2) { - info->textureSize = info->FbMapSize - 3 * bufferSize - depthSize; - } - /* If there's still no space for textures, try without pixmap cache */ - if (info->textureSize < 0) { - info->textureSize = info->FbMapSize - 2 * bufferSize - depthSize - - 64/4*64; - } - - /* Check to see if there is more room available after the 8192nd - scanline for textures */ - if ((int)info->FbMapSize - 8192*width_bytes - bufferSize - depthSize - > info->textureSize) { - info->textureSize = - info->FbMapSize - 8192*width_bytes - bufferSize - depthSize; - } + RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg); - /* If backbuffer is disabled, don't allocate memory for it */ - if (info->noBackBuffer) { - info->textureSize += bufferSize; + if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) { + /* we need to re-calculate bandwidth because of AGPMode difference. */ + RADEONInitDispBandwidth(pScrn); } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); - if (info->textureSize > 0) { - l = RADEONMinBits((info->textureSize-1) / RADEON_NR_TEX_REGIONS); - if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; - - /* Round the texture size up to the nearest whole number of - * texture regions. Again, be greedy about this, don't - * round down. - */ - info->log2TexGran = l; - info->textureSize = (info->textureSize >> l) << l; - } else { - info->textureSize = 0; + /* we might already be in tiled mode, tell drm about it */ + if (info->directRenderingEnabled && info->tilingEnabled) { + drmRadeonSetParam radeonsetparam; + memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam)); + radeonsetparam.param = RADEON_SETPARAM_SWITCH_TILING; + radeonsetparam.value = info->tilingEnabled ? 1 : 0; + if (drmCommandWrite(info->drmFD, DRM_RADEON_SETPARAM, + &radeonsetparam, sizeof(drmRadeonSetParam)) < 0) + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "[drm] failed changing tiling status\n"); } + } else { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Direct rendering disabled\n"); + } +#endif - /* Set a minimum usable local texture heap size. This will fit - * two 256x256x32bpp textures. - */ - if (info->textureSize < 512 * 1024) { - info->textureOffset = 0; - info->textureSize = 0; - } + /* Make sure surfaces are allright since DRI setup may have changed them */ + if (!info->IsSecondary) { + RADEONTRACE(("Setting up final surfaces\n")); + RADEONChangeSurfaces(pScrn); + } - /* Reserve space for textures */ - info->textureOffset = ((info->FbMapSize - info->textureSize + - RADEON_BUFFER_ALIGN) & - ~(CARD32)RADEON_BUFFER_ALIGN); + if(info->MergedFB) + /* need this here to fix up sarea values */ + RADEONAdjustFrameMerged(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); - /* Reserve space for the shared depth - * buffer. - */ - info->depthOffset = ((info->textureOffset - depthSize + - RADEON_BUFFER_ALIGN) & - ~(CARD32)RADEON_BUFFER_ALIGN); - info->depthPitch = pScrn->displayWidth; - - /* Reserve space for the shared back buffer */ - if (info->noBackBuffer) { - info->backOffset = info->depthOffset; - info->backPitch = pScrn->displayWidth; + /* Enable aceleration */ + if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { + RADEONTRACE(("Initializing Acceleration\n")); + if (RADEONAccelInit(pScreen)) { + xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n"); + info->accelOn = TRUE; } else { - info->backOffset = ((info->depthOffset - bufferSize + - RADEON_BUFFER_ALIGN) & - ~(CARD32)RADEON_BUFFER_ALIGN); - info->backPitch = pScrn->displayWidth; + xf86DrvMsg(scrnIndex, X_ERROR, + "Acceleration initialization failed\n"); + xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n"); + info->accelOn = FALSE; } + } else { + xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n"); + info->accelOn = FALSE; + } - info->backY = info->backOffset / width_bytes; - info->backX = (info->backOffset - (info->backY * width_bytes)) / cpp; +#ifdef XF86DRI + /* Init page flipping if enabled now */ + if (info->allowPageFlip) { + RADEONTRACE(("Initializing Page Flipping\n")); + RADEONDRIInitPageFlip(pScreen); + } +#endif - scanlines = info->FbMapSize / width_bytes; - if (scanlines > 8191) scanlines = 8191; + /* Init DPMS */ + RADEONTRACE(("Initializing DPMS\n")); + xf86DPMSInit(pScreen, RADEONDisplayPowerManagementSet, 0); - MemBox.x1 = 0; - MemBox.y1 = 0; - MemBox.x2 = pScrn->displayWidth; - MemBox.y2 = scanlines; + RADEONTRACE(("Initializing Cursor\n")); - if (!xf86InitFBManager(pScreen, &MemBox)) { - xf86DrvMsg(scrnIndex, X_ERROR, - "Memory manager initialization to " - "(%d,%d) (%d,%d) failed\n", - MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2); - return FALSE; - } else { + /* Set Silken Mouse */ + xf86SetSilkenMouse(pScreen); + + /* Cursor setup */ + miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); + + /* Hardware cursor setup */ + if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { + if (RADEONCursorInit(pScreen)) { int width, height; - xf86DrvMsg(scrnIndex, X_INFO, - "Memory manager initialized to (%d,%d) (%d,%d)\n", - MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2); - if ((fbarea = xf86AllocateOffscreenArea(pScreen, - pScrn->displayWidth, - 2, 0, NULL, NULL, - NULL))) { - xf86DrvMsg(scrnIndex, X_INFO, - "Reserved area from (%d,%d) to (%d,%d)\n", - fbarea->box.x1, fbarea->box.y1, - fbarea->box.x2, fbarea->box.y2); - } else { - xf86DrvMsg(scrnIndex, X_ERROR, "Unable to reserve area\n"); - } - if (xf86QueryLargestOffscreenArea(pScreen, &width, - &height, 0, 0, 0)) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Using hardware cursor (scanline %d)\n", + info->cursor_offset / pScrn->displayWidth + / info->CurrentLayout.pixel_bytes); + if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, + 0, 0, 0)) { xf86DrvMsg(scrnIndex, X_INFO, "Largest offscreen area available: %d x %d\n", width, height); - - /* Lines in offscreen area needed for depth buffer and - * textures - */ - info->depthTexLines = (scanlines - - info->depthOffset / width_bytes); - info->backLines = (scanlines - - info->backOffset / width_bytes - - info->depthTexLines); - info->backArea = NULL; - } else { - xf86DrvMsg(scrnIndex, X_ERROR, - "Unable to determine largest offscreen area " - "available\n"); - return FALSE; } + } else { + xf86DrvMsg(scrnIndex, X_ERROR, + "Hardware cursor initialization failed\n"); + xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); } + } else { + info->cursor_offset = 0; + xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); + } - xf86DrvMsg(scrnIndex, X_INFO, - "Will use back buffer at offset 0x%x\n", - info->backOffset); - xf86DrvMsg(scrnIndex, X_INFO, - "Will use depth buffer at offset 0x%x\n", - info->depthOffset); - xf86DrvMsg(scrnIndex, X_INFO, - "Will use %d kb for textures at offset 0x%x\n", - info->textureSize/1024, info->textureOffset); + /* Colormap setup */ + RADEONTRACE(("Initializing color map\n")); + if (!miCreateDefColormap(pScreen)) return FALSE; + if (!xf86HandleColormaps(pScreen, 256, info->dac6bits ? 6 : 8, + RADEONLoadPalette, NULL, + CMAP_PALETTED_TRUECOLOR +#if 0 /* This option messes up text mode! (eich@suse.de) */ + | CMAP_LOAD_EVEN_IF_OFFSCREEN +#endif + | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE; - info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) | - (info->frontOffset >> 10)); + /* DGA setup */ + RADEONTRACE(("Initializing DGA\n")); + RADEONDGAInit(pScreen); - info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) | - (info->backOffset >> 10)); + /* Wrap some funcs for MergedFB */ + if(info->MergedFB) { + info->PointerMoved = pScrn->PointerMoved; + pScrn->PointerMoved = RADEONMergePointerMoved; + /* Pseudo xinerama */ + if(info->UseRADEONXinerama) { + RADEONnoPanoramiXExtension = FALSE; + RADEONXineramaExtensionInit(pScrn); + } else { + info->MouseRestrictions = FALSE; + } + } - info->depthPitchOffset = (((info->depthPitch * cpp / 64) << 22) | - (info->depthOffset >> 10)); - } else -#endif - { - MemBox.x1 = 0; - MemBox.y1 = 0; - MemBox.x2 = pScrn->displayWidth; - y2 = (info->FbMapSize - / (pScrn->displayWidth * - info->CurrentLayout.pixel_bytes)); - if (y2 >= 32768) y2 = 32767; /* because MemBox.y2 is signed short */ - MemBox.y2 = y2; - - /* The acceleration engine uses 14 bit - signed coordinates, so we can't have any - drawable caches beyond this region. */ - if (MemBox.y2 > 8191) MemBox.y2 = 8191; + /* Init Xv */ + RADEONTRACE(("Initializing Xv\n")); + RADEONInitVideo(pScreen); - if (!xf86InitFBManager(pScreen, &MemBox)) { - xf86DrvMsg(scrnIndex, X_ERROR, - "Memory manager initialization to " - "(%d,%d) (%d,%d) failed\n", - MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2); - return FALSE; - } else { - int width, height; - FBAreaPtr fbarea; + if(info->MergedFB) + /* need this here to fix up sarea values */ + RADEONAdjustFrameMerged(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); - xf86DrvMsg(scrnIndex, X_INFO, - "Memory manager initialized to (%d,%d) (%d,%d)\n", - MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2); - if ((fbarea = xf86AllocateOffscreenArea(pScreen, - pScrn->displayWidth, - 2, 0, NULL, NULL, - NULL))) { - xf86DrvMsg(scrnIndex, X_INFO, - "Reserved area from (%d,%d) to (%d,%d)\n", - fbarea->box.x1, fbarea->box.y1, - fbarea->box.x2, fbarea->box.y2); - } else { - xf86DrvMsg(scrnIndex, X_ERROR, "Unable to reserve area\n"); - } - if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, - 0, 0, 0)) { - xf86DrvMsg(scrnIndex, X_INFO, - "Largest offscreen area available: %d x %d\n", - width, height); - } - } - } + /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ + /* Wrap CloseScreen */ + info->CloseScreen = pScreen->CloseScreen; + pScreen->CloseScreen = RADEONCloseScreen; + pScreen->SaveScreen = RADEONSaveScreen; + info->BlockHandler = pScreen->BlockHandler; + pScreen->BlockHandler = RADEONBlockHandler; - /* Acceleration setup */ - if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { - if (RADEONAccelInit(pScreen)) { - xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n"); - info->accelOn = TRUE; + /* Note unused options */ + if (serverGeneration == 1) + xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); - /* FIXME: Figure out why this was added because it shouldn't be! */ - /* This is needed by the DRI and XAA code for shared entities */ - pScrn->pScreen = pScreen; - } else { - xf86DrvMsg(scrnIndex, X_ERROR, - "Acceleration initialization failed\n"); - xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n"); - info->accelOn = FALSE; + RADEONTRACE(("RADEONScreenInit finished\n")); + + return TRUE; +} + +/* Write memory mapping registers */ +static void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, + RADEONSavePtr restore) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + int timeout; + + RADEONTRACE(("RADEONRestoreMemMapRegisters() : \n")); + RADEONTRACE((" MC_FB_LOCATION : 0x%08lx\n", restore->mc_fb_location)); + RADEONTRACE((" MC_AGP_LOCATION : 0x%08lx\n", restore->mc_agp_location)); + + /* Write memory mapping registers only if their value change + * since we must ensure no access is done while they are + * reprogrammed + */ + if (INREG(RADEON_MC_FB_LOCATION) != restore->mc_fb_location || + INREG(RADEON_MC_AGP_LOCATION) != restore->mc_agp_location) { + CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; + CARD32 old_mc_status, status_idle; + + RADEONTRACE((" Map Changed ! Applying ...\n")); + + /* Make sure engine is idle. We assume the CCE is stopped + * at this point + */ + RADEONWaitForIdleMMIO(pScrn); + + if (info->IsIGP) + goto igp_no_mcfb; + + /* Capture MC_STATUS in case things go wrong ... */ + old_mc_status = INREG(RADEON_MC_STATUS); + + /* Stop display & memory access */ + ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); + OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE); + crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); + OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS); + crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); + RADEONWaitForVerticalSync(pScrn); + OUTREG(RADEON_CRTC_GEN_CNTL, + (crtc_gen_cntl + & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) + | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN); + + if (info->HasCRTC2) { + crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); + RADEONWaitForVerticalSync2(pScrn); + OUTREG(RADEON_CRTC2_GEN_CNTL, + (crtc2_gen_cntl + & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) + | RADEON_CRTC2_DISP_REQ_EN_B); } - } else { - xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n"); - info->accelOn = FALSE; - } - /* DGA setup */ - RADEONDGAInit(pScreen); + /* Make sure the chip settles down (paranoid !) */ + usleep(100000); + + /* Wait for MC idle */ + if (IS_R300_VARIANT) + status_idle = R300_MC_IDLE; + else + status_idle = RADEON_MC_IDLE; - /* Backing store setup */ - miInitializeBackingStore(pScreen); - xf86SetBackingStore(pScreen); + timeout = 0; + while (!(INREG(RADEON_MC_STATUS) & status_idle)) { + if (++timeout > 1000000) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Timeout trying to update memory controller settings !\n"); + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "MC_STATUS = 0x%08x (on entry = 0x%08x)\n", + (unsigned int)INREG(RADEON_MC_STATUS), + (unsigned int)old_mc_status); + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "You will probably crash now ... \n"); + /* Nothing we can do except maybe try to kill the server, + * let's wait 2 seconds to leave the above message a chance + * to maybe hit the disk and continue trying to setup despite + * the MC being non-idle + */ + usleep(2000000); + } + usleep(10); + } - /* Set Silken Mouse */ - xf86SetSilkenMouse(pScreen); + /* Update maps, first clearing out AGP to make sure we don't get + * a temporary overlap + */ + OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc); + OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location); + igp_no_mcfb: + OUTREG(RADEON_MC_AGP_LOCATION, restore->mc_agp_location); + /* Make sure map fully reached the chip */ + (void)INREG(RADEON_MC_FB_LOCATION); - /* Cursor setup */ - miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); + RADEONTRACE((" Map applied, resetting engine ...\n")); - /* Hardware cursor setup */ - if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { - if (RADEONCursorInit(pScreen)) { - int width, height; + /* Reset the engine and HDP */ + RADEONEngineReset(pScrn); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using hardware cursor (scanline %ld)\n", - info->cursor_start / pScrn->displayWidth - / info->CurrentLayout.pixel_bytes); - if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, - 0, 0, 0)) { - xf86DrvMsg(scrnIndex, X_INFO, - "Largest offscreen area available: %d x %d\n", - width, height); + /* Make sure we have sane offsets before re-enabling the CRTCs, disable + * stereo, clear offsets, and wait for offsets to catch up with hw + */ + + OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL); + OUTREG(RADEON_CRTC_OFFSET, 0); + OUTREG(RADEON_CUR_OFFSET, 0); + timeout = 0; + while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) { + if (timeout++ > 1000000) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Timeout waiting for CRTC offset to update !\n"); + break; + } + usleep(1000); + } + if (info->HasCRTC2) { + OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL); + OUTREG(RADEON_CRTC2_OFFSET, 0); + OUTREG(RADEON_CUR2_OFFSET, 0); + timeout = 0; + while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) { + if (timeout++ > 1000000) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Timeout waiting for CRTC2 offset to update !\n"); + break; + } + usleep(1000); } - } else { - xf86DrvMsg(scrnIndex, X_ERROR, - "Hardware cursor initialization failed\n"); - xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); } - } else { - info->cursor_start = 0; - xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); } - /* Colormap setup */ - if (!miCreateDefColormap(pScreen)) return FALSE; - if (!xf86HandleColormaps(pScreen, 256, info->dac6bits ? 6 : 8, - RADEONLoadPalette, NULL, - CMAP_PALETTED_TRUECOLOR -#if 0 /* This option messes up text mode! (eich@suse.de) */ - | CMAP_LOAD_EVEN_IF_OFFSCREEN -#endif - | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE; + RADEONTRACE(("Updating display base addresses...\n")); - /* DPMS setup */ - xf86DPMSInit(pScreen, RADEONDisplayPowerManagementSet, 0); + OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr); + if (info->HasCRTC2) + OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr); + OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr); + (void)INREG(RADEON_OV0_BASE_ADDR); - RADEONInitVideo(pScreen); + /* More paranoia delays, wait 100ms */ + usleep(100000); - /* Provide SaveScreen */ - pScreen->SaveScreen = RADEONSaveScreen; + RADEONTRACE(("Memory map updated.\n")); + } - /* Wrap CloseScreen */ - info->CloseScreen = pScreen->CloseScreen; - pScreen->CloseScreen = RADEONCloseScreen; +#ifdef XF86DRI +static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + unsigned fb, agp; + int fb_loc_changed; - /* Note unused options */ - if (serverGeneration == 1) - xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); + fb = INREG(RADEON_MC_FB_LOCATION); + agp = INREG(RADEON_MC_AGP_LOCATION); + fb_loc_changed = (fb != info->mc_fb_location); -#ifdef XF86DRI - /* DRI finalization */ - if (info->directRenderingEnabled) { - /* Now that mi, fb, drm and others have - done their thing, complete the DRI - setup. */ - info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); - } - if (info->directRenderingEnabled) { - if ((info->DispPriority == 1) && (!info->IsPCI)) { - /* we need to re-calculate bandwidth because of AGPMode difference. */ - RADEONInitDispBandwidth(pScrn); - } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering disabled\n"); - } -#endif + if (fb_loc_changed || agp != info->mc_agp_location) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "DRI init changed memory map, adjusting ...\n"); + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + " MC_FB_LOCATION was: 0x%08x is: 0x%08x\n", + (unsigned int)info->mc_fb_location, fb); + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + " MC_AGP_LOCATION was: 0x%08x is: 0x%08x\n", + (unsigned int)info->mc_agp_location, agp); + info->mc_fb_location = fb; + info->mc_agp_location = agp; + info->fbLocation = (save->mc_fb_location & 0xffff) << 16; + info->dst_pitch_offset = + (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) + << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); - info->BlockHandler = pScreen->BlockHandler; - pScreen->BlockHandler = RADEONBlockHandler; - return TRUE; + RADEONInitMemMapRegisters(pScrn, save, info); + + /* If MC_FB_LOCATION was changed, adjust the various offsets */ + if (fb_loc_changed) + RADEONRestoreMemMapRegisters(pScrn, save); + } } +#endif -/* Write common registers (initialized to 0) */ +/* Write common registers */ static void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) { @@ -4813,13 +6186,11 @@ if (info->HasCRTC2 && !info->IsSwitching && info->ChipFamily != CHIP_FAMILY_R200 && - info->ChipFamily != CHIP_FAMILY_R300 && - info->ChipFamily != CHIP_FAMILY_R350 && - info->ChipFamily != CHIP_FAMILY_RV350) { + !IS_R300_VARIANT) { CARD32 tmp; - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - if (pRADEONEnt->HasSecondary || info->Clone) { + if (pRADEONEnt->HasSecondary || info->MergedFB) { tmp = INREG(RADEON_DAC_CNTL2); OUTREG(RADEON_DAC_CNTL2, tmp & ~RADEON_DAC2_DAC_CLK_SEL); usleep(100000); @@ -4859,7 +6230,14 @@ RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl); + RADEONTRACE(("Programming CRTC1, offset: 0x%08lx\n", + restore->crtc_offset)); + + /* We prevent the CRTC from hitting the memory controller until + * fully programmed + */ + OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl | + RADEON_CRTC_DISP_REQ_EN_B); OUTREGP(RADEON_CRTC_EXT_CNTL, restore->crtc_ext_cntl, @@ -4881,6 +6259,15 @@ OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch); OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl); OUTREG(RADEON_CRTC_MORE_CNTL, restore->crtc_more_cntl); + + if (info->IsDellServer) { + OUTREG(RADEON_TV_DAC_CNTL, restore->tv_dac_cntl); + OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug); + OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl); + OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); + } + + OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl); } /* Write CRTC2 registers */ @@ -4889,20 +6276,28 @@ { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; + CARD32 crtc2_gen_cntl; - OUTREGP(RADEON_CRTC2_GEN_CNTL, - restore->crtc2_gen_cntl, - RADEON_CRTC2_VSYNC_DIS | - RADEON_CRTC2_HSYNC_DIS | - RADEON_CRTC2_DISP_DIS); + RADEONTRACE(("Programming CRTC2, offset: 0x%08lx\n", + restore->crtc2_offset)); + + crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL) & + (RADEON_CRTC2_VSYNC_DIS | + RADEON_CRTC2_HSYNC_DIS | + RADEON_CRTC2_DISP_DIS); + crtc2_gen_cntl |= restore->crtc2_gen_cntl; + + /* We prevent the CRTC from hitting the memory controller until + * fully programmed + */ + OUTREG(RADEON_CRTC2_GEN_CNTL, + crtc2_gen_cntl | RADEON_CRTC2_DISP_REQ_EN_B); OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl); OUTREG(RADEON_TV_DAC_CNTL, 0x00280203); if ((info->ChipFamily == CHIP_FAMILY_R200) || - (info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350)) { + IS_R300_VARIANT) { OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl); } else { OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug); @@ -4918,11 +6313,14 @@ OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); if ((info->DisplayType == MT_DFP && info->IsSecondary) || - info->CloneType == MT_DFP) { + info->MergeType == MT_DFP) { OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp2_h_sync_strt_wid); OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp2_v_sync_strt_wid); OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl); } + + OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); + #if 0 /* Hack for restoring text mode -- fixed elsewhere */ usleep(100000); @@ -4953,9 +6351,14 @@ OUTREG(RADEON_GRPH_BUFFER_CNTL, INREG(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000); + if (info->IsMobility) { + OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch); + OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch); + OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch); + } + if (info->DisplayType != MT_DFP) { unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch); if (info->IsMobility || info->IsIGP) { /* Asic bug, when turning off LVDS_ON, we have to make sure @@ -4984,7 +6387,7 @@ if (info->IsMobility || info->IsIGP) { if (!(restore->lvds_gen_cntl & RADEON_LVDS_ON)) { - OUTPLL(RADEON_PIXCLKS_CNTL, tmpPixclksCntl); + OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl); } } } @@ -5006,9 +6409,6 @@ static void RADEONPLLWriteUpdate(ScrnInfoPtr pScrn) { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - while (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, @@ -5032,9 +6432,6 @@ static void RADEONPLL2WriteUpdate(ScrnInfoPtr pScrn) { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - while (INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV, @@ -5049,24 +6446,30 @@ RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - if (info->IsMobility) { - /* + /* * Never do it on Apple iBook to avoid a blank screen. */ #ifdef __powerpc__ if (xf86ReturnOptValBool(info->Options, OPTION_IBOOKHACKS, FALSE)) - return; + return; #endif - /* A temporal workaround for the occational blanking on certain laptop panels. - This appears to related to the PLL divider registers (fail to lock?). + if (info->IsMobility) { + /* A temporal workaround for the occational blanking on certain laptop panels. + This appears to related to the PLL divider registers (fail to lock?). It occurs even when all dividers are the same with their old settings. - In this case we really don't need to fiddle with PLL registers. - By doing this we can avoid the blanking problem with some panels. - */ - if ((restore->ppll_ref_div == (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && - (restore->ppll_div_3 == (INPLL(pScrn, RADEON_PPLL_DIV_3) & (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) - return; + In this case we really don't need to fiddle with PLL registers. + By doing this we can avoid the blanking problem with some panels. + */ + if ((restore->ppll_ref_div == (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && + (restore->ppll_div_3 == (INPLL(pScrn, RADEON_PPLL_DIV_3) & + (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { + OUTREGP(RADEON_CLOCK_CNTL_INDEX, + RADEON_PLL_DIV_SEL, + ~(RADEON_PLL_DIV_SEL)); + RADEONPllErrataAfterIndex(info); + return; + } } OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, @@ -5085,11 +6488,10 @@ OUTREGP(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, ~(RADEON_PLL_DIV_SEL)); + RADEONPllErrataAfterIndex(info); - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_RS300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350)) { + if (IS_R300_VARIANT || + (info->ChipFamily == CHIP_FAMILY_RS300)) { if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { /* When restoring console mode, use saved PPLL_REF_DIV * setting. @@ -5120,7 +6522,7 @@ RADEONPLLWriteUpdate(pScrn); RADEONPLLWaitForReadUpdateComplete(pScrn); - OUTPLL(RADEON_HTOTAL_CNTL, restore->htotal_cntl); + OUTPLL(pScrn, RADEON_HTOTAL_CNTL, restore->htotal_cntl); OUTPLLP(pScrn, RADEON_PPLL_CNTL, 0, @@ -5129,12 +6531,7 @@ | RADEON_PPLL_ATOMIC_UPDATE_EN | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); - xf86DrvMsg(0, X_INFO, "Wrote: rd=%d, fd=%d, pd=%d\n", - restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, - restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, - (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); - - RADEONTRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", + RADEONTRACE(("Wrote: 0x%08x 0x%08x 0x%08lx (0x%08x)\n", restore->ppll_ref_div, restore->ppll_div_3, restore->htotal_cntl, @@ -5144,7 +6541,7 @@ restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16)); - usleep(5000); /* Let the clock to lock */ + usleep(50000); /* Let the clock to lock */ OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, RADEON_VCLK_SRC_SEL_PPLLCLK, @@ -5156,9 +6553,6 @@ static void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore) { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, RADEON_PIX2CLK_SRC_SEL_CPUCLK, ~(RADEON_PIX2CLK_SRC_SEL_MASK)); @@ -5187,7 +6581,7 @@ RADEONPLL2WriteUpdate(pScrn); RADEONPLL2WaitForReadUpdateComplete(pScrn); - OUTPLL(RADEON_HTOTAL2_CNTL, restore->htotal_cntl2); + OUTPLL(pScrn, RADEON_HTOTAL2_CNTL, restore->htotal_cntl2); OUTPLLP(pScrn, RADEON_P2PLL_CNTL, 0, @@ -5196,12 +6590,12 @@ | RADEON_P2PLL_ATOMIC_UPDATE_EN | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN)); - RADEONTRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", + RADEONTRACE(("Wrote: 0x%08lx 0x%08lx 0x%08lx (0x%08x)\n", restore->p2pll_ref_div, restore->p2pll_div_0, restore->htotal_cntl2, INPLL(pScrn, RADEON_P2PLL_CNTL))); - RADEONTRACE(("Wrote: rd=%d, fd=%d, pd=%d\n", + RADEONTRACE(("Wrote: rd=%ld, fd=%ld, pd=%ld\n", restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, (restore->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >>16)); @@ -5213,28 +6607,192 @@ ~(RADEON_PIX2CLK_SRC_SEL_MASK)); } -/* Write palette data */ -static void RADEONRestorePalette(ScrnInfoPtr pScrn, RADEONSavePtr restore) + +/* restore original surface info (for fb console). */ +static void RADEONRestoreSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr restore) { - RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - int i; + unsigned int surfnr; - if (!restore->palette_valid) return; + for ( surfnr = 0; surfnr < 8; surfnr++ ) { + OUTREG(RADEON_SURFACE0_INFO + 16 * surfnr, restore->surfaces[surfnr][0]); + OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr, restore->surfaces[surfnr][1]); + OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr, restore->surfaces[surfnr][2]); + } +} - PAL_SELECT(0); - OUTPAL_START(0); - for (i = 0; i < 256; i++) { - RADEONWaitForFifo(pScrn, 32); /* delay */ - OUTPAL_NEXT_CARD32(restore->palette[i]); +/* save original surface info (for fb console). */ +static void RADEONSaveSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr save) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + unsigned int surfnr; + + for ( surfnr = 0; surfnr < 8; surfnr++ ) { + save->surfaces[surfnr][0] = INREG(RADEON_SURFACE0_INFO + 16 * surfnr); + save->surfaces[surfnr][1] = INREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr); + save->surfaces[surfnr][2] = INREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr); } } -#if 1 -#define RADEONRestorePalette2(pScrn, restore) /* Nullify */ -#else -/* This causes hangs on some Radeon's. Why? */ -static void RADEONRestorePalette2(ScrnInfoPtr pScrn, RADEONSavePtr restore) +void RADEONChangeSurfaces(ScrnInfoPtr pScrn) +{ + /* the idea here is to only set up front buffer as tiled, and back/depth buffer when needed. + Everything else is left as untiled. This means we need to use eplicit src/dst pitch control + when blitting, based on the src/target address, and can no longer use a default offset. + But OTOH we don't need to dynamically change surfaces (for xv for instance), and some + ugly offset / fb reservation (cursor) is gone. And as a bonus, everything actually works... + For simplicity, just always update everything (just let the ioctl fail - could do better). + All surface addresses are relative to RADEON_MC_FB_LOCATION */ + + RADEONInfoPtr info = RADEONPTR(pScrn); + int cpp = info->CurrentLayout.pixel_bytes; + /* depth/front/back pitch must be identical (and the same as displayWidth) */ + int width_bytes = pScrn->displayWidth * cpp; + int bufferSize = ((((pScrn->virtualY + 15) & ~15) * width_bytes + + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); + unsigned int color_pattern, swap_pattern; + + if (!info->allowColorTiling) + return; + + swap_pattern = 0; +#if X_BYTE_ORDER == X_BIG_ENDIAN + switch (pScrn->bitsPerPixel) { + case 16: + swap_pattern = RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; + break; + + case 32: + swap_pattern = RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; + break; + } +#endif + if (info->ChipFamily < CHIP_FAMILY_R200) { + color_pattern = RADEON_SURF_TILE_COLOR_MACRO; + } else if (IS_R300_VARIANT) { + color_pattern = R300_SURF_TILE_COLOR_MACRO; + } else { + color_pattern = R200_SURF_TILE_COLOR_MACRO; + } +#ifdef XF86DRI + if (info->directRenderingInited) { + drmRadeonSurfaceFree drmsurffree; + drmRadeonSurfaceAlloc drmsurfalloc; + int retvalue; + int depthCpp = (info->depthBits - 8) / 4; + int depth_width_bytes = pScrn->displayWidth * depthCpp; + int depthBufferSize = ((((pScrn->virtualY + 15) & ~15) * depth_width_bytes + + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); + unsigned int depth_pattern; + + drmsurffree.address = info->frontOffset; + retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE, + &drmsurffree, sizeof(drmsurffree)); + + if ((info->ChipFamily != CHIP_FAMILY_RV100) || + (info->ChipFamily != CHIP_FAMILY_RS100) || + (info->ChipFamily != CHIP_FAMILY_RS200)) { + drmsurffree.address = info->depthOffset; + retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE, + &drmsurffree, sizeof(drmsurffree)); + } + + if (!info->noBackBuffer) { + drmsurffree.address = info->backOffset; + retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE, + &drmsurffree, sizeof(drmsurffree)); + } + + drmsurfalloc.size = bufferSize; + drmsurfalloc.address = info->frontOffset; + drmsurfalloc.flags = swap_pattern; + + if (info->tilingEnabled) { + if (IS_R300_VARIANT) + drmsurfalloc.flags |= (width_bytes / 8) | color_pattern; + else + drmsurfalloc.flags |= (width_bytes / 16) | color_pattern; + } + retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC, + &drmsurfalloc, sizeof(drmsurfalloc)); + if (retvalue < 0) + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "drm: could not allocate surface for front buffer!\n"); + + if ((info->have3DWindows) && (!info->noBackBuffer)) { + drmsurfalloc.address = info->backOffset; + retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC, + &drmsurfalloc, sizeof(drmsurfalloc)); + if (retvalue < 0) + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "drm: could not allocate surface for back buffer!\n"); + } + + if (info->ChipFamily < CHIP_FAMILY_R200) { + if (depthCpp == 2) + depth_pattern = RADEON_SURF_TILE_DEPTH_16BPP; + else + depth_pattern = RADEON_SURF_TILE_DEPTH_32BPP; + } else if (IS_R300_VARIANT) { + if (depthCpp == 2) + depth_pattern = R300_SURF_TILE_COLOR_MACRO; + else + depth_pattern = R300_SURF_TILE_COLOR_MACRO | R300_SURF_TILE_DEPTH_32BPP; + } else { + if (depthCpp == 2) + depth_pattern = R200_SURF_TILE_DEPTH_16BPP; + else + depth_pattern = R200_SURF_TILE_DEPTH_32BPP; + } + + /* rv100 and probably the derivative igps don't have depth tiling on all the time? */ + if (info->have3DWindows && ((info->ChipFamily != CHIP_FAMILY_RV100) || + (info->ChipFamily != CHIP_FAMILY_RS100) || + (info->ChipFamily != CHIP_FAMILY_RS200))) { + drmsurfalloc.size = depthBufferSize; + drmsurfalloc.address = info->depthOffset; + if (IS_R300_VARIANT) + drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 8) | depth_pattern; + else + drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 16) | depth_pattern; + retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC, + &drmsurfalloc, sizeof(drmsurfalloc)); + if (retvalue < 0) + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "drm: could not allocate surface for depth buffer!\n"); + } + } + else +#endif + { + unsigned int surf_info = swap_pattern; + unsigned char *RADEONMMIO = info->MMIO; + /* we don't need anything like WaitForFifo, no? */ + if (!info->IsSecondary) { + if (info->tilingEnabled) { + if (IS_R300_VARIANT) + surf_info |= (width_bytes / 8) | color_pattern; + else + surf_info |= (width_bytes / 16) | color_pattern; + } + OUTREG(RADEON_SURFACE0_INFO, surf_info); + OUTREG(RADEON_SURFACE0_LOWER_BOUND, 0); + OUTREG(RADEON_SURFACE0_UPPER_BOUND, bufferSize - 1); +/* xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "surface0 set to %x, LB 0x%x UB 0x%x\n", + surf_info, 0, bufferSize - 1024);*/ + } + } + + /* Update surface images */ + RADEONSaveSurfaces(pScrn, &info->ModeReg); +} + +#if 0 +/* Write palette data */ +static void RADEONRestorePalette(ScrnInfoPtr pScrn, RADEONSavePtr restore) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -5248,6 +6806,13 @@ RADEONWaitForFifo(pScrn, 32); /* delay */ OUTPAL_NEXT_CARD32(restore->palette2[i]); } + + PAL_SELECT(0); + OUTPAL_START(0); + for (i = 0; i < 256; i++) { + RADEONWaitForFifo(pScrn, 32); /* delay */ + OUTPAL_NEXT_CARD32(restore->palette[i]); + } } #endif @@ -5258,9 +6823,11 @@ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); static RADEONSaveRec restore0; + RADEONTRACE(("RADEONRestoreMode()\n")); + /* For Non-dual head card, we don't have private field in the Entity */ if (!info->HasCRTC2) { - RADEONRestorePalette(pScrn, restore); + RADEONRestoreMemMapRegisters(pScrn, restore); RADEONRestoreCommonRegisters(pScrn, restore); RADEONRestoreCrtcRegisters(pScrn, restore); RADEONRestoreFPRegisters(pScrn, restore); @@ -5278,15 +6845,18 @@ * order. Regardless the order of X server issuing the calls, we * have to ensure we set registers in the right order!!! Otherwise * we may get a blank screen. + * + * We always restore MemMap first, the saverec should be up to date + * in all cases */ if (info->IsSecondary) { - RADEONRestorePalette2(pScrn, restore); - if (!pRADEONEnt->RestorePrimary && !info->IsSwitching) - RADEONRestoreCommonRegisters(pScrn, restore); + RADEONRestoreMemMapRegisters(pScrn, restore); + RADEONRestoreCommonRegisters(pScrn, restore); RADEONRestoreCrtc2Registers(pScrn, restore); RADEONRestorePLL2Registers(pScrn, restore); - if(info->IsSwitching) return; + if (info->IsSwitching) + return; pRADEONEnt->IsSecondaryRestored = TRUE; @@ -5296,15 +6866,12 @@ RADEONRestoreCrtcRegisters(pScrn, &restore0); RADEONRestoreFPRegisters(pScrn, &restore0); RADEONRestorePLLRegisters(pScrn, &restore0); - RADEONRestorePalette(pScrn, restore); pRADEONEnt->IsSecondaryRestored = FALSE; } } else { - if (!pRADEONEnt->IsSecondaryRestored) - RADEONRestoreCommonRegisters(pScrn, restore); - - if (info->Clone) { - RADEONRestorePalette2(pScrn, restore); + RADEONRestoreMemMapRegisters(pScrn, restore); + RADEONRestoreCommonRegisters(pScrn, restore); + if (info->MergedFB) { RADEONRestoreCrtc2Registers(pScrn, restore); RADEONRestorePLL2Registers(pScrn, restore); } @@ -5316,12 +6883,28 @@ RADEONRestoreCrtcRegisters(pScrn, restore); RADEONRestoreFPRegisters(pScrn, restore); RADEONRestorePLLRegisters(pScrn, restore); - RADEONRestorePalette(pScrn, restore); } else { memcpy(&restore0, restore, sizeof(restore0)); pRADEONEnt->RestorePrimary = TRUE; } } + +#if 0 + RADEONRestorePalette(pScrn, &info->SavedReg); +#endif +} + +/* Read memory map */ +static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + save->mc_fb_location = INREG(RADEON_MC_FB_LOCATION); + save->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION); + save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR); + save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR); + save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR); } /* Read common registers */ @@ -5386,6 +6969,13 @@ save->crtc_pitch = INREG(RADEON_CRTC_PITCH); save->disp_merge_cntl = INREG(RADEON_DISP_MERGE_CNTL); save->crtc_more_cntl = INREG(RADEON_CRTC_MORE_CNTL); + + if (info->IsDellServer) { + save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); + save->dac2_cntl = INREG(RADEON_DAC_CNTL2); + save->disp_hw_debug = INREG(RADEON_DISP_HW_DEBUG); + save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); + } } /* Read flat panel registers */ @@ -5405,7 +6995,9 @@ save->lvds_pll_cntl = INREG(RADEON_LVDS_PLL_CNTL); save->tmds_pll_cntl = INREG(RADEON_TMDS_PLL_CNTL); save->tmds_transmitter_cntl= INREG(RADEON_TMDS_TRANSMITTER_CNTL); + save->bios_4_scratch = INREG(RADEON_BIOS_4_SCRATCH); save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH); + save->bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH); if (info->ChipFamily == CHIP_FAMILY_RV280) { /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ @@ -5421,7 +7013,7 @@ save->dac2_cntl = INREG(RADEON_DAC_CNTL2); save->disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL); - save->disp_hw_debug = INREG (RADEON_DISP_HW_DEBUG); + save->disp_hw_debug = INREG(RADEON_DISP_HW_DEBUG); save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); save->crtc2_h_total_disp = INREG(RADEON_CRTC2_H_TOTAL_DISP); @@ -5432,9 +7024,9 @@ save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL); save->crtc2_pitch = INREG(RADEON_CRTC2_PITCH); - save->fp2_h_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID); - save->fp2_v_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID); - save->fp2_gen_cntl = INREG (RADEON_FP2_GEN_CNTL); + save->fp2_h_sync_strt_wid = INREG(RADEON_FP_H2_SYNC_STRT_WID); + save->fp2_v_sync_strt_wid = INREG(RADEON_FP_V2_SYNC_STRT_WID); + save->fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL); } @@ -5445,7 +7037,7 @@ save->ppll_div_3 = INPLL(pScrn, RADEON_PPLL_DIV_3); save->htotal_cntl = INPLL(pScrn, RADEON_HTOTAL_CNTL); - RADEONTRACE(("Read: 0x%08x 0x%08x 0x%08x\n", + RADEONTRACE(("Read: 0x%08x 0x%08x 0x%08lx\n", save->ppll_ref_div, save->ppll_div_3, save->htotal_cntl)); @@ -5462,11 +7054,11 @@ save->p2pll_div_0 = INPLL(pScrn, RADEON_P2PLL_DIV_0); save->htotal_cntl2 = INPLL(pScrn, RADEON_HTOTAL2_CNTL); - RADEONTRACE(("Read: 0x%08x 0x%08x 0x%08x\n", + RADEONTRACE(("Read: 0x%08lx 0x%08lx 0x%08lx\n", save->p2pll_ref_div, save->p2pll_div_0, save->htotal_cntl2)); - RADEONTRACE(("Read: rd=%d, fd=%d, pd=%d\n", + RADEONTRACE(("Read: rd=%ld, fd=%ld, pd=%ld\n", save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, (save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) >> 16)); @@ -5479,10 +7071,6 @@ unsigned char *RADEONMMIO = info->MMIO; int i; -#ifdef ENABLE_FLAT_PANEL - /* Select palette 0 (main CRTC) if using FP-enabled chip */ - /* if (info->Port1 == MT_DFP) PAL_SELECT(1); */ -#endif PAL_SELECT(1); INPAL_START(0); for (i = 0; i < 256; i++) save->palette2[i] = INPAL_NEXT(); @@ -5498,6 +7086,7 @@ RADEONInfoPtr info = RADEONPTR(pScrn); RADEONTRACE(("RADEONSaveMode(%p)\n", save)); + RADEONSaveMemMapRegisters(pScrn, save); RADEONSaveCommonRegisters(pScrn, save); if (info->IsSecondary) { RADEONSaveCrtc2Registers(pScrn, save); @@ -5507,11 +7096,11 @@ RADEONSaveCrtcRegisters(pScrn, save); RADEONSaveFPRegisters(pScrn, save); - if (info->Clone) { + if (info->MergedFB) { RADEONSaveCrtc2Registers(pScrn, save); RADEONSavePLL2Registers(pScrn, save); } - RADEONSavePalette(pScrn, save); + /* RADEONSavePalette(pScrn, save); */ } RADEONTRACE(("RADEONSaveMode returns %p\n", save)); @@ -5523,35 +7112,33 @@ RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; RADEONSavePtr save = &info->SavedReg; - vgaHWPtr hwp = VGAHWPTR(pScrn); RADEONTRACE(("RADEONSave\n")); if (info->FBDev) { + RADEONSaveMemMapRegisters(pScrn, save); fbdevHWSave(pScrn); return; } if (!info->IsSecondary) { - vgaHWUnlock(hwp); -#if defined(__powerpc__) - /* temporary hack to prevent crashing on PowerMacs when trying to - * read VGA fonts and colormap, will find a better solution - * in the future - */ - vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */ -#else - vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL); /* Save mode - * & fonts & cmap - */ -#endif - vgaHWLock(hwp); + if (info->UseVGAHW) { + vgaHWPtr hwp = VGAHWPTR(pScrn); + + vgaHWUnlock(hwp); + /* Save mode & fonts & cmap */ + vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL); + vgaHWLock(hwp); + } + save->dp_datatype = INREG(RADEON_DP_DATATYPE); save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); - if (info->R300CGWorkaround) R300CGWorkaround(pScrn); + RADEONPllErrataAfterIndex(info); } RADEONSaveMode(pScrn, save); + if (!info->IsSecondary) + RADEONSaveSurfaces(pScrn, save); } /* Restore the original (text) mode */ @@ -5560,7 +7147,6 @@ RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; RADEONSavePtr restore = &info->SavedReg; - vgaHWPtr hwp = VGAHWPTR(pScrn); RADEONTRACE(("RADEONRestore\n")); @@ -5576,7 +7162,7 @@ RADEONBlank(pScrn); OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index); - if (info->R300CGWorkaround) R300CGWorkaround(pScrn); + RADEONPllErrataAfterIndex(info); OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset); OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype); OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl); @@ -5586,12 +7172,14 @@ /* M6 card has trouble restoring text mode for its CRT. * This is fixed elsewhere and will be removed in the future. */ - if ((xf86IsEntityShared(info->pEnt->index) || info->Clone) + if ((xf86IsEntityShared(info->pEnt->index) || info->MergedFB) && info->IsM6) OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl); #endif RADEONRestoreMode(pScrn, restore); + if (!info->IsSecondary) + RADEONRestoreSurfaces(pScrn, restore); #if 0 /* Temp fix to "solve" VT switch problems. When switching VTs on @@ -5602,27 +7190,22 @@ usleep(100000); #endif - if (!info->IsSecondary) { - vgaHWUnlock(hwp); -#if defined(__powerpc__) - /* Temporary hack to prevent crashing on PowerMacs when trying to - * write VGA fonts, will find a better solution in the future - */ - vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE); -#else - vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL); -#endif - vgaHWLock(hwp); - } else { - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - ScrnInfoPtr pScrn0; - vgaHWPtr hwp0; - - pScrn0 = pRADEONEnt->pPrimaryScrn; - hwp0 = VGAHWPTR(pScrn0); - vgaHWUnlock(hwp0); - vgaHWRestore(pScrn0, &hwp0->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); - vgaHWLock(hwp0); + if (info->UseVGAHW) { + vgaHWPtr hwp = VGAHWPTR(pScrn); + if (!info->IsSecondary) { + vgaHWUnlock(hwp); + vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL ); + vgaHWLock(hwp); + } else { + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + ScrnInfoPtr pScrn0 = pRADEONEnt->pPrimaryScrn; + vgaHWPtr hwp0; + + hwp0 = VGAHWPTR(pScrn0); + vgaHWUnlock(hwp0); + vgaHWRestore(pScrn0, &hwp0->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); + vgaHWLock(hwp0); + } } RADEONUnblank(pScrn); @@ -5653,6 +7236,7 @@ save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN; } + /* Calculate display buffer watermark to prevent buffer underflow */ static void RADEONInitDispBandwidth(ScrnInfoPtr pScrn) { @@ -5689,10 +7273,29 @@ int stop_req, max_stop_req; float read_return_rate, time_disp1_drop_priority; + /* + * Set display0/1 priority up on r3/4xx in the memory controller for + * high res modes if the user specifies HIGH for displaypriority + * option. + */ + if ((info->DispPriority == 2) && IS_R300_VARIANT) { + CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); + if (info->MergedFB || pRADEONEnt->HasSecondary) { + mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */ + } else { + mc_init_misc_lat_timer |= 0x0100; /* display 0 only */ + } + OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); + } + + + /* R420 and RV410 family not supported yet */ + if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) return; + if (pRADEONEnt->pSecondaryScrn) { if (info->IsSecondary) return; info2 = RADEONPTR(pRADEONEnt->pSecondaryScrn); - } else if (info->Clone) info2 = info; + } else if (info->MergedFB) info2 = info; /* * Determine if there is enough bandwidth for current display mode @@ -5700,12 +7303,14 @@ mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1); mode1 = info->CurrentLayout.mode; - if (info->Clone) - mode2 = info->CurCloneMode; - else if ((pRADEONEnt->HasSecondary) && info2) + if (info->MergedFB) { + mode1 = ((RADEONMergedDisplayModePtr)(pointer)info->CurrentLayout.mode->Private)->CRT1; + mode2 = ((RADEONMergedDisplayModePtr)(pointer)info->CurrentLayout.mode->Private)->CRT2; + } else if ((pRADEONEnt->HasSecondary) && info2) { mode2 = info2->CurrentLayout.mode; - else + } else { mode2 = NULL; + } pix_clk = mode1->Clock/1000.0; if (mode2) @@ -5724,19 +7329,13 @@ } /* CRTC1 - Set GRPH_BUFFER_CNTL register using h/w defined optimal values. + Set GRPH_BUFFER_CNTL register using h/w defined optimal values. GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] */ stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16; /* setup Max GRPH_STOP_REQ default value */ - if ((info->ChipFamily == CHIP_FAMILY_RV100) || - (info->ChipFamily == CHIP_FAMILY_RV200) || - (info->ChipFamily == CHIP_FAMILY_RV250) || - (info->ChipFamily == CHIP_FAMILY_RV280) || - (info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200) || - (info->ChipFamily == CHIP_FAMILY_RS300)) + if (IS_RV100_VARIANT) max_stop_req = 0x5c; else max_stop_req = 0x7c; @@ -5764,15 +7363,13 @@ mem_tcas = MemTcas2 [data]; } - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350)) { + if (IS_R300_VARIANT) { /* on the R300, Tcas is included in Trbs. */ temp = INREG(RADEON_MEM_CNTL); data = (R300_MEM_NUM_CHANNELS_MASK & temp); - if (data == 2) { + if (data == 1) { if (R300_MEM_USE_CD_CH_ONLY & temp) { temp = INREG(R300_MC_IND_INDEX); temp &= ~R300_MC_IND_ADDR_MASK; @@ -5807,9 +7404,7 @@ /* Find the memory controller latency for the display client. */ - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350)) { + if (IS_R300_VARIANT) { /*not enough for R350 ???*/ /* if (!mode2) sclk_delay = 150; @@ -5881,15 +7476,7 @@ if (critical_point < temp) critical_point = temp; */ if (info->DispPriority == 2) { - if (mode2) { - /*??some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ - if (info->ChipFamily == CHIP_FAMILY_R300) - critical_point += 0x10; - else - critical_point = 0; - } - else - critical_point = 0; + critical_point = 0; } /* @@ -5898,6 +7485,11 @@ */ if (max_stop_req - critical_point < 4) critical_point = 0; + if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) { + /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ + critical_point = 0x10; + } + temp = info->SavedReg.grph_buffer_cntl; temp &= ~(RADEON_GRPH_STOP_REQ_MASK); temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); @@ -5919,7 +7511,7 @@ (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); RADEONTRACE(("GRPH_BUFFER_CNTL from %x to %x\n", - info->SavedReg.grph_buffer_cntl, INREG(RADEON_GRPH_BUFFER_CNTL))); + (unsigned int)info->SavedReg.grph_buffer_cntl, INREG(RADEON_GRPH_BUFFER_CNTL))); if (mode2) { stop_req = mode2->HDisplay * info2->CurrentLayout.pixel_bytes / 16; @@ -5951,21 +7543,23 @@ disp_latency) * disp_drain_rate2 + 0.5); if (info->DispPriority == 2) { - if (info->ChipFamily == CHIP_FAMILY_R300) - critical_point2 += 0x10; - else - critical_point2 = 0; + critical_point2 = 0; } if (max_stop_req - critical_point2 < 4) critical_point2 = 0; } + if (critical_point2 == 0 && info->ChipFamily == CHIP_FAMILY_R300) { + /* some R300 cards have problem with this set to 0 */ + critical_point2 = 0x10; + } + OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); RADEONTRACE(("GRPH2_BUFFER_CNTL from %x to %x\n", - info->SavedReg.grph2_buffer_cntl, INREG(RADEON_GRPH2_BUFFER_CNTL))); + (unsigned int)info->SavedReg.grph2_buffer_cntl, INREG(RADEON_GRPH2_BUFFER_CNTL))); } } @@ -5978,10 +7572,7 @@ int format; int hsync_start; int hsync_wid; - int hsync_fudge; int vsync_wid; - int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 }; - int hsync_fudge_fp[] = { 0x02, 0x02, 0x00, 0x00, 0x05, 0x05 }; switch (info->CurrentLayout.pixel_code) { case 4: format = 1; break; @@ -5999,7 +7590,6 @@ if ((info->DisplayType == MT_DFP) || (info->DisplayType == MT_LCD)) { - hsync_fudge = hsync_fudge_fp[format-1]; if (mode->Flags & RADEON_USE_RMX) { #if 0 mode->CrtcHDisplay = info->PanelXRes; @@ -6014,8 +7604,6 @@ mode->Clock = info->DotClock; mode->Flags = info->Flags | RADEON_USE_RMX; } - } else { - hsync_fudge = hsync_fudge_default[format-1]; } save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN @@ -6031,13 +7619,21 @@ ? RADEON_CRTC_INTERLACE_EN : 0)); + /* Don't try to be smart and unconditionally enable the analog output + * for now as the dodgy code to handle it for the second head doesn't + * work. This will be correctly fixed when Alex' megapatch gets in that + * reworks the whole output mapping + */ +#if 0 if ((info->DisplayType == MT_DFP) || (info->DisplayType == MT_LCD)) { save->crtc_ext_cntl = RADEON_VGA_ATI_LINEAR | RADEON_XCRT_CNT_EN; save->crtc_gen_cntl &= ~(RADEON_CRTC_DBL_SCAN_EN | RADEON_CRTC_CSYNC_EN | RADEON_CRTC_INTERLACE_EN); - } else { + } else +#endif + { save->crtc_ext_cntl = (RADEON_VGA_ATI_LINEAR | RADEON_XCRT_CNT_EN | RADEON_CRTC_CRT_ON); @@ -6053,7 +7649,7 @@ hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; if (!hsync_wid) hsync_wid = 1; - hsync_start = mode->CrtcHSyncStart - 8 + hsync_fudge; + hsync_start = mode->CrtcHSyncStart - 8; save->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) | ((hsync_wid & 0x3f) << 16) @@ -6084,30 +7680,47 @@ ? RADEON_CRTC_V_SYNC_POL : 0)); - save->crtc_offset = 0; + save->crtc_offset = pScrn->fbOffset; save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL); + if (info->tilingEnabled) { + if (IS_R300_VARIANT) + save->crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | + R300_CRTC_MICRO_TILE_BUFFER_DIS | + R300_CRTC_MACRO_TILE_EN); + else + save->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; + } + else { + if (IS_R300_VARIANT) + save->crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | + R300_CRTC_MICRO_TILE_BUFFER_DIS | + R300_CRTC_MACRO_TILE_EN); + else + save->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; + } save->crtc_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) + ((pScrn->bitsPerPixel * 8) -1)) / (pScrn->bitsPerPixel * 8)); save->crtc_pitch |= save->crtc_pitch << 16; - /* Some versions of BIOS setup CRTC_MORE_CNTL for a DFP, if we - have a CRT here, it should be cleared to avoild a blank screen. - */ - if (info->DisplayType == MT_CRT) - save->crtc_more_cntl = (info->SavedReg.crtc_more_cntl & - ~(RADEON_CRTC_H_CUTOFF_ACTIVE_EN | - RADEON_CRTC_V_CUTOFF_ACTIVE_EN)); - else - save->crtc_more_cntl = info->SavedReg.crtc_more_cntl; + save->crtc_more_cntl = 0; + if ((info->ChipFamily == CHIP_FAMILY_RS100) || + (info->ChipFamily == CHIP_FAMILY_RS200)) { + /* This is to workaround the asic bug for RMX, some versions + of BIOS dosen't have this register initialized correctly. + */ + save->crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; + } save->surface_cntl = 0; save->disp_merge_cntl = info->SavedReg.disp_merge_cntl; save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; #if X_BYTE_ORDER == X_BIG_ENDIAN - /* Alhought we current onlu use aperture 0, also setting aperture 1 should not harm -ReneR */ + /* We must set both apertures as they can be both used to map the entire + * video memory. -BenH. + */ switch (pScrn->bitsPerPixel) { case 16: save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP; @@ -6119,9 +7732,26 @@ save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP; break; } -#endif +#endif + + if (info->IsDellServer) { + save->dac2_cntl = info->SavedReg.dac2_cntl; + save->tv_dac_cntl = info->SavedReg.tv_dac_cntl; + save->crtc2_gen_cntl = info->SavedReg.crtc2_gen_cntl; + save->disp_hw_debug = info->SavedReg.disp_hw_debug; + + save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; + save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; + + /* For CRT on DAC2, don't turn it on if BIOS didn't + enable it, even it's detected. + */ + save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL; + save->tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16)); + save->tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16)); + } - RADEONTRACE(("Pitch = %d bytes (virtualX = %d, displayWidth = %d)\n", + RADEONTRACE(("Pitch = %ld bytes (virtualX = %d, displayWidth = %d)\n", save->crtc_pitch, pScrn->virtualX, info->CurrentLayout.displayWidth)); return TRUE; @@ -6137,9 +7767,7 @@ int format; int hsync_start; int hsync_wid; - int hsync_fudge; int vsync_wid; - int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 }; switch (info->CurrentLayout.pixel_code) { case 4: format = 1; break; @@ -6155,8 +7783,6 @@ return FALSE; } - hsync_fudge = hsync_fudge_default[format-1]; - save->crtc2_gen_cntl = (RADEON_CRTC2_EN | RADEON_CRTC2_CRT2_ON | (format << 8) @@ -6171,15 +7797,12 @@ : 0)); /* Turn CRT on in case the first head is a DFP */ - save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON; save->dac2_cntl = info->SavedReg.dac2_cntl; /* always let TVDAC drive CRT2, we don't support tvout yet */ save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; save->disp_output_cntl = info->SavedReg.disp_output_cntl; if (info->ChipFamily == CHIP_FAMILY_R200 || - info->ChipFamily == CHIP_FAMILY_R300 || - info->ChipFamily == CHIP_FAMILY_R350 || - info->ChipFamily == CHIP_FAMILY_RV350) { + IS_R300_VARIANT) { save->disp_output_cntl &= ~(RADEON_DISP_DAC_SOURCE_MASK | RADEON_DISP_DAC2_SOURCE_MASK); if (pRADEONEnt->MonType1 != MT_CRT) { @@ -6220,7 +7843,7 @@ hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; if (!hsync_wid) hsync_wid = 1; - hsync_start = mode->CrtcHSyncStart - 8 + hsync_fudge; + hsync_start = mode->CrtcHSyncStart - 8; save->crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff) | ((hsync_wid & 0x3f) << 16) @@ -6251,33 +7874,57 @@ ? RADEON_CRTC2_V_SYNC_POL : 0)); - save->crtc2_offset = 0; - save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL); + /* It seems all fancy options apart from pflip can be safely disabled + */ + save->crtc2_offset = pScrn->fbOffset; + save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & RADEON_CRTC_OFFSET_FLIP_CNTL; + if (info->tilingEnabled) { + if (IS_R300_VARIANT) + save->crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | + R300_CRTC_MICRO_TILE_BUFFER_DIS | + R300_CRTC_MACRO_TILE_EN); + else + save->crtc2_offset_cntl |= RADEON_CRTC_TILE_EN; + } + else { + if (IS_R300_VARIANT) + save->crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | + R300_CRTC_MICRO_TILE_BUFFER_DIS | + R300_CRTC_MACRO_TILE_EN); + else + save->crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN; + } + /* this should be right */ + if (info->MergedFB) { + save->crtc2_pitch = (((info->CRT2pScrn->displayWidth * pScrn->bitsPerPixel) + + ((pScrn->bitsPerPixel * 8) -1)) / + (pScrn->bitsPerPixel * 8)); + save->crtc2_pitch |= save->crtc2_pitch << 16; + } else { save->crtc2_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) + ((pScrn->bitsPerPixel * 8) -1)) / (pScrn->bitsPerPixel * 8)); save->crtc2_pitch |= save->crtc2_pitch << 16; + } save->disp2_merge_cntl = info->SavedReg.disp2_merge_cntl; save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN); if ((info->DisplayType == MT_DFP && info->IsSecondary) || - info->CloneType == MT_DFP) { + info->MergeType == MT_DFP) { save->crtc2_gen_cntl = (RADEON_CRTC2_EN | (format << 8)); save->fp2_h_sync_strt_wid = save->crtc2_h_sync_strt_wid; save->fp2_v_sync_strt_wid = save->crtc2_v_sync_strt_wid; - save->fp2_gen_cntl = (RADEON_FP2_PANEL_FORMAT | - RADEON_FP2_ON); - if (info->ChipFamily >= CHIP_FAMILY_R200) { - save->fp2_gen_cntl |= RADEON_FP2_DV0_EN; - } + save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl | RADEON_FP2_ON; + save->fp2_gen_cntl &= ~(RADEON_FP2_BLANK_EN); - if (info->ChipFamily == CHIP_FAMILY_R200 || - info->ChipFamily == CHIP_FAMILY_R300 || - info->ChipFamily == CHIP_FAMILY_R350 || - info->ChipFamily == CHIP_FAMILY_RV350) { - save->fp2_gen_cntl &= ~RADEON_FP2_SOURCE_SEL_MASK; - save->fp2_gen_cntl |= RADEON_FP2_SOURCE_SEL_CRTC2; + if ((info->ChipFamily == CHIP_FAMILY_R200) || + IS_R300_VARIANT) { + save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | + RADEON_FP2_DVO_RATE_SEL_SDR); + + save->fp2_gen_cntl |= (R200_FP2_SOURCE_SEL_CRTC2 | + RADEON_FP2_DVO_EN); } else { save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_MASK; save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; @@ -6288,19 +7935,28 @@ else save->fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format */ - /* FIXME: When there are two DFPs, the 2nd DFP is driven by the - * external TMDS transmitter. It may have a problem at - * high dot clock for certain panels. - */ + } - /* If BIOS has not turned it on, we'll keep it on so that we'll - * have a valid VGA screen even after X quits or VT is switched - * to the console mode. - */ - info->SavedReg.fp2_gen_cntl = RADEON_FP2_ON; + /* We must set SURFACE_CNTL properly on the second screen too */ + save->surface_cntl = 0; +#if X_BYTE_ORDER == X_BIG_ENDIAN + /* We must set both apertures as they can be both used to map the entire + * video memory. -BenH. + */ + switch (pScrn->bitsPerPixel) { + case 16: + save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP; + save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP; + break; + + case 32: + save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP; + save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP; + break; } +#endif - RADEONTRACE(("Pitch = %d bytes (virtualX = %d, displayWidth = %d)\n", + RADEONTRACE(("Pitch = %ld bytes (virtualX = %d, displayWidth = %d)\n", save->crtc2_pitch, pScrn->virtualX, info->CurrentLayout.displayWidth)); @@ -6322,23 +7978,23 @@ */ if ((info->DisplayType != MT_DFP) && (info->DisplayType != MT_LCD)) { - save->fp_crtc_h_total_disp = orig->fp_crtc_h_total_disp; - save->fp_crtc_v_total_disp = orig->fp_crtc_v_total_disp; - save->fp_gen_cntl = 0; - save->fp_h_sync_strt_wid = orig->fp_h_sync_strt_wid; - save->fp_horz_stretch = 0; - save->fp_v_sync_strt_wid = orig->fp_v_sync_strt_wid; - save->fp_vert_stretch = 0; - save->lvds_gen_cntl = orig->lvds_gen_cntl; - save->lvds_pll_cntl = orig->lvds_pll_cntl; - save->tmds_pll_cntl = orig->tmds_pll_cntl; - save->tmds_transmitter_cntl= orig->tmds_transmitter_cntl; - - save->lvds_gen_cntl |= ( RADEON_LVDS_DISPLAY_DIS | (1 << 23)); - save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON | RADEON_LVDS_ON); - save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); + save->fp_crtc_h_total_disp = orig->fp_crtc_h_total_disp; + save->fp_crtc_v_total_disp = orig->fp_crtc_v_total_disp; + save->fp_gen_cntl = 0; + save->fp_h_sync_strt_wid = orig->fp_h_sync_strt_wid; + save->fp_horz_stretch = 0; + save->fp_v_sync_strt_wid = orig->fp_v_sync_strt_wid; + save->fp_vert_stretch = 0; + save->lvds_gen_cntl = orig->lvds_gen_cntl; + save->lvds_pll_cntl = orig->lvds_pll_cntl; + save->tmds_pll_cntl = orig->tmds_pll_cntl; + save->tmds_transmitter_cntl= orig->tmds_transmitter_cntl; + + save->lvds_gen_cntl |= ( RADEON_LVDS_DISPLAY_DIS | (1 << 23)); + save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON | RADEON_LVDS_ON); + save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); - return; + return; } if (info->PanelXRes == 0 || info->PanelYRes == 0) { @@ -6411,9 +8067,19 @@ RADEON_FP_CRTC_DONT_SHADOW_HEND ); if (pScrn->rgbBits == 8) - save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ + save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ else - save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ + save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ + + if (IS_R300_VARIANT || + (info->ChipFamily == CHIP_FAMILY_R200)) { + save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; + if (mode->Flags & RADEON_USE_RMX) + save->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; + else + save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; + } else + save->fp_gen_cntl |= RADEON_FP_SEL_CRTC1; save->lvds_gen_cntl = orig->lvds_gen_cntl; save->lvds_pll_cntl = orig->lvds_pll_cntl; @@ -6428,7 +8094,7 @@ save->tmds_pll_cntl = orig->tmds_pll_cntl; save->tmds_transmitter_cntl= orig->tmds_transmitter_cntl; - if (info->PanelOff && info->Clone) { + if (info->PanelOff && info->MergedFB) { info->OverlayOnCRTC2 = TRUE; if (info->DisplayType == MT_LCD) { /* Turning off LVDS_ON seems to make panel white blooming. @@ -6441,15 +8107,6 @@ save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); } else { if (info->DisplayType == MT_LCD) { - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - - /* BIOS will use this setting to reset displays upon lid close/open. - * Here we let BIOS controls LCD, but the driver will control the external CRT. - */ - if (info->Clone || pRADEONEnt->HasSecondary) - save->bios_5_scratch = 0x01020201; - else - save->bios_5_scratch = orig->bios_5_scratch; save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON); save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); @@ -6464,9 +8121,7 @@ break; } } - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350) || + if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RV280)) { if (tmp & 0xfff00000) save->tmds_pll_cntl = tmp; @@ -6474,21 +8129,75 @@ save->tmds_pll_cntl = (orig->tmds_pll_cntl & 0xfff00000) | tmp; } else save->tmds_pll_cntl = tmp; - RADEONTRACE(("TMDS_PLL from %x to %x\n", + RADEONTRACE(("TMDS_PLL from %lx to %lx\n", orig->tmds_pll_cntl, save->tmds_pll_cntl)); - save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLRST); - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350) || + save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLRST); + if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_R200) || !info->HasCRTC2) save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); - else /* weird, RV chips got this bit reversed? */ - save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN); + else /* weird, RV chips got this bit reversed? */ + save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN); save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); - } + } + } + + info->BiosHotkeys = FALSE; + /* + * Allow the bios to toggle outputs. see below for more. + */ + if (xf86ReturnOptValBool(info->Options, OPTION_BIOS_HOTKEYS, FALSE)) { + info->BiosHotkeys = TRUE; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIOS HotKeys Enabled\n"); + } else { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIOS HotKeys Disabled\n"); + } + + if (info->IsMobility && (!info->BiosHotkeys)) { + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + + /* To work correctly with laptop hotkeys. + * Since there is no machnism for accessing ACPI events + * and the driver currently doesn't know how to validate + * a mode dynamically, we have to tell BIOS don't do + * display switching after X has started. + * If LCD is on, lid close/open should still work + * with below settings + */ + if (info->DisplayType == MT_LCD) { + if (pRADEONEnt->MonType2 == MT_CRT) + save->bios_5_scratch = 0x0201; + else if (pRADEONEnt->MonType2 == MT_DFP) + save->bios_5_scratch = 0x0801; + else + save->bios_5_scratch = orig->bios_5_scratch; + } else { + if (pRADEONEnt->MonType2 == MT_CRT) + save->bios_5_scratch = 0x0200; + else if (pRADEONEnt->MonType2 == MT_DFP) + save->bios_5_scratch = 0x0800; + else + save->bios_5_scratch = 0x0; + } + save->bios_4_scratch = 0x4; + save->bios_6_scratch = orig->bios_6_scratch | 0x40000000; + + } else if (info->IsMobility && (info->DisplayType == MT_LCD)) { + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + + /* BIOS will use this setting to reset displays upon lid close/open. + * Here we let BIOS controls LCD, but the driver will control the external CRT. + */ + if (info->MergedFB || pRADEONEnt->HasSecondary) + save->bios_5_scratch = 0x01020201; + else + save->bios_5_scratch = orig->bios_5_scratch; + + save->bios_4_scratch = orig->bios_4_scratch; + save->bios_6_scratch = orig->bios_6_scratch; + } save->fp_crtc_h_total_disp = save->crtc_h_total_disp; @@ -6498,11 +8207,11 @@ } /* Define PLL registers for requested video mode */ -static void RADEONInitPLLRegisters(RADEONSavePtr save, RADEONInfoPtr info, +static void RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, + RADEONSavePtr save, RADEONPLLPtr pll, double dot_clock) { unsigned long freq = dot_clock * 100; - RADEONPLLPtr pll = &info->pll; struct { int divider; @@ -6524,6 +8233,13 @@ { 0, 0 } }; + if (info->UseBiosDividers) { + save->ppll_ref_div = info->RefDivider; + save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16); + save->htotal_cntl = 0; + return; + } + if (freq > pll->max_pll_freq) freq = pll->max_pll_freq; if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12; @@ -6545,30 +8261,30 @@ pll->reference_freq); save->post_div = post_div->divider; - RADEONTRACE(("dc=%d, of=%d, fd=%d, pd=%d\n", + RADEONTRACE(("dc=%ld, of=%ld, fd=%d, pd=%d\n", save->dot_clock_freq, save->pll_output_freq, save->feedback_div, save->post_div)); save->ppll_ref_div = pll->reference_div; - - /* - * on iBooks the LCD pannel needs tweaked PLL timings + /* + * on iBooks the LCD pannel needs tweaked PLL timings */ #ifdef __powerpc__ if (xf86ReturnOptValBool(info->Options, OPTION_IBOOKHACKS, FALSE)) - save->ppll_div_3 = 0x000600ad; + save->ppll_div_3 = 0x000600ad; else #endif - save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16)); + save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16)); save->htotal_cntl = 0; } /* Define PLL2 registers for requested video mode */ -static void RADEONInitPLL2Registers(RADEONSavePtr save, RADEONPLLPtr pll, - double dot_clock) +static void RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, + RADEONPLLPtr pll, double dot_clock, + int no_odd_postdiv) { unsigned long freq = dot_clock * 100; @@ -6595,6 +8311,11 @@ if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12; for (post_div = &post_divs[0]; post_div->divider; ++post_div) { + /* Odd post divider value don't work properly on the second digital + * output + */ + if (no_odd_postdiv && (post_div->divider & 1)) + continue; save->pll_output_freq_2 = post_div->divider * freq; if (save->pll_output_freq_2 >= pll->min_pll_freq && save->pll_output_freq_2 <= pll->max_pll_freq) break; @@ -6611,7 +8332,7 @@ pll->reference_freq); save->post_div_2 = post_div->divider; - RADEONTRACE(("dc=%d, of=%d, fd=%d, pd=%d\n", + RADEONTRACE(("dc=%ld, of=%ld, fd=%d, pd=%d\n", save->dot_clock_freq_2, save->pll_output_freq_2, save->feedback_div_2, @@ -6623,6 +8344,7 @@ save->htotal_cntl2 = 0; } +#if 0 /* Define initial palette for requested video mode. This doesn't do * anything for XFree86 4.0. */ @@ -6630,6 +8352,7 @@ { save->palette_valid = FALSE; } +#endif /* Define registers for a requested video mode */ static Bool RADEONInit(ScrnInfoPtr pScrn, DisplayModePtr mode, @@ -6689,38 +8412,59 @@ info->Flags = mode->Flags; + RADEONInitMemMapRegisters(pScrn, save, info); RADEONInitCommonRegisters(save, info); if (info->IsSecondary) { if (!RADEONInitCrtc2Registers(pScrn, save, mode, info)) return FALSE; - RADEONInitPLL2Registers(save, &info->pll, dot_clock); + RADEONInitPLL2Registers(pScrn, save, &info->pll, dot_clock, info->DisplayType != MT_CRT); + } else if (info->MergedFB) { + if (!RADEONInitCrtcRegisters(pScrn, save, + ((RADEONMergedDisplayModePtr)(pointer)mode->Private)->CRT1, info)) + return FALSE; + dot_clock = (((RADEONMergedDisplayModePtr)(pointer)mode->Private)->CRT1)->Clock / 1000.0; + if (dot_clock) { + RADEONInitPLLRegisters(pScrn, info, save, &info->pll, dot_clock); + } else { + save->ppll_ref_div = info->SavedReg.ppll_ref_div; + save->ppll_div_3 = info->SavedReg.ppll_div_3; + save->htotal_cntl = info->SavedReg.htotal_cntl; + } + RADEONInitCrtc2Registers(pScrn, save, + ((RADEONMergedDisplayModePtr)(pointer)mode->Private)->CRT2, info); + dot_clock = (((RADEONMergedDisplayModePtr)(pointer)mode->Private)->CRT2)->Clock / 1000.0; + RADEONInitPLL2Registers(pScrn, save, &info->pll, dot_clock, info->MergeType != MT_CRT); } else { if (!RADEONInitCrtcRegisters(pScrn, save, mode, info)) return FALSE; dot_clock = mode->Clock/1000.0; if (dot_clock) { - if (info->UseBiosDividers) { - save->ppll_ref_div = info->RefDivider; - save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16); - save->htotal_cntl = 0; - } - else - RADEONInitPLLRegisters(save, info, dot_clock); + RADEONInitPLLRegisters(pScrn, info, save, &info->pll, dot_clock); } else { save->ppll_ref_div = info->SavedReg.ppll_ref_div; save->ppll_div_3 = info->SavedReg.ppll_div_3; save->htotal_cntl = info->SavedReg.htotal_cntl; } - if (info->Clone && info->CurCloneMode) { - RADEONInitCrtc2Registers(pScrn, save, info->CurCloneMode, info); - dot_clock = info->CurCloneMode->Clock / 1000.0; - RADEONInitPLL2Registers(save, &info->pll, dot_clock); - } - if (!info->PaletteSavedOnVT) RADEONInitPalette(save); + /* Not used for now: */ + /* if (!info->PaletteSavedOnVT) RADEONInitPalette(save); */ } - RADEONInitFPRegisters(pScrn, &info->SavedReg, save, mode, info); + /* make RMX work for mergedfb modes on the LCD */ + if (info->MergedFB) { + if ((info->MergeType == MT_LCD) || (info->MergeType == MT_DFP)) { + /* I suppose crtc2 could drive the FP as well... */ + RADEONInitFPRegisters(pScrn, &info->SavedReg, save, + ((RADEONMergedDisplayModePtr)(pointer)mode->Private)->CRT2, info); + } + else { + RADEONInitFPRegisters(pScrn, &info->SavedReg, save, + ((RADEONMergedDisplayModePtr)(pointer)mode->Private)->CRT1, info); + } + } + else { + RADEONInitFPRegisters(pScrn, &info->SavedReg, save, mode, info); + } RADEONTRACE(("RADEONInit returns %p\n", save)); return TRUE; @@ -6731,6 +8475,8 @@ { RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONTRACE(("RADEONModeInit()\n")); + if (!RADEONInit(pScrn, mode, &info->ModeReg)) return FALSE; pScrn->vtSema = TRUE; @@ -6751,6 +8497,8 @@ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; Bool unblank; + RADEONTRACE(("RADEONSaveScreen(%d)\n", mode)); + unblank = xf86IsUnblank(mode); if (unblank) SetTimeSinceLastInputEvent(); @@ -6761,10 +8509,31 @@ return TRUE; } +static void +RADEONResetDPI(ScrnInfoPtr pScrn, Bool force) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + ScreenPtr pScreen = screenInfo.screens[pScrn->scrnIndex]; + + if(force || + (info->RADEONDPIVX != pScrn->virtualX) || + (info->RADEONDPIVY != pScrn->virtualY) + ) { + + pScreen->mmWidth = (pScrn->virtualX * 254 + pScrn->xDpi * 5) / (pScrn->xDpi * 10); + pScreen->mmHeight = (pScrn->virtualY * 254 + pScrn->yDpi * 5) / (pScrn->yDpi * 10); + + info->RADEONDPIVX = pScrn->virtualX; + info->RADEONDPIVY = pScrn->virtualY; + + } +} + Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); + Bool tilingOld = info->tilingEnabled; Bool ret; #ifdef XF86DRI Bool CPStarted = info->CPStarted; @@ -6775,71 +8544,65 @@ } #endif - if (info->accelOn) info->accel->Sync(pScrn); + RADEONTRACE(("RADEONSwitchMode() !n")); + + if (info->allowColorTiling) { + if (info->MergedFB) { + if ((((RADEONMergedDisplayModePtr)(pointer)mode->Private)->CRT1->Flags & + (V_DBLSCAN | V_INTERLACE)) || + (((RADEONMergedDisplayModePtr)(pointer)mode->Private)->CRT2->Flags & + (V_DBLSCAN | V_INTERLACE))) + info->tilingEnabled = FALSE; + else info->tilingEnabled = TRUE; + } + else { + info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; + } +#ifdef XF86DRI + if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) { + RADEONSAREAPrivPtr pSAREAPriv; + drmRadeonSetParam radeonsetparam; + memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam)); + radeonsetparam.param = RADEON_SETPARAM_SWITCH_TILING; + radeonsetparam.value = info->tilingEnabled ? 1 : 0; + if (drmCommandWrite(info->drmFD, DRM_RADEON_SETPARAM, + &radeonsetparam, sizeof(drmRadeonSetParam)) < 0) + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "[drm] failed changing tiling status\n"); + pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); + info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; + } +#endif + } + + if (info->accelOn && info->accel) + (*info->accel->Sync)(pScrn); if (info->FBDev) { RADEONSaveFBDevRegisters(pScrn, &info->ModeReg); ret = fbdevHWSwitchMode(scrnIndex, mode, flags); + pScrn->displayWidth = fbdevHWGetLineLength(pScrn) + / info->CurrentLayout.pixel_bytes; RADEONRestoreFBDevRegisters(pScrn, &info->ModeReg); } else { info->IsSwitching = TRUE; - if (info->Clone && info->CloneModes) { - DisplayModePtr clone_mode = info->CloneModes; - - /* Try to match a mode on primary head - * FIXME: This may not be good if both heads don't have - * exactly the same list of mode. - */ - while (1) { - if ((clone_mode->HDisplay == mode->HDisplay) && - (clone_mode->VDisplay == mode->VDisplay) && - (!info->PanelOff)) { - info->CloneFrameX0 = (info->CurCloneMode->HDisplay + - info->CloneFrameX0 - - clone_mode->HDisplay - 1) / 2; - info->CloneFrameY0 = - (info->CurCloneMode->VDisplay + info->CloneFrameY0 - - clone_mode->VDisplay - 1) / 2; - info->CurCloneMode = clone_mode; - break; - } - - if (!clone_mode->next) { - info->CurCloneMode = info->CloneModes; - break; - } - - clone_mode = clone_mode->next; - } - } ret = RADEONModeInit(xf86Screens[scrnIndex], mode); - - if (info->CurCloneMode) { - if (info->CloneFrameX0 + info->CurCloneMode->HDisplay >= - pScrn->virtualX) - info->CloneFrameX0 = - pScrn->virtualX - info->CurCloneMode->HDisplay; - else if (info->CloneFrameX0 < 0) - info->CloneFrameX0 = 0; - - if (info->CloneFrameY0 + info->CurCloneMode->VDisplay >= - pScrn->virtualY) - info->CloneFrameY0 = - pScrn->virtualY - info->CurCloneMode->VDisplay; - else if (info->CloneFrameY0 < 0) - info->CloneFrameY0 = 0; - - RADEONDoAdjustFrame(pScrn, info->CloneFrameX0, info->CloneFrameY0, - TRUE); - } - info->IsSwitching = FALSE; } + if (info->tilingEnabled != tilingOld) { + /* need to redraw front buffer, I guess this can be considered a hack ? */ + xf86EnableDisableFBAccess(scrnIndex, FALSE); + RADEONChangeSurfaces(pScrn); + xf86EnableDisableFBAccess(scrnIndex, TRUE); + /* xf86SetRootClip would do, but can't access that here */ + } + if (info->accelOn) { - info->accel->Sync(pScrn); + if (info->accel) + (*info->accel->Sync)(pScrn); RADEONEngineRestore(pScrn); } @@ -6850,12 +8613,22 @@ } #endif + /* Since RandR (indirectly) uses SwitchMode(), we need to + * update our Xinerama info here, too, in case of resizing + */ + if (info->MergedFB) { + RADEONMergedFBResetDpi(pScrn, FALSE); + RADEONUpdateXineramaScreenInfo(pScrn); + } else if(info->constantDPI) { + RADEONResetDPI(pScrn, FALSE); + } + return ret; } #ifdef X_XF86MiscPassMessage Bool RADEONHandleMessage(int scrnIndex, const char* msgtype, - const char* msgval, char** retmsg) + const char* msgval, char** retmsg) { ErrorF("RADEONHandleMessage(%d, \"%s\", \"%s\", retmsg)\n", scrnIndex, msgtype, msgval); @@ -6866,7 +8639,7 @@ /* Used to disallow modes that are not supported by the hardware */ ModeStatus RADEONValidMode(int scrnIndex, DisplayModePtr mode, - Bool verbose, int flag) + Bool verbose, int flag) { /* There are problems with double scan mode at high clocks * They're likely related PLL and display buffer settings. @@ -6886,35 +8659,101 @@ { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - int reg, Base = y * info->CurrentLayout.displayWidth + x; + int reg, Base, regcntl, crtcoffsetcntl, xytilereg, crtcxytile = 0; #ifdef XF86DRI RADEONSAREAPrivPtr pSAREAPriv; + XF86DRISAREAPtr pSAREA; #endif - switch (info->CurrentLayout.pixel_code) { - case 15: - case 16: Base *= 2; break; - case 24: Base *= 3; break; - case 32: Base *= 4; break; +#if 0 /* Verbose */ + RADEONTRACE(("RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone)); +#endif + + if (info->showCache && y) { + int lastline = info->FbMapSize / + ((pScrn->displayWidth * pScrn->bitsPerPixel) / 8); + + lastline -= pScrn->currentMode->VDisplay; + y += (pScrn->virtualY - 1) * (y / 3 + 1); + if (y > lastline) y = lastline; } - Base &= ~7; /* 3 lower bits are always 0 */ + Base = pScrn->fbOffset; + /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the + drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes + flickering when scrolling vertically in a virtual screen, possibly because crtc will + pick up the new offset value at the end of each scanline, but the new offset_cntl value + only after a vsync. We'd probably need to wait (in drm) for vsync and only then update + OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ if (clone || info->IsSecondary) { - Base += pScrn->fbOffset; reg = RADEON_CRTC2_OFFSET; + regcntl = RADEON_CRTC2_OFFSET_CNTL; + xytilereg = R300_CRTC2_TILE_X0_Y0; } else { reg = RADEON_CRTC_OFFSET; + regcntl = RADEON_CRTC_OFFSET_CNTL; + xytilereg = R300_CRTC_TILE_X0_Y0; } - + crtcoffsetcntl = INREG(regcntl) & ~0xf; +#if 0 + /* try to get rid of flickering when scrolling at least for 2d */ #ifdef XF86DRI - if (info->directRenderingEnabled) { + if (!info->have3DWindows) +#endif + crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; +#endif + if (info->tilingEnabled) { + if (IS_R300_VARIANT) { + /* On r300/r400 when tiling is enabled crtc_offset is set to the address of + * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc + * Makes tiling MUCH easier. + */ + crtcxytile = x | (y << 16); + Base &= ~0x7ff; + } else { + int byteshift = info->CurrentLayout.bitsPerPixel >> 4; + /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ + int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; + Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); + crtcoffsetcntl = crtcoffsetcntl | (y % 16); + } + } + else { + int offset = y * info->CurrentLayout.displayWidth + x; + switch (info->CurrentLayout.pixel_code) { + case 15: + case 16: offset *= 2; break; + case 24: offset *= 3; break; + case 32: offset *= 4; break; + } + Base += offset; + } - pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); + Base &= ~7; /* 3 lower bits are always 0 */ + +#ifdef XF86DRI + if (info->directRenderingInited) { + /* note cannot use pScrn->pScreen since this is unitialized when called from + RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ + /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for + *** pageflipping! + ***/ + pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); + /* can't get at sarea in a semi-sane way? */ + pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); if (clone || info->IsSecondary) { pSAREAPriv->crtc2_base = Base; } + else { + pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes) + % info->CurrentLayout.displayWidth; + pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes) + / info->CurrentLayout.displayWidth; + pSAREA->frame.width = pScrn->frameX1 - x + 1; + pSAREA->frame.height = pScrn->frameY1 - y + 1; + } if (pSAREAPriv->pfCurrentPage == 1) { Base += info->backOffset; @@ -6923,6 +8762,13 @@ #endif OUTREG(reg, Base); + + if (IS_R300_VARIANT) { + OUTREG(xytilereg, crtcxytile); + } else { + OUTREG(regcntl, crtcoffsetcntl); + } + } void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) @@ -6931,19 +8777,22 @@ RADEONInfoPtr info = RADEONPTR(pScrn); #ifdef XF86DRI - if (info->CPStarted) DRILock(pScrn->pScreen, 0); + if (info->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); #endif - if (info->accelOn) info->accel->Sync(pScrn); + if (info->accelOn && info->accel) + (*info->accel->Sync)(pScrn); - if (info->FBDev) { + if(info->MergedFB) { + RADEONAdjustFrameMerged(scrnIndex, x, y, flags); + } else if (info->FBDev) { fbdevHWAdjustFrame(scrnIndex, x, y, flags); } else { RADEONDoAdjustFrame(pScrn, x, y, FALSE); } #ifdef XF86DRI - if (info->CPStarted) DRIUnlock(pScrn->pScreen); + if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); #endif } @@ -6954,13 +8803,26 @@ { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; RADEONTRACE(("RADEONEnterVT\n")); - RADEONSave(pScrn); + if (INREG(RADEON_CONFIG_MEMSIZE) == 0) { /* Softboot V_BIOS */ + xf86Int10InfoPtr pInt; + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n"); + pInt = xf86InitInt10(info->pEnt->index); + if (pInt) { + pInt->num = 0xe6; + xf86ExecX86int10(pInt); + xf86FreeInt10(pInt); + } + } + + /* Makes sure the engine is idle before doing anything */ + RADEONWaitForIdleMMIO(pScrn); if (info->FBDev) { - unsigned char *RADEONMMIO = info->MMIO; if (!fbdevHWEnterVT(scrnIndex,flags)) return FALSE; info->PaletteSavedOnVT = FALSE; info->ModeReg.surface_cntl = INREG(RADEON_SURFACE_CNTL); @@ -6969,10 +8831,19 @@ } else if (!RADEONModeInit(pScrn, pScrn->currentMode)) return FALSE; + if (!info->IsSecondary) + RADEONRestoreSurfaces(pScrn, &info->ModeReg); #ifdef XF86DRI if (info->directRenderingEnabled) { - /* get the Radeon back into shape after resume */ + if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize) + { + /* we need to backup the PCIE GART TABLE from fb memory */ + memcpy(info->FB + info->pciGartOffset, info->pciGartBackup, info->pciGartSize); + } + + /* get the DRI back into shape after resume */ RADEONDRIResume(pScrn->pScreen); + RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg); } #endif /* this will get XVideo going again, but only if XVideo was initialised @@ -6991,9 +8862,6 @@ #endif pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); - if (info->CurCloneMode) { - RADEONDoAdjustFrame(pScrn, info->CloneFrameX0, info->CloneFrameY0, TRUE); - } return TRUE; } @@ -7009,9 +8877,15 @@ RADEONTRACE(("RADEONLeaveVT\n")); #ifdef XF86DRI - if (RADEONPTR(pScrn)->directRenderingEnabled) { + if (RADEONPTR(pScrn)->directRenderingInited) { DRILock(pScrn->pScreen, 0); RADEONCP_STOP(pScrn, info); + + if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize) + { + /* we need to backup the PCIE GART TABLE from fb memory */ + memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize); + } } #endif @@ -7025,6 +8899,8 @@ } RADEONRestore(pScrn); + + RADEONTRACE(("Ok, leaving now...\n")); } /* Called at the end of each server generation. Restore the original @@ -7038,30 +8914,38 @@ RADEONTRACE(("RADEONCloseScreen\n")); + /* Mark acceleration as stopped or we might try to access the engine at + * wrong times, especially if we had DRI, after DRI has been stopped + */ + info->accelOn = FALSE; + #ifdef XF86DRI - /* Disable direct rendering */ - if (info->directRenderingEnabled) { - RADEONDRICloseScreen(pScreen); - info->directRenderingEnabled = FALSE; - } + RADEONDRIStop(pScreen); #endif if (pScrn->vtSema) { + RADEONDisplayPowerManagementSet(pScrn, DPMSModeOn, 0); RADEONRestore(pScrn); } - RADEONUnmapMem(pScrn); - if (info->accel) XAADestroyInfoRec(info->accel); + RADEONTRACE(("Disposing accel...\n")); + if (info->accel) + XAADestroyInfoRec(info->accel); info->accel = NULL; - if (info->scratch_save) xfree(info->scratch_save); + if (info->scratch_save) + xfree(info->scratch_save); info->scratch_save = NULL; + RADEONTRACE(("Disposing cusor info\n")); if (info->cursor) xf86DestroyCursorInfoRec(info->cursor); info->cursor = NULL; + RADEONTRACE(("Disposing DGA\n")); if (info->DGAModes) xfree(info->DGAModes); info->DGAModes = NULL; + RADEONTRACE(("Unmapping memory\n")); + RADEONUnmapMem(pScrn); pScrn->vtSema = FALSE; @@ -7075,10 +8959,48 @@ void RADEONFreeScreen(int scrnIndex, int flags) { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); RADEONTRACE(("RADEONFreeScreen\n")); - if (xf86LoaderCheckSymbol("vgaHWFreeHWRec")) + /* when server quits at PreInit, we don't need do this anymore*/ + if (!info) return; + + if(info->MergedFB) { + if(pScrn->modes) { + pScrn->currentMode = pScrn->modes; + do { + DisplayModePtr p = pScrn->currentMode->next; + if(pScrn->currentMode->Private) + xfree(pScrn->currentMode->Private); + xfree(pScrn->currentMode); + pScrn->currentMode = p; + } while(pScrn->currentMode != pScrn->modes); + } + pScrn->currentMode = info->CRT1CurrentMode; + pScrn->modes = info->CRT1Modes; + info->CRT1CurrentMode = NULL; + info->CRT1Modes = NULL; + + if(info->CRT2pScrn) { + if(info->CRT2pScrn->modes) { + while(info->CRT2pScrn->modes) + xf86DeleteMode(&info->CRT2pScrn->modes, info->CRT2pScrn->modes); + } + if(info->CRT2pScrn->monitor) { + if(info->CRT2pScrn->monitor->Modes) { + while(info->CRT2pScrn->monitor->Modes) + xf86DeleteMode(&info->CRT2pScrn->monitor->Modes, info->CRT2pScrn->monitor->Modes); + } + if(info->CRT2pScrn->monitor->DDC) xfree(info->CRT2pScrn->monitor->DDC); + xfree(info->CRT2pScrn->monitor); + } + xfree(info->CRT2pScrn); + info->CRT2pScrn = NULL; + } + } + + if (info->UseVGAHW) vgaHWFreeHWRec(pScrn); RADEONFreeRec(pScrn); } @@ -7088,12 +9010,12 @@ * * Note for current DAC mapping when calling this function: * For most of cards: - * single CRT: Driver doesn't change the existing CRTC->DAC mapping, + * single CRT: Driver doesn't change the existing CRTC->DAC mapping, * CRTC1 could be driving either DAC or both DACs. * CRT+CRT: CRTC1->TV DAC, CRTC2->Primary DAC * DFP/LCD+CRT: CRTC2->TV DAC, CRTC2->Primary DAC. * Some boards have two DACs reversed or don't even have a primary DAC, - * this is reflected in pRADEONEnt->ReversedDAC. And radeon 7200 doesn't + * this is reflected in pRADEONEnt->ReversedDAC. And radeon 7200 doesn't * have a second DAC. * It's kind of messy, we'll need to redo DAC mapping part some day. */ @@ -7106,7 +9028,7 @@ CARD32 dac_cntl; CARD32 dac_macro_cntl = 0; dac_cntl = INREG(RADEON_DAC_CNTL); - if ((!info->IsMobility) || (info->ChipFamily == CHIP_FAMILY_RV350)) + if ((!info->IsMobility) || (info->ChipFamily == CHIP_FAMILY_RV350)) dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL); if (IsOn) { dac_cntl &= ~RADEON_DAC_PDWN; @@ -7120,7 +9042,7 @@ RADEON_DAC_PDWN_B); } OUTREG(RADEON_DAC_CNTL, dac_cntl); - if ((!info->IsMobility) || (info->ChipFamily == CHIP_FAMILY_RV350)) + if ((!info->IsMobility) || (info->ChipFamily == CHIP_FAMILY_RV350)) OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); } else { if (info->ChipFamily != CHIP_FAMILY_R200) { @@ -7140,9 +9062,9 @@ } else { CARD32 fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); if (IsOn) { - fp2_gen_cntl |= RADEON_FP2_DV0_EN; + fp2_gen_cntl |= RADEON_FP2_DVO_EN; } else { - fp2_gen_cntl &= ~RADEON_FP2_DV0_EN; + fp2_gen_cntl &= ~RADEON_FP2_DVO_EN; } OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); } @@ -7158,11 +9080,16 @@ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; + if (!pScrn->vtSema) return; + + RADEONTRACE(("RADEONDisplayPowerManagementSet(%d,0x%x)\n", PowerManagementMode, flags)); + #ifdef XF86DRI if (info->CPStarted) DRILock(pScrn->pScreen, 0); #endif - if (info->accelOn) info->accel->Sync(pScrn); + if (info->accelOn && info->accel) + (*info->accel->Sync)(pScrn); if (info->FBDev) { fbdevHWDPMSSet(pScrn, PowerManagementMode, flags); @@ -7180,7 +9107,7 @@ if (info->IsSecondary) OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~mask2); else { - if (info->Clone) + if (info->MergedFB) OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~mask2); OUTREGP(RADEON_CRTC_EXT_CNTL, 0, ~mask1); } @@ -7190,15 +9117,15 @@ /* Screen: Off; HSync: Off, VSync: On */ if (info->IsSecondary) OUTREGP(RADEON_CRTC2_GEN_CNTL, - RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS, + (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), ~mask2); else { - if (info->Clone) + if (info->MergedFB) OUTREGP(RADEON_CRTC2_GEN_CNTL, - RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS, + (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), ~mask2); OUTREGP(RADEON_CRTC_EXT_CNTL, - RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS, + (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS), ~mask1); } break; @@ -7207,15 +9134,15 @@ /* Screen: Off; HSync: On, VSync: Off */ if (info->IsSecondary) OUTREGP(RADEON_CRTC2_GEN_CNTL, - RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS, + (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), ~mask2); else { - if (info->Clone) + if (info->MergedFB) OUTREGP(RADEON_CRTC2_GEN_CNTL, - RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS, + (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), ~mask2); OUTREGP(RADEON_CRTC_EXT_CNTL, - RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS, + (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS), ~mask1); } break; @@ -7225,7 +9152,7 @@ if (info->IsSecondary) OUTREGP(RADEON_CRTC2_GEN_CNTL, mask2, ~mask2); else { - if (info->Clone) + if (info->MergedFB) OUTREGP(RADEON_CRTC2_GEN_CNTL, mask2, ~mask2); OUTREGP(RADEON_CRTC_EXT_CNTL, mask1, ~mask1); } @@ -7235,36 +9162,32 @@ if (PowerManagementMode == DPMSModeOn) { if (info->IsSecondary) { if (info->DisplayType == MT_DFP) { - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN); - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON); + OUTREGP(RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN); + OUTREGP(RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON); if (info->ChipFamily >= CHIP_FAMILY_R200) { - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN); + OUTREGP(RADEON_FP2_GEN_CNTL, RADEON_FP2_DVO_EN, ~RADEON_FP2_DVO_EN); } } else if (info->DisplayType == MT_CRT) { RADEONDacPowerSet(pScrn, TRUE, !pRADEONEnt->ReversedDAC); } } else { - if (info->Clone) { - if (info->CloneType == MT_DFP) { - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN); - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON); - if (info->ChipFamily >= CHIP_FAMILY_R200) { - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN); - } - } else if (info->CloneType == MT_CRT) { - RADEONDacPowerSet(pScrn, TRUE, !pRADEONEnt->ReversedDAC); + if ((info->MergedFB) && (info->MergeType == MT_DFP)) { + OUTREGP(RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN); + OUTREGP(RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON); + if (info->ChipFamily >= CHIP_FAMILY_R200) { + OUTREGP(RADEON_FP2_GEN_CNTL, RADEON_FP2_DVO_EN, ~RADEON_FP2_DVO_EN); } } if (info->DisplayType == MT_DFP) { - OUTREGP (RADEON_FP_GEN_CNTL, (RADEON_FP_FPON | RADEON_FP_TMDS_EN), - ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN)); + OUTREGP(RADEON_FP_GEN_CNTL, (RADEON_FP_FPON | RADEON_FP_TMDS_EN), + ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN)); } else if (info->DisplayType == MT_LCD) { - OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON); + OUTREGP(RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON); usleep (info->PanelPwrDly * 1000); - OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON); + OUTREGP(RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON); } else if (info->DisplayType == MT_CRT) { - if ((pRADEONEnt->HasSecondary) || info->Clone) { + if ((pRADEONEnt->HasSecondary) || info->MergedFB) { RADEONDacPowerSet(pScrn, TRUE, pRADEONEnt->ReversedDAC); } else { RADEONDacPowerSet(pScrn, TRUE, TRUE); @@ -7278,28 +9201,24 @@ (PowerManagementMode == DPMSModeStandby)) { if (info->IsSecondary) { if (info->DisplayType == MT_DFP) { - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN); - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON); + OUTREGP(RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN); + OUTREGP(RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON); if (info->ChipFamily >= CHIP_FAMILY_R200) { - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN); + OUTREGP(RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DVO_EN); } } else if (info->DisplayType == MT_CRT) { RADEONDacPowerSet(pScrn, FALSE, !pRADEONEnt->ReversedDAC); } } else { - if (info->Clone) { - if(info->CloneType == MT_DFP) { - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN); - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON); - if (info->ChipFamily >= CHIP_FAMILY_R200) { - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN); - } - } else if (info->CloneType == MT_CRT) { - RADEONDacPowerSet(pScrn, FALSE, !pRADEONEnt->ReversedDAC); + if ((info->MergedFB) && (info->MergeType == MT_DFP)) { + OUTREGP(RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN); + OUTREGP(RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON); + if (info->ChipFamily >= CHIP_FAMILY_R200) { + OUTREGP(RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DVO_EN); } } if (info->DisplayType == MT_DFP) { - OUTREGP (RADEON_FP_GEN_CNTL, 0, ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN)); + OUTREGP(RADEON_FP_GEN_CNTL, 0, ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN)); } else if (info->DisplayType == MT_LCD) { unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); @@ -7310,17 +9229,17 @@ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); } - OUTREGP (RADEON_LVDS_GEN_CNTL, 0, - ~(RADEON_LVDS_BLON | RADEON_LVDS_ON)); + OUTREGP(RADEON_LVDS_GEN_CNTL, 0, + ~(RADEON_LVDS_BLON | RADEON_LVDS_ON)); if (info->IsMobility || info->IsIGP) { - OUTPLL(RADEON_PIXCLKS_CNTL, tmpPixclksCntl); + OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl); } } else if (info->DisplayType == MT_CRT) { - if ((pRADEONEnt->HasSecondary) || info->Clone) { + if ((pRADEONEnt->HasSecondary) || info->MergedFB) { RADEONDacPowerSet(pScrn, FALSE, pRADEONEnt->ReversedDAC); } else { - /* single CRT, turning both DACs off, we don't really know + /* single CRT, turning both DACs off, we don't really know * which DAC is actually connected. */ RADEONDacPowerSet(pScrn, FALSE, TRUE); @@ -7336,3 +9255,585 @@ if (info->CPStarted) DRIUnlock(pScrn->pScreen); #endif } + +static void +RADEONGetMergedFBOptions(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + char *strptr; + char *default_hsync = "28-33"; + char *default_vrefresh = "43-72"; + Bool val; + Bool default_range = FALSE; + static const char *mybadparm = "\"%s\" is is not a valid parameter for option \"%s\"\n"; + + if (info->FBDev == TRUE) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "MergedFB does not work with Option UseFBDev, MergedFB mode is disabled\n"); + info->MergedFB = FALSE; + return; + } + + /* collect MergedFB options */ + info->MergedFB = TRUE; + info->UseRADEONXinerama = TRUE; + info->CRT2IsScrn0 = FALSE; + info->CRT2Position = radeonClone; + info->MergedFBXDPI = info->MergedFBYDPI = 0; + info->CRT1XOffs = info->CRT1YOffs = info->CRT2XOffs = info->CRT2YOffs = 0; + info->NonRect = info->HaveNonRect = info->HaveOffsRegions = FALSE; + info->MBXNR1XMAX = info->MBXNR1YMAX = info->MBXNR2XMAX = info->MBXNR2YMAX = 65536; + info->MouseRestrictions = TRUE; + + if (info->MergeType == MT_NONE) { + info->MergedFB = FALSE; + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Failed to detect secondary monitor, MergedFB/Clone mode disabled\n"); + } else if (!pRADEONEnt->MonInfo2) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Failed to detect secondary monitor DDC, default HSync and VRefresh used\n"); + default_range = TRUE; + } + + if (xf86GetOptValBool(info->Options, OPTION_MERGEDFB, &val)) { + if (val) { + info->MergedFB = TRUE; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "MergedFB mode forced on.\n"); + } else { + info->MergedFB = FALSE; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "MergedFB mode forced off.\n"); + } + } + + /* Do some MergedFB mode initialisation */ + if(info->MergedFB) { + info->CRT2pScrn = xalloc(sizeof(ScrnInfoRec)); + if(!info->CRT2pScrn) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Failed to allocate memory for merged pScrn, MergedFB mode is disabled\n"); + info->MergedFB = FALSE; + } else { + memcpy(info->CRT2pScrn, pScrn, sizeof(ScrnInfoRec)); + } + } + if(info->MergedFB) { + int result, ival; + Bool valid = FALSE; + char *tempstr; + strptr = (char *)xf86GetOptValString(info->Options, OPTION_CRT2POS); + if (strptr) { + tempstr = xalloc(strlen(strptr) + 1); + result = sscanf(strptr, "%s %d", tempstr, &ival); + } else { /* Not specified - default is "Clone" */ + tempstr = NULL; + result = 0; + info->CRT2Position = radeonClone; + valid = TRUE; + } + if(result >= 1) { + if(!xf86NameCmp(tempstr,"LeftOf")) { + info->CRT2Position = radeonLeftOf; + valid = TRUE; + if(result == 2) { + if(ival < 0) info->CRT1YOffs = -ival; + else info->CRT2YOffs = ival; + } + info->CRT2IsScrn0 = TRUE; + } else if(!xf86NameCmp(tempstr,"RightOf")) { + info->CRT2Position = radeonRightOf; + valid = TRUE; + if(result == 2) { + if(ival < 0) info->CRT1YOffs = -ival; + else info->CRT2YOffs = ival; + } + info->CRT2IsScrn0 = FALSE; + } else if(!xf86NameCmp(tempstr,"Above")) { + info->CRT2Position = radeonAbove; + valid = TRUE; + if(result == 2) { + if(ival < 0) info->CRT1XOffs = -ival; + else info->CRT2XOffs = ival; + } + info->CRT2IsScrn0 = FALSE; + } else if(!xf86NameCmp(tempstr,"Below")) { + info->CRT2Position = radeonBelow; + valid = TRUE; + if(result == 2) { + if(ival < 0) info->CRT1XOffs = -ival; + else info->CRT2XOffs = ival; + } + info->CRT2IsScrn0 = TRUE; + } else if(!xf86NameCmp(tempstr,"Clone")) { + info->CRT2Position = radeonClone; + if(result == 1) valid = TRUE; + /*info->CRT2IsScrn0 = TRUE;*/ + } + } + if(!valid) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "\"%s\" is not a valid parameter for Option \"CRT2Position\"\n", strptr); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Valid parameters are \"RightOf\", \"LeftOf\", \"Above\", \"Below\", or \"Clone\"\n"); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Except for \"Clone\", the parameter may be followed by an integer.\n"); + } + xfree(tempstr); + + strptr = (char *)xf86GetOptValString(info->Options, OPTION_METAMODES); + if(strptr) { + info->MetaModes = xalloc(strlen(strptr) + 1); + if(info->MetaModes) memcpy(info->MetaModes, strptr, strlen(strptr) + 1); + } + strptr = (char *)xf86GetOptValString(info->Options, OPTION_CRT2HSYNC); + if(strptr) { + info->CRT2HSync = xalloc(strlen(strptr) + 1); + if(info->CRT2HSync) memcpy(info->CRT2HSync, strptr, strlen(strptr) + 1); + } + strptr = (char *)xf86GetOptValString(info->Options, OPTION_CRT2VREFRESH); + if(strptr) { + info->CRT2VRefresh = xalloc(strlen(strptr) + 1); + if(info->CRT2VRefresh) memcpy(info->CRT2VRefresh, strptr, strlen(strptr) + 1); + } + + if(xf86GetOptValBool(info->Options, OPTION_RADEONXINERAMA, &val)) { + if (!val) + info->UseRADEONXinerama = FALSE; + } + if(info->UseRADEONXinerama) { + if(xf86GetOptValBool(info->Options, OPTION_CRT2ISSCRN0, &val)) { + if(val) info->CRT2IsScrn0 = TRUE; + else info->CRT2IsScrn0 = FALSE; + } + if(xf86GetOptValBool(info->Options, OPTION_MERGEDFBNONRECT, &val)) { + info->NonRect = val ? TRUE : FALSE; + } + if(xf86GetOptValBool(info->Options, OPTION_MERGEDFBMOUSER, &val)) { + info->MouseRestrictions = val ? TRUE : FALSE; + } + } + strptr = (char *)xf86GetOptValString(info->Options, OPTION_MERGEDDPI); + if(strptr) { + int val1 = 0, val2 = 0; + sscanf(strptr, "%d %d", &val1, &val2); + if(val1 && val2) { + info->MergedFBXDPI = val1; + info->MergedFBYDPI = val2; + } else { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, mybadparm, strptr, "MergedDPI"); + } + } + } + + if(info->MergedFB) { + /* fill in monitor */ + info->CRT2pScrn->monitor = xalloc(sizeof(MonRec)); + if(info->CRT2pScrn->monitor) { + DisplayModePtr tempm = NULL, currentm = NULL, newm = NULL; + memcpy(info->CRT2pScrn->monitor, pScrn->monitor, sizeof(MonRec)); + info->CRT2pScrn->monitor->DDC = NULL; + info->CRT2pScrn->monitor->Modes = NULL; + info->CRT2pScrn->monitor->id = "CRT2 Monitor"; + tempm = pScrn->monitor->Modes; + while(tempm) { + if(!(newm = xalloc(sizeof(DisplayModeRec)))) break; + memcpy(newm, tempm, sizeof(DisplayModeRec)); + if(!(newm->name = xalloc(strlen(tempm->name) + 1))) { + xfree(newm); + break; + } + strcpy(newm->name, tempm->name); + if(!info->CRT2pScrn->monitor->Modes) + info->CRT2pScrn->monitor->Modes = newm; + if(currentm) { + currentm->next = newm; + newm->prev = currentm; + } + currentm = newm; + tempm = tempm->next; + } + + /* xf86SetDDCproperties(info->CRT2pScrn, pRADEONEnt->MonInfo2); */ + info->CRT2pScrn->monitor->DDC = pRADEONEnt->MonInfo2; + if (default_range) { + RADEONStrToRanges(info->CRT2pScrn->monitor->hsync, default_hsync, MAX_HSYNC); + RADEONStrToRanges(info->CRT2pScrn->monitor->vrefresh, default_vrefresh, MAX_VREFRESH); + } + if(info->CRT2HSync) { + info->CRT2pScrn->monitor->nHsync = + RADEONStrToRanges(info->CRT2pScrn->monitor->hsync, info->CRT2HSync, MAX_HSYNC); + } + if(info->CRT2VRefresh) { + info->CRT2pScrn->monitor->nVrefresh = + RADEONStrToRanges(info->CRT2pScrn->monitor->vrefresh, info->CRT2VRefresh, MAX_VREFRESH); + } + + } else { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Failed to allocate memory for CRT2 monitor, MergedFB mode disabled.\n"); + if(info->CRT2pScrn) xfree(info->CRT2pScrn); + info->CRT2pScrn = NULL; + info->MergedFB = FALSE; + } + } +} + +static void RADEONForceSomeClocks(ScrnInfoPtr pScrn) +{ + /* It appears from r300 and rv100 may need some clocks forced-on */ + CARD32 tmp; + + tmp = INPLL(pScrn, RADEON_SCLK_CNTL); + tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; + OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); +} + +static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + CARD32 tmp; + switch(mode) { + case 0: /* Turn everything OFF (ForceON to everything)*/ + if ( !info->HasCRTC2 ) { + tmp = INPLL(pScrn, RADEON_SCLK_CNTL); + tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | + RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP | + RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE | + RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP | + RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB | + RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM | + RADEON_SCLK_FORCE_RB); + OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); + } else if (info->ChipFamily == CHIP_FAMILY_RV350) { + /* for RV350/M10, no delays are required. */ + tmp = INPLL(pScrn, R300_SCLK_CNTL2); + tmp |= (R300_SCLK_FORCE_TCL | + R300_SCLK_FORCE_GA | + R300_SCLK_FORCE_CBA); + OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); + + tmp = INPLL(pScrn, RADEON_SCLK_CNTL); + tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | + RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | + RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | + R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | + RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | + R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | + R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | + R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); + OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); + tmp |= RADEON_SCLK_MORE_FORCEON; + OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_MCLK_CNTL); + tmp |= (RADEON_FORCEON_MCLKA | + RADEON_FORCEON_MCLKB | + RADEON_FORCEON_YCLKA | + RADEON_FORCEON_YCLKB | + RADEON_FORCEON_MC); + OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); + tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | + RADEON_PIXCLK_DAC_ALWAYS_ONb | + R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); + OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); + tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | + RADEON_PIX2CLK_DAC_ALWAYS_ONb | + RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | + R300_DVOCLK_ALWAYS_ONb | + RADEON_PIXCLK_BLEND_ALWAYS_ONb | + RADEON_PIXCLK_GV_ALWAYS_ONb | + R300_PIXCLK_DVO_ALWAYS_ONb | + RADEON_PIXCLK_LVDS_ALWAYS_ONb | + RADEON_PIXCLK_TMDS_ALWAYS_ONb | + R300_PIXCLK_TRANS_ALWAYS_ONb | + R300_PIXCLK_TVO_ALWAYS_ONb | + R300_P2G2CLK_ALWAYS_ONb | + R300_P2G2CLK_ALWAYS_ONb | + R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); + OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); + } else { + tmp = INPLL(pScrn, RADEON_SCLK_CNTL); + tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); + tmp |= RADEON_SCLK_FORCE_SE; + + if ( !info->HasCRTC2 ) { + tmp |= ( RADEON_SCLK_FORCE_RB | + RADEON_SCLK_FORCE_TDM | + RADEON_SCLK_FORCE_TAM | + RADEON_SCLK_FORCE_PB | + RADEON_SCLK_FORCE_RE | + RADEON_SCLK_FORCE_VIP | + RADEON_SCLK_FORCE_IDCT | + RADEON_SCLK_FORCE_TOP | + RADEON_SCLK_FORCE_DISP1 | + RADEON_SCLK_FORCE_DISP2 | + RADEON_SCLK_FORCE_HDP ); + } else if ((info->ChipFamily == CHIP_FAMILY_R300) || + (info->ChipFamily == CHIP_FAMILY_R350)) { + tmp |= ( RADEON_SCLK_FORCE_HDP | + RADEON_SCLK_FORCE_DISP1 | + RADEON_SCLK_FORCE_DISP2 | + RADEON_SCLK_FORCE_TOP | + RADEON_SCLK_FORCE_IDCT | + RADEON_SCLK_FORCE_VIP); + } + OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); + + usleep(16000); + + if ((info->ChipFamily == CHIP_FAMILY_R300) || + (info->ChipFamily == CHIP_FAMILY_R350)) { + tmp = INPLL(pScrn, R300_SCLK_CNTL2); + tmp |= ( R300_SCLK_FORCE_TCL | + R300_SCLK_FORCE_GA | + R300_SCLK_FORCE_CBA); + OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); + usleep(16000); + } + + if (info->IsIGP) { + tmp = INPLL(pScrn, RADEON_MCLK_CNTL); + tmp &= ~(RADEON_FORCEON_MCLKA | + RADEON_FORCEON_YCLKA); + OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); + usleep(16000); + } + + if ((info->ChipFamily == CHIP_FAMILY_RV200) || + (info->ChipFamily == CHIP_FAMILY_RV250) || + (info->ChipFamily == CHIP_FAMILY_RV280)) { + tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); + tmp |= RADEON_SCLK_MORE_FORCEON; + OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); + usleep(16000); + } + + tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); + tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | + RADEON_PIX2CLK_DAC_ALWAYS_ONb | + RADEON_PIXCLK_BLEND_ALWAYS_ONb | + RADEON_PIXCLK_GV_ALWAYS_ONb | + RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | + RADEON_PIXCLK_LVDS_ALWAYS_ONb | + RADEON_PIXCLK_TMDS_ALWAYS_ONb); + + OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); + usleep(16000); + + tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); + tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | + RADEON_PIXCLK_DAC_ALWAYS_ONb); + OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); + } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Clock Scaling Disabled\n"); + break; + case 1: + if (!info->HasCRTC2) { + tmp = INPLL(pScrn, RADEON_SCLK_CNTL); + if ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) > + RADEON_CFG_ATI_REV_A13) { + tmp &= ~(RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_RB); + } + tmp &= ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | + RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE | + RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE | + RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM | + RADEON_SCLK_FORCE_TDM); + OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); + } else if ((info->ChipFamily == CHIP_FAMILY_R300) || + (info->ChipFamily == CHIP_FAMILY_R350) || + (info->ChipFamily == CHIP_FAMILY_RV350)) { + if (info->ChipFamily == CHIP_FAMILY_RV350) { + tmp = INPLL(pScrn, R300_SCLK_CNTL2); + tmp &= ~(R300_SCLK_FORCE_TCL | + R300_SCLK_FORCE_GA | + R300_SCLK_FORCE_CBA); + tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | + R300_SCLK_GA_MAX_DYN_STOP_LAT | + R300_SCLK_CBA_MAX_DYN_STOP_LAT); + OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); + + tmp = INPLL(pScrn, RADEON_SCLK_CNTL); + tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | + RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | + RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | + R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | + RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | + R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | + R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | + R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); + tmp |= RADEON_DYN_STOP_LAT_MASK; + OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); + tmp &= ~RADEON_SCLK_MORE_FORCEON; + tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; + OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); + tmp |= (RADEON_PIXCLK_ALWAYS_ONb | + RADEON_PIXCLK_DAC_ALWAYS_ONb); + OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); + tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | + RADEON_PIX2CLK_DAC_ALWAYS_ONb | + RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | + R300_DVOCLK_ALWAYS_ONb | + RADEON_PIXCLK_BLEND_ALWAYS_ONb | + RADEON_PIXCLK_GV_ALWAYS_ONb | + R300_PIXCLK_DVO_ALWAYS_ONb | + RADEON_PIXCLK_LVDS_ALWAYS_ONb | + RADEON_PIXCLK_TMDS_ALWAYS_ONb | + R300_PIXCLK_TRANS_ALWAYS_ONb | + R300_PIXCLK_TVO_ALWAYS_ONb | + R300_P2G2CLK_ALWAYS_ONb | + R300_P2G2CLK_ALWAYS_ONb); + OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_MCLK_MISC); + tmp |= (RADEON_MC_MCLK_DYN_ENABLE | + RADEON_IO_MCLK_DYN_ENABLE); + OUTPLL(pScrn, RADEON_MCLK_MISC, tmp); + + tmp = INPLL(pScrn, RADEON_MCLK_CNTL); + tmp |= (RADEON_FORCEON_MCLKA | + RADEON_FORCEON_MCLKB); + + tmp &= ~(RADEON_FORCEON_YCLKA | + RADEON_FORCEON_YCLKB | + RADEON_FORCEON_MC); + + /* Some releases of vbios have set DISABLE_MC_MCLKA + and DISABLE_MC_MCLKB bits in the vbios table. Setting these + bits will cause H/W hang when reading video memory with dynamic clocking + enabled. */ + if ((tmp & R300_DISABLE_MC_MCLKA) && + (tmp & R300_DISABLE_MC_MCLKB)) { + /* If both bits are set, then check the active channels */ + tmp = INPLL(pScrn, RADEON_MCLK_CNTL); + if (info->RamWidth == 64) { + if (INREG(RADEON_MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY) + tmp &= ~R300_DISABLE_MC_MCLKB; + else + tmp &= ~R300_DISABLE_MC_MCLKA; + } else { + tmp &= ~(R300_DISABLE_MC_MCLKA | + R300_DISABLE_MC_MCLKB); + } + } + + OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); + } else { + tmp = INPLL(pScrn, RADEON_SCLK_CNTL); + tmp &= ~(R300_SCLK_FORCE_VAP); + tmp |= RADEON_SCLK_FORCE_CP; + OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); + usleep(15000); + + tmp = INPLL(pScrn, R300_SCLK_CNTL2); + tmp &= ~(R300_SCLK_FORCE_TCL | + R300_SCLK_FORCE_GA | + R300_SCLK_FORCE_CBA); + OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); + } + } else { + tmp = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL); + + tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | + RADEON_DISP_DYN_STOP_LAT_MASK | + RADEON_DYN_STOP_MODE_MASK); + + tmp |= (RADEON_ENGIN_DYNCLK_MODE | + (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); + OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL, tmp); + usleep(15000); + + tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL); + tmp |= RADEON_SCLK_DYN_START_CNTL; + OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp); + usleep(15000); + + /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 + to lockup randomly, leave them as set by BIOS. + */ + tmp = INPLL(pScrn, RADEON_SCLK_CNTL); + /*tmp &= RADEON_SCLK_SRC_SEL_MASK;*/ + tmp &= ~RADEON_SCLK_FORCEON_MASK; + + /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/ + if (((info->ChipFamily == CHIP_FAMILY_RV250) && + ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < + RADEON_CFG_ATI_REV_A13)) || + ((info->ChipFamily == CHIP_FAMILY_RV100) && + ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <= + RADEON_CFG_ATI_REV_A13))){ + tmp |= RADEON_SCLK_FORCE_CP; + tmp |= RADEON_SCLK_FORCE_VIP; + } + + OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); + + if ((info->ChipFamily == CHIP_FAMILY_RV200) || + (info->ChipFamily == CHIP_FAMILY_RV250) || + (info->ChipFamily == CHIP_FAMILY_RV280)) { + tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); + tmp &= ~RADEON_SCLK_MORE_FORCEON; + + /* RV200::A11 A12 RV250::A11 A12 */ + if (((info->ChipFamily == CHIP_FAMILY_RV200) || + (info->ChipFamily == CHIP_FAMILY_RV250)) && + ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < + RADEON_CFG_ATI_REV_A13)) { + tmp |= RADEON_SCLK_MORE_FORCEON; + } + OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); + usleep(15000); + } + + /* RV200::A11 A12, RV250::A11 A12 */ + if (((info->ChipFamily == CHIP_FAMILY_RV200) || + (info->ChipFamily == CHIP_FAMILY_RV250)) && + ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < + RADEON_CFG_ATI_REV_A13)) { + tmp = INPLL(pScrn, RADEON_PLL_PWRMGT_CNTL); + tmp |= RADEON_TCL_BYPASS_DISABLE; + OUTPLL(pScrn, RADEON_PLL_PWRMGT_CNTL, tmp); + } + usleep(15000); + + /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK)*/ + tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); + tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | + RADEON_PIX2CLK_DAC_ALWAYS_ONb | + RADEON_PIXCLK_BLEND_ALWAYS_ONb | + RADEON_PIXCLK_GV_ALWAYS_ONb | + RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | + RADEON_PIXCLK_LVDS_ALWAYS_ONb | + RADEON_PIXCLK_TMDS_ALWAYS_ONb); + + OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); + usleep(15000); + + tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); + tmp |= (RADEON_PIXCLK_ALWAYS_ONb | + RADEON_PIXCLK_DAC_ALWAYS_ONb); + + OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); + usleep(15000); + } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Clock Scaling Enabled\n"); + break; + default: + break; + } +} Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_macros.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_macros.h:1.4 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_macros.h:1.5 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_macros.h:1.4 Mon Mar 29 07:15:42 2004 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_macros.h Wed Apr 2 14:02:31 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_macros.h,v 1.4 2004/03/29 15:15:42 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_macros.h,v 1.5 2008/04/02 21:02:31 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -55,6 +55,14 @@ #endif #include "compiler.h" +#define RADEON_BIOS8(v) (info->VBIOS[v]) +#define RADEON_BIOS16(v) (info->VBIOS[v] | \ + (info->VBIOS[(v) + 1] << 8)) +#define RADEON_BIOS32(v) (info->VBIOS[v] | \ + (info->VBIOS[(v) + 1] << 8) | \ + (info->VBIOS[(v) + 2] << 16) | \ + (info->VBIOS[(v) + 3] << 24)) + /* Memory mapped register access macros */ #define INREG8(addr) MMIO_IN8(RADEONMMIO, addr) #define INREG16(addr) MMIO_IN16(RADEONMMIO, addr) @@ -70,25 +78,20 @@ do { \ CARD32 tmp = INREG(addr); \ tmp &= (mask); \ - tmp |= (val); \ + tmp |= ((val) & ~(mask)); \ OUTREG(addr, tmp); \ } while (0) #define INPLL(pScrn, addr) RADEONINPLL(pScrn, addr) -#define OUTPLL(addr, val) \ -do { \ - OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | \ - RADEON_PLL_WR_EN)); \ - OUTREG(RADEON_CLOCK_CNTL_DATA, val); \ -} while (0) +#define OUTPLL(pScrn, addr, val) RADEONOUTPLL(pScrn, addr, val) #define OUTPLLP(pScrn, addr, val, mask) \ do { \ CARD32 tmp_ = INPLL(pScrn, addr); \ tmp_ &= (mask); \ - tmp_ |= (val); \ - OUTPLL(addr, tmp_); \ + tmp_ |= ((val) & ~(mask)); \ + OUTPLL(pScrn, addr, tmp_); \ } while (0) #define OUTPAL_START(idx) \ Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_mergedfb.c diff -u /dev/null xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_mergedfb.c:1.2 --- /dev/null Mon Dec 15 09:54:56 2008 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_mergedfb.c Sun Apr 6 12:17:41 2008 @@ -0,0 +1,2089 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_mergedfb.c,v 1.2 2008/04/06 19:17:41 tsi Exp $ */ +/* + * Copyright 2003 Alex Deucher. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ALEX DEUCHER, OR ANY OTHER + * CONTRIBUTORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Alex Deucher <agd5f@yahoo.com> + * Based, in large part, on the sis driver by Thomas Winischhofer. + */ + +#include "xf86.h" +#include "xf86Priv.h" +#include "xf86Resources.h" +#include "xf86_OSproc.h" +#include "extnsionst.h" /* required */ +#include <X11/extensions/panoramiXproto.h> /* required */ +#include "dixstruct.h" +#include "vbe.h" + + +#include "radeon.h" +#include "radeon_reg.h" +#include "radeon_macros.h" +#include "radeon_mergedfb.h" + +/* pseudo xinerama support */ +#if 0 +static unsigned char RADEONXineramaReqCode = 0; +#endif +int RADEONXineramaPixWidth = 0; +int RADEONXineramaPixHeight = 0; +int RADEONXineramaNumScreens = 0; +RADEONXineramaData *RADEONXineramadataPtr = NULL; +static unsigned long RADEONXineramaGeneration; +Bool RADEONnoPanoramiXExtension = TRUE; + +int RADEONProcXineramaQueryVersion(ClientPtr client); +int RADEONProcXineramaGetState(ClientPtr client); +int RADEONProcXineramaGetScreenCount(ClientPtr client); +int RADEONProcXineramaGetScreenSize(ClientPtr client); +int RADEONProcXineramaIsActive(ClientPtr client); +int RADEONProcXineramaQueryScreens(ClientPtr client); +int RADEONSProcXineramaDispatch(ClientPtr client); + +static void +RADEONChooseCursorCRTC(ScrnInfoPtr pScrn1, int x, int y); + +/* mergedfb functions */ +/* Helper function for CRT2 monitor vrefresh/hsync options + * (Taken from mga, sis drivers) + */ +int +RADEONStrToRanges(range *r, char *s, int max) +{ + float num = 0.0; + int rangenum = 0; + Bool gotdash = FALSE; + Bool nextdash = FALSE; + char* strnum = NULL; + do { + switch(*s) { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case '.': + if(strnum == NULL) { + strnum = s; + gotdash = nextdash; + nextdash = FALSE; + } + break; + case '-': + case ' ': + case 0: + if(strnum == NULL) break; + sscanf(strnum, "%f", &num); + strnum = NULL; + if(gotdash) + r[rangenum - 1].hi = num; + else { + r[rangenum].lo = num; + r[rangenum].hi = num; + rangenum++; + } + if(*s == '-') nextdash = (rangenum != 0); + else if(rangenum >= max) return rangenum; + break; + default : + return 0; + } + } while(*(s++) != 0); + + return rangenum; +} + +/* Copy and link two modes (i, j) for merged-fb mode + * (Taken from mga, sis drivers) + * Copys mode i, merges j to copy of i, links the result to dest, and returns it. + * Links i and j in Private record. + * If dest is NULL, return value is copy of i linked to itself. + * For mergedfb auto-config, we only check the dimension + * against virtualX/Y, if they were user-provided. + */ +static DisplayModePtr +RADEONCopyModeNLink(ScrnInfoPtr pScrn, DisplayModePtr dest, + DisplayModePtr i, DisplayModePtr j, + RADEONScrn2Rel srel) +{ + DisplayModePtr mode; + int dx = 0,dy = 0; + RADEONInfoPtr info = RADEONPTR(pScrn); + + if(!((mode = xalloc(sizeof(DisplayModeRec))))) return dest; + memcpy(mode, i, sizeof(DisplayModeRec)); + if(!((mode->Private = xalloc(sizeof(RADEONMergedDisplayModeRec))))) { + xfree(mode); + return dest; + } + ((RADEONMergedDisplayModePtr)(pointer)mode->Private)->CRT1 = i; + ((RADEONMergedDisplayModePtr)(pointer)mode->Private)->CRT2 = j; + ((RADEONMergedDisplayModePtr)(pointer)mode->Private)->CRT2Position = srel; + mode->PrivSize = 0; + + switch(srel) { + case radeonLeftOf: + case radeonRightOf: + if(!(pScrn->display->virtualX)) { + dx = i->HDisplay + j->HDisplay; + } else { + dx = min(pScrn->virtualX, i->HDisplay + j->HDisplay); + } + dx -= mode->HDisplay; + if(!(pScrn->display->virtualY)) { + dy = max(i->VDisplay, j->VDisplay); + } else { + dy = min(pScrn->virtualY, max(i->VDisplay, j->VDisplay)); + } + dy -= mode->VDisplay; + break; + case radeonAbove: + case radeonBelow: + if(!(pScrn->display->virtualY)) { + dy = i->VDisplay + j->VDisplay; + } else { + dy = min(pScrn->virtualY, i->VDisplay + j->VDisplay); + } + dy -= mode->VDisplay; + if(!(pScrn->display->virtualX)) { + dx = max(i->HDisplay, j->HDisplay); + } else { + dx = min(pScrn->virtualX, max(i->HDisplay, j->HDisplay)); + } + dx -= mode->HDisplay; + break; + case radeonClone: + if(!(pScrn->display->virtualX)) { + dx = max(i->HDisplay, j->HDisplay); + } else { + dx = min(pScrn->virtualX, max(i->HDisplay, j->HDisplay)); + } + dx -= mode->HDisplay; + if(!(pScrn->display->virtualY)) { + dy = max(i->VDisplay, j->VDisplay); + } else { + dy = min(pScrn->virtualY, max(i->VDisplay, j->VDisplay)); + } + dy -= mode->VDisplay; + break; + } + mode->HDisplay += dx; + mode->HSyncStart += dx; + mode->HSyncEnd += dx; + mode->HTotal += dx; + mode->VDisplay += dy; + mode->VSyncStart += dy; + mode->VSyncEnd += dy; + mode->VTotal += dy; + + /* This is needed for not generating negative refesh rates in xrandr with the + faked DotClock below + */ + if (!(mode->VRefresh)) + mode->VRefresh = mode->Clock * 1000.0 / mode->HTotal / mode->VTotal; + + /* Provide a sophisticated fake DotClock in order to trick the vidmode + * extension to allow selecting among a number of modes whose merged result + * looks identical but consists of different modes for CRT1 and CRT2 + */ + mode->Clock = (((i->Clock >> 3) + i->HTotal) << 16) | ((j->Clock >> 2) + j->HTotal); + mode->Clock ^= ((i->VTotal << 19) | (j->VTotal << 3)); + + if( ((mode->HDisplay * ((pScrn->bitsPerPixel + 7) / 8) * mode->VDisplay) > + (pScrn->videoRam * 1024)) || + (mode->HDisplay > 8191) || + (mode->VDisplay > 8191) ) { + + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Skipped \"%s\" (%dx%d), not enough video RAM or beyond hardware specs\n", + mode->name, mode->HDisplay, mode->VDisplay); + xfree(mode->Private); + xfree(mode); + + return dest; + } + + if(srel != radeonClone) { + info->AtLeastOneNonClone = TRUE; + } + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Merged \"%s\" (%dx%d) and \"%s\" (%dx%d) to %dx%d%s\n", + i->name, i->HDisplay, i->VDisplay, j->name, j->HDisplay, j->VDisplay, + mode->HDisplay, mode->VDisplay, (srel == radeonClone) ? " (Clone)" : ""); + + mode->next = mode; + mode->prev = mode; + + if(dest) { + mode->next = dest->next; /* Insert node after "dest" */ + dest->next->prev = mode; + mode->prev = dest; + dest->next = mode; + } + + return mode; +} + +/* Helper function to find a mode from a given name + * (Taken from mga, sis drivers) + */ +static DisplayModePtr +RADEONGetModeFromName(char* str, DisplayModePtr i) +{ + DisplayModePtr c = i; + if(!i) return NULL; + do { + if(strcmp(str, c->name) == 0) return c; + c = c->next; + } while(c != i); + return NULL; +} + +static DisplayModePtr +RADEONFindWidestTallestMode(DisplayModePtr i, Bool tallest) +{ + DisplayModePtr c = i, d = NULL; + int max = 0; + if(!i) return NULL; + do { + if(tallest) { + if(c->VDisplay > max) { + max = c->VDisplay; + d = c; + } + } else { + if(c->HDisplay > max) { + max = c->HDisplay; + d = c; + } + } + c = c->next; + } while(c != i); + return d; +} + +static void +RADEONFindWidestTallestCommonMode(DisplayModePtr i, DisplayModePtr j, Bool tallest, + DisplayModePtr *a, DisplayModePtr *b) +{ + DisplayModePtr c = i, d; + int max = 0; + Bool foundone; + + (*a) = (*b) = NULL; + + if(!i || !j) return; + + do { + d = j; + foundone = FALSE; + do { + if( (c->HDisplay == d->HDisplay) && + (c->VDisplay == d->VDisplay) ) { + foundone = TRUE; + break; + } + d = d->next; + } while(d != j); + if(foundone) { + if(tallest) { + if(c->VDisplay > max) { + max = c->VDisplay; + (*a) = c; + (*b) = d; + } + } else { + if(c->HDisplay > max) { + max = c->HDisplay; + (*a) = c; + (*b) = d; + } + } + } + c = c->next; + } while(c != i); +} + +static DisplayModePtr +RADEONGenerateModeListFromLargestModes(ScrnInfoPtr pScrn, + DisplayModePtr i, DisplayModePtr j, + RADEONScrn2Rel srel) +{ + + RADEONInfoPtr info = RADEONPTR(pScrn); + DisplayModePtr mode1 = NULL; + DisplayModePtr mode2 = NULL; + DisplayModePtr mode3 = NULL; + DisplayModePtr mode4 = NULL; + DisplayModePtr result = NULL; + + info->AtLeastOneNonClone = FALSE; + + /* Now build a default list of MetaModes. + * - Non-clone: If the user enabled NonRectangular, we use the + * largest mode for each CRT1 and CRT2. If not, we use the largest + * common mode for CRT1 and CRT2 (if available). Additionally, and + * regardless if the above, we produce a clone mode consisting of + * the largest common mode (if available) in order to use DGA. + * - Clone: If the (global) CRT2Position is Clone, we use the + * largest common mode if available, otherwise the first two modes + * in each list. + */ + + switch(srel) { + case radeonLeftOf: + case radeonRightOf: + mode1 = RADEONFindWidestTallestMode(i, FALSE); + mode2 = RADEONFindWidestTallestMode(j, FALSE); + RADEONFindWidestTallestCommonMode(i, j, FALSE, &mode3, &mode4); + break; + case radeonAbove: + case radeonBelow: + mode1 = RADEONFindWidestTallestMode(i, TRUE); + mode2 = RADEONFindWidestTallestMode(j, TRUE); + RADEONFindWidestTallestCommonMode(i, j, TRUE, &mode3, &mode4); + break; + case radeonClone: + RADEONFindWidestTallestCommonMode(i, j, FALSE, &mode3, &mode4); + if(mode3 && mode4) { + mode1 = mode3; + mode2 = mode4; + } else { + mode1 = i; + mode2 = j; + } + } + + if(srel != radeonClone) { + if(mode3 && mode4 && !info->NonRect) { + mode1 = mode3; + mode2 = mode2; + } + } + + if(mode1 && mode2) { + result = RADEONCopyModeNLink(pScrn, result, mode1, mode2, srel); + } + + if(srel != radeonClone) { + if(mode3 && mode4) { + result = RADEONCopyModeNLink(pScrn, result, mode3, mode4, radeonClone); + } + } + return result; +} + +/* Generate the merged-fb mode modelist + * (Taken from mga, sis drivers) + */ +static DisplayModePtr +RADEONGenerateModeListFromMetaModes(ScrnInfoPtr pScrn, char* str, + DisplayModePtr i, DisplayModePtr j, + RADEONScrn2Rel srel) +{ + char* modestr = str; + char modename[256]; + Bool gotdash = FALSE; + char gotsep = 0; + RADEONScrn2Rel sr; + DisplayModePtr mode1 = NULL; + DisplayModePtr mode2 = NULL; + DisplayModePtr result = NULL; + int myslen; + RADEONInfoPtr info = RADEONPTR(pScrn); + + info->AtLeastOneNonClone = FALSE; + + do { + switch(*str) { + case 0: + case '-': + case '+': + case ' ': + case ',': + case ';': + if(modestr != str) { + + myslen = str - modestr; + if(myslen > 255) myslen = 255; + strncpy(modename, modestr, myslen); + modename[myslen] = 0; + + if(gotdash) { + if(mode1 == NULL) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Error parsing MetaModes parameter\n"); + return NULL; + } + mode2 = RADEONGetModeFromName(modename, j); + if(!mode2) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Mode \"%s\" is not a supported mode for CRT2\n", modename); + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "\t(Skipping metamode \"%s%c%s\")\n", mode1->name, gotsep, modename); + mode1 = NULL; + gotsep = 0; + } + } else { + mode1 = RADEONGetModeFromName(modename, i); + if(!mode1) { + char* tmps = str; + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Mode \"%s\" is not a supported mode for CRT1\n", modename); + while(*tmps == ' ' || *tmps == ';') tmps++; + /* skip the next mode */ + if(*tmps == '-' || *tmps == '+' || *tmps == ',') { + tmps++; + /* skip spaces */ + while(*tmps == ' ' || *tmps == ';') tmps++; + /* skip modename */ + while(*tmps && *tmps != ' ' && *tmps != ';' && *tmps != '-' && *tmps != '+' && *tmps != ',') tmps++; + myslen = tmps - modestr; + if(myslen > 255) myslen = 255; + strncpy(modename,modestr,myslen); + modename[myslen] = 0; + str = tmps-1; + } + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "\t(Skipping metamode \"%s\")\n", modename); + mode1 = NULL; + gotsep = 0; + } + } + gotdash = FALSE; + } + modestr = str + 1; + gotdash |= (*str == '-' || *str == '+' || *str == ','); + if (*str == '-' || *str == '+' || *str == ',') + gotsep = *str; + + if(*str != 0) break; + /* Fall through otherwise */ + + default: + if(!gotdash && mode1) { + sr = srel; + if(gotsep == '+') sr = radeonClone; + if(!mode2) { + mode2 = RADEONGetModeFromName(mode1->name, j); + sr = radeonClone; + } + if(!mode2) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Mode \"%s\" is not a supported mode for CRT2\n", mode1->name); + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "\t(Skipping metamode \"%s\")\n", modename); + mode1 = NULL; + } else { + result = RADEONCopyModeNLink(pScrn, result, mode1, mode2, sr); + mode1 = NULL; + mode2 = NULL; + } + gotsep = 0; + } + break; + + } + + } while(*(str++) != 0); + + return result; +} + +DisplayModePtr +RADEONGenerateModeList(ScrnInfoPtr pScrn, char* str, + DisplayModePtr i, DisplayModePtr j, + RADEONScrn2Rel srel) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + + if(str != NULL) { + return(RADEONGenerateModeListFromMetaModes(pScrn, str, i, j, srel)); + } else { + if (srel == radeonClone ) { + DisplayModePtr p, q, result = NULL; + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Clone mode, list all common modes\n"); + for (p = i; p->next != i; p = p->next) + for (q = j; q->next != j; q = q->next) + if ((p->HDisplay == q->HDisplay) && + (p->VDisplay == q->VDisplay)) + result = RADEONCopyModeNLink(pScrn, result, p, q, srel); + return result; + } else { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "No MetaModes given, linking %s modes by default\n", + (info->NonRect ? + (((srel == radeonLeftOf) || (srel == radeonRightOf)) ? "widest" : "tallest") + : + (((srel == radeonLeftOf) || (srel == radeonRightOf)) ? "widest common" : "tallest common")) ); + return(RADEONGenerateModeListFromLargestModes(pScrn, i, j, srel)); + } + } +} + +void +RADEONRecalcDefaultVirtualSize(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + DisplayModePtr mode, bmode; + int maxh, maxv; + static const char *str = "MergedFB: Virtual %s %d\n"; + static const char *errstr = "Virtual %s to small for given CRT2Position offset\n"; + + mode = bmode = pScrn->modes; + maxh = maxv = 0; + do { + if(mode->HDisplay > maxh) maxh = mode->HDisplay; + if(mode->VDisplay > maxv) maxv = mode->VDisplay; + mode = mode->next; + } while(mode != bmode); + maxh += info->CRT1XOffs + info->CRT2XOffs; + maxv += info->CRT1YOffs + info->CRT2YOffs; + + if(!(pScrn->display->virtualX)) { + if(maxh > 8191) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Virtual width with CRT2Position offset beyond hardware specs\n"); + info->CRT1XOffs = info->CRT2XOffs = 0; + maxh -= (info->CRT1XOffs + info->CRT2XOffs); + } + pScrn->virtualX = maxh; + pScrn->displayWidth = maxh; + xf86DrvMsg(pScrn->scrnIndex, X_PROBED, str, "width", maxh); + } else { + if(maxh < pScrn->display->virtualX) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, errstr, "width"); + info->CRT1XOffs = info->CRT2XOffs = 0; + } + } + + if(!(pScrn->display->virtualY)) { + pScrn->virtualY = maxv; + xf86DrvMsg(pScrn->scrnIndex, X_PROBED, str, "height", maxv); + } else { + if(maxv < pScrn->display->virtualY) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, errstr, "height"); + info->CRT1YOffs = info->CRT2YOffs = 0; + } + } +} + +/* Pseudo-Xinerama extension for MergedFB mode */ +void +RADEONUpdateXineramaScreenInfo(ScrnInfoPtr pScrn1) +{ + RADEONInfoPtr info = RADEONPTR(pScrn1); + int crt1scrnnum = 0, crt2scrnnum = 1; + /* Upper case to avoid shadow warnings */ + int X1=0, X2=0, Y1=0, Y2=0, H1=0, H2=0, W1=0, W2=0; + int realvirtX, realvirtY; + DisplayModePtr currentMode, firstMode; + Bool infochanged = FALSE; + Bool usenonrect = info->NonRect; + const char *rectxine = "\t... setting up rectangular Xinerama layout\n"; + + info->MBXNR1XMAX = info->MBXNR1YMAX = info->MBXNR2XMAX = info->MBXNR2YMAX = 65536; + info->HaveNonRect = info->HaveOffsRegions = FALSE; + + if(!info->MergedFB) return; + + if(RADEONnoPanoramiXExtension) return; + + if(!RADEONXineramadataPtr) return; + + if(info->CRT2IsScrn0) { + crt1scrnnum = 1; + crt2scrnnum = 0; + } + + /* Attention: Usage of RandR may lead into virtual X and Y values + * actually smaller than our MetaModes! To avoid this, we calculate + * the maxCRT fields here (and not somewhere else, like in CopyNLink) + */ + + /* "Real" virtual: Virtual without the Offset */ + realvirtX = pScrn1->virtualX - info->CRT1XOffs - info->CRT2XOffs; + realvirtY = pScrn1->virtualY - info->CRT1YOffs - info->CRT2YOffs; + + if((info->RADEONXineramaVX != pScrn1->virtualX) || (info->RADEONXineramaVY != pScrn1->virtualY)) { + + if(!(pScrn1->modes)) { + xf86DrvMsg(pScrn1->scrnIndex, X_ERROR, + "Internal error: RADEONUpdateXineramaScreenInfo(): pScrn->modes is NULL\n"); + return; + } + + info->maxCRT1_X1 = info->maxCRT1_X2 = 0; + info->maxCRT1_Y1 = info->maxCRT1_Y2 = 0; + info->maxCRT2_X1 = info->maxCRT2_X2 = 0; + info->maxCRT2_Y1 = info->maxCRT2_Y2 = 0; + info->maxClone_X1 = info->maxClone_X2 = 0; + info->maxClone_Y1 = info->maxClone_Y2 = 0; + + currentMode = firstMode = pScrn1->modes; + + do { + + DisplayModePtr p = currentMode->next; + DisplayModePtr i = ((RADEONMergedDisplayModePtr)(pointer)currentMode->Private)->CRT1; + DisplayModePtr j = ((RADEONMergedDisplayModePtr)(pointer)currentMode->Private)->CRT2; + RADEONScrn2Rel srel = ((RADEONMergedDisplayModePtr)(pointer)currentMode->Private)->CRT2Position; + + if((currentMode->HDisplay <= realvirtX) && (currentMode->VDisplay <= realvirtY) && + (i->HDisplay <= realvirtX) && (j->HDisplay <= realvirtX) && + (i->VDisplay <= realvirtY) && (j->VDisplay <= realvirtY)) { + + if(srel != radeonClone) { + if(info->maxCRT1_X1 == i->HDisplay) { + if(info->maxCRT1_X2 < j->HDisplay) { + info->maxCRT1_X2 = j->HDisplay; /* Widest CRT2 mode displayed with widest CRT1 mode */ + } + } else if(info->maxCRT1_X1 < i->HDisplay) { + info->maxCRT1_X1 = i->HDisplay; /* Widest CRT1 mode */ + info->maxCRT1_X2 = j->HDisplay; + } + if(info->maxCRT2_X2 == j->HDisplay) { + if(info->maxCRT2_X1 < i->HDisplay) { + info->maxCRT2_X1 = i->HDisplay; /* Widest CRT1 mode displayed with widest CRT2 mode */ + } + } else if(info->maxCRT2_X2 < j->HDisplay) { + info->maxCRT2_X2 = j->HDisplay; /* Widest CRT2 mode */ + info->maxCRT2_X1 = i->HDisplay; + } + if(info->maxCRT1_Y1 == i->VDisplay) { /* Same as above, but tallest instead of widest */ + if(info->maxCRT1_Y2 < j->VDisplay) { + info->maxCRT1_Y2 = j->VDisplay; + } + } else if(info->maxCRT1_Y1 < i->VDisplay) { + info->maxCRT1_Y1 = i->VDisplay; + info->maxCRT1_Y2 = j->VDisplay; + } + if(info->maxCRT2_Y2 == j->VDisplay) { + if(info->maxCRT2_Y1 < i->VDisplay) { + info->maxCRT2_Y1 = i->VDisplay; + } + } else if(info->maxCRT2_Y2 < j->VDisplay) { + info->maxCRT2_Y2 = j->VDisplay; + info->maxCRT2_Y1 = i->VDisplay; + } + } else { + if(info->maxClone_X1 < i->HDisplay) { + info->maxClone_X1 = i->HDisplay; + } + if(info->maxClone_X2 < j->HDisplay) { + info->maxClone_X2 = j->HDisplay; + } + if(info->maxClone_Y1 < i->VDisplay) { + info->maxClone_Y1 = i->VDisplay; + } + if(info->maxClone_Y2 < j->VDisplay) { + info->maxClone_Y2 = j->VDisplay; + } + } + } + currentMode = p; + + } while((currentMode) && (currentMode != firstMode)); + + info->RADEONXineramaVX = pScrn1->virtualX; + info->RADEONXineramaVY = pScrn1->virtualY; + infochanged = TRUE; + + } + + if((usenonrect) && (info->CRT2Position != radeonClone) && info->maxCRT1_X1) { + switch(info->CRT2Position) { + case radeonLeftOf: + case radeonRightOf: + if((info->maxCRT1_Y1 != realvirtY) && (info->maxCRT2_Y2 != realvirtY)) { + usenonrect = FALSE; + } + break; + case radeonAbove: + case radeonBelow: + if((info->maxCRT1_X1 != realvirtX) && (info->maxCRT2_X2 != realvirtX)) { + usenonrect = FALSE; + } + break; + case radeonClone: + break; + } + + if(infochanged && !usenonrect) { + xf86DrvMsg(pScrn1->scrnIndex, X_INFO, + "Virtual screen size does not match maximum display modes...\n"); + xf86DrvMsg(pScrn1->scrnIndex, X_INFO, rectxine); + + } + } else if(infochanged && usenonrect) { + usenonrect = FALSE; + xf86DrvMsg(pScrn1->scrnIndex, X_INFO, + "Only clone modes available for this virtual screen size...\n"); + xf86DrvMsg(pScrn1->scrnIndex, X_INFO, rectxine); + } + + if(info->maxCRT1_X1) { /* Means we have at least one non-clone mode */ + switch(info->CRT2Position) { + case radeonLeftOf: + X1 = min(info->maxCRT1_X2, pScrn1->virtualX - info->maxCRT1_X1); + if(X1 < 0) X1 = 0; + Y1 = info->CRT1YOffs; + W1 = pScrn1->virtualX - X1; + H1 = realvirtY; + if((usenonrect) && (info->maxCRT1_Y1 != realvirtY)) { + H1 = info->MBXNR1YMAX = info->maxCRT1_Y1; + info->NonRectDead.x0 = X1; + info->NonRectDead.x1 = X1 + W1 - 1; + info->NonRectDead.y0 = Y1 + H1; + info->NonRectDead.y1 = pScrn1->virtualY - 1; + info->HaveNonRect = TRUE; + } + X2 = 0; + Y2 = info->CRT2YOffs; + W2 = max(info->maxCRT2_X2, pScrn1->virtualX - info->maxCRT2_X1); + if(W2 > pScrn1->virtualX) W2 = pScrn1->virtualX; + H2 = realvirtY; + if((usenonrect) && (info->maxCRT2_Y2 != realvirtY)) { + H2 = info->MBXNR2YMAX = info->maxCRT2_Y2; + info->NonRectDead.x0 = X2; + info->NonRectDead.x1 = X2 + W2 - 1; + info->NonRectDead.y0 = Y2 + H2; + info->NonRectDead.y1 = pScrn1->virtualY - 1; + info->HaveNonRect = TRUE; + } + break; + case radeonRightOf: + X1 = 0; + Y1 = info->CRT1YOffs; + W1 = max(info->maxCRT1_X1, pScrn1->virtualX - info->maxCRT1_X2); + if(W1 > pScrn1->virtualX) W1 = pScrn1->virtualX; + H1 = realvirtY; + if((usenonrect) && (info->maxCRT1_Y1 != realvirtY)) { + H1 = info->MBXNR1YMAX = info->maxCRT1_Y1; + info->NonRectDead.x0 = X1; + info->NonRectDead.x1 = X1 + W1 - 1; + info->NonRectDead.y0 = Y1 + H1; + info->NonRectDead.y1 = pScrn1->virtualY - 1; + info->HaveNonRect = TRUE; + } + X2 = min(info->maxCRT2_X1, pScrn1->virtualX - info->maxCRT2_X2); + if(X2 < 0) X2 = 0; + Y2 = info->CRT2YOffs; + W2 = pScrn1->virtualX - X2; + H2 = realvirtY; + if((usenonrect) && (info->maxCRT2_Y2 != realvirtY)) { + H2 = info->MBXNR2YMAX = info->maxCRT2_Y2; + info->NonRectDead.x0 = X2; + info->NonRectDead.x1 = X2 + W2 - 1; + info->NonRectDead.y0 = Y2 + H2; + info->NonRectDead.y1 = pScrn1->virtualY - 1; + info->HaveNonRect = TRUE; + } + break; + case radeonAbove: + X1 = info->CRT1XOffs; + Y1 = min(info->maxCRT1_Y2, pScrn1->virtualY - info->maxCRT1_Y1); + if(Y1 < 0) Y1 = 0; + W1 = realvirtX; + H1 = pScrn1->virtualY - Y1; + if((usenonrect) && (info->maxCRT1_X1 != realvirtX)) { + W1 = info->MBXNR1XMAX = info->maxCRT1_X1; + info->NonRectDead.x0 = X1 + W1; + info->NonRectDead.x1 = pScrn1->virtualX - 1; + info->NonRectDead.y0 = Y1; + info->NonRectDead.y1 = Y1 + H1 - 1; + info->HaveNonRect = TRUE; + } + X2 = info->CRT2XOffs; + Y2 = 0; + W2 = realvirtX; + H2 = max(info->maxCRT2_Y2, pScrn1->virtualY - info->maxCRT2_Y1); + if(H2 > pScrn1->virtualY) H2 = pScrn1->virtualY; + if((usenonrect) && (info->maxCRT2_X2 != realvirtX)) { + W2 = info->MBXNR2XMAX = info->maxCRT2_X2; + info->NonRectDead.x0 = X2 + W2; + info->NonRectDead.x1 = pScrn1->virtualX - 1; + info->NonRectDead.y0 = Y2; + info->NonRectDead.y1 = Y2 + H2 - 1; + info->HaveNonRect = TRUE; + } + break; + case radeonBelow: + X1 = info->CRT1XOffs; + Y1 = 0; + W1 = realvirtX; + H1 = max(info->maxCRT1_Y1, pScrn1->virtualY - info->maxCRT1_Y2); + if(H1 > pScrn1->virtualY) H1 = pScrn1->virtualY; + if((usenonrect) && (info->maxCRT1_X1 != realvirtX)) { + W1 = info->MBXNR1XMAX = info->maxCRT1_X1; + info->NonRectDead.x0 = X1 + W1; + info->NonRectDead.x1 = pScrn1->virtualX - 1; + info->NonRectDead.y0 = Y1; + info->NonRectDead.y1 = Y1 + H1 - 1; + info->HaveNonRect = TRUE; + } + X2 = info->CRT2XOffs; + Y2 = min(info->maxCRT2_Y1, pScrn1->virtualY - info->maxCRT2_Y2); + if(Y2 < 0) Y2 = 0; + W2 = realvirtX; + H2 = pScrn1->virtualY - Y2; + if((usenonrect) && (info->maxCRT2_X2 != realvirtX)) { + W2 = info->MBXNR2XMAX = info->maxCRT2_X2; + info->NonRectDead.x0 = X2 + W2; + info->NonRectDead.x1 = pScrn1->virtualX - 1; + info->NonRectDead.y0 = Y2; + info->NonRectDead.y1 = Y2 + H2 - 1; + info->HaveNonRect = TRUE; + } + default: + break; + } + + switch(info->CRT2Position) { + case radeonLeftOf: + case radeonRightOf: + if(info->CRT1YOffs) { + info->OffDead1.x0 = X1; + info->OffDead1.x1 = X1 + W1 - 1; + info->OffDead1.y0 = 0; + info->OffDead1.y1 = Y1 - 1; + info->OffDead2.x0 = X2; + info->OffDead2.x1 = X2 + W2 - 1; + info->OffDead2.y0 = Y2 + H2; + info->OffDead2.y1 = pScrn1->virtualY - 1; + info->HaveOffsRegions = TRUE; + } else if(info->CRT2YOffs) { + info->OffDead1.x0 = X2; + info->OffDead1.x1 = X2 + W2 - 1; + info->OffDead1.y0 = 0; + info->OffDead1.y1 = Y2 - 1; + info->OffDead2.x0 = X1; + info->OffDead2.x1 = X1 + W1 - 1; + info->OffDead2.y0 = Y1 + H1; + info->OffDead2.y1 = pScrn1->virtualY - 1; + info->HaveOffsRegions = TRUE; + } + break; + case radeonAbove: + case radeonBelow: + if(info->CRT1XOffs) { + info->OffDead1.x0 = X2 + W2; + info->OffDead1.x1 = pScrn1->virtualX - 1; + info->OffDead1.y0 = Y2; + info->OffDead1.y1 = Y2 + H2 - 1; + info->OffDead2.x0 = 0; + info->OffDead2.x1 = X1 - 1; + info->OffDead2.y0 = Y1; + info->OffDead2.y1 = Y1 + H1 - 1; + info->HaveOffsRegions = TRUE; + } else if(info->CRT2XOffs) { + info->OffDead1.x0 = X1 + W1; + info->OffDead1.x1 = pScrn1->virtualX - 1; + info->OffDead1.y0 = Y1; + info->OffDead1.y1 = Y1 + H1 - 1; + info->OffDead2.x0 = 0; + info->OffDead2.x1 = X2 - 1; + info->OffDead2.y0 = Y2; + info->OffDead2.y1 = Y2 + H2 - 1; + info->HaveOffsRegions = TRUE; + } + default: + break; + } + + } else { /* Only clone-modes left */ + + X1 = X2 = 0; + Y1 = Y2 = 0; + W1 = W2 = max(info->maxClone_X1, info->maxClone_X2); + H1 = H2 = max(info->maxClone_Y1, info->maxClone_Y2); + + } + + RADEONXineramadataPtr[crt1scrnnum].x = X1; + RADEONXineramadataPtr[crt1scrnnum].y = Y1; + RADEONXineramadataPtr[crt1scrnnum].width = W1; + RADEONXineramadataPtr[crt1scrnnum].height = H1; + RADEONXineramadataPtr[crt2scrnnum].x = X2; + RADEONXineramadataPtr[crt2scrnnum].y = Y2; + RADEONXineramadataPtr[crt2scrnnum].width = W2; + RADEONXineramadataPtr[crt2scrnnum].height = H2; + + if(infochanged) { + xf86DrvMsg(pScrn1->scrnIndex, X_INFO, + "Pseudo-Xinerama: CRT1 (Screen %d) (%d,%d)-(%d,%d)\n", + crt1scrnnum, X1, Y1, W1+X1-1, H1+Y1-1); + xf86DrvMsg(pScrn1->scrnIndex, X_INFO, + "Pseudo-Xinerama: CRT2 (Screen %d) (%d,%d)-(%d,%d)\n", + crt2scrnnum, X2, Y2, W2+X2-1, H2+Y2-1); + if(info->HaveNonRect) { + xf86DrvMsg(pScrn1->scrnIndex, X_INFO, + "Pseudo-Xinerama: Inaccessible area (%d,%d)-(%d,%d)\n", + info->NonRectDead.x0, info->NonRectDead.y0, + info->NonRectDead.x1, info->NonRectDead.y1); + } + if(info->HaveOffsRegions) { + xf86DrvMsg(pScrn1->scrnIndex, X_INFO, + "Pseudo-Xinerama: Inaccessible offset area (%d,%d)-(%d,%d)\n", + info->OffDead1.x0, info->OffDead1.y0, + info->OffDead1.x1, info->OffDead1.y1); + xf86DrvMsg(pScrn1->scrnIndex, X_INFO, + "Pseudo-Xinerama: Inaccessible offset area (%d,%d)-(%d,%d)\n", + info->OffDead2.x0, info->OffDead2.y0, + info->OffDead2.x1, info->OffDead2.y1); + } + if(info->HaveNonRect || info->HaveOffsRegions) { + xf86DrvMsg(pScrn1->scrnIndex, X_INFO, + "Mouse restriction for inaccessible areas is %s\n", + info->MouseRestrictions ? "enabled" : "disabled"); + } + } +} +/* Proc */ + +int +RADEONProcXineramaQueryVersion(ClientPtr client) +{ + xPanoramiXQueryVersionReply rep; + register int n; + + REQUEST_SIZE_MATCH(xPanoramiXQueryVersionReq); + rep.type = X_Reply; + rep.length = 0; + rep.sequenceNumber = client->sequence; + rep.majorVersion = RADEON_XINERAMA_MAJOR_VERSION; + rep.minorVersion = RADEON_XINERAMA_MINOR_VERSION; + if(client->swapped) { + swaps(&rep.sequenceNumber, n); + swapl(&rep.length, n); + swaps(&rep.majorVersion, n); + swaps(&rep.minorVersion, n); + } + WriteToClient(client, sizeof(xPanoramiXQueryVersionReply), (char *)&rep); + return (client->noClientException); +} + +int +RADEONProcXineramaGetState(ClientPtr client) +{ + REQUEST(xPanoramiXGetStateReq); + WindowPtr pWin; + xPanoramiXGetStateReply rep; + register int n; + + REQUEST_SIZE_MATCH(xPanoramiXGetStateReq); + pWin = LookupWindow(stuff->window, client); + if(!pWin) return BadWindow; + + rep.type = X_Reply; + rep.length = 0; + rep.sequenceNumber = client->sequence; + rep.state = !RADEONnoPanoramiXExtension; + if(client->swapped) { + swaps (&rep.sequenceNumber, n); + swapl (&rep.length, n); + swaps (&rep.state, n); + } + WriteToClient(client, sizeof(xPanoramiXGetStateReply), (char *)&rep); + return client->noClientException; +} + +int +RADEONProcXineramaGetScreenCount(ClientPtr client) +{ + REQUEST(xPanoramiXGetScreenCountReq); + WindowPtr pWin; + xPanoramiXGetScreenCountReply rep; + register int n; + + REQUEST_SIZE_MATCH(xPanoramiXGetScreenCountReq); + pWin = LookupWindow(stuff->window, client); + if(!pWin) return BadWindow; + + rep.type = X_Reply; + rep.length = 0; + rep.sequenceNumber = client->sequence; + rep.ScreenCount = RADEONXineramaNumScreens; + if(client->swapped) { + swaps(&rep.sequenceNumber, n); + swapl(&rep.length, n); + swaps(&rep.ScreenCount, n); + } + WriteToClient(client, sizeof(xPanoramiXGetScreenCountReply), (char *)&rep); + return client->noClientException; +} + +int +RADEONProcXineramaGetScreenSize(ClientPtr client) +{ + REQUEST(xPanoramiXGetScreenSizeReq); + WindowPtr pWin; + xPanoramiXGetScreenSizeReply rep; + register int n; + + REQUEST_SIZE_MATCH(xPanoramiXGetScreenSizeReq); + pWin = LookupWindow (stuff->window, client); + if(!pWin) return BadWindow; + + rep.type = X_Reply; + rep.length = 0; + rep.sequenceNumber = client->sequence; + rep.width = RADEONXineramadataPtr[stuff->screen].width; + rep.height = RADEONXineramadataPtr[stuff->screen].height; + if(client->swapped) { + swaps(&rep.sequenceNumber, n); + swapl(&rep.length, n); + swaps(&rep.width, n); + swaps(&rep.height, n); + } + WriteToClient(client, sizeof(xPanoramiXGetScreenSizeReply), (char *)&rep); + return client->noClientException; +} + +int +RADEONProcXineramaIsActive(ClientPtr client) +{ + xXineramaIsActiveReply rep; + + REQUEST_SIZE_MATCH(xXineramaIsActiveReq); + + rep.type = X_Reply; + rep.length = 0; + rep.sequenceNumber = client->sequence; + rep.state = !RADEONnoPanoramiXExtension; + if(client->swapped) { + register int n; + swaps(&rep.sequenceNumber, n); + swapl(&rep.length, n); + swapl(&rep.state, n); + } + WriteToClient(client, sizeof(xXineramaIsActiveReply), (char *) &rep); + return client->noClientException; +} + +int +RADEONProcXineramaQueryScreens(ClientPtr client) +{ + xXineramaQueryScreensReply rep; + + REQUEST_SIZE_MATCH(xXineramaQueryScreensReq); + + rep.type = X_Reply; + rep.sequenceNumber = client->sequence; + rep.number = (RADEONnoPanoramiXExtension) ? 0 : RADEONXineramaNumScreens; + rep.length = rep.number * sz_XineramaScreenInfo >> 2; + if(client->swapped) { + register int n; + swaps(&rep.sequenceNumber, n); + swapl(&rep.length, n); + swapl(&rep.number, n); + } + WriteToClient(client, sizeof(xXineramaQueryScreensReply), (char *)&rep); + + if(!RADEONnoPanoramiXExtension) { + xXineramaScreenInfo scratch; + int i; + + for(i = 0; i < RADEONXineramaNumScreens; i++) { + scratch.x_org = RADEONXineramadataPtr[i].x; + scratch.y_org = RADEONXineramadataPtr[i].y; + scratch.width = RADEONXineramadataPtr[i].width; + scratch.height = RADEONXineramadataPtr[i].height; + if(client->swapped) { + register int n; + swaps(&scratch.x_org, n); + swaps(&scratch.y_org, n); + swaps(&scratch.width, n); + swaps(&scratch.height, n); + } + WriteToClient(client, sz_XineramaScreenInfo, (char *)&scratch); + } + } + + return client->noClientException; +} + +static int +RADEONProcXineramaDispatch(ClientPtr client) +{ + REQUEST(xReq); + switch (stuff->data) + { + case X_PanoramiXQueryVersion: + return RADEONProcXineramaQueryVersion(client); + case X_PanoramiXGetState: + return RADEONProcXineramaGetState(client); + case X_PanoramiXGetScreenCount: + return RADEONProcXineramaGetScreenCount(client); + case X_PanoramiXGetScreenSize: + return RADEONProcXineramaGetScreenSize(client); + case X_XineramaIsActive: + return RADEONProcXineramaIsActive(client); + case X_XineramaQueryScreens: + return RADEONProcXineramaQueryScreens(client); + } + return BadRequest; +} + +/* SProc */ + +static int +RADEONSProcXineramaQueryVersion (ClientPtr client) +{ + REQUEST(xPanoramiXQueryVersionReq); + register int n; + swaps(&stuff->length,n); + REQUEST_SIZE_MATCH(xPanoramiXQueryVersionReq); + return RADEONProcXineramaQueryVersion(client); +} + +static int +RADEONSProcXineramaGetState(ClientPtr client) +{ + REQUEST(xPanoramiXGetStateReq); + register int n; + swaps (&stuff->length, n); + REQUEST_SIZE_MATCH(xPanoramiXGetStateReq); + return RADEONProcXineramaGetState(client); +} + +static int +RADEONSProcXineramaGetScreenCount(ClientPtr client) +{ + REQUEST(xPanoramiXGetScreenCountReq); + register int n; + swaps (&stuff->length, n); + REQUEST_SIZE_MATCH(xPanoramiXGetScreenCountReq); + return RADEONProcXineramaGetScreenCount(client); +} + +static int +RADEONSProcXineramaGetScreenSize(ClientPtr client) +{ + REQUEST(xPanoramiXGetScreenSizeReq); + register int n; + swaps (&stuff->length, n); + REQUEST_SIZE_MATCH(xPanoramiXGetScreenSizeReq); + return RADEONProcXineramaGetScreenSize(client); +} + +static int +RADEONSProcXineramaIsActive(ClientPtr client) +{ + REQUEST(xXineramaIsActiveReq); + register int n; + swaps (&stuff->length, n); + REQUEST_SIZE_MATCH(xXineramaIsActiveReq); + return RADEONProcXineramaIsActive(client); +} + +static int +RADEONSProcXineramaQueryScreens(ClientPtr client) +{ + REQUEST(xXineramaQueryScreensReq); + register int n; + swaps (&stuff->length, n); + REQUEST_SIZE_MATCH(xXineramaQueryScreensReq); + return RADEONProcXineramaQueryScreens(client); +} + +int +RADEONSProcXineramaDispatch(ClientPtr client) +{ + REQUEST(xReq); + switch (stuff->data) { + case X_PanoramiXQueryVersion: + return RADEONSProcXineramaQueryVersion(client); + case X_PanoramiXGetState: + return RADEONSProcXineramaGetState(client); + case X_PanoramiXGetScreenCount: + return RADEONSProcXineramaGetScreenCount(client); + case X_PanoramiXGetScreenSize: + return RADEONSProcXineramaGetScreenSize(client); + case X_XineramaIsActive: + return RADEONSProcXineramaIsActive(client); + case X_XineramaQueryScreens: + return RADEONSProcXineramaQueryScreens(client); + } + return BadRequest; +} + +static void +RADEONXineramaResetProc(ExtensionEntry* extEntry) +{ + if(RADEONXineramadataPtr) { + Xfree(RADEONXineramadataPtr); + RADEONXineramadataPtr = NULL; + } +} + +void +RADEONXineramaExtensionInit(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + Bool success = FALSE; + + if(!(RADEONXineramadataPtr)) { + + if(!info->MergedFB) { + RADEONnoPanoramiXExtension = TRUE; + info->MouseRestrictions = FALSE; + return; + } + + if(IsXineramaActive()) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Xinerama active, not initializing Radeon Pseudo-Xinerama\n"); + RADEONnoPanoramiXExtension = TRUE; + info->MouseRestrictions = FALSE; + return; + } + + if(RADEONnoPanoramiXExtension) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Radeon Pseudo-Xinerama disabled\n"); + info->MouseRestrictions = FALSE; + return; + } + + if(info->CRT2Position == radeonClone) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Running MergedFB in Clone mode, Radeon Pseudo-Xinerama disabled\n"); + RADEONnoPanoramiXExtension = TRUE; + info->MouseRestrictions = FALSE; + return; + } + + if(!(info->AtLeastOneNonClone)) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Only Clone modes defined, Radeon Pseudo-Xinerama disabled\n"); + RADEONnoPanoramiXExtension = TRUE; + info->MouseRestrictions = FALSE; + return; + } + + RADEONXineramaNumScreens = 2; + + while(RADEONXineramaGeneration != serverGeneration) { + + info->XineramaExtEntry = AddExtension(PANORAMIX_PROTOCOL_NAME, 0,0, + RADEONProcXineramaDispatch, + RADEONSProcXineramaDispatch, + RADEONXineramaResetProc, + StandardMinorOpcode); + + if(!info->XineramaExtEntry) break; + +#if 0 + RADEONXineramaReqCode = (unsigned char)info->XineramaExtEntry->base; +#endif + + if(!(RADEONXineramadataPtr = (RADEONXineramaData *) + xcalloc(RADEONXineramaNumScreens, sizeof(RADEONXineramaData)))) break; + + RADEONXineramaGeneration = serverGeneration; + success = TRUE; + } + + if(!success) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Failed to initialize Radeon Pseudo-Xinerama extension\n"); + RADEONnoPanoramiXExtension = TRUE; + info->MouseRestrictions = FALSE; + return; + } + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Initialized Radeon Pseudo-Xinerama extension\n"); + + info->RADEONXineramaVX = 0; + info->RADEONXineramaVY = 0; + + } + + RADEONUpdateXineramaScreenInfo(pScrn); + +} +/* End of PseudoXinerama */ + +static Bool +InRegion(int x, int y, region r) +{ + return (r.x0 <= x) && (x <= r.x1) && (r.y0 <= y) && (y <= r.y1); +} + +void +RADEONMergePointerMoved(int scrnIndex, int x, int y) +{ + ScrnInfoPtr pScrn1 = xf86Screens[scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn1); + ScrnInfoPtr pScrn2 = info->CRT2pScrn; + region out, in1, in2, f2, f1; + int deltax, deltay; + int temp1, temp2; + int old1x0, old1y0, old2x0, old2y0; + int CRT1XOffs = 0, CRT1YOffs = 0, CRT2XOffs = 0, CRT2YOffs = 0; + int HVirt = pScrn1->virtualX; + int VVirt = pScrn1->virtualY; + int sigstate; + Bool doit = FALSE, HaveNonRect = FALSE, HaveOffsRegions = FALSE; + RADEONScrn2Rel srel = ((RADEONMergedDisplayModePtr)(pointer)info->CurrentLayout.mode->Private)->CRT2Position; + + if(info->DGAactive) { + return; + /* DGA: There is no cursor and no panning while DGA is active. */ + /* If it were, we would need to do: */ + /* HVirt = info->CurrentLayout.displayWidth; + VVirt = info->CurrentLayout.displayHeight; + BOUND(x, info->CurrentLayout.DGAViewportX, HVirt); + BOUND(y, info->CurrentLayout.DGAViewportY, VVirt); */ + } else { + CRT1XOffs = info->CRT1XOffs; + CRT1YOffs = info->CRT1YOffs; + CRT2XOffs = info->CRT2XOffs; + CRT2YOffs = info->CRT2YOffs; + HaveNonRect = info->HaveNonRect; + HaveOffsRegions = info->HaveOffsRegions; + } + + /* Check if the pointer is inside our dead areas */ + if((info->MouseRestrictions) && (srel != radeonClone) && !RADEONnoPanoramiXExtension) { + if(HaveNonRect) { + if(InRegion(x, y, info->NonRectDead)) { + switch(srel) { + case radeonLeftOf: + case radeonRightOf: y = info->NonRectDead.y0 - 1; + doit = TRUE; + break; + case radeonAbove: + case radeonBelow: x = info->NonRectDead.x0 - 1; + doit = TRUE; + default: break; + } + } + } + if(HaveOffsRegions) { + if(InRegion(x, y, info->OffDead1)) { + switch(srel) { + case radeonLeftOf: + case radeonRightOf: y = info->OffDead1.y1; + doit = TRUE; + break; + case radeonAbove: + case radeonBelow: x = info->OffDead1.x1; + doit = TRUE; + default: break; + } + } else if(InRegion(x, y, info->OffDead2)) { + switch(srel) { + case radeonLeftOf: + case radeonRightOf: y = info->OffDead2.y0 - 1; + doit = TRUE; + break; + case radeonAbove: + case radeonBelow: x = info->OffDead2.x0 - 1; + doit = TRUE; + default: break; + } + } + } + if(doit) { + UpdateCurrentTime(); + sigstate = xf86BlockSIGIO(); + miPointerAbsoluteCursor(x, y, currentTime.milliseconds); + xf86UnblockSIGIO(sigstate); + return; + } + } + + f1.x0 = old1x0 = info->CRT1frameX0; + f1.x1 = info->CRT1frameX1; + f1.y0 = old1y0 = info->CRT1frameY0; + f1.y1 = info->CRT1frameY1; + f2.x0 = old2x0 = pScrn2->frameX0; + f2.x1 = pScrn2->frameX1; + f2.y0 = old2y0 = pScrn2->frameY0; + f2.y1 = pScrn2->frameY1; + + /* Define the outer region. Crossing this causes all frames to move */ + out.x0 = pScrn1->frameX0; + out.x1 = pScrn1->frameX1; + out.y0 = pScrn1->frameY0; + out.y1 = pScrn1->frameY1; + + /* + * Define the inner sliding window. Being outsize both frames but + * inside the outer clipping window will slide corresponding frame + */ + in1 = out; + in2 = out; + switch(srel) { + case radeonLeftOf: + in1.x0 = f1.x0; + in2.x1 = f2.x1; + break; + case radeonRightOf: + in1.x1 = f1.x1; + in2.x0 = f2.x0; + break; + case radeonBelow: + in1.y1 = f1.y1; + in2.y0 = f2.y0; + break; + case radeonAbove: + in1.y0 = f1.y0; + in2.y1 = f2.y1; + break; + case radeonClone: + break; + } + + deltay = 0; + deltax = 0; + + if(InRegion(x, y, out)) { /* inside outer region */ + + /* xf86DrvMsg(0, X_INFO, "1: %d %d | %d %d %d %d | %d %d %d %d\n", + x, y, in1.x0, in1.x1, in1.y0, in1.y1, f1.x0, f1.x1, f1.y0, f1.y1); */ + + if(InRegion(x, y, in1) && !InRegion(x, y, f1)) { + REBOUND(f1.x0, f1.x1, x); + REBOUND(f1.y0, f1.y1, y); + deltax = 1; + /* xf86DrvMsg(0, X_INFO, "2: %d %d | %d %d %d %d | %d %d %d %d\n", + x, y, in1.x0, in1.x1, in1.y0, in1.y1, f1.x0, f1.x1, f1.y0, f1.y1); */ + } + if(InRegion(x, y, in2) && !InRegion(x, y, f2)) { + REBOUND(f2.x0, f2.x1, x); + REBOUND(f2.y0, f2.y1, y); + deltax = 1; + } + + } else { /* outside outer region */ + + /* xf86DrvMsg(0, X_INFO, "3: %d %d | %d %d %d %d | %d %d %d %d\n", + x, y, in1.x0, in1.x1, in1.y0, in1.y1, f1.x0, f1.x1, f1.y0, f1.y1); + xf86DrvMsg(0, X_INFO, "3-out: %d %d %d %d\n", + out.x0, out.x1, out.y0, out.y1); */ + + if(out.x0 > x) { + deltax = x - out.x0; + } + if(out.x1 < x) { + deltax = x - out.x1; + } + if(deltax) { + pScrn1->frameX0 += deltax; + pScrn1->frameX1 += deltax; + f1.x0 += deltax; + f1.x1 += deltax; + f2.x0 += deltax; + f2.x1 += deltax; + } + + if(out.y0 > y) { + deltay = y - out.y0; + } + if(out.y1 < y) { + deltay = y - out.y1; + } + if(deltay) { + pScrn1->frameY0 += deltay; + pScrn1->frameY1 += deltay; + f1.y0 += deltay; + f1.y1 += deltay; + f2.y0 += deltay; + f2.y1 += deltay; + } + + switch(srel) { + case radeonLeftOf: + if(x >= f1.x0) { REBOUND(f1.y0, f1.y1, y); } + if(x <= f2.x1) { REBOUND(f2.y0, f2.y1, y); } + break; + case radeonRightOf: + if(x <= f1.x1) { REBOUND(f1.y0, f1.y1, y); } + if(x >= f2.x0) { REBOUND(f2.y0, f2.y1, y); } + break; + case radeonBelow: + if(y <= f1.y1) { REBOUND(f1.x0, f1.x1, x); } + if(y >= f2.y0) { REBOUND(f2.x0, f2.x1, x); } + break; + case radeonAbove: + if(y >= f1.y0) { REBOUND(f1.x0, f1.x1, x); } + if(y <= f2.y1) { REBOUND(f2.x0, f2.x1, x); } + break; + case radeonClone: + break; + } + + } + + if(deltax || deltay) { + info->CRT1frameX0 = f1.x0; + info->CRT1frameY0 = f1.y0; + pScrn2->frameX0 = f2.x0; + pScrn2->frameY0 = f2.y0; + + switch(((RADEONMergedDisplayModePtr)(pointer)info->CurrentLayout.mode->Private)->CRT2Position) { + case radeonLeftOf: + case radeonRightOf: + if(info->CRT1YOffs || info->CRT2YOffs || HaveNonRect) { + if(info->CRT1frameY0 != old1y0) { + if(info->CRT1frameY0 < info->CRT1YOffs) + info->CRT1frameY0 = info->CRT1YOffs; + temp1 = info->CRT1frameY0 + CDMPTR->CRT1->VDisplay; + /*temp2 = pScrn1->virtualY - info->CRT2YOffs;*/ + temp2 = min((VVirt - CRT2YOffs), (CRT1YOffs + info->MBXNR1YMAX)); + if(temp1 > temp2) + info->CRT1frameY0 -= (temp1 - temp2); + } + if(pScrn2->frameY0 != old2y0) { + if(pScrn2->frameY0 < info->CRT2YOffs) + pScrn2->frameY0 = info->CRT2YOffs; + temp1 = pScrn2->frameY0 + CDMPTR->CRT2->VDisplay; + /*temp2 = pScrn1->virtualY - info->CRT1YOffs;*/ + temp2 = min((VVirt - CRT1YOffs), (CRT2YOffs + info->MBXNR2YMAX)); + if(temp1 > temp2) + pScrn2->frameY0 -= (temp1 - temp2); + } + } + break; + case radeonBelow: + case radeonAbove: + if(info->CRT1XOffs || info->CRT2XOffs || HaveNonRect) { + if(info->CRT1frameX0 != old1x0) { + if(info->CRT1frameX0 < info->CRT1XOffs) + info->CRT1frameX0 = info->CRT1XOffs; + temp1 = info->CRT1frameX0 + CDMPTR->CRT1->HDisplay; + /*temp2 = pScrn1->virtualX - info->CRT2XOffs;*/ + temp2 = min((HVirt - CRT2XOffs), (CRT1XOffs + info->MBXNR1XMAX)); + if(temp1 > temp2) + info->CRT1frameX0 -= (temp1 - temp2); + } + if(pScrn2->frameX0 != old2x0) { + if(pScrn2->frameX0 < info->CRT2XOffs) + pScrn2->frameX0 = info->CRT2XOffs; + temp1 = pScrn2->frameX0 + CDMPTR->CRT2->HDisplay; + /*temp2 = pScrn1->virtualX - info->CRT1XOffs;*/ + temp2 = min((HVirt - CRT1XOffs), (CRT2XOffs + info->MBXNR2XMAX)); + if(temp1 > temp2) + pScrn2->frameX0 -= (temp1 - temp2); + } + } + break; + case radeonClone: + break; + } + + info->CRT1frameX1 = info->CRT1frameX0 + CDMPTR->CRT1->HDisplay - 1; + info->CRT1frameY1 = info->CRT1frameY0 + CDMPTR->CRT1->VDisplay - 1; + pScrn2->frameX1 = pScrn2->frameX0 + CDMPTR->CRT2->HDisplay - 1; + pScrn2->frameY1 = pScrn2->frameY0 + CDMPTR->CRT2->VDisplay - 1; +#if 0 + pScrn1->frameX1 = pScrn1->frameX0 + info->CurrentLayout.mode->HDisplay - 1; + pScrn1->frameY1 = pScrn1->frameY0 + info->CurrentLayout.mode->VDisplay - 1; +#endif + + RADEONDoAdjustFrame(pScrn1, info->CRT1frameX0, info->CRT1frameY0, FALSE); + RADEONDoAdjustFrame(pScrn1, pScrn2->frameX0, pScrn2->frameY0, TRUE); + } +} + +static void +RADEONAdjustFrameMergedHelper(int scrnIndex, int x, int y, int flags) +{ + ScrnInfoPtr pScrn1 = xf86Screens[scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn1); + ScrnInfoPtr pScrn2 = info->CRT2pScrn; + int VTotal = info->CurrentLayout.mode->VDisplay; + int HTotal = info->CurrentLayout.mode->HDisplay; + int VMax = VTotal; + int HMax = HTotal; + int HVirt = pScrn1->virtualX; + int VVirt = pScrn1->virtualY; + /* Uppercase to avoid shadow warnings */ + int X1 = x, X2 = x; + int Y1 = y, Y2 = y; + int CRT1XOffs = 0, CRT1YOffs = 0, CRT2XOffs = 0, CRT2YOffs = 0; + int MBXNR1XMAX = 65536, MBXNR1YMAX = 65536, MBXNR2XMAX = 65536, MBXNR2YMAX = 65536; + + if(info->DGAactive) { + HVirt = info->CurrentLayout.displayWidth; + VVirt = info->CurrentLayout.displayHeight; + } else { + CRT1XOffs = info->CRT1XOffs; + CRT1YOffs = info->CRT1YOffs; + CRT2XOffs = info->CRT2XOffs; + CRT2YOffs = info->CRT2YOffs; + MBXNR1XMAX = info->MBXNR1XMAX; + MBXNR1YMAX = info->MBXNR1YMAX; + MBXNR2XMAX = info->MBXNR2XMAX; + MBXNR2YMAX = info->MBXNR2YMAX; + } + + + BOUND(x, 0, pScrn1->virtualX - HTotal); + BOUND(y, 0, pScrn1->virtualY - VTotal); + if(SDMPTR(pScrn1)->CRT2Position != radeonClone) { +#if 0 + BOUND(X1, info->CRT1XOffs, pScrn1->virtualX - HTotal - info->CRT2XOffs); + BOUND(Y1, info->CRT1YOffs, pScrn1->virtualY - VTotal - info->CRT2YOffs); + BOUND(X2, info->CRT2XOffs, pScrn1->virtualX - HTotal - info->CRT1XOffs); + BOUND(Y2, info->CRT2YOffs, pScrn1->virtualY - VTotal - info->CRT1YOffs); +#endif + BOUND(X1, CRT1XOffs, min(HVirt, MBXNR1XMAX + CRT1XOffs) - min(HTotal, MBXNR1XMAX) - CRT2XOffs); + BOUND(Y1, CRT1YOffs, min(VVirt, MBXNR1YMAX + CRT1YOffs) - min(VTotal, MBXNR1YMAX) - CRT2YOffs); + BOUND(X2, CRT2XOffs, min(HVirt, MBXNR2XMAX + CRT2XOffs) - min(HTotal, MBXNR2XMAX) - CRT1XOffs); + BOUND(Y2, CRT2YOffs, min(VVirt, MBXNR2YMAX + CRT2YOffs) - min(VTotal, MBXNR2YMAX) - CRT1YOffs); + } + + switch(SDMPTR(pScrn1)->CRT2Position) { + case radeonLeftOf: + pScrn2->frameX0 = X2; + /*BOUND(pScrn2->frameY0, Y2, Y2 + VMax - CDMPTR->CRT2->VDisplay);*/ + BOUND(pScrn2->frameY0, Y2, Y2 + min(VMax, MBXNR2YMAX) - CDMPTR->CRT2->VDisplay); + info->CRT1frameX0 = X1 + CDMPTR->CRT2->HDisplay; + /*BOUND(info->CRT1frameY0, Y1, Y1 + VMax - CDMPTR->CRT1->VDisplay);*/ + BOUND(info->CRT1frameY0, Y1, Y1 + min(VMax, MBXNR1YMAX) - CDMPTR->CRT1->VDisplay); + break; + case radeonRightOf: + info->CRT1frameX0 = X1; + /*BOUND(info->CRT1frameY0, Y1, Y1 + VMax - CDMPTR->CRT1->VDisplay);*/ + BOUND(info->CRT1frameY0, Y1, Y1 + min(VMax, MBXNR1YMAX) - CDMPTR->CRT1->VDisplay); + pScrn2->frameX0 = X2 + CDMPTR->CRT1->HDisplay; + /*BOUND(pScrn2->frameY0, Y2, Y2 + VMax - CDMPTR->CRT2->VDisplay);*/ + BOUND(pScrn2->frameY0, Y2, Y2 + min(VMax, MBXNR2YMAX) - CDMPTR->CRT2->VDisplay); + break; + case radeonAbove: + /*BOUND(pScrn2->frameX0, X2, X2 + HMax - CDMPTR->CRT2->HDisplay);*/ + BOUND(pScrn2->frameX0, X2, X2 + min(HMax, MBXNR2XMAX) - CDMPTR->CRT2->HDisplay); + pScrn2->frameY0 = Y2; + /*BOUND(info->CRT1frameX0, X1, X1 + HMax - CDMPTR->CRT1->HDisplay);*/ + BOUND(info->CRT1frameX0, X1, X1 + min(HMax, MBXNR1XMAX) - CDMPTR->CRT1->HDisplay); + info->CRT1frameY0 = Y1 + CDMPTR->CRT2->VDisplay; + break; + case radeonBelow: + /*BOUND(info->CRT1frameX0, X1, X1 + HMax - CDMPTR->CRT1->HDisplay);*/ + BOUND(info->CRT1frameX0, X1, X1 + min(HMax, MBXNR1XMAX) - CDMPTR->CRT1->HDisplay); + info->CRT1frameY0 = Y1; + /*BOUND(pScrn2->frameX0, X2, X2 + HMax - CDMPTR->CRT2->HDisplay);*/ + BOUND(pScrn2->frameX0, X2, X2 + min(HMax, MBXNR2XMAX) - CDMPTR->CRT2->HDisplay); + pScrn2->frameY0 = Y2 + CDMPTR->CRT1->VDisplay; + break; + case radeonClone: + BOUND(info->CRT1frameX0, x, x + HMax - CDMPTR->CRT1->HDisplay); + BOUND(info->CRT1frameY0, y, y + VMax - CDMPTR->CRT1->VDisplay); + BOUND(pScrn2->frameX0, x, x + HMax - CDMPTR->CRT2->HDisplay); + BOUND(pScrn2->frameY0, y, y + VMax - CDMPTR->CRT2->VDisplay); + break; + } + + BOUND(info->CRT1frameX0, 0, pScrn1->virtualX - CDMPTR->CRT1->HDisplay); + BOUND(info->CRT1frameY0, 0, pScrn1->virtualY - CDMPTR->CRT1->VDisplay); + BOUND(pScrn2->frameX0, 0, pScrn1->virtualX - CDMPTR->CRT2->HDisplay); + BOUND(pScrn2->frameY0, 0, pScrn1->virtualY - CDMPTR->CRT2->VDisplay); + + pScrn1->frameX0 = x; + pScrn1->frameY0 = y; + + info->CRT1frameX1 = info->CRT1frameX0 + CDMPTR->CRT1->HDisplay - 1; + info->CRT1frameY1 = info->CRT1frameY0 + CDMPTR->CRT1->VDisplay - 1; + pScrn2->frameX1 = pScrn2->frameX0 + CDMPTR->CRT2->HDisplay - 1; + pScrn2->frameY1 = pScrn2->frameY0 + CDMPTR->CRT2->VDisplay - 1; + pScrn1->frameX1 = pScrn1->frameX0 + info->CurrentLayout.mode->HDisplay - 1; + pScrn1->frameY1 = pScrn1->frameY0 + info->CurrentLayout.mode->VDisplay - 1; + + if(SDMPTR(pScrn1)->CRT2Position != radeonClone) { + pScrn1->frameX1 += CRT1XOffs + CRT2XOffs; + pScrn1->frameY1 += CRT1YOffs + CRT2YOffs; + } + +/* + RADEONDoAdjustFrame(pScrn1, info->CRT1frameX0, info->CRT1frameY0, FALSE); + RADEONDoAdjustFrame(pScrn1, pScrn2->frameX0, pScrn2->frameY0, TRUE); +*/ +} + +void +RADEONAdjustFrameMerged(int scrnIndex, int x, int y, int flags) +{ + ScrnInfoPtr pScrn1 = xf86Screens[scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn1); + ScrnInfoPtr pScrn2 = info->CRT2pScrn; + + RADEONAdjustFrameMergedHelper(scrnIndex, x, y, flags); + RADEONDoAdjustFrame(pScrn1, info->CRT1frameX0, info->CRT1frameY0, FALSE); + RADEONDoAdjustFrame(pScrn1, pScrn2->frameX0, pScrn2->frameY0, TRUE); +} + +static void +RADEONMergedFBCalcDPI(ScrnInfoPtr pScrn1, ScrnInfoPtr pScrn2, RADEONScrn2Rel srel, Bool quiet) +{ + RADEONInfoPtr info = RADEONPTR(pScrn1); + MessageType from = X_DEFAULT; + xf86MonPtr DDC1 = (xf86MonPtr)(pScrn1->monitor->DDC); + xf86MonPtr DDC2 = (xf86MonPtr)(pScrn2->monitor->DDC); + int ddcWidthmm = 0, ddcHeightmm = 0; + const char *dsstr = "MergedFB: Display dimensions: %dx%d mm\n"; + + /* This sets the DPI for MergedFB mode. The problem is that + * this can never be exact, because the output devices may + * have different dimensions. This function tries to compromise + * through a few assumptions, and it just calculates an average + * DPI value for both monitors. + */ + + /* Copy user-given DisplaySize (which should regard BOTH monitors!) */ + pScrn1->widthmm = pScrn1->monitor->widthmm; + pScrn1->heightmm = pScrn1->monitor->heightmm; + + if(monitorResolution > 0) { + + /* Set command line given values (overrules given options) */ + pScrn1->xDpi = monitorResolution; + pScrn1->yDpi = monitorResolution; + from = X_CMDLINE; + + } else if(info->MergedFBXDPI) { + + /* Set option-wise given values (overrules DisplaySize config option) */ + pScrn1->xDpi = info->MergedFBXDPI; + pScrn1->yDpi = info->MergedFBYDPI; + from = X_CONFIG; + + } else if(pScrn1->widthmm > 0 || pScrn1->heightmm > 0) { + + /* Set values calculated from given DisplaySize */ + from = X_CONFIG; + if(pScrn1->widthmm > 0) { + pScrn1->xDpi = (int)((double)pScrn1->virtualX * 25.4 / pScrn1->widthmm); + } + if(pScrn1->heightmm > 0) { + pScrn1->yDpi = (int)((double)pScrn1->virtualY * 25.4 / pScrn1->heightmm); + } + if(!quiet) { + xf86DrvMsg(pScrn1->scrnIndex, from, dsstr, pScrn1->widthmm, pScrn1->heightmm); + } + + } else if(ddcWidthmm && ddcHeightmm) { + + /* Set values from DDC-provided display size */ + + /* Get DDC display size; if only either CRT1 or CRT2 provided these, + * assume equal dimensions for both, otherwise add dimensions + */ + if( (DDC1 && (DDC1->features.hsize > 0 && DDC1->features.vsize > 0)) && + (DDC2 && (DDC2->features.hsize > 0 && DDC2->features.vsize > 0)) ) { + ddcWidthmm = max(DDC1->features.hsize, DDC2->features.hsize) * 10; + ddcHeightmm = max(DDC1->features.vsize, DDC2->features.vsize) * 10; + switch(srel) { + case radeonLeftOf: + case radeonRightOf: + ddcWidthmm = (DDC1->features.hsize + DDC2->features.hsize) * 10; + break; + case radeonAbove: + case radeonBelow: + ddcHeightmm = (DDC1->features.vsize + DDC2->features.vsize) * 10; + default: + break; + } + } else if(DDC1 && (DDC1->features.hsize > 0 && DDC1->features.vsize > 0)) { + ddcWidthmm = DDC1->features.hsize * 10; + ddcHeightmm = DDC1->features.vsize * 10; + switch(srel) { + case radeonLeftOf: + case radeonRightOf: + ddcWidthmm *= 2; + break; + case radeonAbove: + case radeonBelow: + ddcHeightmm *= 2; + default: + break; + } + } else if(DDC2 && (DDC2->features.hsize > 0 && DDC2->features.vsize > 0) ) { + ddcWidthmm = DDC2->features.hsize * 10; + ddcHeightmm = DDC2->features.vsize * 10; + switch(srel) { + case radeonLeftOf: + case radeonRightOf: + ddcWidthmm *= 2; + break; + case radeonAbove: + case radeonBelow: + ddcHeightmm *= 2; + default: + break; + } + } + + from = X_PROBED; + + if(!quiet) { + xf86DrvMsg(pScrn1->scrnIndex, from, dsstr, ddcWidthmm, ddcHeightmm); + } + + pScrn1->widthmm = ddcWidthmm; + pScrn1->heightmm = ddcHeightmm; + if(pScrn1->widthmm > 0) { + pScrn1->xDpi = (int)((double)pScrn1->virtualX * 25.4 / pScrn1->widthmm); + } + if(pScrn1->heightmm > 0) { + pScrn1->yDpi = (int)((double)pScrn1->virtualY * 25.4 / pScrn1->heightmm); + } + + } else { + + pScrn1->xDpi = pScrn1->yDpi = DEFAULT_DPI; + + } + + /* Sanity check */ + if(pScrn1->xDpi > 0 && pScrn1->yDpi <= 0) + pScrn1->yDpi = pScrn1->xDpi; + if(pScrn1->yDpi > 0 && pScrn1->xDpi <= 0) + pScrn1->xDpi = pScrn1->yDpi; + + pScrn2->xDpi = pScrn1->xDpi; + pScrn2->yDpi = pScrn1->yDpi; + + if(!quiet) { + xf86DrvMsg(pScrn1->scrnIndex, from, "MergedFB: DPI set to (%d, %d)\n", + pScrn1->xDpi, pScrn1->yDpi); + } +} + + +void +RADEONMergedFBSetDpi(ScrnInfoPtr pScrn1, ScrnInfoPtr pScrn2, RADEONScrn2Rel srel) +{ + RADEONInfoPtr info = RADEONPTR(pScrn1); + + RADEONMergedFBCalcDPI(pScrn1, pScrn2, srel, FALSE); + + info->MergedDPISRel = srel; + info->RADEONMergedDPIVX = pScrn1->virtualX; + info->RADEONMergedDPIVY = pScrn1->virtualY; + +} + +void +RADEONMergedFBResetDpi(ScrnInfoPtr pScrn, Bool force) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + ScreenPtr pScreen = screenInfo.screens[pScrn->scrnIndex]; + RADEONScrn2Rel srel = ((RADEONMergedDisplayModePtr)(pointer)info->CurrentLayout.mode->Private)->CRT2Position; + + /* This does the same calculation for the DPI as + * the initial run. This means that an eventually + * given -dpi command line switch will lead to + * constant dpi values, regardless of the virtual + * screen size. + * I consider this consequent. If this is undesired, + * one should use the DisplaySize parameter in the + * config file instead of the command line switch. + * The DPI will be calculated then. + */ + + if(force || + (info->MergedDPISRel != srel) || + (info->RADEONMergedDPIVX != pScrn->virtualX) || + (info->RADEONMergedDPIVY != pScrn->virtualY) + ) { + + RADEONMergedFBCalcDPI(pScrn, info->CRT2pScrn, srel, TRUE); + + pScreen->mmWidth = (pScrn->virtualX * 254 + pScrn->xDpi * 5) / (pScrn->xDpi * 10); + pScreen->mmHeight = (pScrn->virtualY * 254 + pScrn->yDpi * 5) / (pScrn->yDpi * 10); + + info->MergedDPISRel = srel; + info->RADEONMergedDPIVX = pScrn->virtualX; + info->RADEONMergedDPIVY = pScrn->virtualY; + + } +} + +/* radeon cursor helpers */ +static void +RADEONChooseCursorCRTC(ScrnInfoPtr pScrn1, int x, int y) +{ + RADEONInfoPtr info = RADEONPTR(pScrn1); + unsigned char *RADEONMMIO = info->MMIO; + RADEONScrn2Rel srel = + ((RADEONMergedDisplayModePtr)(pointer)info->CurrentLayout.mode->Private)->CRT2Position; + ScrnInfoPtr pScrn2 = info->CRT2pScrn; + + if (srel == radeonClone) { + /* show cursor 2 */ + OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN, + ~RADEON_CRTC2_CUR_EN); + /* show cursor 1 */ + OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN, + ~RADEON_CRTC_CUR_EN); + } + else { + if (((x >= pScrn1->frameX0) && (x <= pScrn1->frameX1)) && + ((y >= pScrn1->frameY0) && (y <= pScrn1->frameY1))) { + /* hide cursor 2 */ + OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_CUR_EN); + /* show cursor 1 */ + OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN, + ~RADEON_CRTC_CUR_EN); + } + if (((x >= pScrn2->frameX0) && (x <= pScrn2->frameX1)) && + ((y >= pScrn2->frameY0) && (y <= pScrn2->frameY1))) { + /* hide cursor 1 */ + OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_CUR_EN); + /* show cursor 2 */ + OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN, + ~RADEON_CRTC2_CUR_EN); + } + } +} + +void +RADEONSetCursorPositionMerged(ScrnInfoPtr pScrn, int x, int y) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + xf86CursorInfoPtr cursor = info->cursor; + int xorigin = 0; + int yorigin = 0; + int stride = 256; + ScrnInfoPtr pScrn2 = info->CRT2pScrn; + DisplayModePtr mode1 = CDMPTR->CRT1; + DisplayModePtr mode2 = CDMPTR->CRT2; + /* Uppercase to avoid shadow warnings */ + int X1, Y1, X2, Y2; + int total_y1 = pScrn->frameY1 - pScrn->frameY0; + int total_y2 = pScrn2->frameY1 - pScrn2->frameY0; + + if (x < 0) xorigin = -x+1; + if (y < 0) yorigin = -y+1; + /* if (y > total_y) y = total_y; */ + if (xorigin >= cursor->MaxWidth) xorigin = cursor->MaxWidth - 1; + if (yorigin >= cursor->MaxHeight) yorigin = cursor->MaxHeight - 1; + + x += pScrn->frameX0; + y += pScrn->frameY0; + + X1 = x - info->CRT1frameX0; + Y1 = y - info->CRT1frameY0; + + X2 = x - pScrn2->frameX0; + Y2 = y - pScrn2->frameY0; + + if (Y1 > total_y1) + Y1 = total_y1; + if (Y2 > total_y2) + Y2 = total_y2; + + if(mode1->Flags & V_INTERLACE) + Y1 /= 2; + else if(mode1->Flags & V_DBLSCAN) + Y1 *= 2; + + if(mode2->Flags & V_INTERLACE) + Y2 /= 2; + else if(mode2->Flags & V_DBLSCAN) + Y2 *= 2; + + if (x < 0) + x = 0; + if (y < 0) + y = 0; + + RADEONChooseCursorCRTC(pScrn, x, y); + + /* cursor1 */ + OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK + | (xorigin << 16) + | yorigin)); + OUTREG(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK + | ((xorigin ? 0 : X1) << 16) + | (yorigin ? 0 : Y1))); + OUTREG(RADEON_CUR_OFFSET, info->cursor_offset + yorigin * stride); + /* cursor2 */ + OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK + | (xorigin << 16) + | yorigin)); + OUTREG(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK + | ((xorigin ? 0 : X2) << 16) + | (yorigin ? 0 : Y2))); + OUTREG(RADEON_CUR2_OFFSET, info->cursor_offset + yorigin * stride); +} + +/* radeon Xv helpers */ + +/* choose the crtc for the overlay for mergedfb based on the location + of the output window and the orientation of the crtcs */ + +void +RADEONChooseOverlayCRTC( + ScrnInfoPtr pScrn, + BoxPtr dstBox +) { + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONScrn2Rel srel = + ((RADEONMergedDisplayModePtr)(pointer)info->CurrentLayout.mode->Private)->CRT2Position; + + if (srel == radeonLeftOf) { + if (dstBox->x1 >= info->CRT2pScrn->frameX1) + info->OverlayOnCRTC2 = FALSE; + else + info->OverlayOnCRTC2 = TRUE; + } + if (srel == radeonRightOf) { + if (dstBox->x2 <= info->CRT2pScrn->frameX0) + info->OverlayOnCRTC2 = FALSE; + else + info->OverlayOnCRTC2 = TRUE; + } + if (srel == radeonAbove) { + if (dstBox->y1 >= info->CRT2pScrn->frameY1) + info->OverlayOnCRTC2 = FALSE; + else + info->OverlayOnCRTC2 = TRUE; + } + if (srel == radeonBelow) { + if (dstBox->y2 <= info->CRT2pScrn->frameY0) + info->OverlayOnCRTC2 = FALSE; + else + info->OverlayOnCRTC2 = TRUE; + } +} Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_mergedfb.h diff -u /dev/null xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_mergedfb.h:1.1 --- /dev/null Mon Dec 15 09:54:56 2008 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_mergedfb.h Wed Apr 2 14:02:32 2008 @@ -0,0 +1,100 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_mergedfb.h,v 1.1 2008/04/02 21:02:32 tsi Exp $ */ +/* + * Copyright 2003 Alex Deucher. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ALEX DEUCHER, OR ANY OTHER + * CONTRIBUTORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Alex Deucher <agd5f@yahoo.com> + * + */ + +#ifndef _RADEON_MERGEDFB_H_ +#define _RADEON_MERGEDFB_H_ + +#include "xf86.h" + +#include "radeon.h" + +#define SDMPTR(x) ((RADEONMergedDisplayModePtr)(pointer)(x->currentMode->Private)) +#define CDMPTR ((RADEONMergedDisplayModePtr)(pointer)(info->CurrentLayout.mode->Private)) + +#define BOUND(test,low,hi) { \ + if(test < low) test = low; \ + if(test > hi) test = hi; } + +#define REBOUND(low,hi,test) { \ + if(test < low) { \ + hi += test-low; \ + low = test; } \ + if(test > hi) { \ + low += test-hi; \ + hi = test; } } + +typedef struct _MergedDisplayModeRec { + DisplayModePtr CRT1; + DisplayModePtr CRT2; + RADEONScrn2Rel CRT2Position; +} RADEONMergedDisplayModeRec, *RADEONMergedDisplayModePtr; + +typedef struct _RADEONXineramaData { + int x; + int y; + int width; + int height; +} RADEONXineramaData; + +/* needed by radeon_driver.c */ +extern void +RADEONAdjustFrameMerged(int scrnIndex, int x, int y, int flags); +extern void +RADEONMergePointerMoved(int scrnIndex, int x, int y); +extern DisplayModePtr +RADEONGenerateModeList(ScrnInfoPtr pScrn, char* str, + DisplayModePtr i, DisplayModePtr j, + RADEONScrn2Rel srel); +extern int +RADEONStrToRanges(range *r, char *s, int max); +extern void +RADEONXineramaExtensionInit(ScrnInfoPtr pScrn); +extern void +RADEONUpdateXineramaScreenInfo(ScrnInfoPtr pScrn1); +extern void +RADEONMergedFBSetDpi(ScrnInfoPtr pScrn1, ScrnInfoPtr pScrn2, RADEONScrn2Rel srel); +extern void +RADEONMergedFBResetDpi(ScrnInfoPtr pScrn, Bool force); +extern void +RADEONRecalcDefaultVirtualSize(ScrnInfoPtr pScrn); + +/* needed by radeon_cursor.c */ +extern void +RADEONSetCursorPositionMerged(ScrnInfoPtr pScrn, int x, int y); + +/* needed by radeon_video.c */ +extern void +RADEONChooseOverlayCRTC(ScrnInfoPtr, BoxPtr); + +#endif /* _RADEON_MERGEDFB_H_ */ Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_misc.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_misc.c:1.13 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_misc.c:1.14 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_misc.c:1.13 Mon Jan 1 08:08:18 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_misc.c Mon Dec 31 16:40:02 2007 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_misc.c,v 1.13 2007/01/01 16:08:18 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_misc.c,v 1.14 2008/01/01 00:40:02 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c:1.34 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c:1.38 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c:1.34 Thu Mar 16 08:50:00 2006 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c Wed Apr 30 08:43:48 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c,v 1.34 2006/03/16 16:50:00 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c,v 1.38 2008/04/30 15:43:48 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -83,138 +83,318 @@ #endif SymTabRec RADEONChipsets[] = { - { PCI_CHIP_RADEON_QD, "ATI Radeon QD (AGP)" }, - { PCI_CHIP_RADEON_QE, "ATI Radeon QE (AGP)" }, - { PCI_CHIP_RADEON_QF, "ATI Radeon QF (AGP)" }, - { PCI_CHIP_RADEON_QG, "ATI Radeon QG (AGP)" }, - { PCI_CHIP_RV100_QY, "ATI Radeon VE/7000 QY (AGP/PCI)" }, - { PCI_CHIP_RV100_QZ, "ATI Radeon VE/7000 QZ (AGP/PCI)" }, - { PCI_CHIP_RADEON_LW, "ATI Radeon Mobility M7 LW (AGP)" }, - { PCI_CHIP_RADEON_LX, "ATI Mobility FireGL 7800 M7 LX (AGP)" }, - { PCI_CHIP_RADEON_LY, "ATI Radeon Mobility M6 LY (AGP)" }, - { PCI_CHIP_RADEON_LZ, "ATI Radeon Mobility M6 LZ (AGP)" }, + /* Please keep these in PCI chip ID order */ + { PCI_CHIP_RV380_3150, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" }, + { PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" }, + { PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" }, + { PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" }, + { PCI_CHIP_RV380_3E54, "ATI FireGL V3200 (RV380) 3E54 (PCIE)" }, { PCI_CHIP_RS100_4136, "ATI Radeon IGP320 (A3) 4136" }, - { PCI_CHIP_RS100_4336, "ATI Radeon IGP320M (U1) 4336" }, { PCI_CHIP_RS200_4137, "ATI Radeon IGP330/340/350 (A4) 4137" }, - { PCI_CHIP_RS200_4337, "ATI Radeon IGP330M/340M/350M (U2) 4337" }, + { PCI_CHIP_R300_AD, "ATI Radeon 9500 AD (AGP)" }, + { PCI_CHIP_R300_AE, "ATI Radeon 9500 AE (AGP)" }, + { PCI_CHIP_R300_AF, "ATI Radeon 9600TX AF (AGP)" }, + { PCI_CHIP_R300_AG, "ATI FireGL Z1 AG (AGP)" }, + { PCI_CHIP_R350_AH, "ATI Radeon 9800SE AH (AGP)" }, + { PCI_CHIP_R350_AI, "ATI Radeon 9800 AI (AGP)" }, + { PCI_CHIP_R350_AJ, "ATI Radeon 9800 AJ (AGP)" }, + { PCI_CHIP_R350_AK, "ATI FireGL X2 AK (AGP)" }, + { PCI_CHIP_RV350_AP, "ATI Radeon 9600 AP (AGP)" }, + { PCI_CHIP_RV350_AQ, "ATI Radeon 9600SE AQ (AGP)" }, + { PCI_CHIP_RV360_AR, "ATI Radeon 9600XT AR (AGP)" }, + { PCI_CHIP_RV350_AS, "ATI Radeon 9600 AS (AGP)" }, + { PCI_CHIP_RV350_AT, "ATI FireGL T2 AT (AGP)" }, + { PCI_CHIP_RV350_4155, "ATI Radeon 9650" }, + { PCI_CHIP_RV350_AV, "ATI FireGL RV360 AV (AGP)" }, + { PCI_CHIP_RV350_AW, "ATI FireGL RV360 AW (AGP)" }, { PCI_CHIP_RS250_4237, "ATI Radeon 7000 IGP (A4+) 4237" }, - { PCI_CHIP_RS250_4437, "ATI Radeon Mobility 7000 IGP 4437" }, - { PCI_CHIP_R200_QH, "ATI FireGL 8700/8800 QH (AGP)" }, - { PCI_CHIP_R200_QL, "ATI Radeon 8500 QL (AGP)" }, - { PCI_CHIP_R200_QM, "ATI Radeon 9100 QM (AGP)" }, { PCI_CHIP_R200_BB, "ATI Radeon 8500 AIW BB (AGP)" }, { PCI_CHIP_R200_BC, "ATI Radeon 8500 AIW BC (AGP)" }, - { PCI_CHIP_RV200_QW, "ATI Radeon 7500 QW (AGP/PCI)" }, - { PCI_CHIP_RV200_QX, "ATI Radeon 7500 QX (AGP/PCI)" }, + { PCI_CHIP_RS100_4336, "ATI Radeon IGP320M (U1) 4336" }, + { PCI_CHIP_RS200_4337, "ATI Radeon IGP330M/340M/350M (U2) 4337" }, + { PCI_CHIP_RS250_4437, "ATI Radeon Mobility 7000 IGP 4437" }, + { PCI_CHIP_RV250_Id, "ATI Radeon 9000/PRO Id (AGP/PCI)" }, + { PCI_CHIP_RV250_Ie, "ATI Radeon 9000/PRO Ie (AGP/PCI)" }, { PCI_CHIP_RV250_If, "ATI Radeon 9000/PRO If (AGP/PCI)" }, { PCI_CHIP_RV250_Ig, "ATI Radeon 9000 Ig (AGP/PCI)" }, + { PCI_CHIP_R420_JH, "ATI Radeon X800 (R420) JH (AGP)" }, + { PCI_CHIP_R420_JI, "ATI Radeon X800PRO (R420) JI (AGP)" }, + { PCI_CHIP_R420_JJ, "ATI Radeon X800SE (R420) JJ (AGP)" }, + { PCI_CHIP_R420_JK, "ATI Radeon X800 (R420) JK (AGP)" }, + { PCI_CHIP_R420_JL, "ATI Radeon X800 (R420) JL (AGP)" }, + { PCI_CHIP_R420_JM, "ATI FireGL X3 (R420) JM (AGP)" }, + { PCI_CHIP_R420_JN, "ATI Radeon Mobility 9800 (M18) JN (AGP)" }, + { PCI_CHIP_R420_4A4F, "ATI Radeon X800 SE (R420) (AGP)" }, + { PCI_CHIP_R420_JP, "ATI Radeon X800XT (R420) JP (AGP)" }, + { PCI_CHIP_R420_4A54, "ATI Radeon AIW X800 VE (R420) JT (AGP)" }, + { PCI_CHIP_R481_4B49, "ATI Radeon X850 XT (R480) (AGP)" }, + { PCI_CHIP_R481_4B4A, "ATI Radeon X850 SE (R480) (AGP)" }, + { PCI_CHIP_R481_4B4B, "ATI Radeon X850 PRO (R480) (AGP)" }, + { PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" }, + { PCI_CHIP_RADEON_LW, "ATI Radeon Mobility M7 LW (AGP)" }, + { PCI_CHIP_RADEON_LX, "ATI Mobility FireGL 7800 M7 LX (AGP)" }, + { PCI_CHIP_RADEON_LY, "ATI Radeon Mobility M6 LY (AGP)" }, + { PCI_CHIP_RADEON_LZ, "ATI Radeon Mobility M6 LZ (AGP)" }, { PCI_CHIP_RV250_Ld, "ATI FireGL Mobility 9000 (M9) Ld (AGP)" }, + { PCI_CHIP_RV250_Le, "ATI FireGL Mobility 9000 (M9) Le (AGP)" }, { PCI_CHIP_RV250_Lf, "ATI Radeon Mobility 9000 (M9) Lf (AGP)" }, { PCI_CHIP_RV250_Lg, "ATI Radeon Mobility 9000 (M9) Lg (AGP)" }, - { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" }, - { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" }, - { PCI_CHIP_RV280_5960, "ATI Radeon 9200PRO 5960 (AGP)" }, - { PCI_CHIP_RV280_5961, "ATI Radeon 9200 5961 (AGP)" }, - { PCI_CHIP_RV280_5962, "ATI Radeon 9200 5962 (AGP)" }, - { PCI_CHIP_RV280_5964, "ATI Radeon 9200SE 5964 (AGP)" }, - { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" }, - { PCI_CHIP_RV280_5C63, "ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" }, - { PCI_CHIP_R300_AD, "ATI Radeon 9500 AD (AGP)" }, - { PCI_CHIP_R300_AE, "ATI Radeon 9500 AE (AGP)" }, - { PCI_CHIP_R300_AF, "ATI Radeon 9600TX AF (AGP)" }, - { PCI_CHIP_R300_AG, "ATI FireGL Z1 AG (AGP)" }, { PCI_CHIP_R300_ND, "ATI Radeon 9700 Pro ND (AGP)" }, { PCI_CHIP_R300_NE, "ATI Radeon 9700/9500Pro NE (AGP)" }, - { PCI_CHIP_R300_NF, "ATI Radeon 9700 NF (AGP)" }, + { PCI_CHIP_R300_NF, "ATI Radeon 9600TX NF (AGP)" }, { PCI_CHIP_R300_NG, "ATI FireGL X1 NG (AGP)" }, - { PCI_CHIP_RV350_AP, "ATI Radeon 9600 AP (AGP)" }, - { PCI_CHIP_RV350_AQ, "ATI Radeon 9600SE AQ (AGP)" }, - { PCI_CHIP_RV360_AR, "ATI Radeon 9600XT AR (AGP)" }, - { PCI_CHIP_RV350_AS, "ATI Radeon 9600 AS (AGP)" }, - { PCI_CHIP_RV350_AT, "ATI FireGL T2 AT (AGP)" }, - { PCI_CHIP_RV350_AV, "ATI FireGL RV360 AV (AGP)" }, - { PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600 (M10) NP (AGP)" }, + { PCI_CHIP_R350_NH, "ATI Radeon 9800PRO NH (AGP)" }, + { PCI_CHIP_R350_NI, "ATI Radeon 9800 NI (AGP)" }, + { PCI_CHIP_R360_NJ, "ATI Radeon 9800XT NJ (AGP)" }, + { PCI_CHIP_R350_NK, "ATI FireGL X2 NK (AGP)" }, + { PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" }, { PCI_CHIP_RV350_NQ, "ATI Radeon Mobility 9600 (M10) NQ (AGP)" }, { PCI_CHIP_RV350_NR, "ATI Radeon Mobility 9600 (M11) NR (AGP)" }, { PCI_CHIP_RV350_NS, "ATI Radeon Mobility 9600 (M10) NS (AGP)" }, { PCI_CHIP_RV350_NT, "ATI FireGL Mobility T2 (M10) NT (AGP)" }, - { PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2 (M11) NV (AGP)" }, - { PCI_CHIP_R350_AH, "ATI Radeon 9800SE AH (AGP)" }, - { PCI_CHIP_R350_AI, "ATI Radeon 9800 AI (AGP)" }, - { PCI_CHIP_R350_AJ, "ATI Radeon 9800 AJ (AGP)" }, - { PCI_CHIP_R350_AK, "ATI FireGL X2 AK (AGP)" }, - { PCI_CHIP_R350_NH, "ATI Radeon 9800PRO NH (AGP)" }, - { PCI_CHIP_R350_NI, "ATI Radeon 9800 NI (AGP)" }, - { PCI_CHIP_R350_NK, "ATI FireGL X2 NK (AGP)" }, - { PCI_CHIP_R360_NJ, "ATI Radeon 9800XT NJ (AGP)" }, + { PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2e (M11) NV (AGP)" }, + { PCI_CHIP_RADEON_QD, "ATI Radeon QD (AGP)" }, + { PCI_CHIP_RADEON_QE, "ATI Radeon QE (AGP)" }, + { PCI_CHIP_RADEON_QF, "ATI Radeon QF (AGP)" }, + { PCI_CHIP_RADEON_QG, "ATI Radeon QG (AGP)" }, + { PCI_CHIP_R200_QH, "ATI FireGL 8700/8800 QH (AGP)" }, + { PCI_CHIP_R200_QI, "ATI Radeon 8500 QI (AGP)" }, + { PCI_CHIP_R200_QJ, "ATI Radeon 8500 QJ (AGP)" }, + { PCI_CHIP_R200_QK, "ATI Radeon 8500 QK (AGP)" }, + { PCI_CHIP_R200_QL, "ATI Radeon 8500 QL (AGP)" }, + { PCI_CHIP_R200_QM, "ATI Radeon 9100 QM (AGP)" }, + { PCI_CHIP_R200_QN, "ATI Radeon 8500 QN (AGP)" }, + { PCI_CHIP_R200_QO, "ATI Radeon 8500 QO (AGP)" }, + { PCI_CHIP_RV200_QW, "ATI Radeon 7500 QW (AGP/PCI)" }, + { PCI_CHIP_RV200_QX, "ATI Radeon 7500 QX (AGP/PCI)" }, + { PCI_CHIP_RV100_QY, "ATI Radeon VE/7000 QY (AGP/PCI)" }, + { PCI_CHIP_RV100_QZ, "ATI Radeon VE/7000 QZ (AGP/PCI)" }, + { PCI_CHIP_RN50_515E, "ATI ES1000 515E (PCI)" }, + { PCI_CHIP_R200_Qh, "ATI Radeon R200 Qh (AGP)" }, + { PCI_CHIP_R200_Qi, "ATI Radeon R200 Qi (AGP)" }, + { PCI_CHIP_R200_Qj, "ATI Radeon R200 Qj (AGP)" }, + { PCI_CHIP_R200_Qk, "ATI Radeon R200 Qk (AGP)" }, + { PCI_CHIP_R200_Ql, "ATI Radeon R200 Ql (AGP)" }, + { PCI_CHIP_RV370_5460, "ATI Radeon Mobility X300 (M22) 5460 (PCIE)" }, + { PCI_CHIP_RV370_5462, "ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" }, + { PCI_CHIP_RV370_5464, "ATI FireGL M22 GL 5464 (PCIE)" }, + { PCI_CHIP_R423_UH, "ATI Radeon X800 (R423) UH (PCIE)" }, + { PCI_CHIP_R423_UI, "ATI Radeon X800PRO (R423) UI (PCIE)" }, + { PCI_CHIP_R423_UJ, "ATI Radeon X800LE (R423) UJ (PCIE)" }, + { PCI_CHIP_R423_UK, "ATI Radeon X800SE (R423) UK (PCIE)" }, + { PCI_CHIP_R430_554C, "ATI Radeon X800 XTP (R430) (PCIE)" }, + { PCI_CHIP_R430_554D, "ATI Radeon X800 XL (R430) (PCIE)" }, + { PCI_CHIP_R430_554E, "ATI Radeon X800 SE (R430) (PCIE)" }, + { PCI_CHIP_R430_554F, "ATI Radeon X800 (R430) (PCIE)" }, + { PCI_CHIP_R423_5550, "ATI FireGL V7100 (R423) (PCIE)" }, + { PCI_CHIP_R423_UQ, "ATI FireGL V5100 (R423) UQ (PCIE)" }, + { PCI_CHIP_R423_UR, "ATI FireGL V5100 (R423) UR (PCIE)" }, + { PCI_CHIP_R423_UT, "ATI FireGL V7100 (R423) UT (PCIE)" }, + { PCI_CHIP_RV410_564A, "ATI Mobility FireGL V5000 (M26) (PCIE)" }, + { PCI_CHIP_RV410_564B, "ATI Mobility FireGL V5000 (M26) (PCIE)" }, + { PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" }, + { PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" }, + { PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" }, + { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" }, + { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" }, + { PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" }, + { PCI_CHIP_RS480_5955, "ATI Radeon XPRESS 200M 5955 (PCIE)" }, + { PCI_CHIP_RV280_5960, "ATI Radeon 9250 5960 (AGP)" }, + { PCI_CHIP_RV280_5961, "ATI Radeon 9200 5961 (AGP)" }, + { PCI_CHIP_RV280_5962, "ATI Radeon 9200 5962 (AGP)" }, + { PCI_CHIP_RV280_5964, "ATI Radeon 9200SE 5964 (AGP)" }, + { PCI_CHIP_RV280_5965, "ATI FireMV 2200 (PCI)" }, + { PCI_CHIP_RN50_5969, "ATI ES1000 5969 (PCI)" }, + { PCI_CHIP_RS482_5974, "ATI Radeon XPRESS 200 5974 (PCIE)" }, + { PCI_CHIP_RS482_5975, "ATI Radeon XPRESS 200M 5975 (PCIE)" }, + { PCI_CHIP_RS400_5A41, "ATI Radeon XPRESS 200 5A41 (PCIE)" }, + { PCI_CHIP_RS400_5A42, "ATI Radeon XPRESS 200M 5A42 (PCIE)" }, + { PCI_CHIP_RC410_5A61, "ATI Radeon XPRESS 200 5A61 (PCIE)" }, + { PCI_CHIP_RC410_5A62, "ATI Radeon XPRESS 200M 5A62 (PCIE)" }, + { PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" }, + { PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" }, + { PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" }, + { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" }, + { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" }, + { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" }, + { PCI_CHIP_RV280_5C63, "ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" }, + { PCI_CHIP_R430_5D48, "ATI Mobility Radeon X800 XT (M28) (PCIE)" }, + { PCI_CHIP_R430_5D49, "ATI Mobility FireGL V5100 (M28) (PCIE)" }, + { PCI_CHIP_R430_5D4A, "ATI Mobility Radeon X800 (M28) (PCIE)" }, + { PCI_CHIP_R480_5D4C, "ATI Radeon X850 5D4C (PCIE)" }, + { PCI_CHIP_R480_5D4D, "ATI Radeon X850 XT PE (R480) (PCIE)" }, + { PCI_CHIP_R480_5D4E, "ATI Radeon X850 SE (R480) (PCIE)" }, + { PCI_CHIP_R480_5D4F, "ATI Radeon X850 PRO (R480) (PCIE)" }, + { PCI_CHIP_R480_5D50, "ATI FireGL V7200 (R480) 5D50 (PCIE)" }, + { PCI_CHIP_R480_5D52, "ATI Radeon X850 XT (R480) (PCIE)" }, + { PCI_CHIP_R423_5D57, "ATI Radeon X800XT (R423) 5D57 (PCIE)" }, + { PCI_CHIP_RV410_5E48, "ATI FireGL V5000 (RV410) (PCIE)" }, + { PCI_CHIP_RV410_5E4A, "ATI Radeon X700 XT (RV410) (PCIE)" }, + { PCI_CHIP_RV410_5E4B, "ATI Radeon X700 PRO (RV410) (PCIE)" }, + { PCI_CHIP_RV410_5E4C, "ATI Radeon X700 SE (RV410) (PCIE)" }, + { PCI_CHIP_RV410_5E4D, "ATI Radeon X700 (RV410) (PCIE)" }, + { PCI_CHIP_RV410_5E4F, "ATI Radeon X700 SE (RV410) (PCIE)" }, + { PCI_CHIP_RS350_7834, "ATI Radeon 9100 PRO IGP 7834" }, + { PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" }, + { -1, NULL } }; PciChipsets RADEONPciChipsets[] = { - { PCI_CHIP_RADEON_QD, PCI_CHIP_RADEON_QD, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_QE, PCI_CHIP_RADEON_QE, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_QF, PCI_CHIP_RADEON_QF, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_QG, PCI_CHIP_RADEON_QG, RES_SHARED_VGA }, - { PCI_CHIP_RV100_QY, PCI_CHIP_RV100_QY, RES_SHARED_VGA }, - { PCI_CHIP_RV100_QZ, PCI_CHIP_RV100_QZ, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_LW, PCI_CHIP_RADEON_LW, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_LX, PCI_CHIP_RADEON_LX, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_LY, PCI_CHIP_RADEON_LY, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_LZ, PCI_CHIP_RADEON_LZ, RES_SHARED_VGA }, + /* These must be in the same order as RADEONChipsets above */ + { PCI_CHIP_RV380_3150, PCI_CHIP_RV380_3150, RES_SHARED_VGA }, + { PCI_CHIP_RV380_3152, PCI_CHIP_RV380_3152, RES_SHARED_VGA }, + { PCI_CHIP_RV380_3154, PCI_CHIP_RV380_3154, RES_SHARED_VGA }, + { PCI_CHIP_RV380_3E50, PCI_CHIP_RV380_3E50, RES_SHARED_VGA }, + { PCI_CHIP_RV380_3E54, PCI_CHIP_RV380_3E54, RES_SHARED_VGA }, { PCI_CHIP_RS100_4136, PCI_CHIP_RS100_4136, RES_SHARED_VGA }, - { PCI_CHIP_RS100_4336, PCI_CHIP_RS100_4336, RES_SHARED_VGA }, { PCI_CHIP_RS200_4137, PCI_CHIP_RS200_4137, RES_SHARED_VGA }, - { PCI_CHIP_RS200_4337, PCI_CHIP_RS200_4337, RES_SHARED_VGA }, + { PCI_CHIP_R300_AD, PCI_CHIP_R300_AD, RES_SHARED_VGA }, + { PCI_CHIP_R300_AE, PCI_CHIP_R300_AE, RES_SHARED_VGA }, + { PCI_CHIP_R300_AF, PCI_CHIP_R300_AF, RES_SHARED_VGA }, + { PCI_CHIP_R300_AG, PCI_CHIP_R300_AG, RES_SHARED_VGA }, + { PCI_CHIP_R350_AH, PCI_CHIP_R350_AH, RES_SHARED_VGA }, + { PCI_CHIP_R350_AI, PCI_CHIP_R350_AI, RES_SHARED_VGA }, + { PCI_CHIP_R350_AJ, PCI_CHIP_R350_AJ, RES_SHARED_VGA }, + { PCI_CHIP_R350_AK, PCI_CHIP_R350_AK, RES_SHARED_VGA }, + { PCI_CHIP_RV350_AP, PCI_CHIP_RV350_AP, RES_SHARED_VGA }, + { PCI_CHIP_RV350_AQ, PCI_CHIP_RV350_AQ, RES_SHARED_VGA }, + { PCI_CHIP_RV360_AR, PCI_CHIP_RV360_AR, RES_SHARED_VGA }, + { PCI_CHIP_RV350_AS, PCI_CHIP_RV350_AS, RES_SHARED_VGA }, + { PCI_CHIP_RV350_AT, PCI_CHIP_RV350_AT, RES_SHARED_VGA }, + { PCI_CHIP_RV350_4155, PCI_CHIP_RV350_4155, RES_SHARED_VGA }, + { PCI_CHIP_RV350_AV, PCI_CHIP_RV350_AV, RES_SHARED_VGA }, + { PCI_CHIP_RV350_AW, PCI_CHIP_RV350_AW, RES_SHARED_VGA }, { PCI_CHIP_RS250_4237, PCI_CHIP_RS250_4237, RES_SHARED_VGA }, - { PCI_CHIP_RS250_4437, PCI_CHIP_RS250_4437, RES_SHARED_VGA }, - { PCI_CHIP_R200_QH, PCI_CHIP_R200_QH, RES_SHARED_VGA }, - { PCI_CHIP_R200_QL, PCI_CHIP_R200_QL, RES_SHARED_VGA }, - { PCI_CHIP_R200_QM, PCI_CHIP_R200_QM, RES_SHARED_VGA }, { PCI_CHIP_R200_BB, PCI_CHIP_R200_BB, RES_SHARED_VGA }, { PCI_CHIP_R200_BC, PCI_CHIP_R200_BC, RES_SHARED_VGA }, - { PCI_CHIP_RV200_QW, PCI_CHIP_RV200_QW, RES_SHARED_VGA }, - { PCI_CHIP_RV200_QX, PCI_CHIP_RV200_QX, RES_SHARED_VGA }, + { PCI_CHIP_RS100_4336, PCI_CHIP_RS100_4336, RES_SHARED_VGA }, + { PCI_CHIP_RS200_4337, PCI_CHIP_RS200_4337, RES_SHARED_VGA }, + { PCI_CHIP_RS250_4437, PCI_CHIP_RS250_4437, RES_SHARED_VGA }, + { PCI_CHIP_RV250_Id, PCI_CHIP_RV250_Id, RES_SHARED_VGA }, + { PCI_CHIP_RV250_Ie, PCI_CHIP_RV250_Ie, RES_SHARED_VGA }, { PCI_CHIP_RV250_If, PCI_CHIP_RV250_If, RES_SHARED_VGA }, { PCI_CHIP_RV250_Ig, PCI_CHIP_RV250_Ig, RES_SHARED_VGA }, + { PCI_CHIP_R420_JH, PCI_CHIP_R420_JH, RES_SHARED_VGA }, + { PCI_CHIP_R420_JI, PCI_CHIP_R420_JI, RES_SHARED_VGA }, + { PCI_CHIP_R420_JJ, PCI_CHIP_R420_JJ, RES_SHARED_VGA }, + { PCI_CHIP_R420_JK, PCI_CHIP_R420_JK, RES_SHARED_VGA }, + { PCI_CHIP_R420_JL, PCI_CHIP_R420_JL, RES_SHARED_VGA }, + { PCI_CHIP_R420_JM, PCI_CHIP_R420_JM, RES_SHARED_VGA }, + { PCI_CHIP_R420_JN, PCI_CHIP_R420_JN, RES_SHARED_VGA }, + { PCI_CHIP_R420_4A4F, PCI_CHIP_R420_4A4F, RES_SHARED_VGA }, + { PCI_CHIP_R420_JP, PCI_CHIP_R420_JP, RES_SHARED_VGA }, + { PCI_CHIP_R420_4A54, PCI_CHIP_R420_4A54, RES_SHARED_VGA }, + { PCI_CHIP_R481_4B49, PCI_CHIP_R481_4B49, RES_SHARED_VGA }, + { PCI_CHIP_R481_4B4A, PCI_CHIP_R481_4B4A, RES_SHARED_VGA }, + { PCI_CHIP_R481_4B4B, PCI_CHIP_R481_4B4B, RES_SHARED_VGA }, + { PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA }, + { PCI_CHIP_RADEON_LW, PCI_CHIP_RADEON_LW, RES_SHARED_VGA }, + { PCI_CHIP_RADEON_LX, PCI_CHIP_RADEON_LX, RES_SHARED_VGA }, + { PCI_CHIP_RADEON_LY, PCI_CHIP_RADEON_LY, RES_SHARED_VGA }, + { PCI_CHIP_RADEON_LZ, PCI_CHIP_RADEON_LZ, RES_SHARED_VGA }, { PCI_CHIP_RV250_Ld, PCI_CHIP_RV250_Ld, RES_SHARED_VGA }, + { PCI_CHIP_RV250_Le, PCI_CHIP_RV250_Le, RES_SHARED_VGA }, { PCI_CHIP_RV250_Lf, PCI_CHIP_RV250_Lf, RES_SHARED_VGA }, { PCI_CHIP_RV250_Lg, PCI_CHIP_RV250_Lg, RES_SHARED_VGA }, - { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA }, - { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5960, PCI_CHIP_RV280_5960, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5961, PCI_CHIP_RV280_5961, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5962, PCI_CHIP_RV280_5962, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5964, PCI_CHIP_RV280_5964, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5C63, PCI_CHIP_RV280_5C63, RES_SHARED_VGA }, - { PCI_CHIP_R300_AD, PCI_CHIP_R300_AD, RES_SHARED_VGA }, - { PCI_CHIP_R300_AE, PCI_CHIP_R300_AE, RES_SHARED_VGA }, - { PCI_CHIP_R300_AF, PCI_CHIP_R300_AF, RES_SHARED_VGA }, - { PCI_CHIP_R300_AG, PCI_CHIP_R300_AG, RES_SHARED_VGA }, { PCI_CHIP_R300_ND, PCI_CHIP_R300_ND, RES_SHARED_VGA }, { PCI_CHIP_R300_NE, PCI_CHIP_R300_NE, RES_SHARED_VGA }, { PCI_CHIP_R300_NF, PCI_CHIP_R300_NF, RES_SHARED_VGA }, { PCI_CHIP_R300_NG, PCI_CHIP_R300_NG, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AP, PCI_CHIP_RV350_AP, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AQ, PCI_CHIP_RV350_AQ, RES_SHARED_VGA }, - { PCI_CHIP_RV360_AR, PCI_CHIP_RV360_AR, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AS, PCI_CHIP_RV350_AS, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AT, PCI_CHIP_RV350_AT, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AV, PCI_CHIP_RV350_AV, RES_SHARED_VGA }, + { PCI_CHIP_R350_NH, PCI_CHIP_R350_NH, RES_SHARED_VGA }, + { PCI_CHIP_R350_NI, PCI_CHIP_R350_NI, RES_SHARED_VGA }, + { PCI_CHIP_R360_NJ, PCI_CHIP_R360_NJ, RES_SHARED_VGA }, + { PCI_CHIP_R350_NK, PCI_CHIP_R350_NK, RES_SHARED_VGA }, { PCI_CHIP_RV350_NP, PCI_CHIP_RV350_NP, RES_SHARED_VGA }, { PCI_CHIP_RV350_NQ, PCI_CHIP_RV350_NQ, RES_SHARED_VGA }, { PCI_CHIP_RV350_NR, PCI_CHIP_RV350_NR, RES_SHARED_VGA }, { PCI_CHIP_RV350_NS, PCI_CHIP_RV350_NS, RES_SHARED_VGA }, { PCI_CHIP_RV350_NT, PCI_CHIP_RV350_NT, RES_SHARED_VGA }, { PCI_CHIP_RV350_NV, PCI_CHIP_RV350_NV, RES_SHARED_VGA }, - { PCI_CHIP_R350_AH, PCI_CHIP_R350_AH, RES_SHARED_VGA }, - { PCI_CHIP_R350_AI, PCI_CHIP_R350_AI, RES_SHARED_VGA }, - { PCI_CHIP_R350_AJ, PCI_CHIP_R350_AJ, RES_SHARED_VGA }, - { PCI_CHIP_R350_AK, PCI_CHIP_R350_AK, RES_SHARED_VGA }, - { PCI_CHIP_R350_NH, PCI_CHIP_R350_NH, RES_SHARED_VGA }, - { PCI_CHIP_R350_NI, PCI_CHIP_R350_NI, RES_SHARED_VGA }, - { PCI_CHIP_R350_NK, PCI_CHIP_R350_NK, RES_SHARED_VGA }, - { PCI_CHIP_R360_NJ, PCI_CHIP_R360_NJ, RES_SHARED_VGA }, + { PCI_CHIP_RADEON_QD, PCI_CHIP_RADEON_QD, RES_SHARED_VGA }, + { PCI_CHIP_RADEON_QE, PCI_CHIP_RADEON_QE, RES_SHARED_VGA }, + { PCI_CHIP_RADEON_QF, PCI_CHIP_RADEON_QF, RES_SHARED_VGA }, + { PCI_CHIP_RADEON_QG, PCI_CHIP_RADEON_QG, RES_SHARED_VGA }, + { PCI_CHIP_R200_QH, PCI_CHIP_R200_QH, RES_SHARED_VGA }, + { PCI_CHIP_R200_QI, PCI_CHIP_R200_QI, RES_SHARED_VGA }, + { PCI_CHIP_R200_QJ, PCI_CHIP_R200_QJ, RES_SHARED_VGA }, + { PCI_CHIP_R200_QK, PCI_CHIP_R200_QK, RES_SHARED_VGA }, + { PCI_CHIP_R200_QL, PCI_CHIP_R200_QL, RES_SHARED_VGA }, + { PCI_CHIP_R200_QM, PCI_CHIP_R200_QM, RES_SHARED_VGA }, + { PCI_CHIP_R200_QN, PCI_CHIP_R200_QN, RES_SHARED_VGA }, + { PCI_CHIP_R200_QO, PCI_CHIP_R200_QO, RES_SHARED_VGA }, + { PCI_CHIP_RV200_QW, PCI_CHIP_RV200_QW, RES_SHARED_VGA }, + { PCI_CHIP_RV200_QX, PCI_CHIP_RV200_QX, RES_SHARED_VGA }, + { PCI_CHIP_RV100_QY, PCI_CHIP_RV100_QY, RES_SHARED_VGA }, + { PCI_CHIP_RV100_QZ, PCI_CHIP_RV100_QZ, RES_SHARED_VGA }, + { PCI_CHIP_R200_Qh, PCI_CHIP_R200_Qh, RES_SHARED_VGA }, + { PCI_CHIP_R200_Qi, PCI_CHIP_R200_Qi, RES_SHARED_VGA }, + { PCI_CHIP_R200_Qj, PCI_CHIP_R200_Qj, RES_SHARED_VGA }, + { PCI_CHIP_R200_Qk, PCI_CHIP_R200_Qk, RES_SHARED_VGA }, + { PCI_CHIP_R200_Ql, PCI_CHIP_R200_Ql, RES_SHARED_VGA }, + { PCI_CHIP_RN50_515E, PCI_CHIP_RN50_515E, RES_SHARED_VGA }, + { PCI_CHIP_RV370_5460, PCI_CHIP_RV370_5460, RES_SHARED_VGA }, + { PCI_CHIP_RV370_5462, PCI_CHIP_RV370_5462, RES_SHARED_VGA }, + { PCI_CHIP_RV370_5464, PCI_CHIP_RV370_5464, RES_SHARED_VGA }, + { PCI_CHIP_R423_UH, PCI_CHIP_R423_UH, RES_SHARED_VGA }, + { PCI_CHIP_R423_UI, PCI_CHIP_R423_UI, RES_SHARED_VGA }, + { PCI_CHIP_R423_UJ, PCI_CHIP_R423_UJ, RES_SHARED_VGA }, + { PCI_CHIP_R423_UK, PCI_CHIP_R423_UK, RES_SHARED_VGA }, + { PCI_CHIP_R430_554C, PCI_CHIP_R430_554C, RES_SHARED_VGA }, + { PCI_CHIP_R430_554D, PCI_CHIP_R430_554D, RES_SHARED_VGA }, + { PCI_CHIP_R430_554E, PCI_CHIP_R430_554E, RES_SHARED_VGA }, + { PCI_CHIP_R430_554F, PCI_CHIP_R430_554F, RES_SHARED_VGA }, + { PCI_CHIP_R423_5550, PCI_CHIP_R423_5550, RES_SHARED_VGA }, + { PCI_CHIP_R423_UQ, PCI_CHIP_R423_UQ, RES_SHARED_VGA }, + { PCI_CHIP_R423_UR, PCI_CHIP_R423_UR, RES_SHARED_VGA }, + { PCI_CHIP_R423_UT, PCI_CHIP_R423_UT, RES_SHARED_VGA }, + { PCI_CHIP_RV410_564A, PCI_CHIP_RV410_564A, RES_SHARED_VGA }, + { PCI_CHIP_RV410_564B, PCI_CHIP_RV410_564B, RES_SHARED_VGA }, + { PCI_CHIP_RV410_564F, PCI_CHIP_RV410_564F, RES_SHARED_VGA }, + { PCI_CHIP_RV410_5652, PCI_CHIP_RV410_5652, RES_SHARED_VGA }, + { PCI_CHIP_RV410_5653, PCI_CHIP_RV410_5653, RES_SHARED_VGA }, + { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA }, + { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA }, + { PCI_CHIP_RS480_5954, PCI_CHIP_RS480_5954, RES_SHARED_VGA }, + { PCI_CHIP_RS480_5955, PCI_CHIP_RS480_5955, RES_SHARED_VGA }, + { PCI_CHIP_RV280_5960, PCI_CHIP_RV280_5960, RES_SHARED_VGA }, + { PCI_CHIP_RV280_5961, PCI_CHIP_RV280_5961, RES_SHARED_VGA }, + { PCI_CHIP_RV280_5962, PCI_CHIP_RV280_5962, RES_SHARED_VGA }, + { PCI_CHIP_RV280_5964, PCI_CHIP_RV280_5964, RES_SHARED_VGA }, + { PCI_CHIP_RV280_5965, PCI_CHIP_RV280_5965, RES_SHARED_VGA }, + { PCI_CHIP_RN50_5969, PCI_CHIP_RN50_5969, RES_SHARED_VGA }, + { PCI_CHIP_RS482_5974, PCI_CHIP_RS482_5974, RES_SHARED_VGA }, + { PCI_CHIP_RS482_5975, PCI_CHIP_RS482_5975, RES_SHARED_VGA }, + { PCI_CHIP_RS400_5A41, PCI_CHIP_RS400_5A41, RES_SHARED_VGA }, + { PCI_CHIP_RS400_5A42, PCI_CHIP_RS400_5A42, RES_SHARED_VGA }, + { PCI_CHIP_RC410_5A61, PCI_CHIP_RC410_5A61, RES_SHARED_VGA }, + { PCI_CHIP_RC410_5A62, PCI_CHIP_RC410_5A62, RES_SHARED_VGA }, + { PCI_CHIP_RV370_5B60, PCI_CHIP_RV370_5B60, RES_SHARED_VGA }, + { PCI_CHIP_RV370_5B62, PCI_CHIP_RV370_5B62, RES_SHARED_VGA }, + { PCI_CHIP_RV370_5B63, PCI_CHIP_RV370_5B63, RES_SHARED_VGA }, + { PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA }, + { PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA }, + { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA }, + { PCI_CHIP_RV280_5C63, PCI_CHIP_RV280_5C63, RES_SHARED_VGA }, + { PCI_CHIP_R430_5D48, PCI_CHIP_R430_5D48, RES_SHARED_VGA }, + { PCI_CHIP_R430_5D49, PCI_CHIP_R430_5D49, RES_SHARED_VGA }, + { PCI_CHIP_R430_5D4A, PCI_CHIP_R430_5D4A, RES_SHARED_VGA }, + { PCI_CHIP_R480_5D4C, PCI_CHIP_R480_5D4C, RES_SHARED_VGA }, + { PCI_CHIP_R480_5D4D, PCI_CHIP_R480_5D4D, RES_SHARED_VGA }, + { PCI_CHIP_R480_5D4E, PCI_CHIP_R480_5D4E, RES_SHARED_VGA }, + { PCI_CHIP_R480_5D4F, PCI_CHIP_R480_5D4F, RES_SHARED_VGA }, + { PCI_CHIP_R480_5D50, PCI_CHIP_R480_5D50, RES_SHARED_VGA }, + { PCI_CHIP_R480_5D52, PCI_CHIP_R480_5D52, RES_SHARED_VGA }, + { PCI_CHIP_R423_5D57, PCI_CHIP_R423_5D57, RES_SHARED_VGA }, + { PCI_CHIP_RV410_5E48, PCI_CHIP_RV410_5E48, RES_SHARED_VGA }, + { PCI_CHIP_RV410_5E4A, PCI_CHIP_RV410_5E4A, RES_SHARED_VGA }, + { PCI_CHIP_RV410_5E4B, PCI_CHIP_RV410_5E4B, RES_SHARED_VGA }, + { PCI_CHIP_RV410_5E4C, PCI_CHIP_RV410_5E4C, RES_SHARED_VGA }, + { PCI_CHIP_RV410_5E4D, PCI_CHIP_RV410_5E4D, RES_SHARED_VGA }, + { PCI_CHIP_RV410_5E4F, PCI_CHIP_RV410_5E4F, RES_SHARED_VGA }, + { PCI_CHIP_RS350_7834, PCI_CHIP_RS350_7834, RES_SHARED_VGA }, + { PCI_CHIP_RS350_7835, PCI_CHIP_RS350_7835, RES_SHARED_VGA }, + { -1, -1, RES_UNDEFINED } }; @@ -300,10 +480,12 @@ foundScreen = TRUE; } else { for (i = 0; i < numUsed; i++) { - ScrnInfoPtr pScrn = NULL; - EntityInfoPtr pEnt; - pEnt = xf86GetEntityInfo(usedChips[i]); - if ((pScrn = xf86ConfigPciEntity(pScrn, 0, usedChips[i], + ScrnInfoPtr pScrn; + EntityInfoPtr pEnt; + DevUnion *pPriv; + RADEONEntPtr pRADEONEnt; + + if ((pScrn = xf86ConfigPciEntity(NULL, 0, usedChips[i], RADEONPciChipsets, 0, 0, 0, 0, 0))) { #ifdef XFree86LOADER @@ -338,38 +520,34 @@ pEnt = xf86GetEntityInfo(usedChips[i]); - /* create a RADEONEntity for all chips, even with - old single head Radeon, need to use pRADEONEnt - for new monitor detection routines - */ - { - DevUnion *pPriv; - RADEONEntPtr pRADEONEnt; - - xf86SetEntitySharable(usedChips[i]); - - if (gRADEONEntityIndex == -1) - gRADEONEntityIndex = xf86AllocateEntityPrivateIndex(); - - pPriv = xf86GetEntityPrivate(pEnt->index, - gRADEONEntityIndex); - - if (!pPriv->ptr) { - int j; - int instance = xf86GetNumEntityInstances(pEnt->index); - - for (j = 0; j < instance; j++) - xf86SetEntityInstanceForScreen(pScrn, pEnt->index, j); - - pPriv->ptr = xnfcalloc(sizeof(RADEONEntRec), 1); - pRADEONEnt = pPriv->ptr; - pRADEONEnt->HasSecondary = FALSE; - pRADEONEnt->IsSecondaryRestored = FALSE; - } else { - pRADEONEnt = pPriv->ptr; - pRADEONEnt->HasSecondary = TRUE; - } + /* + * Create a RADEONEntity for all chips, even with old single head + * Radeon, need to use pRADEONEnt for new monitor detection + * routines. + */ + xf86SetEntitySharable(usedChips[i]); + + if (gRADEONEntityIndex == -1) + gRADEONEntityIndex = xf86AllocateEntityPrivateIndex(); + + pPriv = xf86GetEntityPrivate(pEnt->index, gRADEONEntityIndex); + + if (!pPriv->ptr) { + int j; + int instance = xf86GetNumEntityInstances(pEnt->index); + + for (j = 0; j < instance; j++) + xf86SetEntityInstanceForScreen(pScrn, pEnt->index, j); + + pPriv->ptr = xnfcalloc(sizeof(RADEONEntRec), 1); + pRADEONEnt = pPriv->ptr; + pRADEONEnt->HasSecondary = FALSE; + pRADEONEnt->IsSecondaryRestored = FALSE; + } else { + pRADEONEnt = pPriv->ptr; + pRADEONEnt->HasSecondary = TRUE; } + xfree(pEnt); } } Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.h:1.19 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.h:1.21 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.h:1.19 Tue Jan 23 10:03:00 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.h Sun Apr 6 12:17:41 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.h,v 1.19 2007/01/23 18:03:00 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.h,v 1.21 2008/04/06 19:17:41 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -45,6 +45,76 @@ #define _XF86MISC_SERVER_ #include <X11/extensions/xf86misc.h> +typedef enum +{ + DDC_NONE_DETECTED, + DDC_MONID, + DDC_DVI, + DDC_VGA, + DDC_CRT2 +} RADEONDDCType; + +typedef enum +{ + MT_UNKNOWN = -1, + MT_NONE = 0, + MT_CRT = 1, + MT_LCD = 2, + MT_DFP = 3, + MT_CTV = 4, + MT_STV = 5 +} RADEONMonitorType; + +typedef enum +{ + CONNECTOR_NONE, + CONNECTOR_PROPRIETARY, + CONNECTOR_CRT, + CONNECTOR_DVI_I, + CONNECTOR_DVI_D, + CONNECTOR_CTV, + CONNECTOR_STV, + CONNECTOR_UNSUPPORTED +} RADEONConnectorType; + +typedef enum +{ + CONNECTOR_NONE_ATOM, + CONNECTOR_VGA_ATOM, + CONNECTOR_DVI_I_ATOM, + CONNECTOR_DVI_D_ATOM, + CONNECTOR_DVI_A_ATOM, + CONNECTOR_STV_ATOM, + CONNECTOR_CTV_ATOM, + CONNECTOR_LVDS_ATOM, + CONNECTOR_DIGITAL_ATOM, + CONNECTOR_UNSUPPORTED_ATOM +} RADEONConnectorTypeATOM; + +typedef enum +{ + DAC_UNKNOWN = -1, + DAC_PRIMARY = 0, + DAC_TVDAC = 1 +} RADEONDacType; + +typedef enum +{ + TMDS_UNKNOWN = -1, + TMDS_INT = 0, + TMDS_EXT = 1 +} RADEONTmdsType; + +typedef struct +{ + RADEONDDCType DDCType; + RADEONDacType DACType; + RADEONTmdsType TMDSType; + RADEONConnectorType ConnectorType; + RADEONMonitorType MonType; + xf86MonPtr MonInfo; +} RADEONConnector; + typedef struct { Bool HasSecondary; @@ -59,12 +129,13 @@ ScrnInfoPtr pSecondaryScrn; ScrnInfoPtr pPrimaryScrn; - int MonType1; - int MonType2; + RADEONMonitorType MonType1; + RADEONMonitorType MonType2; xf86MonPtr MonInfo1; xf86MonPtr MonInfo2; Bool ReversedDAC; /* TVDAC used as primary dac */ Bool ReversedTMDS; /* DDC_DVI is used for external TMDS */ + RADEONConnector PortInfo[2]; } RADEONEntRec, *RADEONEntPtr; /* radeon_probe.c */ Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h:1.33 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h:1.34 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h:1.33 Wed Mar 3 10:11:45 2004 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h Wed Apr 2 14:02:32 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.33 2004/03/03 18:11:45 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.34 2008/04/02 21:02:32 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -53,6 +53,22 @@ #ifndef _RADEON_REG_H_ #define _RADEON_REG_H_ +#define ATI_DATATYPE_VQ 0 +#define ATI_DATATYPE_CI4 1 +#define ATI_DATATYPE_CI8 2 +#define ATI_DATATYPE_ARGB1555 3 +#define ATI_DATATYPE_RGB565 4 +#define ATI_DATATYPE_RGB888 5 +#define ATI_DATATYPE_ARGB8888 6 +#define ATI_DATATYPE_RGB332 7 +#define ATI_DATATYPE_Y8 8 +#define ATI_DATATYPE_RGB8 9 +#define ATI_DATATYPE_CI16 10 +#define ATI_DATATYPE_VYUY_422 11 +#define ATI_DATATYPE_YVYU_422 12 +#define ATI_DATATYPE_AYUV_444 14 +#define ATI_DATATYPE_ARGB4444 15 + /* Registers for 2D/Video/Overlay */ #define RADEON_ADAPTER_ID 0x0f2c /* PCI */ #define RADEON_AGP_BASE 0x0170 @@ -65,6 +81,13 @@ # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) +#define RADEON_STATUS_PCI_CONFIG 0x06 +# define RADEON_CAP_LIST 0x100000 +#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ +# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ +# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ +# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ +# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */ #define RADEON_AGP_COMMAND 0x0f60 /* PCI */ #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ # define RADEON_AGP_ENABLE (1<<8) @@ -75,9 +98,9 @@ # define RADEON_AGP_4X_MODE 0x04 # define RADEON_AGP_FW_MODE 0x10 # define RADEON_AGP_MODE_MASK 0x17 -#define RADEON_ATTRDR 0x03c1 /* VGA */ -#define RADEON_ATTRDW 0x03c0 /* VGA */ -#define RADEON_ATTRX 0x03c0 /* VGA */ +# define RADEON_AGPv3_MODE 0x08 +# define RADEON_AGPv3_4X_MODE 0x01 +# define RADEON_AGPv3_8X_MODE 0x02 #define RADEON_AUX_SC_CNTL 0x1660 # define RADEON_AUX1_SC_EN (1 << 0) # define RADEON_AUX1_SC_MODE_OR (0 << 1) @@ -192,16 +215,23 @@ #define RADEON_CACHE_CNTL 0x1724 #define RADEON_CACHE_LINE 0x0f0c /* PCI */ -#define RADEON_CAP0_TRIG_CNTL 0x0950 /* ? */ -#define RADEON_CAP1_TRIG_CNTL 0x09c0 /* ? */ #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ #define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ #define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ +# define RADEON_SCLK_DYN_START_CNTL (1 << 15) #define RADEON_CLOCK_CNTL_DATA 0x000c #define RADEON_CLOCK_CNTL_INDEX 0x0008 # define RADEON_PLL_WR_EN (1 << 7) # define RADEON_PLL_DIV_SEL (3 << 8) # define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) +#define RADEON_CLK_PWRMGT_CNTL 0x0014 +# define RADEON_ENGIN_DYNCLK_MODE (1 << 12) +# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13) +# define RADEON_ACTIVE_HILO_LAT_SHIFT 13 +# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12) +# define RADEON_DYN_STOP_MODE_MASK (7 << 21) +#define RADEON_PLL_PWRMGT_CNTL 0x0015 +# define RADEON_TCL_BYPASS_DISABLE (1 << 20) #define RADEON_CLR_CMP_CLR_3D 0x1a24 #define RADEON_CLR_CMP_CLR_DST 0x15c8 #define RADEON_CLR_CMP_CLR_SRC 0x15c4 @@ -219,6 +249,8 @@ #define RADEON_CONFIG_APER_SIZE 0x0108 #define RADEON_CONFIG_BONDS 0x00e8 #define RADEON_CONFIG_CNTL 0x00e0 +# define RADEON_CFG_VGA_RAM_EN (1 << 8) +# define RADEON_CFG_VGA_IO_DIS (1 << 9) # define RADEON_CFG_ATI_REV_A11 (0 << 16) # define RADEON_CFG_ATI_REV_A12 (1 << 16) # define RADEON_CFG_ATI_REV_A13 (2 << 16) @@ -274,9 +306,9 @@ # define RADEON_CRTC_DBL_SCAN_EN (1 << 0) # define RADEON_CRTC_INTERLACE_EN (1 << 1) # define RADEON_CRTC_CSYNC_EN (1 << 4) +# define RADEON_CRTC_ICON_EN (1 << 15) # define RADEON_CRTC_CUR_EN (1 << 16) # define RADEON_CRTC_CUR_MODE_MASK (7 << 17) -# define RADEON_CRTC_ICON_EN (1 << 20) # define RADEON_CRTC_EXT_DISP_EN (1 << 24) # define RADEON_CRTC_EN (1 << 25) # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) @@ -297,8 +329,8 @@ # define RADEON_CRTC2_HSYNC_DIS (1 << 28) # define RADEON_CRTC2_VSYNC_DIS (1 << 29) #define RADEON_CRTC_MORE_CNTL 0x27c -# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) -# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) @@ -324,13 +356,49 @@ # define RADEON_CRTC2_H_TOTAL_SHIFT 0 # define RADEON_CRTC2_H_DISP (0x01ff << 16) # define RADEON_CRTC2_H_DISP_SHIFT 16 + +#define RADEON_CRTC_OFFSET_RIGHT 0x0220 #define RADEON_CRTC_OFFSET 0x0224 +# define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30) +# define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31) + #define RADEON_CRTC2_OFFSET 0x0324 +# define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30) +# define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31) #define RADEON_CRTC_OFFSET_CNTL 0x0228 -# define RADEON_CRTC_TILE_EN (1 << 15) +# define RADEON_CRTC_TILE_LINE_SHIFT 0 +# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4 +# define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) +# define R300_CRTC_X_Y_MODE_EN (1 << 9) +# define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) +# define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) +# define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) +# define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) +# define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) +# define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) +# define R300_CRTC_MICRO_TILE_EN (1 << 13) +# define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) +# define R300_CRTC_MACRO_TILE_EN (1 << 15) +# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14) +# define RADEON_CRTC_TILE_EN (1 << 15) +# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) +# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17) + +#define R300_CRTC_TILE_X0_Y0 0x0350 +#define R300_CRTC2_TILE_X0_Y0 0x0358 + #define RADEON_CRTC2_OFFSET_CNTL 0x0328 +# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16) # define RADEON_CRTC2_TILE_EN (1 << 15) #define RADEON_CRTC_PITCH 0x022c +# define RADEON_CRTC_PITCH__SHIFT 0 +# define RADEON_CRTC_PITCH__RIGHT_SHIFT 16 + #define RADEON_CRTC2_PITCH 0x032c #define RADEON_CRTC_STATUS 0x005c # define RADEON_CRTC_VBLANK_SAVE (1 << 1) @@ -366,8 +434,6 @@ #define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 #define RADEON_CRTC2_STATUS 0x03fc #define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 -#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ -#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ #define RADEON_CUR_CLR0 0x026c #define RADEON_CUR_CLR1 0x0270 #define RADEON_CUR_HORZ_VERT_OFF 0x0268 @@ -407,10 +473,10 @@ # define RADEON_DAC_PDWN_B (1 << 18) #define RADEON_TV_DAC_CNTL 0x088c # define RADEON_TV_DAC_STD_MASK 0x0300 +# define RADEON_TV_DAC_BGSLEEP (1 << 6) # define RADEON_TV_DAC_RDACPD (1 << 24) # define RADEON_TV_DAC_GDACPD (1 << 25) # define RADEON_TV_DAC_BDACPD (1 << 26) -# define RADEON_TV_DAC_BGSLEEP (1 << 26) #define RADEON_DISP_HW_DEBUG 0x0d14 # define RADEON_CRT2_DISP1_SEL (1 << 5) #define RADEON_DISP_OUTPUT_CNTL 0x0d64 @@ -419,10 +485,6 @@ # define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 # define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 #define RADEON_DAC_CRC_SIG 0x02cc -#define RADEON_DAC_DATA 0x03c9 /* VGA */ -#define RADEON_DAC_MASK 0x03c6 /* VGA */ -#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ -#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ #define RADEON_DDA_CONFIG 0x02e0 #define RADEON_DDA_ON_OFF 0x02e4 #define RADEON_DEFAULT_OFFSET 0x16e0 @@ -443,7 +505,7 @@ # define RADEON_DISP_RGB_OFFSET_EN (1<<8) # define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) # define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) -# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) +# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) #define RADEON_DISP2_MERGE_CNTL 0x0d68 # define RADEON_DISP2_RGB_OFFSET_EN (1<<8) #define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 @@ -457,6 +519,10 @@ #define RADEON_DP_CNTL 0x16c0 # define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) # define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) +# define RADEON_DP_DST_TILE_LINEAR (0 << 3) +# define RADEON_DP_DST_TILE_MACRO (1 << 3) +# define RADEON_DP_DST_TILE_MICRO (2 << 3) +# define RADEON_DP_DST_TILE_BOTH (3 << 3) #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 # define RADEON_DST_Y_MAJOR (1 << 2) # define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) @@ -623,10 +689,17 @@ # define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 #define RADEON_FP_GEN_CNTL 0x0284 # define RADEON_FP_FPON (1 << 0) +# define RADEON_FP_BLANK_EN (1 << 1) # define RADEON_FP_TMDS_EN (1 << 2) # define RADEON_FP_PANEL_FORMAT (1 << 3) # define RADEON_FP_EN_TMDS (1 << 7) # define RADEON_FP_DETECT_SENSE (1 << 8) +# define R200_FP_SOURCE_SEL_MASK (3 << 10) +# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) +# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) +# define R200_FP_SOURCE_SEL_RMX (2 << 10) +# define R200_FP_SOURCE_SEL_TRANS (3 << 10) +# define RADEON_FP_SEL_CRTC1 (0 << 13) # define RADEON_FP_SEL_CRTC2 (1 << 13) # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) @@ -642,8 +715,10 @@ # define RADEON_FP2_BLANK_EN (1 << 1) # define RADEON_FP2_ON (1 << 2) # define RADEON_FP2_PANEL_FORMAT (1 << 3) -# define RADEON_FP2_SOURCE_SEL_MASK (3 << 10) -# define RADEON_FP2_SOURCE_SEL_CRTC2 (1 << 10) +# define R200_FP2_SOURCE_SEL_MASK (3 << 10) +# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) +# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) +# define R200_FP2_SOURCE_SEL_RMX (2 << 10) # define RADEON_FP2_SRC_SEL_MASK (3 << 13) # define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) # define RADEON_FP2_FP_POL (1 << 16) @@ -653,8 +728,8 @@ # define RADEON_FP2_PAD_FLOP_EN (1 << 22) # define RADEON_FP2_CRC_EN (1 << 23) # define RADEON_FP2_CRC_READ_EN (1 << 24) -# define RADEON_FP2_DV0_EN (1 << 25) -# define RADEON_FP2_DV0_RATE_SEL_SDR (1 << 26) +# define RADEON_FP2_DVO_EN (1 << 25) +# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) #define RADEON_FP_H_SYNC_STRT_WID 0x02c4 #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 #define RADEON_FP_HORZ_STRETCH 0x028c @@ -690,13 +765,6 @@ # define RADEON_VSYNC_INT (1 << 2) # define RADEON_VSYNC2_INT_AK (1 << 6) # define RADEON_VSYNC2_INT (1 << 6) -#define RADEON_GENENB 0x03c3 /* VGA */ -#define RADEON_GENFC_RD 0x03ca /* VGA */ -#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ -#define RADEON_GENMO_RD 0x03cc /* VGA */ -#define RADEON_GENMO_WT 0x03c2 /* VGA */ -#define RADEON_GENS0 0x03c2 /* VGA */ -#define RADEON_GENS1 0x03da /* VGA, 0x03ba */ #define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ #define RADEON_GPIO_MONIDB 0x006c #define RADEON_GPIO_CRT2_DDC 0x006c @@ -712,8 +780,6 @@ # define RADEON_GPIO_EN_1 (1 << 17) # define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ # define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ -#define RADEON_GRPH8_DATA 0x03cf /* VGA */ -#define RADEON_GRPH8_IDX 0x03ce /* VGA */ #define RADEON_GUI_SCRATCH_REG0 0x15e0 #define RADEON_GUI_SCRATCH_REG1 0x15e4 #define RADEON_GUI_SCRATCH_REG2 0x15e8 @@ -733,11 +799,19 @@ #define RADEON_HOST_DATA_LAST 0x17e0 #define RADEON_HOST_PATH_CNTL 0x0130 # define RADEON_HDP_SOFT_RESET (1 << 26) +# define RADEON_HDP_APER_CNTL (1 << 23) #define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ #define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ -#define RADEON_I2C_CNTL_1 0x0094 /* ? */ + /* Multimedia I2C bus */ +#define RADEON_I2C_CNTL_0 0x0090 +#define RADEON_I2C_CNTL_1 0x0094 +#define RADEON_I2C_DATA 0x0098 + +#define RADEON_DVI_I2C_CNTL_0 0x02e0 #define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */ +#define RADEON_DVI_I2C_DATA 0x02e8 + #define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ #define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ #define RADEON_IO_BASE 0x0f14 /* PCI */ @@ -762,10 +836,14 @@ #define RADEON_MAX_LATENCY 0x0f3f /* PCI */ #define RADEON_MC_AGP_LOCATION 0x014c #define RADEON_MC_FB_LOCATION 0x0148 +#define RADEON_MC_STATUS 0x0150 +# define RADEON_MC_IDLE (1 << 2) +# define R300_MC_IDLE (1 << 4) #define RADEON_DISPLAY_BASE_ADDR 0x23c #define RADEON_DISPLAY2_BASE_ADDR 0x33c #define RADEON_OV0_BASE_ADDR 0x43c #define RADEON_NB_TOM 0x15c +#define R300_MC_INIT_MISC_LAT_TIMER 0x180 #define RADEON_MCLK_CNTL 0x0012 /* PLL */ # define RADEON_FORCEON_MCLKA (1 << 16) # define RADEON_FORCEON_MCLKB (1 << 17) @@ -773,6 +851,13 @@ # define RADEON_FORCEON_YCLKB (1 << 19) # define RADEON_FORCEON_MC (1 << 20) # define RADEON_FORCEON_AIC (1 << 21) +# define R300_DISABLE_MC_MCLKA (1 << 21) +# define R300_DISABLE_MC_MCLKB (1 << 21) +#define RADEON_MCLK_MISC 0x001f /* PLL */ +# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1<<12) +# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1<<13) +# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) +# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) #define RADEON_MDGPIO_A_REG 0x01ac #define RADEON_MDGPIO_EN_REG 0x01b0 #define RADEON_MDGPIO_MASK 0x0198 @@ -809,22 +894,42 @@ #define RADEON_N_VIF_COUNT 0x0248 #define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 +# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 +# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 +# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 +# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 +# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 +# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 +# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 +# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 +# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 +# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 + #define RADEON_OV0_COLOUR_CNTL 0x04E0 #define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 #define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 -# define RADEON_EXCL_HORZ_START_MASK 0x000000ff -# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 -# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 -# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +# define RADEON_EXCL_HORZ_START_MASK 0x000000ff +# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 +# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 #define RADEON_OV0_EXCLUSIVE_VERT 0x040C -# define RADEON_EXCL_VERT_START_MASK 0x000003ff -# define RADEON_EXCL_VERT_END_MASK 0x03ff0000 +# define RADEON_EXCL_VERT_START_MASK 0x000003ff +# define RADEON_EXCL_VERT_END_MASK 0x03ff0000 #define RADEON_OV0_FILTER_CNTL 0x04A0 +# define RADEON_FILTER_PROGRAMMABLE_COEF 0x0 +# define RADEON_FILTER_HC_COEF_HORZ_Y 0x1 +# define RADEON_FILTER_HC_COEF_HORZ_UV 0x2 +# define RADEON_FILTER_HC_COEF_VERT_Y 0x4 +# define RADEON_FILTER_HC_COEF_VERT_UV 0x8 +# define RADEON_FILTER_HARDCODED_COEF 0xf +# define RADEON_FILTER_COEF_MASK 0xf + #define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 #define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 #define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 #define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC #define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 +#define RADEON_OV0_FLAG_CNTL 0x04DC #define RADEON_OV0_GAMMA_000_00F 0x0d40 #define RADEON_OV0_GAMMA_010_01F 0x0d44 #define RADEON_OV0_GAMMA_020_03F 0x0d48 @@ -847,19 +952,19 @@ #define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 #define RADEON_OV0_H_INC 0x0480 #define RADEON_OV0_KEY_CNTL 0x04F4 -# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L -# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L -# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L -# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L -# define RADEON_VIDEO_KEY_FN_NE 0x00000003L -# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L -# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L -# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L -# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L -# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L -# define RADEON_CMP_MIX_MASK 0x00000100L -# define RADEON_CMP_MIX_OR 0x00000000L -# define RADEON_CMP_MIX_AND 0x00000100L +# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L +# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L +# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L +# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L +# define RADEON_VIDEO_KEY_FN_NE 0x00000003L +# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L +# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L +# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L +# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L +# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L +# define RADEON_CMP_MIX_MASK 0x00000100L +# define RADEON_CMP_MIX_OR 0x00000000L +# define RADEON_CMP_MIX_AND 0x00000100L #define RADEON_OV0_LIN_TRANS_A 0x0d20 #define RADEON_OV0_LIN_TRANS_B 0x0d24 #define RADEON_OV0_LIN_TRANS_C 0x0d28 @@ -867,73 +972,74 @@ #define RADEON_OV0_LIN_TRANS_E 0x0d30 #define RADEON_OV0_LIN_TRANS_F 0x0d34 #define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 -# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL -# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L +# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L #define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 #define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 -# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L -# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L #define RADEON_OV0_P1_X_START_END 0x0494 #define RADEON_OV0_P2_X_START_END 0x0498 #define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 -# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL -# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L +# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L #define RADEON_OV0_P23_H_ACCUM_INIT 0x048C #define RADEON_OV0_P23_V_ACCUM_INIT 0x042C #define RADEON_OV0_P3_X_START_END 0x049C #define RADEON_OV0_REG_LOAD_CNTL 0x0410 -# define RADEON_REG_LD_CTL_LOCK 0x00000001L -# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L -# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L -# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L +# define RADEON_REG_LD_CTL_LOCK 0x00000001L +# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L #define RADEON_OV0_SCALE_CNTL 0x0420 -# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L -# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L -# define RADEON_SCALER_SIGNED_UV 0x00000010L -# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L -# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L -# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L -# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L -# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L -# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L -# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L -# define RADEON_SCALER_SOURCE_15BPP 0x00000300L -# define RADEON_SCALER_SOURCE_16BPP 0x00000400L -# define RADEON_SCALER_SOURCE_32BPP 0x00000600L -# define RADEON_SCALER_SOURCE_YUV9 0x00000900L -# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L -# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L -# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L -# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L -# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L -# define RADEON_SCALER_SMART_SWITCH 0x00008000L -# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L -# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L -# define RADEON_SCALER_DIS_LIMIT 0x08000000L -# define RADEON_SCALER_INT_EMU 0x20000000L -# define RADEON_SCALER_ENABLE 0x40000000L -# define RADEON_SCALER_SOFT_RESET 0x80000000L -# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L +# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L +# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L +# define RADEON_SCALER_SIGNED_UV 0x00000010L +# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L +# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L +# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L +# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L +# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L +# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L +# define RADEON_SCALER_SOURCE_15BPP 0x00000300L +# define RADEON_SCALER_SOURCE_16BPP 0x00000400L +# define RADEON_SCALER_SOURCE_32BPP 0x00000600L +# define RADEON_SCALER_SOURCE_YUV9 0x00000900L +# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L +# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L +# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L +# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L +# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L +# define RADEON_SCALER_CRTC_SEL 0x00004000L +# define RADEON_SCALER_SMART_SWITCH 0x00008000L +# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L +# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L +# define RADEON_SCALER_DIS_LIMIT 0x08000000L +# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L +# define RADEON_SCALER_INT_EMU 0x20000000L +# define RADEON_SCALER_ENABLE 0x40000000L +# define RADEON_SCALER_SOFT_RESET 0x80000000L #define RADEON_OV0_STEP_BY 0x0484 #define RADEON_OV0_TEST 0x04F8 #define RADEON_OV0_V_INC 0x0424 #define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 #define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 #define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 -# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L -# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L -# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L -# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L #define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 -# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L -# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L -# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L -# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L #define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 -# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L -# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L -# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L -# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L #define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C #define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 #define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 @@ -947,6 +1053,106 @@ #define RADEON_OVR_WID_LEFT_RIGHT 0x0234 #define RADEON_OVR_WID_TOP_BOTTOM 0x0238 +/* first capture unit */ + +#define RADEON_CAP0_BUF0_OFFSET 0x0920 +#define RADEON_CAP0_BUF1_OFFSET 0x0924 +#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928 +#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C + +#define RADEON_CAP0_BUF_PITCH 0x0930 +#define RADEON_CAP0_V_WINDOW 0x0934 +#define RADEON_CAP0_H_WINDOW 0x0938 +#define RADEON_CAP0_VBI0_OFFSET 0x093C +#define RADEON_CAP0_VBI1_OFFSET 0x0940 +#define RADEON_CAP0_VBI_V_WINDOW 0x0944 +#define RADEON_CAP0_VBI_H_WINDOW 0x0948 +#define RADEON_CAP0_PORT_MODE_CNTL 0x094C +#define RADEON_CAP0_TRIG_CNTL 0x0950 +#define RADEON_CAP0_DEBUG 0x0954 +#define RADEON_CAP0_CONFIG 0x0958 +# define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001 +# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002 +# define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004 +# define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008 +# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 +# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 +# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 +# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 +# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 +# define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200 +# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 +# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 +# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000 +# define RADEON_CAP0_CONFIG_VBI_EN 0x00002000 +# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 +# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 +# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 +# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 +# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 +# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 +# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 +# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 +# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 +# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 +# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000 +# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000 +# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000 +# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 +# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 +# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 +# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 +# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 +# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 +#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C +#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960 +#define RADEON_CAP0_ANC_H_WINDOW 0x0964 +#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968 +#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C +#define RADEON_CAP0_BUF_STATUS 0x0970 +/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */ +/* #define RADEON_CAP0_XSHARPNESS 0x097C */ +#define RADEON_CAP0_VBI2_OFFSET 0x0980 +#define RADEON_CAP0_VBI3_OFFSET 0x0984 +#define RADEON_CAP0_ANC2_OFFSET 0x0988 +#define RADEON_CAP0_ANC3_OFFSET 0x098C +#define RADEON_VID_BUFFER_CONTROL 0x0900 + +/* second capture unit */ + +#define RADEON_CAP1_BUF0_OFFSET 0x0990 +#define RADEON_CAP1_BUF1_OFFSET 0x0994 +#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998 +#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C + +#define RADEON_CAP1_BUF_PITCH 0x09A0 +#define RADEON_CAP1_V_WINDOW 0x09A4 +#define RADEON_CAP1_H_WINDOW 0x09A8 +#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC +#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0 +#define RADEON_CAP1_VBI_V_WINDOW 0x09B4 +#define RADEON_CAP1_VBI_H_WINDOW 0x09B8 +#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC +#define RADEON_CAP1_TRIG_CNTL 0x09C0 +#define RADEON_CAP1_DEBUG 0x09C4 +#define RADEON_CAP1_CONFIG 0x09C8 +#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC +#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0 +#define RADEON_CAP1_ANC_H_WINDOW 0x09D4 +#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8 +#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC +#define RADEON_CAP1_BUF_STATUS 0x09E0 +#define RADEON_CAP1_DWNSC_XRATIO 0x09E8 +#define RADEON_CAP1_XSHARPNESS 0x09EC + +/* misc multimedia registers */ + +#define RADEON_IDCT_RUNS 0x1F80 +#define RADEON_IDCT_LEVELS 0x1F84 +#define RADEON_IDCT_CONTROL 0x1FBC +#define RADEON_IDCT_AUTH_CONTROL 0x1F88 +#define RADEON_IDCT_AUTH 0x1F8C + #define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ # define RADEON_P2PLL_RESET (1 << 0) # define RADEON_P2PLL_SLEEP (1 << 1) @@ -975,8 +1181,19 @@ # define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) # define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) # define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) +# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) +# define R300_DVOCLK_ALWAYS_ONb (1 << 10) +# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11) +# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12) +# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) +# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) # define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) # define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) +# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) +# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) +# define R300_P2G2CLK_ALWAYS_ONb (1 << 18) +# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) +# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) #define RADEON_PLANE_3D_MASK_C 0x1d44 #define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ #define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ @@ -1026,6 +1243,28 @@ # define RADEON_RB2D_DC_FLUSH_ALL 0xf # define RADEON_RB2D_DC_BUSY (1 << 31) #define RADEON_RB2D_DSTCACHE_MODE 0x3428 + +#define RADEON_RB3D_DSTCACHE_MODE 0x3258 +# define RADEON_RB3D_DC_CACHE_ENABLE (0) +# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1) +# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2) +# define RADEON_RB3D_DC_CACHE_DISABLE (3) +# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) +# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) +# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) +# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) +# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) +# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) +# define RADEON_RB3D_DC_FORCE_RMW (1 << 16) +# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24) +# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25) + +#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C +# define RADEON_RB3D_DC_FLUSH (3 << 0) +# define RADEON_RB3D_DC_FREE (3 << 2) +# define RADEON_RB3D_DC_FLUSH_ALL 0xf +# define RADEON_RB3D_DC_BUSY (1 << 31) + #define RADEON_REG_BASE 0x0f18 /* PCI */ #define RADEON_REGPROG_INF 0x0f09 /* PCI */ #define RADEON_REVISION_ID 0x0f08 /* PCI */ @@ -1041,14 +1280,44 @@ # define RADEON_SC_SIGN_MASK_LO 0x8000 # define RADEON_SC_SIGN_MASK_HI 0x80000000 #define RADEON_SCLK_CNTL 0x000d /* PLL */ +# define RADEON_SCLK_SRC_SEL_MASK 0x0007 # define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 # define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 # define RADEON_SCLK_FORCEON_MASK 0xffff8000 +# define RADEON_SCLK_FORCE_DISP2 (1<<15) +# define RADEON_SCLK_FORCE_CP (1<<16) +# define RADEON_SCLK_FORCE_HDP (1<<17) +# define RADEON_SCLK_FORCE_DISP1 (1<<18) +# define RADEON_SCLK_FORCE_TOP (1<<19) +# define RADEON_SCLK_FORCE_E2 (1<<20) +# define RADEON_SCLK_FORCE_SE (1<<21) +# define RADEON_SCLK_FORCE_IDCT (1<<22) +# define RADEON_SCLK_FORCE_VIP (1<<23) +# define RADEON_SCLK_FORCE_RE (1<<24) +# define RADEON_SCLK_FORCE_PB (1<<25) +# define RADEON_SCLK_FORCE_TAM (1<<26) +# define RADEON_SCLK_FORCE_TDM (1<<27) +# define RADEON_SCLK_FORCE_RB (1<<28) +# define RADEON_SCLK_FORCE_TV_SCLK (1<<29) +# define RADEON_SCLK_FORCE_SUBPIC (1<<30) +# define RADEON_SCLK_FORCE_OV0 (1<<31) +# define R300_SCLK_FORCE_VAP (1<<21) +# define R300_SCLK_FORCE_SR (1<<25) +# define R300_SCLK_FORCE_PX (1<<26) +# define R300_SCLK_FORCE_TX (1<<27) +# define R300_SCLK_FORCE_US (1<<28) +# define R300_SCLK_FORCE_SU (1<<30) +#define R300_SCLK_CNTL2 0x1e /* PLL */ +# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) +# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) +# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) +# define R300_SCLK_FORCE_TCL (1<<13) +# define R300_SCLK_FORCE_CBA (1<<14) +# define R300_SCLK_FORCE_GA (1<<15) #define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ +# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 # define RADEON_SCLK_MORE_FORCEON 0x0700 #define RADEON_SDRAM_MODE_REG 0x0158 -#define RADEON_SEQ8_DATA 0x03c5 /* VGA */ -#define RADEON_SEQ8_IDX 0x03c4 /* VGA */ #define RADEON_SNAPSHOT_F_COUNT 0x0244 #define RADEON_SNAPSHOT_VH_COUNTS 0x0240 #define RADEON_SNAPSHOT_VIF_COUNT 0x024c @@ -1072,6 +1341,23 @@ # define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22) # define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23) #define RADEON_SURFACE0_INFO 0x0b0c +# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) +# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) +# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) +# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) +# define R200_SURF_TILE_NONE (0 << 16) +# define R200_SURF_TILE_COLOR_MACRO (1 << 16) +# define R200_SURF_TILE_COLOR_MICRO (2 << 16) +# define R200_SURF_TILE_COLOR_BOTH (3 << 16) +# define R200_SURF_TILE_DEPTH_32BPP (4 << 16) +# define R200_SURF_TILE_DEPTH_16BPP (5 << 16) +# define R300_SURF_TILE_NONE (0 << 16) +# define R300_SURF_TILE_COLOR_MACRO (1 << 16) +# define R300_SURF_TILE_DEPTH_32BPP (2 << 16) +# define RADEON_SURF_AP0_SWP_16BPP (1 << 20) +# define RADEON_SURF_AP0_SWP_32BPP (1 << 21) +# define RADEON_SURF_AP1_SWP_16BPP (1 << 22) +# define RADEON_SURF_AP1_SWP_32BPP (1 << 23) #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 #define RADEON_SURFACE1_INFO 0x0b1c @@ -1098,6 +1384,8 @@ #define RADEON_SW_SEMAPHORE 0x013c #define RADEON_TEST_DEBUG_CNTL 0x0120 +#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 + #define RADEON_TEST_DEBUG_MUX 0x0124 #define RADEON_TEST_DEBUG_OUT 0x012c #define RADEON_TMDS_PLL_CNTL 0x02a8 @@ -1118,13 +1406,43 @@ # define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 # define RADEON_PIXCLK_ALWAYS_ONb (1<<6) # define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) +# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) #define RADEON_VENDOR_ID 0x0f00 /* PCI */ #define RADEON_VGA_DDA_CONFIG 0x02e8 #define RADEON_VGA_DDA_ON_OFF 0x02ec #define RADEON_VID_BUFFER_CONTROL 0x0900 #define RADEON_VIDEOMUX_CNTL 0x0190 -#define RADEON_VIPH_CONTROL 0x0c40 /* ? */ + + /* VIP bus */ +#define RADEON_VIPH_CH0_DATA 0x0c00 +#define RADEON_VIPH_CH1_DATA 0x0c04 +#define RADEON_VIPH_CH2_DATA 0x0c08 +#define RADEON_VIPH_CH3_DATA 0x0c0c +#define RADEON_VIPH_CH0_ADDR 0x0c10 +#define RADEON_VIPH_CH1_ADDR 0x0c14 +#define RADEON_VIPH_CH2_ADDR 0x0c18 +#define RADEON_VIPH_CH3_ADDR 0x0c1c +#define RADEON_VIPH_CH0_SBCNT 0x0c20 +#define RADEON_VIPH_CH1_SBCNT 0x0c24 +#define RADEON_VIPH_CH2_SBCNT 0x0c28 +#define RADEON_VIPH_CH3_SBCNT 0x0c2c +#define RADEON_VIPH_CH0_ABCNT 0x0c30 +#define RADEON_VIPH_CH1_ABCNT 0x0c34 +#define RADEON_VIPH_CH2_ABCNT 0x0c38 +#define RADEON_VIPH_CH3_ABCNT 0x0c3c +#define RADEON_VIPH_CONTROL 0x0c40 +#define RADEON_VIPH_DV_LAT 0x0c44 +#define RADEON_VIPH_BM_CHUNK 0x0c48 +#define RADEON_VIPH_DV_INT 0x0c4c +#define RADEON_VIPH_TIMEOUT_STAT 0x0c50 +#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 +#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 +#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 + +#define RADEON_VIPH_REG_DATA 0x0084 +#define RADEON_VIPH_REG_ADDR 0x0080 + #define RADEON_WAIT_UNTIL 0x1720 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) @@ -1712,6 +2030,18 @@ # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) # define RADEON_ROUND_PREC_4TH_PIX (2 << 30) # define RADEON_ROUND_PREC_HALF_PIX (3 << 30) +#define R200_RE_CNTL 0x1c50 +# define R200_STIPPLE_ENABLE 0x1 +# define R200_SCISSOR_ENABLE 0x2 +# define R200_PATTERN_ENABLE 0x4 +# define R200_PERSPECTIVE_ENABLE 0x8 +# define R200_POINT_SMOOTH 0x20 +# define R200_VTX_STQ0_D3D 0x00010000 +# define R200_VTX_STQ1_D3D 0x00040000 +# define R200_VTX_STQ2_D3D 0x00100000 +# define R200_VTX_STQ3_D3D 0x00400000 +# define R200_VTX_STQ4_D3D 0x01000000 +# define R200_VTX_STQ5_D3D 0x04000000 #define RADEON_SE_CNTL_STATUS 0x2140 # define RADEON_VC_NO_SWAP (0 << 0) # define RADEON_VC_16BIT_SWAP (1 << 0) @@ -1931,7 +2261,566 @@ #define RADEON_SE_ZBIAS_FACTOR 0x1db0 #define RADEON_SE_ZBIAS_CONSTANT 0x1db4 - +#define RADEON_SE_VTX_FMT 0x2080 +# define RADEON_SE_VTX_FMT_XY 0x00000000 +# define RADEON_SE_VTX_FMT_W0 0x00000001 +# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 +# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 +# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 +# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 +# define RADEON_SE_VTX_FMT_FPFOG 0x00000020 +# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 +# define RADEON_SE_VTX_FMT_ST0 0x00000080 +# define RADEON_SE_VTX_FMT_ST1 0x00000100 +# define RADEON_SE_VTX_FMT_Q1 0x00000200 +# define RADEON_SE_VTX_FMT_ST2 0x00000400 +# define RADEON_SE_VTX_FMT_Q2 0x00000800 +# define RADEON_SE_VTX_FMT_ST3 0x00001000 +# define RADEON_SE_VTX_FMT_Q3 0x00002000 +# define RADEON_SE_VTX_FMT_Q0 0x00004000 +# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 +# define RADEON_SE_VTX_FMT_N0 0x00040000 +# define RADEON_SE_VTX_FMT_XY1 0x08000000 +# define RADEON_SE_VTX_FMT_Z1 0x10000000 +# define RADEON_SE_VTX_FMT_W1 0x20000000 +# define RADEON_SE_VTX_FMT_N1 0x40000000 +# define RADEON_SE_VTX_FMT_Z 0x80000000 + +#define RADEON_SE_VF_CNTL 0x2084 +# define RADEON_VF_PRIM_TYPE_POINT_LIST 1 +# define RADEON_VF_PRIM_TYPE_LINE_LIST 2 +# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7 +# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8 +# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9 +# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10 +# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11 +# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12 +# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13 +# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14 +# define RADEON_VF_PRIM_TYPE_POLYGON 15 +# define RADEON_VF_PRIM_WALK_STATE (0<<4) +# define RADEON_VF_PRIM_WALK_INDEX (1<<4) +# define RADEON_VF_PRIM_WALK_LIST (2<<4) +# define RADEON_VF_PRIM_WALK_DATA (3<<4) +# define RADEON_VF_COLOR_ORDER_RGBA (1<<6) +# define RADEON_VF_RADEON_MODE (1<<8) +# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9) +# define RADEON_VF_PROG_STREAM_ENA (1<<10) +# define RADEON_VF_INDEX_SIZE_SHIFT 11 +# define RADEON_VF_NUM_VERTICES_SHIFT 16 + +#define RADEON_SE_PORT_DATA0 0x2000 + +#define R200_SE_VAP_CNTL 0x2080 +# define R200_VAP_TCL_ENABLE 0x00000001 +# define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 +# define R200_VAP_FORCE_W_TO_ONE 0x00010000 +# define R200_VAP_D3D_TEX_DEFAULT 0x00020000 +# define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 +# define R200_VAP_VF_MAX_VTX_NUM (9 << 18) +# define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 +#define R200_VF_MAX_VTX_INDX 0x210c +#define R200_VF_MIN_VTX_INDX 0x2110 +#define R200_SE_VTE_CNTL 0x20b0 +# define R200_VPORT_X_SCALE_ENA 0x00000001 +# define R200_VPORT_X_OFFSET_ENA 0x00000002 +# define R200_VPORT_Y_SCALE_ENA 0x00000004 +# define R200_VPORT_Y_OFFSET_ENA 0x00000008 +# define R200_VPORT_Z_SCALE_ENA 0x00000010 +# define R200_VPORT_Z_OFFSET_ENA 0x00000020 +# define R200_VTX_XY_FMT 0x00000100 +# define R200_VTX_Z_FMT 0x00000200 +# define R200_VTX_W0_FMT 0x00000400 +# define R200_VTX_W0_NORMALIZE 0x00000800 +# define R200_VTX_ST_DENORMALIZED 0x00001000 +#define R200_SE_VAP_CNTL_STATUS 0x2140 +# define R200_VC_NO_SWAP (0 << 0) +# define R200_VC_16BIT_SWAP (1 << 0) +# define R200_VC_32BIT_SWAP (2 << 0) +#define R200_PP_TXFILTER_0 0x2c00 +#define R200_PP_TXFILTER_1 0x2c20 +#define R200_PP_TXFILTER_2 0x2c40 +#define R200_PP_TXFILTER_3 0x2c60 +#define R200_PP_TXFILTER_4 0x2c80 +#define R200_PP_TXFILTER_5 0x2ca0 +# define R200_MAG_FILTER_NEAREST (0 << 0) +# define R200_MAG_FILTER_LINEAR (1 << 0) +# define R200_MAG_FILTER_MASK (1 << 0) +# define R200_MIN_FILTER_NEAREST (0 << 1) +# define R200_MIN_FILTER_LINEAR (1 << 1) +# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) +# define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +# define R200_MIN_FILTER_MASK (15 << 1) +# define R200_MAX_ANISO_1_TO_1 (0 << 5) +# define R200_MAX_ANISO_2_TO_1 (1 << 5) +# define R200_MAX_ANISO_4_TO_1 (2 << 5) +# define R200_MAX_ANISO_8_TO_1 (3 << 5) +# define R200_MAX_ANISO_16_TO_1 (4 << 5) +# define R200_MAX_ANISO_MASK (7 << 5) +# define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) +# define R200_MAX_MIP_LEVEL_SHIFT 16 +# define R200_YUV_TO_RGB (1 << 20) +# define R200_YUV_TEMPERATURE_COOL (0 << 21) +# define R200_YUV_TEMPERATURE_HOT (1 << 21) +# define R200_YUV_TEMPERATURE_MASK (1 << 21) +# define R200_WRAPEN_S (1 << 22) +# define R200_CLAMP_S_WRAP (0 << 23) +# define R200_CLAMP_S_MIRROR (1 << 23) +# define R200_CLAMP_S_CLAMP_LAST (2 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +# define R200_CLAMP_S_CLAMP_BORDER (4 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +# define R200_CLAMP_S_CLAMP_GL (6 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +# define R200_CLAMP_S_MASK (7 << 23) +# define R200_WRAPEN_T (1 << 26) +# define R200_CLAMP_T_WRAP (0 << 27) +# define R200_CLAMP_T_MIRROR (1 << 27) +# define R200_CLAMP_T_CLAMP_LAST (2 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +# define R200_CLAMP_T_CLAMP_BORDER (4 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +# define R200_CLAMP_T_CLAMP_GL (6 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +# define R200_CLAMP_T_MASK (7 << 27) +# define R200_KILL_LT_ZERO (1 << 30) +# define R200_BORDER_MODE_OGL (0 << 31) +# define R200_BORDER_MODE_D3D (1 << 31) +#define R200_PP_TXFORMAT_0 0x2c04 +#define R200_PP_TXFORMAT_1 0x2c24 +#define R200_PP_TXFORMAT_2 0x2c44 +#define R200_PP_TXFORMAT_3 0x2c64 +#define R200_PP_TXFORMAT_4 0x2c84 +#define R200_PP_TXFORMAT_5 0x2ca4 +# define R200_TXFORMAT_I8 (0 << 0) +# define R200_TXFORMAT_AI88 (1 << 0) +# define R200_TXFORMAT_RGB332 (2 << 0) +# define R200_TXFORMAT_ARGB1555 (3 << 0) +# define R200_TXFORMAT_RGB565 (4 << 0) +# define R200_TXFORMAT_ARGB4444 (5 << 0) +# define R200_TXFORMAT_ARGB8888 (6 << 0) +# define R200_TXFORMAT_RGBA8888 (7 << 0) +# define R200_TXFORMAT_Y8 (8 << 0) +# define R200_TXFORMAT_AVYU4444 (9 << 0) +# define R200_TXFORMAT_VYUY422 (10 << 0) +# define R200_TXFORMAT_YVYU422 (11 << 0) +# define R200_TXFORMAT_DXT1 (12 << 0) +# define R200_TXFORMAT_DXT23 (14 << 0) +# define R200_TXFORMAT_DXT45 (15 << 0) +# define R200_TXFORMAT_ABGR8888 (22 << 0) +# define R200_TXFORMAT_FORMAT_MASK (31 << 0) +# define R200_TXFORMAT_FORMAT_SHIFT 0 +# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) +# define R200_TXFORMAT_NON_POWER2 (1 << 7) +# define R200_TXFORMAT_WIDTH_MASK (15 << 8) +# define R200_TXFORMAT_WIDTH_SHIFT 8 +# define R200_TXFORMAT_HEIGHT_MASK (15 << 12) +# define R200_TXFORMAT_HEIGHT_SHIFT 12 +# define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ +# define R200_TXFORMAT_F5_WIDTH_SHIFT 16 +# define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) +# define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 +# define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) +# define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) +# define R200_TXFORMAT_ST_ROUTE_SHIFT 24 +# define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +# define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +# define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +#define R200_PP_TXFORMAT_X_0 0x2c08 +#define R200_PP_TXFORMAT_X_1 0x2c28 +#define R200_PP_TXFORMAT_X_2 0x2c48 +#define R200_PP_TXFORMAT_X_3 0x2c68 +#define R200_PP_TXFORMAT_X_4 0x2c88 +#define R200_PP_TXFORMAT_X_5 0x2ca8 + +#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ +#define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */ +#define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */ +#define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */ +#define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */ +#define R200_PP_TXSIZE_5 0x2cac /* NPOT only */ + +#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ +#define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */ +#define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */ +#define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */ +#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ +#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ + +#define R200_PP_TXOFFSET_0 0x2d00 +# define R200_TXO_ENDIAN_NO_SWAP (0 << 0) +# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) +# define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) +# define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) +# define R200_TXO_MACRO_LINEAR (0 << 2) +# define R200_TXO_MACRO_TILE (1 << 2) +# define R200_TXO_MICRO_LINEAR (0 << 3) +# define R200_TXO_MICRO_TILE (1 << 3) +# define R200_TXO_OFFSET_MASK 0xffffffe0 +# define R200_TXO_OFFSET_SHIFT 5 +#define R200_PP_TXOFFSET_1 0x2d18 +#define R200_PP_TXOFFSET_2 0x2d30 +#define R200_PP_TXOFFSET_3 0x2d48 +#define R200_PP_TXOFFSET_4 0x2d60 +#define R200_PP_TXOFFSET_5 0x2d78 + +#define R200_PP_TFACTOR_0 0x2ee0 +#define R200_PP_TFACTOR_1 0x2ee4 +#define R200_PP_TFACTOR_2 0x2ee8 +#define R200_PP_TFACTOR_3 0x2eec +#define R200_PP_TFACTOR_4 0x2ef0 +#define R200_PP_TFACTOR_5 0x2ef4 + +#define R200_PP_TXCBLEND_0 0x2f00 +# define R200_TXC_ARG_A_ZERO (0) +# define R200_TXC_ARG_A_CURRENT_COLOR (2) +# define R200_TXC_ARG_A_CURRENT_ALPHA (3) +# define R200_TXC_ARG_A_DIFFUSE_COLOR (4) +# define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) +# define R200_TXC_ARG_A_SPECULAR_COLOR (6) +# define R200_TXC_ARG_A_SPECULAR_ALPHA (7) +# define R200_TXC_ARG_A_TFACTOR_COLOR (8) +# define R200_TXC_ARG_A_TFACTOR_ALPHA (9) +# define R200_TXC_ARG_A_R0_COLOR (10) +# define R200_TXC_ARG_A_R0_ALPHA (11) +# define R200_TXC_ARG_A_R1_COLOR (12) +# define R200_TXC_ARG_A_R1_ALPHA (13) +# define R200_TXC_ARG_A_R2_COLOR (14) +# define R200_TXC_ARG_A_R2_ALPHA (15) +# define R200_TXC_ARG_A_R3_COLOR (16) +# define R200_TXC_ARG_A_R3_ALPHA (17) +# define R200_TXC_ARG_A_R4_COLOR (18) +# define R200_TXC_ARG_A_R4_ALPHA (19) +# define R200_TXC_ARG_A_R5_COLOR (20) +# define R200_TXC_ARG_A_R5_ALPHA (21) +# define R200_TXC_ARG_A_TFACTOR1_COLOR (26) +# define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) +# define R200_TXC_ARG_A_MASK (31 << 0) +# define R200_TXC_ARG_A_SHIFT 0 +# define R200_TXC_ARG_B_ZERO (0 << 5) +# define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) +# define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) +# define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) +# define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) +# define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) +# define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) +# define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) +# define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) +# define R200_TXC_ARG_B_R0_COLOR (10 << 5) +# define R200_TXC_ARG_B_R0_ALPHA (11 << 5) +# define R200_TXC_ARG_B_R1_COLOR (12 << 5) +# define R200_TXC_ARG_B_R1_ALPHA (13 << 5) +# define R200_TXC_ARG_B_R2_COLOR (14 << 5) +# define R200_TXC_ARG_B_R2_ALPHA (15 << 5) +# define R200_TXC_ARG_B_R3_COLOR (16 << 5) +# define R200_TXC_ARG_B_R3_ALPHA (17 << 5) +# define R200_TXC_ARG_B_R4_COLOR (18 << 5) +# define R200_TXC_ARG_B_R4_ALPHA (19 << 5) +# define R200_TXC_ARG_B_R5_COLOR (20 << 5) +# define R200_TXC_ARG_B_R5_ALPHA (21 << 5) +# define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) +# define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) +# define R200_TXC_ARG_B_MASK (31 << 5) +# define R200_TXC_ARG_B_SHIFT 5 +# define R200_TXC_ARG_C_ZERO (0 << 10) +# define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) +# define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) +# define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) +# define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) +# define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) +# define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) +# define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) +# define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) +# define R200_TXC_ARG_C_R0_COLOR (10 << 10) +# define R200_TXC_ARG_C_R0_ALPHA (11 << 10) +# define R200_TXC_ARG_C_R1_COLOR (12 << 10) +# define R200_TXC_ARG_C_R1_ALPHA (13 << 10) +# define R200_TXC_ARG_C_R2_COLOR (14 << 10) +# define R200_TXC_ARG_C_R2_ALPHA (15 << 10) +# define R200_TXC_ARG_C_R3_COLOR (16 << 10) +# define R200_TXC_ARG_C_R3_ALPHA (17 << 10) +# define R200_TXC_ARG_C_R4_COLOR (18 << 10) +# define R200_TXC_ARG_C_R4_ALPHA (19 << 10) +# define R200_TXC_ARG_C_R5_COLOR (20 << 10) +# define R200_TXC_ARG_C_R5_ALPHA (21 << 10) +# define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) +# define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) +# define R200_TXC_ARG_C_MASK (31 << 10) +# define R200_TXC_ARG_C_SHIFT 10 +# define R200_TXC_COMP_ARG_A (1 << 16) +# define R200_TXC_COMP_ARG_A_SHIFT (16) +# define R200_TXC_BIAS_ARG_A (1 << 17) +# define R200_TXC_SCALE_ARG_A (1 << 18) +# define R200_TXC_NEG_ARG_A (1 << 19) +# define R200_TXC_COMP_ARG_B (1 << 20) +# define R200_TXC_COMP_ARG_B_SHIFT (20) +# define R200_TXC_BIAS_ARG_B (1 << 21) +# define R200_TXC_SCALE_ARG_B (1 << 22) +# define R200_TXC_NEG_ARG_B (1 << 23) +# define R200_TXC_COMP_ARG_C (1 << 24) +# define R200_TXC_COMP_ARG_C_SHIFT (24) +# define R200_TXC_BIAS_ARG_C (1 << 25) +# define R200_TXC_SCALE_ARG_C (1 << 26) +# define R200_TXC_NEG_ARG_C (1 << 27) +# define R200_TXC_OP_MADD (0 << 28) +# define R200_TXC_OP_CND0 (2 << 28) +# define R200_TXC_OP_LERP (3 << 28) +# define R200_TXC_OP_DOT3 (4 << 28) +# define R200_TXC_OP_DOT4 (5 << 28) +# define R200_TXC_OP_CONDITIONAL (6 << 28) +# define R200_TXC_OP_DOT2_ADD (7 << 28) +# define R200_TXC_OP_MASK (7 << 28) +#define R200_PP_TXCBLEND2_0 0x2f04 +# define R200_TXC_TFACTOR_SEL_SHIFT 0 +# define R200_TXC_TFACTOR_SEL_MASK 0x7 +# define R200_TXC_TFACTOR1_SEL_SHIFT 4 +# define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) +# define R200_TXC_SCALE_SHIFT 8 +# define R200_TXC_SCALE_MASK (7 << 8) +# define R200_TXC_SCALE_1X (0 << 8) +# define R200_TXC_SCALE_2X (1 << 8) +# define R200_TXC_SCALE_4X (2 << 8) +# define R200_TXC_SCALE_8X (3 << 8) +# define R200_TXC_SCALE_INV2 (5 << 8) +# define R200_TXC_SCALE_INV4 (6 << 8) +# define R200_TXC_SCALE_INV8 (7 << 8) +# define R200_TXC_CLAMP_SHIFT 12 +# define R200_TXC_CLAMP_MASK (3 << 12) +# define R200_TXC_CLAMP_WRAP (0 << 12) +# define R200_TXC_CLAMP_0_1 (1 << 12) +# define R200_TXC_CLAMP_8_8 (2 << 12) +# define R200_TXC_OUTPUT_REG_MASK (7 << 16) +# define R200_TXC_OUTPUT_REG_NONE (0 << 16) +# define R200_TXC_OUTPUT_REG_R0 (1 << 16) +# define R200_TXC_OUTPUT_REG_R1 (2 << 16) +# define R200_TXC_OUTPUT_REG_R2 (3 << 16) +# define R200_TXC_OUTPUT_REG_R3 (4 << 16) +# define R200_TXC_OUTPUT_REG_R4 (5 << 16) +# define R200_TXC_OUTPUT_REG_R5 (6 << 16) +# define R200_TXC_OUTPUT_MASK_MASK (7 << 20) +# define R200_TXC_OUTPUT_MASK_RGB (0 << 20) +# define R200_TXC_OUTPUT_MASK_RG (1 << 20) +# define R200_TXC_OUTPUT_MASK_RB (2 << 20) +# define R200_TXC_OUTPUT_MASK_R (3 << 20) +# define R200_TXC_OUTPUT_MASK_GB (4 << 20) +# define R200_TXC_OUTPUT_MASK_G (5 << 20) +# define R200_TXC_OUTPUT_MASK_B (6 << 20) +# define R200_TXC_OUTPUT_MASK_NONE (7 << 20) +# define R200_TXC_REPL_NORMAL 0 +# define R200_TXC_REPL_RED 1 +# define R200_TXC_REPL_GREEN 2 +# define R200_TXC_REPL_BLUE 3 +# define R200_TXC_REPL_ARG_A_SHIFT 26 +# define R200_TXC_REPL_ARG_A_MASK (3 << 26) +# define R200_TXC_REPL_ARG_B_SHIFT 28 +# define R200_TXC_REPL_ARG_B_MASK (3 << 28) +# define R200_TXC_REPL_ARG_C_SHIFT 30 +# define R200_TXC_REPL_ARG_C_MASK (3 << 30) +#define R200_PP_TXABLEND_0 0x2f08 +# define R200_TXA_ARG_A_ZERO (0) +# define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ +# define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ +# define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) +# define R200_TXA_ARG_A_DIFFUSE_BLUE (5) +# define R200_TXA_ARG_A_SPECULAR_ALPHA (6) +# define R200_TXA_ARG_A_SPECULAR_BLUE (7) +# define R200_TXA_ARG_A_TFACTOR_ALPHA (8) +# define R200_TXA_ARG_A_TFACTOR_BLUE (9) +# define R200_TXA_ARG_A_R0_ALPHA (10) +# define R200_TXA_ARG_A_R0_BLUE (11) +# define R200_TXA_ARG_A_R1_ALPHA (12) +# define R200_TXA_ARG_A_R1_BLUE (13) +# define R200_TXA_ARG_A_R2_ALPHA (14) +# define R200_TXA_ARG_A_R2_BLUE (15) +# define R200_TXA_ARG_A_R3_ALPHA (16) +# define R200_TXA_ARG_A_R3_BLUE (17) +# define R200_TXA_ARG_A_R4_ALPHA (18) +# define R200_TXA_ARG_A_R4_BLUE (19) +# define R200_TXA_ARG_A_R5_ALPHA (20) +# define R200_TXA_ARG_A_R5_BLUE (21) +# define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) +# define R200_TXA_ARG_A_TFACTOR1_BLUE (27) +# define R200_TXA_ARG_A_MASK (31 << 0) +# define R200_TXA_ARG_A_SHIFT 0 +# define R200_TXA_ARG_B_ZERO (0 << 5) +# define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ +# define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ +# define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) +# define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) +# define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) +# define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) +# define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) +# define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) +# define R200_TXA_ARG_B_R0_ALPHA (10 << 5) +# define R200_TXA_ARG_B_R0_BLUE (11 << 5) +# define R200_TXA_ARG_B_R1_ALPHA (12 << 5) +# define R200_TXA_ARG_B_R1_BLUE (13 << 5) +# define R200_TXA_ARG_B_R2_ALPHA (14 << 5) +# define R200_TXA_ARG_B_R2_BLUE (15 << 5) +# define R200_TXA_ARG_B_R3_ALPHA (16 << 5) +# define R200_TXA_ARG_B_R3_BLUE (17 << 5) +# define R200_TXA_ARG_B_R4_ALPHA (18 << 5) +# define R200_TXA_ARG_B_R4_BLUE (19 << 5) +# define R200_TXA_ARG_B_R5_ALPHA (20 << 5) +# define R200_TXA_ARG_B_R5_BLUE (21 << 5) +# define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) +# define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) +# define R200_TXA_ARG_B_MASK (31 << 5) +# define R200_TXA_ARG_B_SHIFT 5 +# define R200_TXA_ARG_C_ZERO (0 << 10) +# define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ +# define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ +# define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) +# define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) +# define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) +# define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) +# define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) +# define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) +# define R200_TXA_ARG_C_R0_ALPHA (10 << 10) +# define R200_TXA_ARG_C_R0_BLUE (11 << 10) +# define R200_TXA_ARG_C_R1_ALPHA (12 << 10) +# define R200_TXA_ARG_C_R1_BLUE (13 << 10) +# define R200_TXA_ARG_C_R2_ALPHA (14 << 10) +# define R200_TXA_ARG_C_R2_BLUE (15 << 10) +# define R200_TXA_ARG_C_R3_ALPHA (16 << 10) +# define R200_TXA_ARG_C_R3_BLUE (17 << 10) +# define R200_TXA_ARG_C_R4_ALPHA (18 << 10) +# define R200_TXA_ARG_C_R4_BLUE (19 << 10) +# define R200_TXA_ARG_C_R5_ALPHA (20 << 10) +# define R200_TXA_ARG_C_R5_BLUE (21 << 10) +# define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) +# define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) +# define R200_TXA_ARG_C_MASK (31 << 10) +# define R200_TXA_ARG_C_SHIFT 10 +# define R200_TXA_COMP_ARG_A (1 << 16) +# define R200_TXA_COMP_ARG_A_SHIFT (16) +# define R200_TXA_BIAS_ARG_A (1 << 17) +# define R200_TXA_SCALE_ARG_A (1 << 18) +# define R200_TXA_NEG_ARG_A (1 << 19) +# define R200_TXA_COMP_ARG_B (1 << 20) +# define R200_TXA_COMP_ARG_B_SHIFT (20) +# define R200_TXA_BIAS_ARG_B (1 << 21) +# define R200_TXA_SCALE_ARG_B (1 << 22) +# define R200_TXA_NEG_ARG_B (1 << 23) +# define R200_TXA_COMP_ARG_C (1 << 24) +# define R200_TXA_COMP_ARG_C_SHIFT (24) +# define R200_TXA_BIAS_ARG_C (1 << 25) +# define R200_TXA_SCALE_ARG_C (1 << 26) +# define R200_TXA_NEG_ARG_C (1 << 27) +# define R200_TXA_OP_MADD (0 << 28) +# define R200_TXA_OP_CND0 (2 << 28) +# define R200_TXA_OP_LERP (3 << 28) +# define R200_TXA_OP_CONDITIONAL (6 << 28) +# define R200_TXA_OP_MASK (7 << 28) +#define R200_PP_TXABLEND2_0 0x2f0c +# define R200_TXA_TFACTOR_SEL_SHIFT 0 +# define R200_TXA_TFACTOR_SEL_MASK 0x7 +# define R200_TXA_TFACTOR1_SEL_SHIFT 4 +# define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) +# define R200_TXA_SCALE_SHIFT 8 +# define R200_TXA_SCALE_MASK (7 << 8) +# define R200_TXA_SCALE_1X (0 << 8) +# define R200_TXA_SCALE_2X (1 << 8) +# define R200_TXA_SCALE_4X (2 << 8) +# define R200_TXA_SCALE_8X (3 << 8) +# define R200_TXA_SCALE_INV2 (5 << 8) +# define R200_TXA_SCALE_INV4 (6 << 8) +# define R200_TXA_SCALE_INV8 (7 << 8) +# define R200_TXA_CLAMP_SHIFT 12 +# define R200_TXA_CLAMP_MASK (3 << 12) +# define R200_TXA_CLAMP_WRAP (0 << 12) +# define R200_TXA_CLAMP_0_1 (1 << 12) +# define R200_TXA_CLAMP_8_8 (2 << 12) +# define R200_TXA_OUTPUT_REG_MASK (7 << 16) +# define R200_TXA_OUTPUT_REG_NONE (0 << 16) +# define R200_TXA_OUTPUT_REG_R0 (1 << 16) +# define R200_TXA_OUTPUT_REG_R1 (2 << 16) +# define R200_TXA_OUTPUT_REG_R2 (3 << 16) +# define R200_TXA_OUTPUT_REG_R3 (4 << 16) +# define R200_TXA_OUTPUT_REG_R4 (5 << 16) +# define R200_TXA_OUTPUT_REG_R5 (6 << 16) +# define R200_TXA_DOT_ALPHA (1 << 20) +# define R200_TXA_REPL_NORMAL 0 +# define R200_TXA_REPL_RED 1 +# define R200_TXA_REPL_GREEN 2 +# define R200_TXA_REPL_ARG_A_SHIFT 26 +# define R200_TXA_REPL_ARG_A_MASK (3 << 26) +# define R200_TXA_REPL_ARG_B_SHIFT 28 +# define R200_TXA_REPL_ARG_B_MASK (3 << 28) +# define R200_TXA_REPL_ARG_C_SHIFT 30 +# define R200_TXA_REPL_ARG_C_MASK (3 << 30) + +#define R200_SE_VTX_FMT_0 0x2088 +# define R200_VTX_XY 0 /* always have xy */ +# define R200_VTX_Z0 (1<<0) +# define R200_VTX_W0 (1<<1) +# define R200_VTX_WEIGHT_COUNT_SHIFT (2) +# define R200_VTX_PV_MATRIX_SEL (1<<5) +# define R200_VTX_N0 (1<<6) +# define R200_VTX_POINT_SIZE (1<<7) +# define R200_VTX_DISCRETE_FOG (1<<8) +# define R200_VTX_SHININESS_0 (1<<9) +# define R200_VTX_SHININESS_1 (1<<10) +# define R200_VTX_COLOR_NOT_PRESENT 0 +# define R200_VTX_PK_RGBA 1 +# define R200_VTX_FP_RGB 2 +# define R200_VTX_FP_RGBA 3 +# define R200_VTX_COLOR_MASK 3 +# define R200_VTX_COLOR_0_SHIFT 11 +# define R200_VTX_COLOR_1_SHIFT 13 +# define R200_VTX_COLOR_2_SHIFT 15 +# define R200_VTX_COLOR_3_SHIFT 17 +# define R200_VTX_COLOR_4_SHIFT 19 +# define R200_VTX_COLOR_5_SHIFT 21 +# define R200_VTX_COLOR_6_SHIFT 23 +# define R200_VTX_COLOR_7_SHIFT 25 +# define R200_VTX_XY1 (1<<28) +# define R200_VTX_Z1 (1<<29) +# define R200_VTX_W1 (1<<30) +# define R200_VTX_N1 (1<<31) +#define R200_SE_VTX_FMT_1 0x208c +# define R200_VTX_TEX0_COMP_CNT_SHIFT 0 +# define R200_VTX_TEX1_COMP_CNT_SHIFT 3 +# define R200_VTX_TEX2_COMP_CNT_SHIFT 6 +# define R200_VTX_TEX3_COMP_CNT_SHIFT 9 +# define R200_VTX_TEX4_COMP_CNT_SHIFT 12 +# define R200_VTX_TEX5_COMP_CNT_SHIFT 15 + +#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 +#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 +#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 +# define R200_OUTPUT_XYZW (1<<0) +# define R200_OUTPUT_COLOR_0 (1<<8) +# define R200_OUTPUT_COLOR_1 (1<<9) +# define R200_OUTPUT_TEX_0 (1<<16) +# define R200_OUTPUT_TEX_1 (1<<17) +# define R200_OUTPUT_TEX_2 (1<<18) +# define R200_OUTPUT_TEX_3 (1<<19) +# define R200_OUTPUT_TEX_4 (1<<20) +# define R200_OUTPUT_TEX_5 (1<<21) +# define R200_OUTPUT_TEX_MASK (0x3f<<16) +# define R200_OUTPUT_DISCRETE_FOG (1<<24) +# define R200_OUTPUT_PT_SIZE (1<<25) +# define R200_FORCE_INORDER_PROC (1<<31) +#define R200_PP_CNTL_X 0x2cc4 +#define R200_PP_TXMULTI_CTL_0 0x2c1c +#define R200_SE_VTX_STATE_CNTL 0x2180 +# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) /* Registers for CP and Microcode Engine */ #define RADEON_CP_ME_RAM_ADDR 0x07d4 @@ -2007,6 +2896,7 @@ #define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 #define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 #define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 +#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500 #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 #define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 #define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h:1.7 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h:1.8 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h:1.7 Fri Dec 10 08:07:01 2004 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h Wed Apr 2 14:02:32 2008 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h,v 1.7 2004/12/10 16:07:01 alanh Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h,v 1.8 2008/04/02 21:02:32 tsi Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, * VA Linux Systems Inc., Fremont, California. @@ -222,10 +222,11 @@ /* last time texture was uploaded */ unsigned int texAge[RADEON_NR_TEX_HEAPS]; - int ctxOwner; /* last context to upload state */ + drm_context_t ctxOwner; /* last context to upload state */ int pfAllowPageFlip; /* set by the 2d driver, read by the client */ int pfCurrentPage; /* set by kernel, read by others */ int crtc2_base; /* for pageflipping with CloneMode */ + int tiling_enabled; /* set by drm, read by 2d + 3d clients */ } RADEONSAREAPriv, *RADEONSAREAPrivPtr; #endif Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_version.h diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_version.h:1.14 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_version.h:1.16 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_version.h:1.14 Mon Jan 1 08:08:18 2007 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_version.h Wed Apr 2 14:02:32 2008 @@ -1,6 +1,6 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_version.h,v 1.14 2007/01/01 16:08:18 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_version.h,v 1.16 2008/04/02 21:02:32 tsi Exp $ */ /* - * Copyright 2000 through 2007 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org + * Copyright 2000 through 2008 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -27,6 +27,8 @@ #undef RADEON_NAME #undef RADEON_DRIVER_NAME #undef R200_DRIVER_NAME +#undef R300_DRIVER_NAME + #undef RADEON_VERSION_MAJOR #undef RADEON_VERSION_MINOR #undef RADEON_VERSION_PATCH @@ -38,10 +40,12 @@ #define RADEON_NAME "RADEON" #define RADEON_DRIVER_NAME "radeon" #define R200_DRIVER_NAME "r200" +#define R300_DRIVER_NAME "r300" #define RADEON_VERSION_MAJOR 4 -#define RADEON_VERSION_MINOR 0 -#define RADEON_VERSION_PATCH 1 +#define RADEON_VERSION_MAJOR_TILED 5 +#define RADEON_VERSION_MINOR 1 +#define RADEON_VERSION_PATCH 0 #ifndef RADEON_VERSION_EXTRA #define RADEON_VERSION_EXTRA "" Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c diff -u xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c:1.33 xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c:1.35 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c:1.33 Tue Jun 27 11:42:33 2006 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c Sun Apr 6 12:17:41 2008 @@ -1,7 +1,8 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c,v 1.33 2006/06/27 18:42:33 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c,v 1.35 2008/04/06 19:17:41 tsi Exp $ */ #include "radeon.h" #include "radeon_macros.h" +#include "radeon_mergedfb.h" #include "radeon_probe.h" #include "radeon_reg.h" @@ -20,8 +21,6 @@ #define TIMER_MASK (OFF_TIMER | FREE_TIMER) -extern int gRADEONEntityIndex; - static void RADEONInitOffscreenImages(ScreenPtr); static XF86VideoAdaptorPtr RADEONSetupImageVideo(ScreenPtr); @@ -39,13 +38,18 @@ static void RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now); #define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE) +#define ClipValue(v,min,max) ((v) < (min) ? (min) : (v) > (max) ? (max) : (v)) static Atom xvBrightness, xvColorKey, xvSaturation, xvDoubleBuffer; static Atom xvRedIntensity, xvGreenIntensity, xvBlueIntensity; static Atom xvContrast, xvHue, xvColor, xvAutopaintColorkey, xvSetDefaults; +static Atom xvGamma, xvColorspace, xvSwitchCRT; +static Atom xvLocationID, xvDeviceID, xvInstanceID; +static Atom xvOvAlpha, xvGrAlpha, xvAlphaMode; typedef struct { CARD32 transform_index; + CARD32 gamma; /* gamma value x 1000 */ int brightness; int saturation; int hue; @@ -55,6 +59,13 @@ int blue_intensity; int ecp_div; + /* overlay composition mode */ + int alpha_mode; /* 0 = key mode, 1 = global mode */ + int ov_alpha; + int gr_alpha; + + int overlay_scaler_buffer_width; + Bool doubleBuffer; unsigned char currentBuffer; RegionRec clip; @@ -63,12 +74,15 @@ Time offTime; Time freeTime; Bool autopaint_colorkey; -} RADEONPortPrivRec, *RADEONPortPrivPtr; + Bool crt2; /* 0=CRT1, 1=CRT2 */ + Atom device_id, location_id, instance_id; +} RADEONPortPrivRec, *RADEONPortPrivPtr; #define GET_PORT_PRIVATE(pScrn) \ (RADEONPortPrivPtr)((RADEONPTR(pScrn))->adaptor->pPortPrivates[0].ptr) + void RADEONInitVideo(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; @@ -123,15 +137,20 @@ {15, DirectColor}, {16, DirectColor}, {24, DirectColor} }; +#define NUM_ATTRIBUTES 21 -#define NUM_ATTRIBUTES 9+3 - -static XF86AttributeRec Attributes[NUM_ATTRIBUTES] = +static XF86AttributeRec Attributes[NUM_ATTRIBUTES+1] = { - {XvSettable , 0, 1, "XV_SET_DEFAULTS"}, - {XvSettable | XvGettable, 0, 1, "XV_AUTOPAINT_COLORKEY"}, - {XvSettable | XvGettable, 0, ~0, "XV_COLORKEY"}, - {XvSettable | XvGettable, 0, 1, "XV_DOUBLE_BUFFER"}, + { XvGettable, 0, ~0, "XV_DEVICE_ID"}, + { XvGettable, 0, ~0, "XV_LOCATION_ID"}, + { XvGettable, 0, ~0, "XV_INSTANCE_ID"}, + {XvSettable , 0, 1, "XV_SET_DEFAULTS"}, + {XvSettable | XvGettable, 0, 1, "XV_AUTOPAINT_COLORKEY"}, + {XvSettable | XvGettable, 0, ~0,"XV_COLORKEY"}, + {XvSettable | XvGettable, 0, 1, "XV_DOUBLE_BUFFER"}, + {XvSettable | XvGettable, 0, 255, "XV_OVERLAY_ALPHA"}, + {XvSettable | XvGettable, 0, 255, "XV_GRAPHICS_ALPHA"}, + {XvSettable | XvGettable, 0, 1, "XV_ALPHA_MODE"}, {XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"}, {XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"}, {XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"}, @@ -140,16 +159,110 @@ {XvSettable | XvGettable, -1000, 1000, "XV_RED_INTENSITY"}, {XvSettable | XvGettable, -1000, 1000, "XV_GREEN_INTENSITY"}, {XvSettable | XvGettable, -1000, 1000, "XV_BLUE_INTENSITY"}, + {XvSettable | XvGettable, 0, 1, "XV_SWITCHCRT"}, + {XvSettable | XvGettable, 100, 10000, "XV_GAMMA"}, + {XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"}, + + { 0, 0, 0, NULL} /* just a place holder so I don't have to be fancy with commas */ }; -#define NUM_IMAGES 4 +#define NUM_IMAGES 8 + +/* Note: GUIDs are bogus... - but nothing uses them anyway */ + +#define FOURCC_RGBA32 0x41424752 + +#define XVIMAGE_RGBA32(byte_order) \ + { \ + FOURCC_RGBA32, \ + XvRGB, \ + byte_order, \ + { 'R', 'G', 'B', 'A', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 32, \ + XvPacked, \ + 1, \ + 32, 0x00FF0000, 0x0000FF00, 0x000000FF, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + {'A', 'R', 'G', 'B', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#define FOURCC_RGB24 0x00000000 + +#define XVIMAGE_RGB24(byte_order) \ + { \ + FOURCC_RGB24, \ + XvRGB, \ + byte_order, \ + { 'R', 'G', 'B', 0, \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 24, \ + XvPacked, \ + 1, \ + 24, 0x00FF0000, 0x0000FF00, 0x000000FF, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + { 'R', 'G', 'B', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#define FOURCC_RGBT16 0x54424752 + +#define XVIMAGE_RGBT16(byte_order) \ + { \ + FOURCC_RGBT16, \ + XvRGB, \ + byte_order, \ + { 'R', 'G', 'B', 'T', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 16, \ + XvPacked, \ + 1, \ + 16, 0x00007C00, 0x000003E0, 0x0000001F, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + {'A', 'R', 'G', 'B', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#define FOURCC_RGB16 0x32424752 + +#define XVIMAGE_RGB16(byte_order) \ + { \ + FOURCC_RGB16, \ + XvRGB, \ + byte_order, \ + { 'R', 'G', 'B', 0x00, \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 16, \ + XvPacked, \ + 1, \ + 16, 0x0000F800, 0x000007E0, 0x0000001F, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + {'R', 'G', 'B', \ + 0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } static XF86ImageRec Images[NUM_IMAGES] = { - XVIMAGE_YUY2, - XVIMAGE_UYVY, - XVIMAGE_YV12, - XVIMAGE_I420 +#if X_BYTE_ORDER == X_BIG_ENDIAN + XVIMAGE_RGBA32(MSBFirst), + XVIMAGE_RGB24(MSBFirst), + XVIMAGE_RGBT16(MSBFirst), + XVIMAGE_RGB16(MSBFirst), +#else + XVIMAGE_RGBA32(LSBFirst), + XVIMAGE_RGB24(LSBFirst), + XVIMAGE_RGBT16(LSBFirst), + XVIMAGE_RGB16(LSBFirst), +#endif + XVIMAGE_YUY2, + XVIMAGE_UYVY, + XVIMAGE_YV12, + XVIMAGE_I420 }; /* Reference color space transform data */ @@ -172,37 +285,391 @@ }; -/* Gamma curve definition */ -typedef struct +/* Gamma curve definition for preset gammas */ +typedef struct tagGAMMA_CURVE_R100 +{ + CARD32 GAMMA_0_F_SLOPE; + CARD32 GAMMA_0_F_OFFSET; + CARD32 GAMMA_10_1F_SLOPE; + CARD32 GAMMA_10_1F_OFFSET; + CARD32 GAMMA_20_3F_SLOPE; + CARD32 GAMMA_20_3F_OFFSET; + CARD32 GAMMA_40_7F_SLOPE; + CARD32 GAMMA_40_7F_OFFSET; + CARD32 GAMMA_380_3BF_SLOPE; + CARD32 GAMMA_380_3BF_OFFSET; + CARD32 GAMMA_3C0_3FF_SLOPE; + CARD32 GAMMA_3C0_3FF_OFFSET; + float OvGammaCont; +} GAMMA_CURVE_R100; + +typedef struct tagGAMMA_CURVE_R200 { - unsigned int gammaReg; - unsigned int gammaSlope; - unsigned int gammaOffset; -} GAMMA_SETTINGS; - -/* Recommended gamma curve parameters */ -static GAMMA_SETTINGS def_gamma[18] = -{ - {RADEON_OV0_GAMMA_000_00F, 0x100, 0x0000}, - {RADEON_OV0_GAMMA_010_01F, 0x100, 0x0020}, - {RADEON_OV0_GAMMA_020_03F, 0x100, 0x0040}, - {RADEON_OV0_GAMMA_040_07F, 0x100, 0x0080}, - {RADEON_OV0_GAMMA_080_0BF, 0x100, 0x0100}, - {RADEON_OV0_GAMMA_0C0_0FF, 0x100, 0x0100}, - {RADEON_OV0_GAMMA_100_13F, 0x100, 0x0200}, - {RADEON_OV0_GAMMA_140_17F, 0x100, 0x0200}, - {RADEON_OV0_GAMMA_180_1BF, 0x100, 0x0300}, - {RADEON_OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, - {RADEON_OV0_GAMMA_200_23F, 0x100, 0x0400}, - {RADEON_OV0_GAMMA_240_27F, 0x100, 0x0400}, - {RADEON_OV0_GAMMA_280_2BF, 0x100, 0x0500}, - {RADEON_OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, - {RADEON_OV0_GAMMA_300_33F, 0x100, 0x0600}, - {RADEON_OV0_GAMMA_340_37F, 0x100, 0x0600}, - {RADEON_OV0_GAMMA_380_3BF, 0x100, 0x0700}, - {RADEON_OV0_GAMMA_3C0_3FF, 0x100, 0x0700} + CARD32 GAMMA_0_F_SLOPE; + CARD32 GAMMA_0_F_OFFSET; + CARD32 GAMMA_10_1F_SLOPE; + CARD32 GAMMA_10_1F_OFFSET; + CARD32 GAMMA_20_3F_SLOPE; + CARD32 GAMMA_20_3F_OFFSET; + CARD32 GAMMA_40_7F_SLOPE; + CARD32 GAMMA_40_7F_OFFSET; + CARD32 GAMMA_80_BF_SLOPE; + CARD32 GAMMA_80_BF_OFFSET; + CARD32 GAMMA_C0_FF_SLOPE; + CARD32 GAMMA_C0_FF_OFFSET; + CARD32 GAMMA_100_13F_SLOPE; + CARD32 GAMMA_100_13F_OFFSET; + CARD32 GAMMA_140_17F_SLOPE; + CARD32 GAMMA_140_17F_OFFSET; + CARD32 GAMMA_180_1BF_SLOPE; + CARD32 GAMMA_180_1BF_OFFSET; + CARD32 GAMMA_1C0_1FF_SLOPE; + CARD32 GAMMA_1C0_1FF_OFFSET; + CARD32 GAMMA_200_23F_SLOPE; + CARD32 GAMMA_200_23F_OFFSET; + CARD32 GAMMA_240_27F_SLOPE; + CARD32 GAMMA_240_27F_OFFSET; + CARD32 GAMMA_280_2BF_SLOPE; + CARD32 GAMMA_280_2BF_OFFSET; + CARD32 GAMMA_2C0_2FF_SLOPE; + CARD32 GAMMA_2C0_2FF_OFFSET; + CARD32 GAMMA_300_33F_SLOPE; + CARD32 GAMMA_300_33F_OFFSET; + CARD32 GAMMA_340_37F_SLOPE; + CARD32 GAMMA_340_37F_OFFSET; + CARD32 GAMMA_380_3BF_SLOPE; + CARD32 GAMMA_380_3BF_OFFSET; + CARD32 GAMMA_3C0_3FF_SLOPE; + CARD32 GAMMA_3C0_3FF_OFFSET; + float OvGammaCont; +} GAMMA_CURVE_R200; + + +/* Preset gammas */ +static GAMMA_CURVE_R100 gamma_curve_r100[8] = +{ + /* GAMMA 1.0 */ + {0x100, 0x0, + 0x100, 0x20, + 0x100, 0x40, + 0x100, 0x80, + 0x100, 0x100, + 0x100, 0x100, + 1.0}, + /* GAMMA 0.85 */ + {0x75, 0x0, + 0xA2, 0xF, + 0xAC, 0x23, + 0xC6, 0x4E, + 0x129, 0xD6, + 0x12B, 0xD5, + 1.0}, + /* GAMMA 1.1 */ + {0x180, 0x0, + 0x13C, 0x30, + 0x13C, 0x57, + 0x123, 0xA5, + 0xEA, 0x116, + 0xEA, 0x116, + 0.9913}, + /* GAMMA 1.2 */ + {0x21B, 0x0, + 0x16D, 0x43, + 0x172, 0x71, + 0x13D, 0xCD, + 0xD9, 0x128, + 0xD6, 0x12A, + 0.9827}, + /* GAMMA 1.45 */ + {0x404, 0x0, + 0x1B9, 0x81, + 0x1EE, 0xB8, + 0x16A, 0x133, + 0xB7, 0x14B, + 0xB2, 0x14E, + 0.9567}, + /* GAMMA 1.7 */ + {0x658, 0x0, + 0x1B5, 0xCB, + 0x25F, 0x102, + 0x181, 0x199, + 0x9C, 0x165, + 0x98, 0x167, + 0.9394}, + /* GAMMA 2.2 */ + {0x7FF, 0x0, + 0x625, 0x100, + 0x1E4, 0x1C4, + 0x1BD, 0x23D, + 0x79, 0x187, + 0x76, 0x188, + 0.9135}, + /* GAMMA 2.5 */ + {0x7FF, 0x0, + 0x7FF, 0x100, + 0x2AD, 0x200, + 0x1A2, 0x2AB, + 0x6E, 0x194, + 0x67, 0x197, + 0.9135} }; +static GAMMA_CURVE_R200 gamma_curve_r200[8] = + { + /* GAMMA 1.0 */ + {0x00000040, 0x00000000, + 0x00000040, 0x00000020, + 0x00000080, 0x00000040, + 0x00000100, 0x00000080, + 0x00000100, 0x00000100, + 0x00000100, 0x00000100, + 0x00000100, 0x00000200, + 0x00000100, 0x00000200, + 0x00000100, 0x00000300, + 0x00000100, 0x00000300, + 0x00000100, 0x00000400, + 0x00000100, 0x00000400, + 0x00000100, 0x00000500, + 0x00000100, 0x00000500, + 0x00000100, 0x00000600, + 0x00000100, 0x00000600, + 0x00000100, 0x00000700, + 0x00000100, 0x00000700, + 1.0}, + /* GAMMA 0.85 */ + {0x0000001D, 0x00000000, + 0x00000028, 0x0000000F, + 0x00000056, 0x00000023, + 0x000000C5, 0x0000004E, + 0x000000DA, 0x000000B0, + 0x000000E6, 0x000000AA, + 0x000000F1, 0x00000190, + 0x000000F9, 0x0000018C, + 0x00000101, 0x00000286, + 0x00000108, 0x00000282, + 0x0000010D, 0x0000038A, + 0x00000113, 0x00000387, + 0x00000118, 0x0000049A, + 0x0000011C, 0x00000498, + 0x00000120, 0x000005B4, + 0x00000124, 0x000005B2, + 0x00000128, 0x000006D6, + 0x0000012C, 0x000006D5, + 1.0}, + /* GAMMA 1.1 */ + {0x00000060, 0x00000000, + 0x0000004F, 0x00000030, + 0x0000009C, 0x00000057, + 0x00000121, 0x000000A5, + 0x00000113, 0x00000136, + 0x0000010B, 0x0000013A, + 0x00000105, 0x00000245, + 0x00000100, 0x00000247, + 0x000000FD, 0x00000348, + 0x000000F9, 0x00000349, + 0x000000F6, 0x00000443, + 0x000000F4, 0x00000444, + 0x000000F2, 0x00000538, + 0x000000F0, 0x00000539, + 0x000000EE, 0x00000629, + 0x000000EC, 0x00000629, + 0x000000EB, 0x00000716, + 0x000000E9, 0x00000717, + 0.9913}, + /* GAMMA 1.2 */ + {0x00000087, 0x00000000, + 0x0000005B, 0x00000043, + 0x000000B7, 0x00000071, + 0x0000013D, 0x000000CD, + 0x00000121, 0x0000016B, + 0x00000113, 0x00000172, + 0x00000107, 0x00000286, + 0x000000FF, 0x0000028A, + 0x000000F8, 0x00000389, + 0x000000F2, 0x0000038B, + 0x000000ED, 0x0000047D, + 0x000000E9, 0x00000480, + 0x000000E5, 0x00000568, + 0x000000E1, 0x0000056A, + 0x000000DE, 0x0000064B, + 0x000000DB, 0x0000064D, + 0x000000D9, 0x00000728, + 0x000000D6, 0x00000729, + 0.9827}, + /* GAMMA 1.45 */ + {0x00000101, 0x00000000, + 0x0000006E, 0x00000081, + 0x000000F7, 0x000000B8, + 0x0000016E, 0x00000133, + 0x00000139, 0x000001EA, + 0x0000011B, 0x000001F9, + 0x00000105, 0x00000314, + 0x000000F6, 0x0000031C, + 0x000000E9, 0x00000411, + 0x000000DF, 0x00000417, + 0x000000D7, 0x000004F6, + 0x000000CF, 0x000004F9, + 0x000000C9, 0x000005C9, + 0x000000C4, 0x000005CC, + 0x000000BF, 0x0000068F, + 0x000000BA, 0x00000691, + 0x000000B6, 0x0000074B, + 0x000000B2, 0x0000074D, + 0.9567}, + /* GAMMA 1.7 */ + {0x00000196, 0x00000000, + 0x0000006D, 0x000000CB, + 0x0000012F, 0x00000102, + 0x00000187, 0x00000199, + 0x00000144, 0x0000025b, + 0x00000118, 0x00000273, + 0x000000FE, 0x0000038B, + 0x000000E9, 0x00000395, + 0x000000DA, 0x0000047E, + 0x000000CE, 0x00000485, + 0x000000C3, 0x00000552, + 0x000000BB, 0x00000556, + 0x000000B3, 0x00000611, + 0x000000AC, 0x00000614, + 0x000000A7, 0x000006C1, + 0x000000A1, 0x000006C3, + 0x0000009D, 0x00000765, + 0x00000098, 0x00000767, + 0.9394}, + /* GAMMA 2.2 */ + {0x000001FF, 0x00000000, + 0x0000018A, 0x00000100, + 0x000000F1, 0x000001C5, + 0x000001D6, 0x0000023D, + 0x00000124, 0x00000328, + 0x00000116, 0x0000032F, + 0x000000E2, 0x00000446, + 0x000000D3, 0x0000044D, + 0x000000BC, 0x00000520, + 0x000000B0, 0x00000526, + 0x000000A4, 0x000005D6, + 0x0000009B, 0x000005DB, + 0x00000092, 0x00000676, + 0x0000008B, 0x00000679, + 0x00000085, 0x00000704, + 0x00000080, 0x00000707, + 0x0000007B, 0x00000787, + 0x00000076, 0x00000789, + 0.9135}, + /* GAMMA 2.5 */ + {0x000001FF, 0x00000000, + 0x000001FF, 0x00000100, + 0x00000159, 0x000001FF, + 0x000001AC, 0x000002AB, + 0x0000012F, 0x00000381, + 0x00000101, 0x00000399, + 0x000000D9, 0x0000049A, + 0x000000C3, 0x000004A5, + 0x000000AF, 0x00000567, + 0x000000A1, 0x0000056E, + 0x00000095, 0x00000610, + 0x0000008C, 0x00000614, + 0x00000084, 0x000006A0, + 0x0000007D, 0x000006A4, + 0x00000077, 0x00000721, + 0x00000071, 0x00000723, + 0x0000006D, 0x00000795, + 0x00000068, 0x00000797, + 0.9135} +}; + +static void +RADEONSetOverlayGamma(ScrnInfoPtr pScrn, CARD32 GAMMA) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + CARD32 ov0_scale_cntl; + + /* Set gamma */ + RADEONWaitForIdleMMIO(pScrn); + ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL) & ~RADEON_SCALER_GAMMA_SEL_MASK; + OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl | (GAMMA << 0x00000005)); + + /* Load gamma curve adjustments */ + if (info->ChipFamily >= CHIP_FAMILY_R200) { + OUTREG(RADEON_OV0_GAMMA_000_00F, + (gamma_curve_r200[GAMMA].GAMMA_0_F_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_0_F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_010_01F, + (gamma_curve_r200[GAMMA].GAMMA_10_1F_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_10_1F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_020_03F, + (gamma_curve_r200[GAMMA].GAMMA_20_3F_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_20_3F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_040_07F, + (gamma_curve_r200[GAMMA].GAMMA_40_7F_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_40_7F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_080_0BF, + (gamma_curve_r200[GAMMA].GAMMA_80_BF_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_80_BF_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_0C0_0FF, + (gamma_curve_r200[GAMMA].GAMMA_C0_FF_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_C0_FF_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_100_13F, + (gamma_curve_r200[GAMMA].GAMMA_100_13F_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_100_13F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_140_17F, + (gamma_curve_r200[GAMMA].GAMMA_140_17F_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_140_17F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_180_1BF, + (gamma_curve_r200[GAMMA].GAMMA_180_1BF_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_180_1BF_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_1C0_1FF, + (gamma_curve_r200[GAMMA].GAMMA_1C0_1FF_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_1C0_1FF_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_200_23F, + (gamma_curve_r200[GAMMA].GAMMA_200_23F_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_200_23F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_240_27F, + (gamma_curve_r200[GAMMA].GAMMA_240_27F_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_240_27F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_280_2BF, + (gamma_curve_r200[GAMMA].GAMMA_280_2BF_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_280_2BF_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_2C0_2FF, + (gamma_curve_r200[GAMMA].GAMMA_2C0_2FF_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_2C0_2FF_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_300_33F, + (gamma_curve_r200[GAMMA].GAMMA_300_33F_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_300_33F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_340_37F, + (gamma_curve_r200[GAMMA].GAMMA_340_37F_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_340_37F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_380_3BF, + (gamma_curve_r200[GAMMA].GAMMA_380_3BF_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_380_3BF_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_3C0_3FF, + (gamma_curve_r200[GAMMA].GAMMA_3C0_3FF_OFFSET << 0x00000000) | + (gamma_curve_r200[GAMMA].GAMMA_3C0_3FF_SLOPE << 0x00000010)); + } else { + OUTREG(RADEON_OV0_GAMMA_000_00F, + (gamma_curve_r100[GAMMA].GAMMA_0_F_OFFSET << 0x00000000) | + (gamma_curve_r100[GAMMA].GAMMA_0_F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_010_01F, + (gamma_curve_r100[GAMMA].GAMMA_10_1F_OFFSET << 0x00000000) | + (gamma_curve_r100[GAMMA].GAMMA_10_1F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_020_03F, + (gamma_curve_r100[GAMMA].GAMMA_20_3F_OFFSET << 0x00000000) | + (gamma_curve_r100[GAMMA].GAMMA_20_3F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_040_07F, + (gamma_curve_r100[GAMMA].GAMMA_40_7F_OFFSET << 0x00000000) | + (gamma_curve_r100[GAMMA].GAMMA_40_7F_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_380_3BF, + (gamma_curve_r100[GAMMA].GAMMA_380_3BF_OFFSET << 0x00000000) | + (gamma_curve_r100[GAMMA].GAMMA_380_3BF_SLOPE << 0x00000010)); + OUTREG(RADEON_OV0_GAMMA_3C0_3FF, + (gamma_curve_r100[GAMMA].GAMMA_3C0_3FF_OFFSET << 0x00000000) | + (gamma_curve_r100[GAMMA].GAMMA_3C0_3FF_SLOPE << 0x00000010)); + } + +} + + /**************************************************************************** * SetTransform * * Function: Calculates and sets color space transform from supplied * @@ -216,6 +683,7 @@ * green_intensity - intensity of green component * * blue_intensity - intensity of blue component * * ref - index to the table of refernce transforms * + * user_gamma - gamma value x 1000 (e.g., 1200 = gamma of 1.2) * * Outputs: NONE * ****************************************************************************/ @@ -227,7 +695,8 @@ float red_intensity, float green_intensity, float blue_intensity, - CARD32 ref) + CARD32 ref, + CARD32 user_gamma) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -236,7 +705,6 @@ float CAdjRCb, CAdjRCr; float CAdjGCb, CAdjGCr; float CAdjBCb, CAdjBCr; - float RedAdj,GreenAdj,BlueAdj; float OvLuma, OvROff, OvGOff, OvBOff; float OvRCb, OvRCr; float OvGCb, OvGCr; @@ -248,18 +716,37 @@ CARD32 dwOvRCb, dwOvRCr; CARD32 dwOvGCb, dwOvGCr; CARD32 dwOvBCb, dwOvBCr; + CARD32 GAMMA = 0; if (ref >= 2) return; + /* translate from user_gamma (gamma x 1000) to radeon gamma table index value */ + if (user_gamma <= 925) /* 0.85 */ + GAMMA = 1; + else if (user_gamma <= 1050) /* 1.0 */ + GAMMA = 0; + else if (user_gamma <= 1150) /* 1.1 */ + GAMMA = 2; + else if (user_gamma <= 1325) /* 1.2 */ + GAMMA = 3; + else if (user_gamma <= 1575) /* 1.45 */ + GAMMA = 4; + else if (user_gamma <= 1950) /* 1.7 */ + GAMMA = 5; + else if (user_gamma <= 2350) /* 2.2 */ + GAMMA = 6; + else if (user_gamma > 2350) /* 2.5 */ + GAMMA = 7; + + if (GAMMA >= 8) + return; + OvHueSin = sin(hue); OvHueCos = cos(hue); CAdjLuma = cont * trans[ref].RefLuma; CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; - RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; - GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; - BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; @@ -278,34 +765,34 @@ CAdjBCb = 2.01708984375; CAdjBCr = 0; #endif - OvLuma = CAdjLuma; - OvRCb = CAdjRCb; - OvRCr = CAdjRCr; - OvGCb = CAdjGCb; - OvGCr = CAdjGCr; - OvBCb = CAdjBCb; - OvBCr = CAdjBCr; - OvROff = RedAdj + CAdjOff - - OvLuma * Loff - (OvRCb + OvRCr) * Coff; - OvGOff = GreenAdj + CAdjOff - - OvLuma * Loff - (OvGCb + OvGCr) * Coff; - OvBOff = BlueAdj + CAdjOff - - OvLuma * Loff - (OvBCb + OvBCr) * Coff; + + OvLuma = CAdjLuma * gamma_curve_r100[GAMMA].OvGammaCont; + OvRCb = CAdjRCb * gamma_curve_r100[GAMMA].OvGammaCont; + OvRCr = CAdjRCr * gamma_curve_r100[GAMMA].OvGammaCont; + OvGCb = CAdjGCb * gamma_curve_r100[GAMMA].OvGammaCont; + OvGCr = CAdjGCr * gamma_curve_r100[GAMMA].OvGammaCont; + OvBCb = CAdjBCb * gamma_curve_r100[GAMMA].OvGammaCont; + OvBCr = CAdjBCr * gamma_curve_r100[GAMMA].OvGammaCont; + OvROff = CAdjOff * gamma_curve_r100[GAMMA].OvGammaCont - + OvLuma * Loff - (OvRCb + OvRCr) * Coff; + OvGOff = CAdjOff * gamma_curve_r100[GAMMA].OvGammaCont - + OvLuma * Loff - (OvGCb + OvGCr) * Coff; + OvBOff = CAdjOff * gamma_curve_r100[GAMMA].OvGammaCont - + OvLuma * Loff - (OvBCb + OvBCr) * Coff; #if 0 /* default constants */ OvROff = -888.5; OvGOff = 545; OvBOff = -1104; #endif + OvROff = ClipValue(OvROff, -2048.0, 2047.5); + OvGOff = ClipValue(OvGOff, -2048.0, 2047.5); + OvBOff = ClipValue(OvBOff, -2048.0, 2047.5); dwOvROff = ((INT32)(OvROff * 2.0)) & 0x1fff; dwOvGOff = ((INT32)(OvGOff * 2.0)) & 0x1fff; dwOvBOff = ((INT32)(OvBOff * 2.0)) & 0x1fff; - /* - * Whatever docs say about R200 having 3.8 format instead of 3.11 - * as in Radeon is a lie - * Or more precisely the location of bit fields is a lie - */ - if(1 || info->ChipFamily < CHIP_FAMILY_R200) + + if(info->ChipFamily == CHIP_FAMILY_RADEON) { dwOvLuma =(((INT32)(OvLuma * 2048.0))&0x7fff)<<17; dwOvRCb = (((INT32)(OvRCb * 2048.0))&0x7fff)<<1; @@ -317,14 +804,19 @@ } else { - dwOvLuma = (((INT32)(OvLuma * 256.0))&0x7ff)<<20; - dwOvRCb = (((INT32)(OvRCb * 256.0))&0x7ff)<<4; - dwOvRCr = (((INT32)(OvRCr * 256.0))&0x7ff)<<20; - dwOvGCb = (((INT32)(OvGCb * 256.0))&0x7ff)<<4; - dwOvGCr = (((INT32)(OvGCr * 256.0))&0x7ff)<<20; - dwOvBCb = (((INT32)(OvBCb * 256.0))&0x7ff)<<4; - dwOvBCr = (((INT32)(OvBCr * 256.0))&0x7ff)<<20; + dwOvLuma = (((INT32)(OvLuma * 256.0))&0xfff)<<20; + dwOvRCb = (((INT32)(OvRCb * 256.0))&0xfff)<<4; + dwOvRCr = (((INT32)(OvRCr * 256.0))&0xfff)<<20; + dwOvGCb = (((INT32)(OvGCb * 256.0))&0xfff)<<4; + dwOvGCr = (((INT32)(OvGCr * 256.0))&0xfff)<<20; + dwOvBCb = (((INT32)(OvBCb * 256.0))&0xfff)<<4; + dwOvBCr = (((INT32)(OvBCr * 256.0))&0xfff)<<20; } + + /* set gamma */ + RADEONSetOverlayGamma(pScrn, GAMMA); + + /* color transforms */ OUTREG(RADEON_OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); OUTREG(RADEON_OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); OUTREG(RADEON_OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); @@ -333,6 +825,58 @@ OUTREG(RADEON_OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); } +static void RADEONSetOverlayAlpha(ScrnInfoPtr pScrn, int ov_alpha, int gr_alpha, int alpha_mode) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + if (alpha_mode == 0) { /* key mode */ + OUTREG(RADEON_OV0_KEY_CNTL, + RADEON_GRAPHIC_KEY_FN_EQ | /* what does this do? */ + RADEON_VIDEO_KEY_FN_FALSE | /* what does this do? */ + RADEON_CMP_MIX_OR); + /* crtc 1 */ + OUTREG(RADEON_DISP_MERGE_CNTL, + (RADEON_DISP_ALPHA_MODE_KEY & + RADEON_DISP_ALPHA_MODE_MASK) | + ((gr_alpha << 0x00000010) & + RADEON_DISP_GRPH_ALPHA_MASK) | + ((ov_alpha << 0x00000018) & + RADEON_DISP_OV0_ALPHA_MASK)); + /* crtc 2 */ + OUTREG(RADEON_DISP2_MERGE_CNTL, + (RADEON_DISP_ALPHA_MODE_KEY & + RADEON_DISP_ALPHA_MODE_MASK) | + ((gr_alpha << 0x00000010) & + RADEON_DISP_GRPH_ALPHA_MASK) | + ((ov_alpha << 0x00000018) & + RADEON_DISP_OV0_ALPHA_MASK)); + } else { /* global mode */ + OUTREG(RADEON_OV0_KEY_CNTL, + RADEON_GRAPHIC_KEY_FN_FALSE | /* what does this do? */ + RADEON_VIDEO_KEY_FN_FALSE | /* what does this do? */ + RADEON_CMP_MIX_AND); + /* crtc 2 */ + OUTREG(RADEON_DISP2_MERGE_CNTL, + (RADEON_DISP_ALPHA_MODE_GLOBAL & + RADEON_DISP_ALPHA_MODE_MASK) | + ((gr_alpha << 0x00000010) & + RADEON_DISP_GRPH_ALPHA_MASK) | + ((ov_alpha << 0x00000018) & + RADEON_DISP_OV0_ALPHA_MASK)); + /* crtc 1 */ + OUTREG(RADEON_DISP_MERGE_CNTL, + (RADEON_DISP_ALPHA_MODE_GLOBAL & + RADEON_DISP_ALPHA_MODE_MASK) | + ((gr_alpha << 0x00000010) & + RADEON_DISP_GRPH_ALPHA_MASK) | + ((ov_alpha << 0x00000018) & + RADEON_DISP_OV0_ALPHA_MASK)); + } + /* per-pixel mode - RADEON_DISP_ALPHA_MODE_PER_PIXEL */ + /* not yet supported */ +} + static void RADEONSetColorKey(ScrnInfoPtr pScrn, CARD32 colorKey) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -375,14 +919,52 @@ RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; RADEONPortPrivPtr pPriv = info->adaptor->pPortPrivates[0].ptr; + char tmp[200]; - if (info->accelOn) info->accel->Sync(pScrn); + /* this function is called from ScreenInit. pScreen is used + by XAA internally, but not valid until ScreenInit finishs. + */ + if (info->accelOn && pScrn->pScreen && info->accel) + (*info->accel->Sync)(pScrn); - RADEONWaitForIdleMMIO(pScrn); - OUTREG(RADEON_OV0_SCALE_CNTL, 0x80000000); + /* this is done here because each time the server is reset these + could change.. Otherwise they remain constant */ + xvInstanceID = MAKE_ATOM("XV_INSTANCE_ID"); + xvDeviceID = MAKE_ATOM("XV_DEVICE_ID"); + xvLocationID = MAKE_ATOM("XV_LOCATION_ID"); + + xvBrightness = MAKE_ATOM("XV_BRIGHTNESS"); + xvSaturation = MAKE_ATOM("XV_SATURATION"); + xvColor = MAKE_ATOM("XV_COLOR"); + xvContrast = MAKE_ATOM("XV_CONTRAST"); + xvColorKey = MAKE_ATOM("XV_COLORKEY"); + xvDoubleBuffer = MAKE_ATOM("XV_DOUBLE_BUFFER"); + xvHue = MAKE_ATOM("XV_HUE"); + xvRedIntensity = MAKE_ATOM("XV_RED_INTENSITY"); + xvGreenIntensity = MAKE_ATOM("XV_GREEN_INTENSITY"); + xvBlueIntensity = MAKE_ATOM("XV_BLUE_INTENSITY"); + xvGamma = MAKE_ATOM("XV_GAMMA"); + xvColorspace = MAKE_ATOM("XV_COLORSPACE"); + + xvAutopaintColorkey = MAKE_ATOM("XV_AUTOPAINT_COLORKEY"); + xvSetDefaults = MAKE_ATOM("XV_SET_DEFAULTS"); + xvSwitchCRT = MAKE_ATOM("XV_SWITCHCRT"); + + xvOvAlpha = MAKE_ATOM("XV_OVERLAY_ALPHA"); + xvGrAlpha = MAKE_ATOM("XV_GRAPHICS_ALPHA"); + xvAlphaMode = MAKE_ATOM("XV_ALPHA_MODE"); + + sprintf(tmp, "RXXX:%d.%d.%d", info->PciInfo->vendor, info->PciInfo->chipType, info->PciInfo->chipRev); + pPriv->device_id = MAKE_ATOM(tmp); + sprintf(tmp, "PCI:%02d:%02d.%d", info->PciInfo->bus, info->PciInfo->device, info->PciInfo->func); + pPriv->location_id = MAKE_ATOM(tmp); + sprintf(tmp, "INSTANCE:%d", pScrn->scrnIndex); + pPriv->instance_id = MAKE_ATOM(tmp); + + OUTREG(RADEON_OV0_SCALE_CNTL, RADEON_SCALER_SOFT_RESET); OUTREG(RADEON_OV0_AUTO_FLIP_CNTL, 0); /* maybe */ OUTREG(RADEON_OV0_EXCLUSIVE_HORZ, 0); - OUTREG(RADEON_OV0_FILTER_CNTL, 0x0000000f); + OUTREG(RADEON_OV0_FILTER_CNTL, RADEON_FILTER_PROGRAMMABLE_COEF); OUTREG(RADEON_OV0_KEY_CNTL, RADEON_GRAPHIC_KEY_FN_EQ | RADEON_VIDEO_KEY_FN_FALSE | RADEON_CMP_MIX_OR); @@ -391,12 +973,16 @@ OUTREG(RADEON_CAP0_TRIG_CNTL, 0); RADEONSetColorKey(pScrn, pPriv->colorKey); - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350) || - (info->ChipFamily == CHIP_FAMILY_R200) || - (info->ChipFamily == CHIP_FAMILY_RADEON)) { - int i; + if (info->ChipFamily == CHIP_FAMILY_RADEON) { + + OUTREG(RADEON_OV0_LIN_TRANS_A, 0x12a00000); + OUTREG(RADEON_OV0_LIN_TRANS_B, 0x1990190e); + OUTREG(RADEON_OV0_LIN_TRANS_C, 0x12a0f9c0); + OUTREG(RADEON_OV0_LIN_TRANS_D, 0xf3000442); + OUTREG(RADEON_OV0_LIN_TRANS_E, 0x12a02040); + OUTREG(RADEON_OV0_LIN_TRANS_F, 0x175f); + + } else { OUTREG(RADEON_OV0_LIN_TRANS_A, 0x12a20000); OUTREG(RADEON_OV0_LIN_TRANS_B, 0x198a190e); @@ -404,28 +990,17 @@ OUTREG(RADEON_OV0_LIN_TRANS_D, 0xf2fe0442); OUTREG(RADEON_OV0_LIN_TRANS_E, 0x12a22046); OUTREG(RADEON_OV0_LIN_TRANS_F, 0x175f); - + } /* - * Set default Gamma ramp: + * Set default gamma ramp: * * Of 18 segments for gamma curve, all segments in R200 (and * newer) are programmable, while only lower 4 and upper 2 * segments are programmable in the older Radeons. */ - for (i = 0; i < 18; i++) { - OUTREG(def_gamma[i].gammaReg, - (def_gamma[i].gammaSlope<<16) | def_gamma[i].gammaOffset); - } - } else { - OUTREG(RADEON_OV0_LIN_TRANS_A, 0x12a00000); - OUTREG(RADEON_OV0_LIN_TRANS_B, 0x1990190e); - OUTREG(RADEON_OV0_LIN_TRANS_C, 0x12a0f9c0); - OUTREG(RADEON_OV0_LIN_TRANS_D, 0xf3000442); - OUTREG(RADEON_OV0_LIN_TRANS_E, 0x12a02040); - OUTREG(RADEON_OV0_LIN_TRANS_F, 0x175f); - } -} + RADEONSetOverlayGamma(pScrn, 0); /* gamma = 1.0 */ +} static XF86VideoAdaptorPtr RADEONAllocAdaptor(ScrnInfoPtr pScrn) @@ -433,7 +1008,7 @@ XF86VideoAdaptorPtr adapt; RADEONInfoPtr info = RADEONPTR(pScrn); RADEONPortPrivPtr pPriv; - unsigned char *RADEONMMIO = info->MMIO; + CARD32 dot_clock; if(!(adapt = xf86XVAllocateVideoAdaptorRec(pScrn))) return NULL; @@ -460,30 +1035,59 @@ pPriv->hue = 0; pPriv->currentBuffer = 0; pPriv->autopaint_colorkey = TRUE; + pPriv->gamma = 1000; + if (info->OverlayOnCRTC2) + pPriv->crt2 = TRUE; + else + pPriv->crt2 = FALSE; + + pPriv->ov_alpha = 255; + pPriv->gr_alpha = 255; + pPriv->alpha_mode = 0; /* * Unlike older Mach64 chips, RADEON has only two ECP settings: * 0 for PIXCLK < 175Mhz, and 1 (divide by 2) * for higher clocks, sure makes life nicer */ - if(info->ModeReg.dot_clock_freq < 17500) + + /* Figure out which head we are on */ + if ((info->MergedFB && info->OverlayOnCRTC2) || info->IsSecondary) + dot_clock = info->ModeReg.dot_clock_freq_2; + else + dot_clock = info->ModeReg.dot_clock_freq; + + if(dot_clock < 17500) pPriv->ecp_div = 0; else pPriv->ecp_div = 1; -#if 0 - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dotclock is %g Mhz, setting ecp_div to %d\n", info->ModeReg.dot_clock_freq/100.0, pPriv->ecp_div); -#endif + OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & + 0xfffffCff) | (pPriv->ecp_div << 8)); + + /* I suspect we may need a usleep after writing to the PLL. if you play a video too soon + after switching crtcs in mergedfb clone mode you get a temporary one pixel line of colorkey + on the right edge video output. */ - OUTPLL(RADEON_VCLK_ECP_CNTL, (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & - 0xfffffCff) | (pPriv->ecp_div << 8)); if ((info->ChipFamily == CHIP_FAMILY_RS100) || (info->ChipFamily == CHIP_FAMILY_RS200) || (info->ChipFamily == CHIP_FAMILY_RS300)) { - /* Force the overlay clock on for integrated chips + /* Force the overlay clock on for integrated chips */ - OUTPLL(RADEON_VCLK_ECP_CNTL, (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) | (1<<18))); + OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, + (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) | (1<<18))); + } + + /* overlay scaler line length differs for different revisions + this needs to be maintained by hand */ + switch(info->ChipFamily){ + case CHIP_FAMILY_R200: + case CHIP_FAMILY_R300: + pPriv->overlay_scaler_buffer_width=1920; + break; + default: + pPriv->overlay_scaler_buffer_width=1536; } info->adaptor = adapt; @@ -527,20 +1131,6 @@ pPriv = (RADEONPortPrivPtr)(adapt->pPortPrivates[0].ptr); REGION_NULL(pScreen, &(pPriv->clip)); - xvBrightness = MAKE_ATOM("XV_BRIGHTNESS"); - xvSaturation = MAKE_ATOM("XV_SATURATION"); - xvColor = MAKE_ATOM("XV_COLOR"); - xvContrast = MAKE_ATOM("XV_CONTRAST"); - xvColorKey = MAKE_ATOM("XV_COLORKEY"); - xvDoubleBuffer = MAKE_ATOM("XV_DOUBLE_BUFFER"); - xvHue = MAKE_ATOM("XV_HUE"); - xvRedIntensity = MAKE_ATOM("XV_RED_INTENSITY"); - xvGreenIntensity = MAKE_ATOM("XV_GREEN_INTENSITY"); - xvBlueIntensity = MAKE_ATOM("XV_BLUE_INTENSITY"); - - xvAutopaintColorkey = MAKE_ATOM("XV_AUTOPAINT_COLORKEY"); - xvSetDefaults = MAKE_ATOM("XV_SET_DEFAULTS"); - RADEONResetVideo(pScrn); return adapt; @@ -560,9 +1150,9 @@ RADEONWaitForFifo(pScrn, 2); OUTREG(RADEON_OV0_SCALE_CNTL, 0); } - if(info->videoLinear) { - xf86FreeOffscreenLinear(info->videoLinear); - info->videoLinear = NULL; + if (info->videoLinear != NULL) { + xf86FreeOffscreenLinear(info->videoLinear); + info->videoLinear = NULL; } pPriv->videoStatus = 0; } else { @@ -582,15 +1172,16 @@ RADEONInfoPtr info = RADEONPTR(pScrn); RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; Bool setTransform = FALSE; + Bool setAlpha = FALSE; - info->accel->Sync(pScrn); + if (info->accel) + (*info->accel->Sync)(pScrn); #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) #define RTFBrightness(a) (((a)*1.0)/2000.0) #define RTFIntensity(a) (((a)*1.0)/2000.0) #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) #define RTFHue(a) (((a)*3.1416)/1000.0) -#define ClipValue(v,min,max) ((v) < (min) ? (min) : (v) > (max) ? (max) : (v)) if(attribute == xvAutopaintColorkey) { @@ -606,8 +1197,18 @@ pPriv->red_intensity = 0; pPriv->green_intensity = 0; pPriv->blue_intensity = 0; + pPriv->gamma = 1000; + pPriv->transform_index = 0; pPriv->doubleBuffer = FALSE; + pPriv->ov_alpha = 255; + pPriv->gr_alpha = 255; + pPriv->alpha_mode = 0; + + /* It is simpler to call itself */ + RADEONSetPortAttribute(pScrn, xvDoubleBuffer, 1, data); + setTransform = TRUE; + setAlpha = TRUE; } else if(attribute == xvBrightness) { @@ -644,10 +1245,19 @@ pPriv->blue_intensity = ClipValue (value, -1000, 1000); setTransform = TRUE; } + else if(attribute == xvGamma) + { + pPriv->gamma = ClipValue (value, 100, 10000); + setTransform = TRUE; + } + else if(attribute == xvColorspace) + { + pPriv->transform_index = ClipValue (value, 0, 1); + setTransform = TRUE; + } else if(attribute == xvDoubleBuffer) { pPriv->doubleBuffer = ClipValue (value, 0, 1); - pPriv->doubleBuffer = value; } else if(attribute == xvColorKey) { @@ -655,6 +1265,30 @@ RADEONSetColorKey (pScrn, pPriv->colorKey); REGION_EMPTY(pScrn->pScreen, &pPriv->clip); } + else if(attribute == xvSwitchCRT) + { + pPriv->crt2 = ClipValue (value, 0, 1); + pPriv->crt2 = value; + if (pPriv->crt2) + info->OverlayOnCRTC2 = TRUE; + else + info->OverlayOnCRTC2 = FALSE; + } + else if(attribute == xvOvAlpha) + { + pPriv->ov_alpha = ClipValue (value, 0, 255); + setAlpha = TRUE; + } + else if(attribute == xvGrAlpha) + { + pPriv->gr_alpha = ClipValue (value, 0, 255); + setAlpha = TRUE; + } + else if(attribute == xvAlphaMode) + { + pPriv->alpha_mode = ClipValue (value, 0, 1); + setAlpha = TRUE; + } else return BadMatch; @@ -668,7 +1302,13 @@ RTFIntensity(pPriv->red_intensity), RTFIntensity(pPriv->green_intensity), RTFIntensity(pPriv->blue_intensity), - pPriv->transform_index); + pPriv->transform_index, + pPriv->gamma); + } + + if (setAlpha) + { + RADEONSetOverlayAlpha(pScrn, pPriv->ov_alpha, pPriv->gr_alpha, pPriv->alpha_mode); } return Success; @@ -683,7 +1323,8 @@ RADEONInfoPtr info = RADEONPTR(pScrn); RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; - if (info->accelOn) info->accel->Sync(pScrn); + if (info->accelOn && info->accel) + (*info->accel->Sync)(pScrn); if(attribute == xvAutopaintColorkey) *value = pPriv->autopaint_colorkey; @@ -701,10 +1342,28 @@ *value = pPriv->green_intensity; else if(attribute == xvBlueIntensity) *value = pPriv->blue_intensity; + else if(attribute == xvGamma) + *value = pPriv->gamma; + else if(attribute == xvColorspace) + *value = pPriv->transform_index; else if(attribute == xvDoubleBuffer) *value = pPriv->doubleBuffer ? 1 : 0; else if(attribute == xvColorKey) *value = pPriv->colorKey; + else if(attribute == xvSwitchCRT) + *value = pPriv->crt2 ? 1 : 0; + else if(attribute == xvOvAlpha) + *value = pPriv->ov_alpha; + else if(attribute == xvGrAlpha) + *value = pPriv->gr_alpha; + else if(attribute == xvAlphaMode) + *value = pPriv->alpha_mode; + else if(attribute == xvDeviceID) + *value = pPriv->device_id; + else if(attribute == xvLocationID) + *value = pPriv->location_id; + else if(attribute == xvInstanceID) + *value = pPriv->instance_id; else return BadMatch; @@ -729,115 +1388,421 @@ *p_h = drw_h; } +static struct { + double range; + signed char coeff[5][4]; + } TapCoeffs[]= + { + {0.25, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.26, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.27, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.28, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.29, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.30, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.31, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.32, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.33, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.34, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.35, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.36, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.37, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.38, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.39, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.40, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.41, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.42, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.43, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.44, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.45, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.46, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.47, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.48, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.49, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.50, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.51, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 2, 14, 14, 2}, }}, + {0.52, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 5, 16, 11, 0}, { 3, 15, 13, 1}, { 2, 14, 14, 2}, }}, + {0.53, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 5, 16, 11, 0}, { 3, 15, 13, 1}, { 2, 14, 14, 2}, }}, + {0.54, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 4, 17, 11, 0}, { 3, 15, 13, 1}, { 2, 14, 14, 2}, }}, + {0.55, {{ 7, 18, 7, 0}, { 6, 17, 9, 0}, { 4, 17, 11, 0}, { 3, 15, 13, 1}, { 1, 15, 15, 1}, }}, + {0.56, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.57, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.58, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.59, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.60, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.61, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.62, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.63, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.64, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 12, -1}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.65, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 12, -1}, { 2, 17, 13, 0}, { 0, 16, 16, 0}, }}, + {0.66, {{ 7, 18, 8, -1}, { 6, 18, 10, -2}, { 4, 17, 12, -1}, { 2, 17, 13, 0}, { 0, 16, 16, 0}, }}, + {0.67, {{ 7, 20, 7, -2}, { 5, 19, 10, -2}, { 3, 18, 12, -1}, { 2, 17, 13, 0}, { 0, 16, 16, 0}, }}, + {0.68, {{ 7, 20, 7, -2}, { 5, 19, 10, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }}, + {0.69, {{ 7, 20, 7, -2}, { 5, 19, 10, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }}, + {0.70, {{ 7, 20, 7, -2}, { 5, 20, 9, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }}, + {0.71, {{ 7, 20, 7, -2}, { 5, 20, 9, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }}, + {0.72, {{ 7, 20, 7, -2}, { 5, 20, 9, -2}, { 2, 20, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, + {0.73, {{ 7, 20, 7, -2}, { 4, 21, 9, -2}, { 2, 20, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, + {0.74, {{ 6, 22, 6, -2}, { 4, 21, 9, -2}, { 2, 20, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, + {0.75, {{ 6, 22, 6, -2}, { 4, 21, 9, -2}, { 1, 21, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, + {0.76, {{ 6, 22, 6, -2}, { 4, 21, 9, -2}, { 1, 21, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, + {0.77, {{ 6, 22, 6, -2}, { 3, 22, 9, -2}, { 1, 22, 12, -3}, { 0, 19, 15, -2}, {-2, 18, 18, -2}, }}, + {0.78, {{ 6, 21, 6, -1}, { 3, 22, 9, -2}, { 1, 22, 12, -3}, { 0, 19, 15, -2}, {-2, 18, 18, -2}, }}, + {0.79, {{ 5, 23, 5, -1}, { 3, 22, 9, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-2, 18, 18, -2}, }}, + {0.80, {{ 5, 23, 5, -1}, { 3, 23, 8, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-2, 18, 18, -2}, }}, + {0.81, {{ 5, 23, 5, -1}, { 2, 24, 8, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-2, 18, 18, -2}, }}, + {0.82, {{ 5, 23, 5, -1}, { 2, 24, 8, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-3, 19, 19, -3}, }}, + {0.83, {{ 5, 23, 5, -1}, { 2, 24, 8, -2}, { 0, 23, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, + {0.84, {{ 4, 25, 4, -1}, { 1, 25, 8, -2}, { 0, 23, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, + {0.85, {{ 4, 25, 4, -1}, { 1, 25, 8, -2}, { 0, 23, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, + {0.86, {{ 4, 24, 4, 0}, { 1, 25, 7, -1}, {-1, 24, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, + {0.87, {{ 4, 24, 4, 0}, { 1, 25, 7, -1}, {-1, 24, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, + {0.88, {{ 3, 26, 3, 0}, { 0, 26, 7, -1}, {-1, 24, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.89, {{ 3, 26, 3, 0}, { 0, 26, 7, -1}, {-1, 24, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.90, {{ 3, 26, 3, 0}, { 0, 26, 7, -1}, {-2, 25, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.91, {{ 3, 26, 3, 0}, { 0, 27, 6, -1}, {-2, 25, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.92, {{ 2, 28, 2, 0}, { 0, 27, 6, -1}, {-2, 25, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.93, {{ 2, 28, 2, 0}, { 0, 26, 6, 0}, {-2, 25, 10, -1}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.94, {{ 2, 28, 2, 0}, { 0, 26, 6, 0}, {-2, 25, 10, -1}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.95, {{ 1, 30, 1, 0}, {-1, 28, 5, 0}, {-3, 26, 10, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }}, + {0.96, {{ 1, 30, 1, 0}, {-1, 28, 5, 0}, {-3, 26, 10, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }}, + {0.97, {{ 1, 30, 1, 0}, {-1, 28, 5, 0}, {-3, 26, 10, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }}, + {0.98, {{ 1, 30, 1, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }}, + {0.99, {{ 0, 32, 0, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-4, 24, 14, -2}, {-3, 19, 19, -3}, }}, + {1.00, {{ 0, 32, 0, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-4, 24, 14, -2}, {-3, 19, 19, -3}, }} + }; + static void RADEONCopyData( + ScrnInfoPtr pScrn, + unsigned char *src, + unsigned char *dst, + unsigned int srcPitch, + unsigned int dstPitch, + unsigned int h, + unsigned int w, + unsigned int bpp +){ + RADEONInfoPtr info = RADEONPTR(pScrn); +#ifdef XF86DRI + + if ( info->directRenderingEnabled && info->DMAForXv ) + { + CARD8 *buf; + CARD32 bufPitch, dstPitchOff; + int x, y; + unsigned int hpass; + + /* Get the byte-swapping right for big endian systems */ + if ( bpp == 2 ) + { + w *= 2; + bpp = 1; + } + + RADEONHostDataParams( pScrn, dst, dstPitch, bpp, &dstPitchOff, &x, &y ); + + while ( (buf = RADEONHostDataBlit( pScrn, bpp, w, dstPitchOff, &bufPitch, + x, &y, &h, &hpass )) ) + { + RADEONHostDataBlitCopyPass( pScrn, bpp, buf, src, hpass, bufPitch, + srcPitch ); + src += hpass * srcPitch; + } + + FLUSH_RING(); + + return; + } + else +#endif /* XF86DRI */ + { +#if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; + unsigned int swapper = info->ModeReg.surface_cntl & + ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP | + RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP); + + switch(bpp) { + case 2: + swapper |= RADEON_NONSURF_AP0_SWP_16BPP + | RADEON_NONSURF_AP1_SWP_16BPP; + break; + case 4: + swapper |= RADEON_NONSURF_AP0_SWP_32BPP + | RADEON_NONSURF_AP1_SWP_32BPP; + break; + } + OUTREG(RADEON_SURFACE_CNTL, swapper); +#endif + w *= bpp; + + while (h--) { + memcpy(dst, src, w); + src += srcPitch; + dst += dstPitch; + } + +#if X_BYTE_ORDER == X_BIG_ENDIAN + /* restore byte swapping */ + OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); +#endif + } +} + +#ifdef XF86DRI +static void RADEON_420_422( + unsigned int *d, + unsigned char *s1, + unsigned char *s2, + unsigned char *s3, + unsigned int n +) +{ + while ( n ) { + *(d++) = s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24); + s1+=2; s2++; s3++; + n--; + } +} +#endif + +static void +RADEONCopyRGB24Data( + ScrnInfoPtr pScrn, unsigned char *src, unsigned char *dst, - int srcPitch, - int dstPitch, - int h, - int w + unsigned int srcPitch, + unsigned int dstPitch, + unsigned int h, + unsigned int w ){ - w <<= 1; - while(h--) { - memcpy(dst, src, w); - src += srcPitch; - dst += dstPitch; + CARD32 *dptr; + CARD8 *sptr = 0; + unsigned int i,j; + RADEONInfoPtr info = RADEONPTR(pScrn); +#ifdef XF86DRI + + if ( info->directRenderingEnabled && info->DMAForXv ) + { + CARD32 bufPitch, dstPitchOff; + int x, y; + unsigned int hpass; + + /* XXX Fix endian flip on R300 */ + + RADEONHostDataParams( pScrn, dst, dstPitch, 4, &dstPitchOff, &x, &y ); + + while ( (dptr = ( CARD32* )RADEONHostDataBlit( pScrn, 4, w, dstPitch, + &bufPitch, x, &y, &h, + &hpass )) ) + { + for( j = 0; j < hpass; j++ ) + { + sptr = src; + + for ( i = 0 ; i < w; i++, sptr += 3 ) + { + *dptr++ = (sptr[0] << 24) | (sptr[1] << 16) | sptr[2]; + } + + src += hpass * srcPitch; + dptr += hpass * bufPitch; + } + } + + FLUSH_RING(); + + return; + } + else +#endif /* XF86DRI */ + { +#if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; + OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl + | RADEON_NONSURF_AP0_SWP_32BPP) + & ~RADEON_NONSURF_AP0_SWP_16BPP); +#endif + + for(j=0;j<h;j++){ + dptr=(CARD32 *)(pointer)(dst+j*dstPitch); + sptr=src+j*srcPitch; + + for(i=w;i>0;i--){ + dptr[0]=((sptr[0])<<24)|((sptr[1])<<16)|(sptr[2]); + dptr++; + sptr+=3; + } + } + +#if X_BYTE_ORDER == X_BIG_ENDIAN + /* restore byte swapping */ + OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); +#endif } } static void RADEONCopyMungedData( + ScrnInfoPtr pScrn, unsigned char *src1, unsigned char *src2, unsigned char *src3, unsigned char *dst1, - int srcPitch, - int srcPitch2, - int dstPitch, - int h, - int w + unsigned int srcPitch, + unsigned int srcPitch2, + unsigned int dstPitch, + unsigned int h, + unsigned int w ){ - CARD32 *dst; - CARD8 *s1, *s2, *s3; - int i, j; - - w >>= 1; - - for(j = 0; j < h; j++) { - dst = (pointer)dst1; - s1 = src1; s2 = src2; s3 = src3; - i = w; - while(i > 4) { - dst[0] = s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24); - dst[1] = s1[2] | (s1[3] << 16) | (s3[1] << 8) | (s2[1] << 24); - dst[2] = s1[4] | (s1[5] << 16) | (s3[2] << 8) | (s2[2] << 24); - dst[3] = s1[6] | (s1[7] << 16) | (s3[3] << 8) | (s2[3] << 24); - dst += 4; s2 += 4; s3 += 4; s1 += 8; - i -= 4; - } - while(i--) { - dst[0] = s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24); - dst++; s2++; s3++; - s1 += 2; - } - - dst1 += dstPitch; - src1 += srcPitch; - if(j & 1) { - src2 += srcPitch2; - src3 += srcPitch2; + RADEONInfoPtr info = RADEONPTR(pScrn); +#ifdef XF86DRI + + if ( info->directRenderingEnabled && info->DMAForXv ) + { + CARD8 *buf; + CARD32 y = 0, bufPitch, dstPitchOff; + int blitX, blitY; + unsigned int hpass; + + /* XXX Fix endian flip on R300 */ + + RADEONHostDataParams( pScrn, dst1, dstPitch, 4, &dstPitchOff, &blitX, &blitY ); + + while ( (buf = RADEONHostDataBlit( pScrn, 4, w/2, dstPitchOff, &bufPitch, + blitX, &blitY, &h, &hpass )) ) + { + while ( hpass-- ) + { + RADEON_420_422( (unsigned int *) (pointer) buf, + src1, src2, src3, bufPitch / 4 ); + src1 += srcPitch; + if ( y & 1 ) + { + src2 += srcPitch2; + src3 += srcPitch2; + } + buf += bufPitch; + y++; + } } - } -} + FLUSH_RING(); + } + else +#endif /* XF86DRI */ + { + CARD32 *dst; + CARD8 *s1, *s2, *s3; + unsigned int i, j; + +#if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; + OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl + | RADEON_NONSURF_AP0_SWP_32BPP) + & ~RADEON_NONSURF_AP0_SWP_16BPP); +#endif -static FBLinearPtr + w /= 2; + + for( j = 0; j < h; j++ ) + { + dst = (pointer)dst1; + s1 = src1; s2 = src2; s3 = src3; + i = w; + while( i > 4 ) + { + dst[0] = s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24); + dst[1] = s1[2] | (s1[3] << 16) | (s3[1] << 8) | (s2[1] << 24); + dst[2] = s1[4] | (s1[5] << 16) | (s3[2] << 8) | (s2[2] << 24); + dst[3] = s1[6] | (s1[7] << 16) | (s3[3] << 8) | (s2[3] << 24); + dst += 4; s2 += 4; s3 += 4; s1 += 8; + i -= 4; + } + while( i-- ) + { + dst[0] = s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24); + dst++; s2++; s3++; + s1 += 2; + } + + dst1 += dstPitch; + src1 += srcPitch; + if( j & 1 ) + { + src2 += srcPitch2; + src3 += srcPitch2; + } + } +#if X_BYTE_ORDER == X_BIG_ENDIAN + /* restore byte swapping */ + OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); +#endif + } +} + +/* Allocates memory, either by resizing the allocation pointed to by mem_struct, + * or by freeing mem_struct (if non-NULL) and allocating a new space. The size + * is measured in bytes, and the offset from the beginning of card space is + * returned. + */ +static CARD32 RADEONAllocateMemory( ScrnInfoPtr pScrn, - FBLinearPtr linear, + FBLinearPtr *linear, int size ){ - ScreenPtr pScreen; - FBLinearPtr new_linear; + ScreenPtr pScreen; + RADEONInfoPtr info = RADEONPTR(pScrn); + int offset = 0; + int cpp = info->CurrentLayout.bitsPerPixel / 8; - if(linear) { - if(linear->size >= size) - return linear; + pScreen = screenInfo.screens[pScrn->scrnIndex]; - if(xf86ResizeOffscreenLinear(linear, size)) - return linear; + /* XAA allocates in units of pixels at the screen bpp, so adjust size + * appropriately. + */ + size = (size + cpp - 1) / cpp; - xf86FreeOffscreenLinear(linear); - } + if (*linear) { + if ((*linear)->size >= size) + return (*linear)->offset * cpp; - pScreen = screenInfo.screens[pScrn->scrnIndex]; + if (xf86ResizeOffscreenLinear(*linear, size)) + return (*linear)->offset * cpp; - new_linear = xf86AllocateOffscreenLinear(pScreen, size, 16, - NULL, NULL, NULL); + xf86FreeOffscreenLinear(*linear); + } - if(!new_linear) { + *linear = xf86AllocateOffscreenLinear(pScreen, size, 16, NULL, NULL, NULL); + + if (!*linear) { int max_size; xf86QueryLargestOffscreenLinear(pScreen, &max_size, 16, - PRIORITY_EXTREME); + PRIORITY_EXTREME); - if(max_size < size) - return NULL; + if (max_size < size) + return 0; xf86PurgeUnlockedOffscreenAreas(pScreen); - new_linear = xf86AllocateOffscreenLinear(pScreen, size, 16, - NULL, NULL, NULL); - } + *linear = xf86AllocateOffscreenLinear(pScreen, size, 16, + NULL, NULL, NULL); + if (!*linear) + return 0; + } + offset = (*linear)->offset * cpp; - return new_linear; + return offset; } static void RADEONDisplayVideo( ScrnInfoPtr pScrn, + RADEONPortPrivPtr pPriv, int id, int offset1, int offset2, + int offset3, int offset4, short width, short height, int pitch, int left, int right, int top, @@ -847,118 +1812,236 @@ ){ RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - int v_inc, h_inc, step_by, tmp; + CARD32 v_inc, h_inc, h_inc_uv, step_by_y, step_by_uv, tmp; + double h_inc_d; int p1_h_accum_init, p23_h_accum_init; int p1_v_accum_init; int ecp_div; int v_inc_shift; int y_mult; int x_off; + int y_off; CARD32 scaler_src; + CARD32 dot_clock; + DisplayModePtr overlay_mode; + int is_rgb; + int i; + CARD32 scale_cntl; + double dsr; + int tap_set; + + is_rgb=0; + switch(id){ + case FOURCC_RGBA32: + case FOURCC_RGB24: + case FOURCC_RGBT16: + case FOURCC_RGB16: + is_rgb=1; + break; + default: + break; + } /* Unlike older Mach64 chips, RADEON has only two ECP settings: 0 for PIXCLK < 175Mhz, and 1 (divide by 2) for higher clocks, sure makes life nicer Here we need to find ecp_div again, as the user may have switched resolutions */ - if(info->ModeReg.dot_clock_freq < 17500) + + /* Figure out which head we are on for dot clock */ + if ((info->MergedFB && info->OverlayOnCRTC2) || info->IsSecondary) + dot_clock = info->ModeReg.dot_clock_freq_2; + else + dot_clock = info->ModeReg.dot_clock_freq; + + if (dot_clock < 17500) ecp_div = 0; else ecp_div = 1; - OUTPLL(RADEON_VCLK_ECP_CNTL, (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & 0xfffffCff) | (ecp_div << 8)); + OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, + (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & 0xfffffCff) | (ecp_div << 8)); + + /* I suspect we may need a usleep after writing to the PLL. if you play a video too soon + after switching crtcs in mergedfb clone mode you get a temporary one pixel line of colorkey + on the right edge video output. */ v_inc_shift = 20; - if (pScrn->currentMode->Flags & V_INTERLACE) - v_inc_shift++; - if (pScrn->currentMode->Flags & V_DBLSCAN) - v_inc_shift--; - if (pScrn->currentMode->Flags & RADEON_USE_RMX) { - v_inc = ((src_h * pScrn->currentMode->CrtcVDisplay / info->PanelYRes) << v_inc_shift) / drw_h; + y_mult = 1; + + if (info->MergedFB) { + if (info->OverlayOnCRTC2) + overlay_mode = ((RADEONMergedDisplayModePtr)(pointer)info->CurrentLayout.mode->Private)->CRT2; + else + overlay_mode = ((RADEONMergedDisplayModePtr)(pointer)info->CurrentLayout.mode->Private)->CRT1; + if (overlay_mode->Flags & V_INTERLACE) + v_inc_shift++; + if (overlay_mode->Flags & V_DBLSCAN) { + v_inc_shift--; + y_mult = 2; + } + if (overlay_mode->Flags & RADEON_USE_RMX) { + v_inc = ((src_h * overlay_mode->CrtcVDisplay / info->PanelYRes) << v_inc_shift) / drw_h; + } else { + v_inc = (src_h << v_inc_shift) / drw_h; + } } else { - v_inc = (src_h << v_inc_shift) / drw_h; + if (pScrn->currentMode->Flags & V_INTERLACE) + v_inc_shift++; + if (pScrn->currentMode->Flags & V_DBLSCAN) { + v_inc_shift--; + y_mult = 2; + } + if (pScrn->currentMode->Flags & RADEON_USE_RMX) { + v_inc = ((src_h * pScrn->currentMode->CrtcVDisplay / info->PanelYRes) << v_inc_shift) / drw_h; + } else { + v_inc = (src_h << v_inc_shift) / drw_h; + } } - h_inc = ((src_w << (12 + ecp_div)) / drw_w); - step_by = 1; - while(h_inc >= (2 << 12)) { - step_by++; + h_inc = (1 << (12 + ecp_div)); + + step_by_y = 1; + step_by_uv = step_by_y; + + /* if the source width was larger than what would fit in overlay scaler increase step_by values */ + i=src_w; + while(i>pPriv->overlay_scaler_buffer_width){ + step_by_y++; + step_by_uv++; + h_inc >>=1; + i=i/2; + } + + + h_inc_d = src_w; + h_inc_d = h_inc_d/drw_w; + /* we could do a tad better - but why + bother when this concerns downscaling and the code is so much more + hairy */ + while(h_inc*h_inc_d >= (2 << 12)) { + if(!is_rgb && (((h_inc+h_inc/2)*h_inc_d)<(2<<12))){ + step_by_uv = step_by_y+1; + break; + } + step_by_y++; + step_by_uv = step_by_y; h_inc >>= 1; - } + } + h_inc_uv = h_inc>>(step_by_uv-step_by_y); + h_inc = h_inc * h_inc_d; + h_inc_uv = h_inc_uv * h_inc_d; + /* pPriv->overlay_scaler_buffer_width is magic number - maximum line length the overlay scaler can fit + in the buffer for 2 tap filtering */ + /* the only place it is documented in is in ATI source code */ + /* we need twice as much space for 4 tap filtering.. */ + /* under special circumstances turn on 4 tap filtering */ + /* disable this code for now as it has a DISASTROUS effect on image quality when upscaling + at least on rv250 (only as long as the drw_w*2 <=... requirement is still met of course) */ +#if 0 + if(!is_rgb && (step_by_y==1) && (step_by_uv==1) && (h_inc < (1<<12)) && + (drw_w*2 <= pPriv->overlay_scaler_buffer_width)){ + step_by_y=0; + step_by_uv=1; + h_inc_uv = h_inc; + } +#endif /* keep everything in 16.16 */ offset1 += ((left >> 16) & ~7) << 1; offset2 += ((left >> 16) & ~7) << 1; + offset3 += ((left >> 16) & ~7) << 1; + offset4 += ((left >> 16) & ~7) << 1; if (info->IsSecondary) { offset1 += info->FbMapSize; offset2 += info->FbMapSize; + offset3 += info->FbMapSize; + offset4 += info->FbMapSize; } tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); p1_h_accum_init = ((tmp << 4) & 0x000f8000) | ((tmp << 12) & 0xf0000000); - tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); + tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc_uv << 2); p23_h_accum_init = ((tmp << 4) & 0x000f8000) | ((tmp << 12) & 0x70000000); tmp = (top & 0x0000ffff) + 0x00018000; - p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001; + p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | ((!is_rgb)?0x03:0x01); left = (left >> 16) & 7; RADEONWaitForFifo(pScrn, 2); - OUTREG(RADEON_OV0_REG_LOAD_CNTL, 1); - if (info->accelOn) info->accel->Sync(pScrn); - while(!(INREG(RADEON_OV0_REG_LOAD_CNTL) & (1 << 3))); - - RADEONWaitForFifo(pScrn, 14); - OUTREG(RADEON_OV0_H_INC, h_inc | ((h_inc >> 1) << 16)); - OUTREG(RADEON_OV0_STEP_BY, step_by | (step_by << 8)); + OUTREG(RADEON_OV0_REG_LOAD_CNTL, RADEON_REG_LD_CTL_LOCK); + if (info->accelOn && info->accel) + (*info->accel->Sync)(pScrn); + while(!(INREG(RADEON_OV0_REG_LOAD_CNTL) & RADEON_REG_LD_CTL_LOCK_READBACK)); + + RADEONWaitForFifo(pScrn, 10); + OUTREG(RADEON_OV0_H_INC, h_inc | ((h_inc_uv >> 1) << 16)); + OUTREG(RADEON_OV0_STEP_BY, step_by_y | (step_by_uv << 8)); - y_mult = 1; - if (pScrn->currentMode->Flags & V_DBLSCAN) - y_mult = 2; x_off = 8; + y_off = 0; - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350) || - (info->ChipFamily == CHIP_FAMILY_RV350) || - (info->ChipFamily == CHIP_FAMILY_R200)) + if (IS_R300_VARIANT || + (info->ChipFamily == CHIP_FAMILY_R200)) x_off = 0; + /* needed to make the overlay work on crtc1 in leftof and above modes */ + if (info->MergedFB) { + RADEONScrn2Rel srel = + ((RADEONMergedDisplayModePtr)(pointer)info->CurrentLayout.mode->Private)->CRT2Position; + overlay_mode = ((RADEONMergedDisplayModePtr)(pointer)info->CurrentLayout.mode->Private)->CRT2; + if (srel == radeonLeftOf) { + x_off -= overlay_mode->CrtcHDisplay; + /* y_off -= pScrn->frameY0; */ + } + if (srel == radeonAbove) { + y_off -= overlay_mode->CrtcVDisplay; + /* x_off -= pScrn->frameX0; */ + } + } + /* Put the hardware overlay on CRTC2: * * Since one hardware overlay can not be displayed on two heads * at the same time, we might need to consider using software * rendering for the second head. */ - if ((info->Clone && info->OverlayOnCRTC2) || info->IsSecondary) { + + if ((info->MergedFB && info->OverlayOnCRTC2) || info->IsSecondary) { x_off = 0; - OUTREG(RADEON_OV1_Y_X_START, ((dstBox->x1 - + x_off - - info->CloneFrameX0 - + pScrn->frameX0) | - ((dstBox->y1*y_mult - - info->CloneFrameY0 - + pScrn->frameY0) << 16))); - OUTREG(RADEON_OV1_Y_X_END, ((dstBox->x2 - + x_off - - info->CloneFrameX0 - + pScrn->frameX0) | - ((dstBox->y2*y_mult - - info->CloneFrameY0 - + pScrn->frameY0) << 16))); - scaler_src = (1 << 14); + OUTREG(RADEON_OV1_Y_X_START, ((dstBox->x1 + x_off) | + ((dstBox->y1*y_mult) << 16))); + OUTREG(RADEON_OV1_Y_X_END, ((dstBox->x2 + x_off) | + ((dstBox->y2*y_mult) << 16))); + scaler_src = RADEON_SCALER_CRTC_SEL; } else { OUTREG(RADEON_OV0_Y_X_START, ((dstBox->x1 + x_off) | - ((dstBox->y1*y_mult) << 16))); + (((dstBox->y1*y_mult) + y_off) << 16))); OUTREG(RADEON_OV0_Y_X_END, ((dstBox->x2 + x_off) | - ((dstBox->y2*y_mult) << 16))); + (((dstBox->y2*y_mult) + y_off) << 16))); scaler_src = 0; } + /* program the tap coefficients for better downscaling quality. + Could do slightly better by using hardcoded coefficients for one axis + in case only the other axis is downscaled (see RADEON_OV0_FILTER_CNTL) */ + dsr=(double)(1<<0xC)/h_inc; + if(dsr<0.25)dsr=0.25; + if(dsr>1.0)dsr=1.0; + tap_set=(int)((dsr-0.25)*100); + for(i=0;i<5;i++){ + OUTREG(RADEON_OV0_FOUR_TAP_COEF_0+i*4, (TapCoeffs[tap_set].coeff[i][0] &0xf) | + ((TapCoeffs[tap_set].coeff[i][1] &0x7f)<<8) | + ((TapCoeffs[tap_set].coeff[i][2] &0x7f)<<16) | + ((TapCoeffs[tap_set].coeff[i][3] &0xf)<<24)); + } + + RADEONWaitForFifo(pScrn, 10); OUTREG(RADEON_OV0_V_INC, v_inc); OUTREG(RADEON_OV0_P1_BLANK_LINES_AT_TOP, 0x00000fff | ((src_h - 1) << 16)); OUTREG(RADEON_OV0_VID_BUF_PITCH0_VALUE, pitch); @@ -969,38 +2052,41 @@ OUTREG(RADEON_OV0_P3_X_START_END, (src_w + left - 1) | (left << 16)); OUTREG(RADEON_OV0_VID_BUF0_BASE_ADRS, offset1 & 0xfffffff0); OUTREG(RADEON_OV0_VID_BUF1_BASE_ADRS, offset2 & 0xfffffff0); - OUTREG(RADEON_OV0_VID_BUF2_BASE_ADRS, offset1 & 0xfffffff0); + OUTREG(RADEON_OV0_VID_BUF2_BASE_ADRS, offset3 & 0xfffffff0); RADEONWaitForFifo(pScrn, 9); - OUTREG(RADEON_OV0_VID_BUF3_BASE_ADRS, offset2 & 0xfffffff0); + OUTREG(RADEON_OV0_VID_BUF3_BASE_ADRS, offset4 & 0xfffffff0); OUTREG(RADEON_OV0_VID_BUF4_BASE_ADRS, offset1 & 0xfffffff0); OUTREG(RADEON_OV0_VID_BUF5_BASE_ADRS, offset2 & 0xfffffff0); OUTREG(RADEON_OV0_P1_V_ACCUM_INIT, p1_v_accum_init); OUTREG(RADEON_OV0_P1_H_ACCUM_INIT, p1_h_accum_init); OUTREG(RADEON_OV0_P23_H_ACCUM_INIT, p23_h_accum_init); -#if 0 - if(id == FOURCC_UYVY) - OUTREG(RADEON_OV0_SCALE_CNTL, 0x41008C03); - else - OUTREG(RADEON_OV0_SCALE_CNTL, 0x41008B03); -#endif - - if (id == FOURCC_UYVY) - OUTREG(RADEON_OV0_SCALE_CNTL, (RADEON_SCALER_SOURCE_YVYU422 - | RADEON_SCALER_ADAPTIVE_DEINT - | RADEON_SCALER_SMART_SWITCH - | RADEON_SCALER_DOUBLE_BUFFER - | RADEON_SCALER_ENABLE - | scaler_src)); - else - OUTREG(RADEON_OV0_SCALE_CNTL, (RADEON_SCALER_SOURCE_VYUY422 - | RADEON_SCALER_ADAPTIVE_DEINT - | RADEON_SCALER_SMART_SWITCH - | RADEON_SCALER_DOUBLE_BUFFER - | RADEON_SCALER_ENABLE - | scaler_src)); - + scale_cntl = RADEON_SCALER_ADAPTIVE_DEINT | RADEON_SCALER_DOUBLE_BUFFER + | RADEON_SCALER_ENABLE | RADEON_SCALER_SMART_SWITCH | (0x7f<<16) | scaler_src; + switch(id){ + case FOURCC_UYVY: + scale_cntl |= RADEON_SCALER_SOURCE_YVYU422; + break; + case FOURCC_RGB24: + case FOURCC_RGBA32: + scale_cntl |= RADEON_SCALER_SOURCE_32BPP | RADEON_SCALER_LIN_TRANS_BYPASS; + break; + case FOURCC_RGB16: + scale_cntl |= RADEON_SCALER_SOURCE_16BPP | RADEON_SCALER_LIN_TRANS_BYPASS; + break; + case FOURCC_RGBT16: + scale_cntl |= RADEON_SCALER_SOURCE_15BPP | RADEON_SCALER_LIN_TRANS_BYPASS; + break; + case FOURCC_YUY2: + case FOURCC_YV12: + case FOURCC_I420: + default: + scale_cntl |= RADEON_SCALER_SOURCE_VYUY422 + | ((info->ChipFamily >= CHIP_FAMILY_R200) ? RADEON_SCALER_TEMPORAL_DEINT : 0); + break; + } + OUTREG(RADEON_OV0_SCALE_CNTL, scale_cntl); OUTREG(RADEON_OV0_REG_LOAD_CNTL, 0); } @@ -1023,16 +2109,10 @@ unsigned char *dst_start; int new_size, offset, s2offset, s3offset; int srcPitch, srcPitch2, dstPitch; - int top, left, npixels, nlines, bpp; + int top, left, npixels, nlines; + int video_offset; BoxRec dstBox; CARD32 tmp; -#if X_BYTE_ORDER == X_BIG_ENDIAN - unsigned char *RADEONMMIO = info->MMIO; - CARD32 surface_cntl = INREG(RADEON_SURFACE_CNTL); - - OUTREG(RADEON_SURFACE_CNTL, (surface_cntl | - RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); -#endif /* * s2offset, s3offset - byte offsets into U and V plane of the @@ -1064,22 +2144,42 @@ dstBox.y1 = drw_y; dstBox.y2 = drw_y + drw_h; + if (info->MergedFB) + RADEONChooseOverlayCRTC(pScrn, &dstBox); + if(!xf86XVClipVideoHelper(&dstBox, &xa, &xb, &ya, &yb, clipBoxes, width, height)) return Success; - dstBox.x1 -= pScrn->frameX0; - dstBox.x2 -= pScrn->frameX0; - dstBox.y1 -= pScrn->frameY0; - dstBox.y2 -= pScrn->frameY0; - - bpp = pScrn->bitsPerPixel >> 3; + if (info->MergedFB && info->OverlayOnCRTC2) { + dstBox.x1 -= info->CRT2pScrn->frameX0; + dstBox.x2 -= info->CRT2pScrn->frameX0; + dstBox.y1 -= info->CRT2pScrn->frameY0; + dstBox.y2 -= info->CRT2pScrn->frameY0; + } else { + dstBox.x1 -= pScrn->frameX0; + dstBox.x2 -= pScrn->frameX0; + dstBox.y1 -= pScrn->frameY0; + dstBox.y2 -= pScrn->frameY0; + } switch(id) { + case FOURCC_RGB24: + dstPitch=(width*4+0x0f)&(~0x0f); + srcPitch=width*3; + break; + case FOURCC_RGBA32: + dstPitch=(width*4+0x0f)&(~0x0f); + srcPitch=width*4; + break; + case FOURCC_RGB16: + case FOURCC_RGBT16: + dstPitch=(width*2+0x0f)&(~0x0f); + srcPitch=(width*2+3)&(~0x03); + break; case FOURCC_YV12: case FOURCC_I420: - dstPitch = ((width << 1) + 15) & ~15; - new_size = ((dstPitch * height) + bpp - 1) / bpp; + dstPitch = ((width << 1) + 63) & ~63; srcPitch = (width + 3) & ~3; s2offset = srcPitch * height; srcPitch2 = ((width >> 1) + 3) & ~3; @@ -1088,17 +2188,17 @@ case FOURCC_UYVY: case FOURCC_YUY2: default: - dstPitch = ((width << 1) + 15) & ~15; - new_size = ((dstPitch * height) + bpp - 1) / bpp; + dstPitch = ((width << 1) + 63) & ~63; srcPitch = (width << 1); break; } - if(!(info->videoLinear = RADEONAllocateMemory(pScrn, info->videoLinear, - pPriv->doubleBuffer ? (new_size << 1) : new_size))) - { - return BadAlloc; - } + new_size = dstPitch * height; + video_offset = RADEONAllocateMemory(pScrn, &info->videoLinear, + (pPriv->doubleBuffer ? + (new_size * 2) : new_size)); + if (video_offset == 0) + return BadAlloc; pPriv->currentBuffer ^= 1; @@ -1107,9 +2207,10 @@ left = (xa >> 16) & ~1; npixels = ((((xb + 0xffff) >> 16) + 1) & ~1) - left; - offset = (info->videoLinear->offset * bpp) + (top * dstPitch); + offset = video_offset + (top * dstPitch); + if(pPriv->doubleBuffer) - offset += pPriv->currentBuffer * new_size * bpp; + offset += pPriv->currentBuffer * new_size; dst_start = info->FB + offset; @@ -1127,14 +2228,12 @@ s3offset = tmp; } nlines = ((((yb + 0xffff) >> 16) + 1) & ~1) - top; -#if X_BYTE_ORDER == X_BIG_ENDIAN - OUTREG(RADEON_SURFACE_CNTL, (surface_cntl | RADEON_NONSURF_AP0_SWP_32BPP) - & ~RADEON_NONSURF_AP0_SWP_16BPP); -#endif - RADEONCopyMungedData(buf + (top * srcPitch) + left, buf + s2offset, - buf + s3offset, dst_start, srcPitch, srcPitch2, - dstPitch, nlines, npixels); + RADEONCopyMungedData(pScrn, buf + (top * srcPitch) + left, + buf + s2offset, buf + s3offset, dst_start, + srcPitch, srcPitch2, dstPitch, nlines, npixels); break; + case FOURCC_RGBT16: + case FOURCC_RGB16: case FOURCC_UYVY: case FOURCC_YUY2: default: @@ -1142,19 +2241,22 @@ buf += (top * srcPitch) + left; nlines = ((yb + 0xffff) >> 16) - top; dst_start += left; -#if X_BYTE_ORDER == X_BIG_ENDIAN - OUTREG(RADEON_SURFACE_CNTL, surface_cntl & ~(RADEON_NONSURF_AP0_SWP_32BPP - | RADEON_NONSURF_AP0_SWP_16BPP)); -#endif - RADEONCopyData(buf, dst_start, srcPitch, dstPitch, nlines, npixels); + RADEONCopyData(pScrn, buf, dst_start, srcPitch, dstPitch, nlines, npixels, 2); + break; + case FOURCC_RGBA32: + buf += (top * srcPitch) + left*4; + nlines = ((yb + 0xffff) >> 16) - top; + dst_start += left*4; + RADEONCopyData(pScrn, buf, dst_start, srcPitch, dstPitch, nlines, npixels, 4); + break; + case FOURCC_RGB24: + buf += (top * srcPitch) + left*3; + nlines = ((yb + 0xffff) >> 16) - top; + dst_start += left*4; + RADEONCopyRGB24Data(pScrn, buf, dst_start, srcPitch, dstPitch, nlines, npixels); break; } -#if X_BYTE_ORDER == X_BIG_ENDIAN - /* restore byte swapping */ - OUTREG(RADEON_SURFACE_CNTL, surface_cntl); -#endif - /* update cliplist */ if(!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) { @@ -1164,7 +2266,7 @@ xf86XVFillKeyHelper(pScrn->pScreen, pPriv->colorKey, clipBoxes); } - RADEONDisplayVideo(pScrn, id, offset, offset, width, height, dstPitch, + RADEONDisplayVideo(pScrn, pPriv, id, offset, offset, offset, offset, width, height, dstPitch, xa, xb, ya, &dstBox, src_w, src_h, drw_w, drw_h); pPriv->videoStatus = CLIENT_VIDEO_ON; @@ -1205,6 +2307,18 @@ if(offsets) offsets[2] = size; size += tmp; break; + case FOURCC_RGBA32: + size = *w << 2; + if(pitches) pitches[0] = size; + size *= *h; + break; + case FOURCC_RGB24: + size = *w * 3; + if(pitches) pitches[0] = size; + size *= *h; + break; + case FOURCC_RGBT16: + case FOURCC_RGB16: case FOURCC_UYVY: case FOURCC_YUY2: default: @@ -1233,9 +2347,9 @@ } } else { /* FREE_TIMER */ if(pPriv->freeTime < now) { - if(info->videoLinear) { - xf86FreeOffscreenLinear(info->videoLinear); - info->videoLinear = NULL; + if (info->videoLinear != NULL) { + xf86FreeOffscreenLinear(info->videoLinear); + info->videoLinear = NULL; } pPriv->videoStatus = 0; info->VideoTimerCallback = NULL; @@ -1247,7 +2361,7 @@ /****************** Offscreen stuff ***************/ typedef struct { - FBLinearPtr linear; + void *surface_memory; Bool isOn; } OffscreenPrivRec, * OffscreenPrivPtr; @@ -1259,46 +2373,46 @@ unsigned short h, XF86SurfacePtr surface ){ - FBLinearPtr linear; - int pitch, size, bpp; + int offset, pitch, size; OffscreenPrivPtr pPriv; + FBLinearPtr surface_memory = NULL; if((w > 1024) || (h > 1024)) return BadAlloc; w = (w + 1) & ~1; pitch = ((w << 1) + 15) & ~15; - bpp = pScrn->bitsPerPixel >> 3; - size = ((pitch * h) + bpp - 1) / bpp; + size = pitch * h; - if(!(linear = RADEONAllocateMemory(pScrn, NULL, size))) + offset = RADEONAllocateMemory(pScrn, &surface_memory, size); + if (offset == 0) return BadAlloc; surface->width = w; surface->height = h; if(!(surface->pitches = xalloc(sizeof(int)))) { - xf86FreeOffscreenLinear(linear); + xf86FreeOffscreenLinear(surface_memory); return BadAlloc; } if(!(surface->offsets = xalloc(sizeof(int)))) { xfree(surface->pitches); - xf86FreeOffscreenLinear(linear); + xf86FreeOffscreenLinear(surface_memory); return BadAlloc; } if(!(pPriv = xalloc(sizeof(OffscreenPrivRec)))) { xfree(surface->pitches); xfree(surface->offsets); - xf86FreeOffscreenLinear(linear); + xf86FreeOffscreenLinear(surface_memory); return BadAlloc; } - pPriv->linear = linear; + pPriv->surface_memory = surface_memory; pPriv->isOn = FALSE; surface->pScrn = pScrn; surface->id = id; surface->pitches[0] = pitch; - surface->offsets[0] = linear->offset * bpp; + surface->offsets[0] = offset; surface->devPrivate.ptr = (pointer)pPriv; return Success; @@ -1328,7 +2442,8 @@ if(pPriv->isOn) RADEONStopSurface(surface); - xf86FreeOffscreenLinear(pPriv->linear); + if (pPriv->surface_memory) + xf86FreeOffscreenLinear(pPriv->surface_memory); xfree(surface->pitches); xfree(surface->offsets); xfree(surface->devPrivate.ptr); @@ -1390,18 +2505,27 @@ dstBox.y1 = drw_y; dstBox.y2 = drw_y + drw_h; + if (info->MergedFB) + RADEONChooseOverlayCRTC(pScrn, &dstBox); + if (!xf86XVClipVideoHelper(&dstBox, &xa, &xb, &ya, &yb, clipBoxes, surface->width, surface->height)) return Success; - dstBox.x1 -= pScrn->frameX0; - dstBox.x2 -= pScrn->frameX0; - dstBox.y1 -= pScrn->frameY0; - dstBox.y2 -= pScrn->frameY0; - - RADEONResetVideo(pScrn); + if (info->MergedFB && info->OverlayOnCRTC2) { + dstBox.x1 -= info->CRT2pScrn->frameX0; + dstBox.x2 -= info->CRT2pScrn->frameX0; + dstBox.y1 -= info->CRT2pScrn->frameY0; + dstBox.y2 -= info->CRT2pScrn->frameY0; + } else { + dstBox.x1 -= pScrn->frameX0; + dstBox.x2 -= pScrn->frameX0; + dstBox.y1 -= pScrn->frameY0; + dstBox.y2 -= pScrn->frameY0; + } - RADEONDisplayVideo(pScrn, surface->id, + RADEONDisplayVideo(pScrn, portPriv, surface->id, + surface->offsets[0], surface->offsets[0], surface->offsets[0], surface->offsets[0], surface->width, surface->height, surface->pitches[0], xa, xb, ya, &dstBox, src_w, src_h, drw_w, drw_h); @@ -1443,8 +2567,8 @@ offscreenImages[0].stop = RADEONStopSurface; offscreenImages[0].setAttribute = RADEONSetSurfaceAttribute; offscreenImages[0].getAttribute = RADEONGetSurfaceAttribute; - offscreenImages[0].max_width = 1024; - offscreenImages[0].max_height = 1024; + offscreenImages[0].max_width = 2048; + offscreenImages[0].max_height = 2048; offscreenImages[0].num_attributes = NUM_ATTRIBUTES; offscreenImages[0].attributes = Attributes;