Sender: f1oat@teaser.fr
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Date: 	Sun, 14 Sep 1997 12:57:13 +0200
From: Frederic RIBLE F1OAT <frible@teaser.fr>
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To: Joerg Reuter <jreuter@lykos.oche.de>
CC: dev-hams <dev-hams@zone.pspt.fi>
Subject: scc: fix for corrupted rx frames
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Resent-Date: Sun, 14 Sep 1997 17:04:12 +0300

Hello Joerg,

  Me and some friends have seen corrupted rx frames on listen traces on
1200 bit/s half-duplex channels. We use kernel 2.0.30 with
z8530drv-2.4c.dl1bke.tar.gz and ATEPRA SCC boards. Clock source is
"divider".

  The problem is worse with a 386-SX16 than with a P5-90. Corrupted
frames appear only just after tx goes down. There is no problem in
full-duplex. So I suspect the scc_key_trx() function.  I have done a
small fix to avoid switching off the rx portion of Z8530 : this fix
cures the problem !!! May be another silicium bug of the Z8530 ...
Grrrrr %$@##"$%$ !!!

  This patched driver is running well here and on F6FBB station for some
weeks. We did not see any side effect. For purists, some code must be
added to trash rx frames when the driver is in transmit phase.

73's Frederic F1OAT.

==========================================================================================
  My fix for scc_key_trx() (against z8530drv-2.4c.dl1bke.tar.gz)
========================================================================================== 


/* ----> scc_key_trx sets the time constant for the baudrate 
         generator and keys the transmitter		     <---- */

static void
scc_key_trx(struct scc_channel *scc, char tx)
{
	unsigned int time_const;
		
	if (scc->brand & PRIMUS)
		Outb(scc->ctrl + 4, scc->option | (tx? 0x80 : 0));

	if (scc->modem.speed < 300) 
		scc->modem.speed = 1200;

	time_const = (unsigned) (scc->clock / (scc->modem.speed * (tx? 2:64)))
- 2;

	disable_irq(scc->irq);

	if (tx)
	{
		or(scc, R1, TxINT_ENAB);	/* t_maxkeyup may have reset these */
		or(scc, R15, TxUIE);
	}

	if (scc->modem.clocksrc == CLK_DPLL)
	{				/* force simplex operation */
		if (tx)
		{
			cl(scc, R3, RxENABLE|ENT_HM);	/* switch off receiver */
			cl(scc, R15, DCDIE);		/* No DCD changes, please */
			set_brg(scc, time_const);	/* reprogram baudrate generator */

			/* DPLL -> Rx clk, BRG -> Tx CLK, TRxC mode output, TRxC = BRG */
			wr(scc, R11, RCDPLL|TCBR|TRxCOI|TRxCBR);
			
			or(scc,R5,RTS|TxENAB);		/* set the RTS line and enable TX */
		} else {
			cl(scc,R5,RTS|TxENAB);
			
			set_brg(scc, time_const);	/* reprogram baudrate generator */
			
			/* DPLL -> Rx clk, DPLL -> Tx CLK, TRxC mode output, TRxC = DPLL */
			wr(scc, R11, RCDPLL|TCDPLL|TRxCOI|TRxCDP);
			
			or(scc,R3,RxENABLE|ENT_HM);
			or(scc,R15, DCDIE);
		}
	} else {
		if (tx)
		{
/* F1OAT		if (scc->kiss.fulldup == KISS_DUPLEX_HALF)
			{
				cl(scc, R3, RxENABLE);
				cl(scc, R15, DCDIE);
			}
*/				
				
			or(scc,R5,RTS|TxENAB);		/* enable tx */
		} else {
			cl(scc,R5,RTS|TxENAB);		/* disable tx */
			
/* F1OAT		if (scc->kiss.fulldup == KISS_DUPLEX_HALF)
			{
				or(scc, R3, RxENABLE|ENT_HM);
				or(scc, R15, DCDIE);
			}
*/		}
	}

	enable_irq(scc->irq);
}