diff -uprN binutils-2.12.90.0.11/ChangeLog binutils-2.12.90.0.12/ChangeLog --- binutils-2.12.90.0.11/ChangeLog Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/ChangeLog Tue Jun 18 21:41:58 2002 @@ -1,3 +1,12 @@ +2002-06-18 Dave Brolley + + * configure.in: Add support for frv. + * config.sub: Add support for frv. + +2002-06-12 Kaveh R. Ghazi + + * Makefile.in (CFLAGS_FOR_TARGET): Add -O2. + 2002-06-08 Jason Thorpe * configure.in (vax-*-netbsd*): Re-enable gas. diff -uprN binutils-2.12.90.0.11/Makefile.in binutils-2.12.90.0.12/Makefile.in --- binutils-2.12.90.0.11/Makefile.in Fri Jun 7 19:22:16 2002 +++ binutils-2.12.90.0.12/Makefile.in Tue Jun 18 21:41:58 2002 @@ -100,7 +100,11 @@ CXXFLAGS = -g -O2 LDFLAGS = LIBCFLAGS = $(CFLAGS) CFLAGS_FOR_BUILD = $(CFLAGS) -CFLAGS_FOR_TARGET = $(CFLAGS) +# During gcc bootstrap, if we use some random cc for stage1 then +# CFLAGS will be just -g. We want to ensure that TARGET libraries +# (which we know are built with gcc) are built with optimizations so +# prepend -O2 when setting CFLAGS_FOR_TARGET. +CFLAGS_FOR_TARGET = -O2 $(CFLAGS) LDFLAGS_FOR_TARGET = LIBCFLAGS_FOR_TARGET = $(CFLAGS_FOR_TARGET) PICFLAG = diff -uprN binutils-2.12.90.0.11/bfd/ChangeLog binutils-2.12.90.0.12/bfd/ChangeLog --- binutils-2.12.90.0.11/bfd/ChangeLog Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/bfd/ChangeLog Tue Jun 18 21:41:58 2002 @@ -1,3 +1,113 @@ +2002-06-18 Dave Brolley + + From Catherine Moore, Michael Meissner, Dave Brolley: + * po/SRC-POTFILES.in: Add cpu-frv.c and elf32-frv.c + * targets.c: Support bfd_elf32_frv_vec. + * reloc.c: Add FRV relocs. + * configure.in: Add support for bfd-elf32-frv-vec. + * config.bfd (targ_cpu): Add support for frv-*-elf. + * archures.c: Add frv arch and machines. + * Makefile.am (ALL_MACHINES): Add cpu-frv.lo. + (ALL_MACHINES_CFILES): Add cpu-frv.c. + (BFD32_BACKENDS): Add elf32-frv.lo. + (BFD32_BACKENDS_CFILES): Add elf32-frv.c + (cpu-frv.lo): New target. + (elf32-frv.lo): New target. + * cpu-frv.c: New file. + * elf32-frv.c: New file. + +2002-06-18 Jakub Jelinek + + * elfcode.h (elf_object_p): Sanity check eh_shoff == 0 implies + e_shnum == 0. + Only read the first section header if e_shoff is non-zero. + Don't consider e_shstrndx if there are no sections. + +2002-06-17 Tom Rix + + * elf32-d10v.c (elf_d10v_howto_table): Change R_D10V_10_PCREL_R, + R_D10V_10_PCREL_L and R_D10V_18_PCREL to use + complain_overflow_bitfield. + +2002-06-17 Alan Modra + + * opncls.c (bfd_openr): Remove redundant bfd_set_error. + (bfd_fdopenr): Likewise. + (bfd_openstreamr): Likewise. + (bfd_openw): Likewise. + + * targets.c: Sort target vecs. + (_bfd_target_vector): Add aix5coff64_vec, bfd_elf32_sh64_vec, + bfd_elf32_sh64l_vec, bfd_elf32_sh64lnbsd_vec, + bfd_elf32_sh64nbsd_vec, bfd_elf64_sh64_vec, bfd_elf64_sh64l_vec, + bfd_elf64_sh64lnbsd_vec, bfd_elf64_sh64nbsd_vec. + * configure.in: Sort target vecs. Add m88kmach3_vec. + * configure: Regenerate. + +2002-06-16 Hans-Peter Nilsson + + * elf64-mmix.c (bpo_reloc_request_sort_fn): Use member + bpo_reloc_no to break sort order ties, not address of items. + +2002-06-16 John David Anglin + + * elf-hppa.h (elf_hppa_final_link): Fix formatting in comment. + Skip excluded sections in determing __gp value. + (elf_hppa_final_link_relocate): Use the symbol's address in + R_PARISC_FPTR64 relocations that don't need an opd entry. + * elf64-hppa.c (allocate_dynrel_entries): Simplify code. + (elf64_hppa_finalize_dynreloc): Likewise. + (elf64_hppa_size_dynamic_sections): Move comments and fix typo. + (elf64_hppa_finish_dynamic_symbol): Break up assert. + +2002-06-14 Sergey Grigoriev + + * pei-i386.c (COFF_SECTION_ALIGNMENT_ENTRIES): Enable 16 byte + alignment for .bss, .data and .text sections so that sse and sse2 + code will work. + * pe-i386.c (COFF_SECTION_ALIGNMENT_ENTRIES): Likewise. + +2002-06013 J"orn Rennecke + + config.bfd: Add support for sh[1234]l*-*-elf* | sh3el*-*-elf*, + sh[1234]*-elf*. + +2002-06-12 John David Anglin + + * elflink.h (elf_bfd_final_link): Improve error handling for missing + dynamic sections. + + * elf64-hppa.c (allocate_global_data_opd): We don't need an opd entry + for a symbol that has no output section. + (allocate_dynrel_entries): Correct comment. + (elf64_hppa_finalize_dynreloc): Likewise. Don't create an opd entry + unless we want one. + (elf64_hppa_finalize_opd): Prevent segfault if dyn_h is NULL. + (elf64_hppa_finalize_dlt): Likewise. Prevent segfault for symbols + with no section. Remove unnecessary parentheses. + +2002-06-11 Tom Rix + + * coffcode.h (coff_compute_section_file_positions): Add data + section to AIX loader alignment check. + + * coff-rs6000.c (_bfd_xcoff_mkobject): Set default text section + alignment to 4 bytes. + (_bfd_xcoff_copy_private_bfd_data): Use text and data alignment + power accessor macro. + (do_shared_object_padding): Remove invalid assertion. + +2002-06-10 Richard Sandiford + + * section.c (_bfd_strip_section_from_output): Set SEC_EXCLUDE + for removed output sections. + +2002-06-10 Geoffrey Keating + + * merge.c (merge_strings): Use htab_create_alloc with calloc, not + htab_alloc. + * elf-strtab.c (_bfd_elf_strtab_finalize): Likewise. + 2002-06-08 H.J. Lu * elf.c (copy_private_bfd_data): Don't cast to bfd_size_type to diff -uprN binutils-2.12.90.0.11/bfd/Makefile.am binutils-2.12.90.0.12/bfd/Makefile.am --- binutils-2.12.90.0.11/bfd/Makefile.am Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/bfd/Makefile.am Tue Jun 18 21:41:58 2002 @@ -58,6 +58,7 @@ ALL_MACHINES = \ cpu-d30v.lo \ cpu-dlx.lo \ cpu-fr30.lo \ + cpu-frv.lo \ cpu-h8300.lo \ cpu-h8500.lo \ cpu-hppa.lo \ @@ -107,6 +108,7 @@ ALL_MACHINES_CFILES = \ cpu-d30v.c \ cpu-dlx.c \ cpu-fr30.c \ + cpu-frv.c \ cpu-h8300.c \ cpu-h8500.c \ cpu-hppa.c \ @@ -202,6 +204,7 @@ BFD32_BACKENDS = \ elf32-d30v.lo \ elf32-dlx.lo \ elf32-fr30.lo \ + elf32-frv.lo \ elf32-gen.lo \ elf32-h8300.lo \ elf32-hppa.lo \ @@ -357,6 +360,7 @@ BFD32_BACKENDS_CFILES = \ elf32-d30v.c \ elf32-dlx.c \ elf32-fr30.c \ + elf32-frv.c \ elf32-gen.c \ elf32-h8300.c \ elf32-hppa.c \ @@ -830,7 +834,6 @@ DISTCLEANFILES = $(BUILD_CFILES) $(BUILD config.status: $(srcdir)/configure $(srcdir)/config.bfd $(srcdir)/configure.host $(SHELL) ./config.status --recheck - # What appears below is generated by a hacked mkdep using gcc -MM. # DO NOT DELETE THIS LINE -- mkdep uses it. @@ -886,6 +889,7 @@ cpu-d10v.lo: cpu-d10v.c $(INCDIR)/filena cpu-d30v.lo: cpu-d30v.c $(INCDIR)/filenames.h cpu-dlx.lo: cpu-dlx.c $(INCDIR)/filenames.h cpu-fr30.lo: cpu-fr30.c $(INCDIR)/filenames.h +cpu-frv.lo: cpu-frv.c $(INCDIR)/filenames.h cpu-h8300.lo: cpu-h8300.c $(INCDIR)/filenames.h cpu-h8500.lo: cpu-h8500.c $(INCDIR)/filenames.h cpu-hppa.lo: cpu-hppa.c $(INCDIR)/filenames.h @@ -1109,6 +1113,10 @@ elf32-fr30.lo: elf32-fr30.c $(INCDIR)/fi $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h $(INCDIR)/elf/fr30.h $(INCDIR)/elf/reloc-macros.h \ elf32-target.h +elf32-frv.lo: elf32-frv.c elf-bfd.h $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \ + $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h \ + elf32-target.h elf32-gen.lo: elf32-gen.c $(INCDIR)/filenames.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h elf32-target.h diff -uprN binutils-2.12.90.0.11/bfd/Makefile.in binutils-2.12.90.0.12/bfd/Makefile.in --- binutils-2.12.90.0.11/bfd/Makefile.in Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/bfd/Makefile.in Tue Jun 18 21:41:58 2002 @@ -163,18 +163,18 @@ BFD64_LIBS_CFILES = archive64.c # This list is alphabetized to make it easier to keep in sync # with the decls and initializer in archures.c. -ALL_MACHINES = cpu-a29k.lo cpu-alpha.lo cpu-arc.lo cpu-arm.lo cpu-avr.lo cpu-cris.lo cpu-d10v.lo cpu-d30v.lo cpu-dlx.lo cpu-fr30.lo cpu-h8300.lo cpu-h8500.lo cpu-hppa.lo cpu-ia64.lo cpu-i370.lo cpu-i386.lo cpu-i860.lo cpu-i960.lo cpu-m32r.lo cpu-m68hc11.lo cpu-m68hc12.lo cpu-m68k.lo cpu-m88k.lo cpu-m10200.lo cpu-m10300.lo cpu-mcore.lo cpu-mips.lo cpu-mmix.lo cpu-or32.lo cpu-ns32k.lo cpu-openrisc.lo cpu-pdp11.lo cpu-pj.lo cpu-powerpc.lo cpu-rs6000.lo cpu-s390.lo cpu-sh.lo cpu-sparc.lo cpu-tic30.lo cpu-tic54x.lo cpu-tic80.lo cpu-v850.lo cpu-vax.lo cpu-we32k.lo cpu-w65.lo cpu-xstormy16.lo cpu-z8k.lo +ALL_MACHINES = cpu-a29k.lo cpu-alpha.lo cpu-arc.lo cpu-arm.lo cpu-avr.lo cpu-cris.lo cpu-d10v.lo cpu-d30v.lo cpu-dlx.lo cpu-fr30.lo cpu-frv.lo cpu-h8300.lo cpu-h8500.lo cpu-hppa.lo cpu-ia64.lo cpu-i370.lo cpu-i386.lo cpu-i860.lo cpu-i960.lo cpu-m32r.lo cpu-m68hc11.lo cpu-m68hc12.lo cpu-m68k.lo cpu-m88k.lo cpu-m10200.lo cpu-m10300.lo cpu-mcore.lo cpu-mips.lo cpu-mmix.lo cpu-or32.lo cpu-ns32k.lo cpu-openrisc.lo cpu-pdp11.lo cpu-pj.lo cpu-powerpc.lo cpu-rs6000.lo cpu-s390.lo cpu-sh.lo cpu-sparc.lo cpu-tic30.lo cpu-tic54x.lo cpu-tic80.lo cpu-v850.lo cpu-vax.lo cpu-we32k.lo cpu-w65.lo cpu-xstormy16.lo cpu-z8k.lo -ALL_MACHINES_CFILES = cpu-a29k.c cpu-alpha.c cpu-arc.c cpu-arm.c cpu-avr.c cpu-cris.c cpu-d10v.c cpu-d30v.c cpu-dlx.c cpu-fr30.c cpu-h8300.c cpu-h8500.c cpu-hppa.c cpu-ia64.c cpu-i370.c cpu-i386.c cpu-i860.c cpu-i960.c cpu-m32r.c cpu-m68hc11.c cpu-m68hc12.c cpu-m68k.c cpu-m88k.c cpu-m10200.c cpu-m10300.c cpu-mcore.c cpu-mips.c cpu-mmix.c cpu-or32.c cpu-ns32k.c cpu-openrisc.c cpu-pdp11.c cpu-pj.c cpu-powerpc.c cpu-rs6000.c cpu-s390.c cpu-sh.c cpu-sparc.c cpu-tic30.c cpu-tic54x.c cpu-tic80.c cpu-v850.c cpu-vax.c cpu-we32k.c cpu-w65.c cpu-xstormy16.c cpu-z8k.c +ALL_MACHINES_CFILES = cpu-a29k.c cpu-alpha.c cpu-arc.c cpu-arm.c cpu-avr.c cpu-cris.c cpu-d10v.c cpu-d30v.c cpu-dlx.c cpu-fr30.c cpu-frv.c cpu-h8300.c cpu-h8500.c cpu-hppa.c cpu-ia64.c cpu-i370.c cpu-i386.c cpu-i860.c cpu-i960.c cpu-m32r.c cpu-m68hc11.c cpu-m68hc12.c cpu-m68k.c cpu-m88k.c cpu-m10200.c cpu-m10300.c cpu-mcore.c cpu-mips.c cpu-mmix.c cpu-or32.c cpu-ns32k.c cpu-openrisc.c cpu-pdp11.c cpu-pj.c cpu-powerpc.c cpu-rs6000.c cpu-s390.c cpu-sh.c cpu-sparc.c cpu-tic30.c cpu-tic54x.c cpu-tic80.c cpu-v850.c cpu-vax.c cpu-we32k.c cpu-w65.c cpu-xstormy16.c cpu-z8k.c # The .o files needed by all of the 32 bit vectors that are configured into # target_vector in targets.c if configured with --enable-targets=all. -BFD32_BACKENDS = aout-adobe.lo aout-arm.lo aout-cris.lo aout-ns32k.lo aout-sparcle.lo aout-tic30.lo aout0.lo aout32.lo armnetbsd.lo bout.lo cf-i386lynx.lo cf-m68klynx.lo cf-sparclynx.lo coff-a29k.lo coff-apollo.lo coff-arm.lo coff-aux.lo coff-h8300.lo coff-h8500.lo coff-i386.lo coff-go32.lo coff-i860.lo coff-i960.lo coff-m68k.lo coff-m88k.lo coff-mips.lo coff-or32.lo coff-rs6000.lo coff-sh.lo coff-sparc.lo coff-stgo32.lo coff-svm68k.lo coff-tic30.lo coff-tic54x.lo coff-tic80.lo coff-u68k.lo coff-we32k.lo coff-w65.lo coff-z8k.lo cofflink.lo dwarf1.lo ecoff.lo ecofflink.lo efi-app-ia32.lo elf.lo elf32-arc.lo elfarm-oabi.lo elfarm-nabi.lo elf32-avr.lo elf32-cris.lo elf32-d10v.lo elf32-d30v.lo elf32-dlx.lo elf32-fr30.lo elf32-gen.lo elf32-h8300.lo elf32-hppa.lo elf32-i370.lo elf32-i386.lo elf32-i386qnx.lo elf32-i860.lo elf32-i960.lo elf32-ia64.lo elf32-m32r.lo elf32-m68hc11.lo elf32-m68hc12.lo elf32-m68k.lo elf32-m88k.lo elf-m10200.lo elf-m10300.lo elf32-mcore.lo elfxx-mips.lo elf32-mips.lo elf32-openrisc.lo elf32-or32.lo elf32-pj.lo elf32-ppc.lo elf32-s390.lo elf32-sh.lo elf32-sh-lin.lo elf32-sh64.lo elf32-sh64-com.lo elf32-sh-nbsd.lo elf32-sh64-nbsd.lo elf32-sparc.lo elf32-v850.lo elf32-vax.lo elf32-xstormy16.lo elf32.lo elflink.lo elf-strtab.lo elf-eh-frame.lo epoc-pe-arm.lo epoc-pei-arm.lo hp300bsd.lo hp300hpux.lo som.lo i386aout.lo i386bsd.lo i386dynix.lo i386freebsd.lo i386linux.lo i386lynx.lo i386msdos.lo i386netbsd.lo i386mach3.lo i386os9k.lo ieee.lo m68k4knetbsd.lo m68klinux.lo m68klynx.lo m68knetbsd.lo m88kmach3.lo mipsbsd.lo newsos3.lo nlm.lo nlm32-i386.lo nlm32-sparc.lo nlm32-ppc.lo nlm32.lo ns32knetbsd.lo oasys.lo pc532-mach.lo pdp11.lo pe-arm.lo pei-arm.lo pe-i386.lo pei-i386.lo pe-mcore.lo pei-mcore.lo pe-ppc.lo pei-ppc.lo pe-sh.lo pei-sh.lo pe-mips.lo pei-mips.lo peigen.lo ppcboot.lo reloc16.lo riscix.lo sparclinux.lo sparclynx.lo sparcnetbsd.lo sunos.lo vaxnetbsd.lo vax1knetbsd.lo versados.lo vms.lo vms-gsd.lo vms-hdr.lo vms-misc.lo vms-tir.lo xcofflink.lo +BFD32_BACKENDS = aout-adobe.lo aout-arm.lo aout-cris.lo aout-ns32k.lo aout-sparcle.lo aout-tic30.lo aout0.lo aout32.lo armnetbsd.lo bout.lo cf-i386lynx.lo cf-m68klynx.lo cf-sparclynx.lo coff-a29k.lo coff-apollo.lo coff-arm.lo coff-aux.lo coff-h8300.lo coff-h8500.lo coff-i386.lo coff-go32.lo coff-i860.lo coff-i960.lo coff-m68k.lo coff-m88k.lo coff-mips.lo coff-or32.lo coff-rs6000.lo coff-sh.lo coff-sparc.lo coff-stgo32.lo coff-svm68k.lo coff-tic30.lo coff-tic54x.lo coff-tic80.lo coff-u68k.lo coff-we32k.lo coff-w65.lo coff-z8k.lo cofflink.lo dwarf1.lo ecoff.lo ecofflink.lo efi-app-ia32.lo elf.lo elf32-arc.lo elfarm-oabi.lo elfarm-nabi.lo elf32-avr.lo elf32-cris.lo elf32-d10v.lo elf32-d30v.lo elf32-dlx.lo elf32-fr30.lo elf32-frv.lo elf32-gen.lo elf32-h8300.lo elf32-hppa.lo elf32-i370.lo elf32-i386.lo elf32-i386qnx.lo elf32-i860.lo elf32-i960.lo elf32-ia64.lo elf32-m32r.lo elf32-m68hc11.lo elf32-m68hc12.lo elf32-m68k.lo elf32-m88k.lo elf-m10200.lo elf-m10300.lo elf32-mcore.lo elfxx-mips.lo elf32-mips.lo elf32-openrisc.lo elf32-or32.lo elf32-pj.lo elf32-ppc.lo elf32-s390.lo elf32-sh.lo elf32-sh-lin.lo elf32-sh64.lo elf32-sh64-com.lo elf32-sh-nbsd.lo elf32-sh64-nbsd.lo elf32-sparc.lo elf32-v850.lo elf32-vax.lo elf32-xstormy16.lo elf32.lo elflink.lo elf-strtab.lo elf-eh-frame.lo epoc-pe-arm.lo epoc-pei-arm.lo hp300bsd.lo hp300hpux.lo som.lo i386aout.lo i386bsd.lo i386dynix.lo i386freebsd.lo i386linux.lo i386lynx.lo i386msdos.lo i386netbsd.lo i386mach3.lo i386os9k.lo ieee.lo m68k4knetbsd.lo m68klinux.lo m68klynx.lo m68knetbsd.lo m88kmach3.lo mipsbsd.lo newsos3.lo nlm.lo nlm32-i386.lo nlm32-sparc.lo nlm32-ppc.lo nlm32.lo ns32knetbsd.lo oasys.lo pc532-mach.lo pdp11.lo pe-arm.lo pei-arm.lo pe-i386.lo pei-i386.lo pe-mcore.lo pei-mcore.lo pe-ppc.lo pei-ppc.lo pe-sh.lo pei-sh.lo pe-mips.lo pei-mips.lo peigen.lo ppcboot.lo reloc16.lo riscix.lo sparclinux.lo sparclynx.lo sparcnetbsd.lo sunos.lo vaxnetbsd.lo vax1knetbsd.lo versados.lo vms.lo vms-gsd.lo vms-hdr.lo vms-misc.lo vms-tir.lo xcofflink.lo -BFD32_BACKENDS_CFILES = aout-adobe.c aout-arm.c aout-cris.c aout-ns32k.c aout-sparcle.c aout-tic30.c aout0.c aout32.c armnetbsd.c bout.c cf-i386lynx.c cf-m68klynx.c cf-sparclynx.c coff-a29k.c coff-apollo.c coff-arm.c coff-aux.c coff-h8300.c coff-h8500.c coff-i386.c coff-i860.c coff-go32.c coff-i960.c coff-m68k.c coff-m88k.c coff-mips.c coff-or32.c coff-rs6000.c coff-sh.c coff-sparc.c coff-stgo32.c coff-svm68k.c coff-tic30.c coff-tic54x.c coff-tic80.c coff-u68k.c coff-we32k.c coff-w65.c coff-z8k.c cofflink.c dwarf1.c ecoff.c ecofflink.c efi-app-ia32.c elf.c elf32-arc.c elfarm-oabi.c elfarm-nabi.c elf32-avr.c elf32-cris.c elf32-d10v.c elf32-d30v.c elf32-dlx.c elf32-fr30.c elf32-gen.c elf32-h8300.c elf32-hppa.c elf32-i370.c elf32-i386.c elf32-i386qnx.c elf32-i860.c elf32-i960.c elf32-m32r.c elf32-m68k.c elf32-m68hc11.c elf32-m68hc12.c elf32-m88k.c elf-m10200.c elf-m10300.c elf32-mcore.c elfxx-mips.c elf32-mips.c elf32-openrisc.c elf32-or32.c elf32-pj.c elf32-ppc.c elf32-sh64.c elf32-sh64-com.c elf32-s390.c elf32-sh.c elf32-sh-lin.c elf32-sh-nbsd.c elf32-sh64-nbsd.c elf32-sparc.c elf32-v850.c elf32-vax.c elf32-xstormy16.c elf32.c elflink.c elf-strtab.c elf-eh-frame.c epoc-pe-arm.c epoc-pei-arm.c hp300bsd.c hp300hpux.c som.c i386aout.c i386bsd.c i386dynix.c i386freebsd.c i386linux.c i386lynx.c i386msdos.c i386netbsd.c i386mach3.c i386os9k.c ieee.c m68k4knetbsd.c m68klinux.c m68klynx.c m68knetbsd.c m88kmach3.c mipsbsd.c newsos3.c nlm.c nlm32-i386.c nlm32-sparc.c nlm32-ppc.c nlm32.c ns32knetbsd.c oasys.c pc532-mach.c pdp11.c pe-arm.c pei-arm.c pe-i386.c pei-i386.c pe-mcore.c pei-mcore.c pe-ppc.c pei-ppc.c pe-sh.c pei-sh.c pe-mips.c pei-mips.c ppcboot.c reloc16.c riscix.c sparclinux.c sparclynx.c sparcnetbsd.c sunos.c vaxnetbsd.c vax1knetbsd.c versados.c vms.c vms-gsd.c vms-hdr.c vms-misc.c vms-tir.c xcofflink.c +BFD32_BACKENDS_CFILES = aout-adobe.c aout-arm.c aout-cris.c aout-ns32k.c aout-sparcle.c aout-tic30.c aout0.c aout32.c armnetbsd.c bout.c cf-i386lynx.c cf-m68klynx.c cf-sparclynx.c coff-a29k.c coff-apollo.c coff-arm.c coff-aux.c coff-h8300.c coff-h8500.c coff-i386.c coff-i860.c coff-go32.c coff-i960.c coff-m68k.c coff-m88k.c coff-mips.c coff-or32.c coff-rs6000.c coff-sh.c coff-sparc.c coff-stgo32.c coff-svm68k.c coff-tic30.c coff-tic54x.c coff-tic80.c coff-u68k.c coff-we32k.c coff-w65.c coff-z8k.c cofflink.c dwarf1.c ecoff.c ecofflink.c efi-app-ia32.c elf.c elf32-arc.c elfarm-oabi.c elfarm-nabi.c elf32-avr.c elf32-cris.c elf32-d10v.c elf32-d30v.c elf32-dlx.c elf32-fr30.c elf32-frv.c elf32-gen.c elf32-h8300.c elf32-hppa.c elf32-i370.c elf32-i386.c elf32-i386qnx.c elf32-i860.c elf32-i960.c elf32-m32r.c elf32-m68k.c elf32-m68hc11.c elf32-m68hc12.c elf32-m88k.c elf-m10200.c elf-m10300.c elf32-mcore.c elfxx-mips.c elf32-mips.c elf32-openrisc.c elf32-or32.c elf32-pj.c elf32-ppc.c elf32-sh64.c elf32-sh64-com.c elf32-s390.c elf32-sh.c elf32-sh-lin.c elf32-sh-nbsd.c elf32-sh64-nbsd.c elf32-sparc.c elf32-v850.c elf32-vax.c elf32-xstormy16.c elf32.c elflink.c elf-strtab.c elf-eh-frame.c epoc-pe-arm.c epoc-pei-arm.c hp300bsd.c hp300hpux.c som.c i386aout.c i386bsd.c i386dynix.c i386freebsd.c i386linux.c i386lynx.c i386msdos.c i386netbsd.c i386mach3.c i386os9k.c ieee.c m68k4knetbsd.c m68klinux.c m68klynx.c m68knetbsd.c m88kmach3.c mipsbsd.c newsos3.c nlm.c nlm32-i386.c nlm32-sparc.c nlm32-ppc.c nlm32.c ns32knetbsd.c oasys.c pc532-mach.c pdp11.c pe-arm.c pei-arm.c pe-i386.c pei-i386.c pe-mcore.c pei-mcore.c pe-ppc.c pei-ppc.c pe-sh.c pei-sh.c pe-mips.c pei-mips.c ppcboot.c reloc16.c riscix.c sparclinux.c sparclynx.c sparcnetbsd.c sunos.c vaxnetbsd.c vax1knetbsd.c versados.c vms.c vms-gsd.c vms-hdr.c vms-misc.c vms-tir.c xcofflink.c # The .o files needed by all of the 64 bit vectors that are configured into @@ -930,6 +930,7 @@ cpu-d10v.lo: cpu-d10v.c $(INCDIR)/filena cpu-d30v.lo: cpu-d30v.c $(INCDIR)/filenames.h cpu-dlx.lo: cpu-dlx.c $(INCDIR)/filenames.h cpu-fr30.lo: cpu-fr30.c $(INCDIR)/filenames.h +cpu-frv.lo: cpu-frv.c $(INCDIR)/filenames.h cpu-h8300.lo: cpu-h8300.c $(INCDIR)/filenames.h cpu-h8500.lo: cpu-h8500.c $(INCDIR)/filenames.h cpu-hppa.lo: cpu-hppa.c $(INCDIR)/filenames.h @@ -1153,6 +1154,10 @@ elf32-fr30.lo: elf32-fr30.c $(INCDIR)/fi $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h $(INCDIR)/elf/fr30.h $(INCDIR)/elf/reloc-macros.h \ elf32-target.h +elf32-frv.lo: elf32-frv.c $(INCDIR)/filenames.h elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h \ + elf32-target.h elf32-gen.lo: elf32-gen.c $(INCDIR)/filenames.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h elf32-target.h diff -uprN binutils-2.12.90.0.11/bfd/archures.c binutils-2.12.90.0.12/bfd/archures.c --- binutils-2.12.90.0.11/bfd/archures.c Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/bfd/archures.c Tue Jun 18 21:41:58 2002 @@ -247,6 +247,13 @@ DESCRIPTION .#define bfd_mach_am33 330 . bfd_arch_fr30, .#define bfd_mach_fr30 0x46523330 +. bfd_arch_frv, +.#define bfd_mach_frv 0 +.#define bfd_mach_frvsimple 1 +.#define bfd_mach_fr300 300 +.#define bfd_mach_fr400 400 +.#define bfd_mach_frvtomcat 499 {* fr500 prototype *} +.#define bfd_mach_fr500 500 . bfd_arch_mcore, . bfd_arch_ia64, {* HP/Intel ia64 *} .#define bfd_mach_ia64_elf64 0 @@ -315,6 +322,7 @@ extern const bfd_arch_info_type bfd_d10v extern const bfd_arch_info_type bfd_d30v_arch; extern const bfd_arch_info_type bfd_dlx_arch; extern const bfd_arch_info_type bfd_fr30_arch; +extern const bfd_arch_info_type bfd_frv_arch; extern const bfd_arch_info_type bfd_h8300_arch; extern const bfd_arch_info_type bfd_h8500_arch; extern const bfd_arch_info_type bfd_hppa_arch; @@ -369,6 +377,7 @@ static const bfd_arch_info_type * const &bfd_d30v_arch, &bfd_dlx_arch, &bfd_fr30_arch, + &bfd_frv_arch, &bfd_h8300_arch, &bfd_h8500_arch, &bfd_hppa_arch, diff -uprN binutils-2.12.90.0.11/bfd/bfd-in2.h binutils-2.12.90.0.12/bfd/bfd-in2.h --- binutils-2.12.90.0.11/bfd/bfd-in2.h Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/bfd/bfd-in2.h Tue Jun 18 21:41:58 2002 @@ -1637,6 +1637,13 @@ enum bfd_architecture #define bfd_mach_am33 330 bfd_arch_fr30, #define bfd_mach_fr30 0x46523330 + bfd_arch_frv, +#define bfd_mach_frv 0 +#define bfd_mach_frvsimple 1 +#define bfd_mach_fr300 300 +#define bfd_mach_fr400 400 +#define bfd_mach_frvtomcat 499 /* fr500 prototype */ +#define bfd_mach_fr500 500 bfd_arch_mcore, bfd_arch_ia64, /* HP/Intel ia64 */ #define bfd_mach_ia64_elf64 0 @@ -2832,6 +2839,17 @@ value of SUBI insn. */ into 22 bits. */ BFD_RELOC_AVR_CALL, +/* Fujitsu Frv Relocations. */ + BFD_RELOC_FRV_LABEL16, + BFD_RELOC_FRV_LABEL24, + BFD_RELOC_FRV_LO16, + BFD_RELOC_FRV_HI16, + BFD_RELOC_FRV_GPREL12, + BFD_RELOC_FRV_GPRELU12, + BFD_RELOC_FRV_GPREL32, + BFD_RELOC_FRV_GPRELHI, + BFD_RELOC_FRV_GPRELLO, + /* Direct 12 bit. */ BFD_RELOC_390_12, diff -uprN binutils-2.12.90.0.11/bfd/coff-rs6000.c binutils-2.12.90.0.12/bfd/coff-rs6000.c --- binutils-2.12.90.0.11/bfd/coff-rs6000.c Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/bfd/coff-rs6000.c Tue Jun 18 21:41:58 2002 @@ -237,7 +237,7 @@ _bfd_xcoff_mkobject (abfd) xcoff_data (abfd)->debug_indices = NULL; /* text section alignment is different than the default */ - /* xcoff_data (abfd)->text_align_power = 5; */ + bfd_xcoff_text_align_power (abfd) = 2; return true; } @@ -278,8 +278,8 @@ _bfd_xcoff_copy_private_bfd_data (ibfd, else ox->snentry = sec->output_section->target_index; } - ox->text_align_power = ix->text_align_power; - ox->data_align_power = ix->data_align_power; + bfd_xcoff_text_align_power (obfd) = bfd_xcoff_text_align_power (ibfd); + bfd_xcoff_data_align_power (obfd) = bfd_xcoff_data_align_power (ibfd); ox->modtype = ix->modtype; ox->cputype = ix->cputype; ox->maxdata = ix->maxdata; @@ -1730,7 +1730,6 @@ do_shared_object_padding (out_bfd, in_bf int text_align_power; text_align_power = bfd_xcoff_text_align_power (in_bfd); - BFD_ASSERT (2 < text_align_power); pad = 1 << text_align_power; pad -= (*offset + ar_header_size) & (pad - 1); diff -uprN binutils-2.12.90.0.11/bfd/coffcode.h binutils-2.12.90.0.12/bfd/coffcode.h --- binutils-2.12.90.0.11/bfd/coffcode.h Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/bfd/coffcode.h Tue Jun 18 21:41:58 2002 @@ -1782,8 +1782,8 @@ coff_mkobject_hook (abfd, filehdr, aouth xcoff->toc = internal_a->o_toc; xcoff->sntoc = internal_a->o_sntoc; xcoff->snentry = internal_a->o_snentry; - xcoff->text_align_power = internal_a->o_algntext; - xcoff->data_align_power = internal_a->o_algndata; + bfd_xcoff_text_align_power (abfd) = internal_a->o_algntext; + bfd_xcoff_data_align_power (abfd) = internal_a->o_algndata; xcoff->modtype = internal_a->o_modtype; xcoff->cputype = internal_a->o_cputype; xcoff->maxdata = internal_a->o_maxdata; @@ -3084,8 +3084,10 @@ coff_compute_section_file_positions (abf AIX executable is stripped with gnu strip because the default vma of native is 0x10000150 but default for gnu is 0x10000140. Gnu stripped gnu excutable passes this check because the filepos is - 0x0140. */ - if (!strcmp (current->name, _TEXT)) + 0x0140. This problem also show up with 64 bit shared objects. The + data section must also be aligned. */ + if (!strcmp (current->name, _TEXT) + || !strcmp (current->name, _DATA)) { bfd_vma pad; bfd_vma align; diff -uprN binutils-2.12.90.0.11/bfd/config.bfd binutils-2.12.90.0.12/bfd/config.bfd --- binutils-2.12.90.0.11/bfd/config.bfd Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/bfd/config.bfd Tue Jun 18 21:41:58 2002 @@ -281,6 +281,10 @@ case "${targ}" in targ_defvec=bfd_elf32_fr30_vec ;; + frv-*-elf) + targ_defvec=bfd_elf32_frv_vec + ;; + h8300*-*-elf) targ_defvec=bfd_elf32_h8300_vec @@ -953,7 +957,7 @@ case "${targ}" in targ_selvecs="bfd_elf32_shlnbsd_vec shcoff_vec shlcoff_vec" ;; - shl*-*-elf*) + shl*-*-elf* | sh[1234]l*-*-elf* | sh3el*-*-elf*) targ_defvec=bfd_elf32_shl_vec targ_selvecs="bfd_elf32_sh_vec shlcoff_vec shcoff_vec shlcoff_small_vec shcoff_small_vec" #ifdef BFD64 @@ -961,7 +965,7 @@ case "${targ}" in #endif targ_underscore=yes ;; - sh-*-elf* | sh-*-rtemself*) + sh-*-elf* | sh[1234]*-elf* | sh-*-rtemself*) targ_defvec=bfd_elf32_sh_vec targ_selvecs="bfd_elf32_shl_vec shcoff_vec shlcoff_vec shcoff_small_vec shlcoff_small_vec" #ifdef BFD64 diff -uprN binutils-2.12.90.0.11/bfd/configure binutils-2.12.90.0.12/bfd/configure --- binutils-2.12.90.0.11/bfd/configure Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/bfd/configure Tue Jun 18 21:41:58 2002 @@ -1118,7 +1118,7 @@ fi PACKAGE=bfd -VERSION=2.12.90.0.11 +VERSION=2.12.90.0.12 if test "`cd $srcdir && pwd`" != "`pwd`" && test -f $srcdir/config.status; then { echo "configure: error: source directory already configured; run "make distclean" there first" 1>&2; exit 1; } @@ -3285,7 +3285,7 @@ EOF fi -for ac_hdr in stdlib.h unistd.h sys/stat.h sys/types.h +for ac_hdr in unistd.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 @@ -3417,24 +3417,11 @@ else #include #include -#if HAVE_SYS_TYPES_H -# include -#endif - -#if HAVE_STDLIB_H -# include -#endif - -#if HAVE_SYS_STAT_H -# include -#endif - -#if HAVE_UNISTD_H -# include -#endif - /* This mess was copied from the GNU getpagesize.h. */ #ifndef HAVE_GETPAGESIZE +# ifdef HAVE_UNISTD_H +# include +# endif /* Assume that all systems that can run configure have sys/param.h. */ # ifndef HAVE_SYS_PARAM_H @@ -3542,7 +3529,7 @@ main() } EOF -if { (eval echo configure:3546: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:3533: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_func_mmap_fixed_mapped=yes else @@ -3570,17 +3557,17 @@ unistd.h values.h sys/param.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:3574: checking for $ac_hdr" >&5 +echo "configure:3561: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3584: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3571: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3610,12 +3597,12 @@ done __argz_count __argz_stringify __argz_next do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3614: checking for $ac_func" >&5 +echo "configure:3601: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3629: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3667,12 +3654,12 @@ done for ac_func in stpcpy do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3671: checking for $ac_func" >&5 +echo "configure:3658: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3686: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3729,19 +3716,19 @@ EOF if test $ac_cv_header_locale_h = yes; then echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6 -echo "configure:3733: checking for LC_MESSAGES" >&5 +echo "configure:3720: checking for LC_MESSAGES" >&5 if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < int main() { return LC_MESSAGES ; return 0; } EOF -if { (eval echo configure:3745: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3732: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* am_cv_val_LC_MESSAGES=yes else @@ -3762,7 +3749,7 @@ EOF fi fi echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6 -echo "configure:3766: checking whether NLS is requested" >&5 +echo "configure:3753: checking whether NLS is requested" >&5 # Check whether --enable-nls or --disable-nls was given. if test "${enable_nls+set}" = set; then enableval="$enable_nls" @@ -3782,7 +3769,7 @@ fi EOF echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6 -echo "configure:3786: checking whether included gettext is requested" >&5 +echo "configure:3773: checking whether included gettext is requested" >&5 # Check whether --with-included-gettext or --without-included-gettext was given. if test "${with_included_gettext+set}" = set; then withval="$with_included_gettext" @@ -3801,17 +3788,17 @@ fi ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for libintl.h""... $ac_c" 1>&6 -echo "configure:3805: checking for libintl.h" >&5 +echo "configure:3792: checking for libintl.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3815: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3802: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3828,19 +3815,19 @@ fi if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6 -echo "configure:3832: checking for gettext in libc" >&5 +echo "configure:3819: checking for gettext in libc" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:3844: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3831: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libc=yes else @@ -3856,7 +3843,7 @@ echo "$ac_t""$gt_cv_func_gettext_libc" 1 if test "$gt_cv_func_gettext_libc" != "yes"; then echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6 -echo "configure:3860: checking for bindtextdomain in -lintl" >&5 +echo "configure:3847: checking for bindtextdomain in -lintl" >&5 ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -3864,7 +3851,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lintl $LIBS" cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3866: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -3891,19 +3878,19 @@ fi if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6 -echo "configure:3895: checking for gettext in libintl" >&5 +echo "configure:3882: checking for gettext in libintl" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3894: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libintl=yes else @@ -3931,7 +3918,7 @@ EOF # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3935: checking for $ac_word" >&5 +echo "configure:3922: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3965,12 +3952,12 @@ fi for ac_func in dcgettext do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3969: checking for $ac_func" >&5 +echo "configure:3956: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3984: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -4020,7 +4007,7 @@ done # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4024: checking for $ac_word" >&5 +echo "configure:4011: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4056,7 +4043,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4060: checking for $ac_word" >&5 +echo "configure:4047: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4088,7 +4075,7 @@ else fi cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4087: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* CATOBJEXT=.gmo DATADIRNAME=share @@ -4128,7 +4115,7 @@ fi # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4132: checking for $ac_word" >&5 +echo "configure:4119: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4162,7 +4149,7 @@ fi # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4166: checking for $ac_word" >&5 +echo "configure:4153: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4198,7 +4185,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4202: checking for $ac_word" >&5 +echo "configure:4189: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4288,7 +4275,7 @@ fi LINGUAS= else echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6 -echo "configure:4292: checking for catalogs to be installed" >&5 +echo "configure:4279: checking for catalogs to be installed" >&5 NEW_LINGUAS= for lang in ${LINGUAS=$ALL_LINGUAS}; do case "$ALL_LINGUAS" in @@ -4316,17 +4303,17 @@ echo "configure:4292: checking for catal if test "$CATOBJEXT" = ".cat"; then ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6 -echo "configure:4320: checking for linux/version.h" >&5 +echo "configure:4307: checking for linux/version.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4330: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4317: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4404,7 +4391,7 @@ fi # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # ./install, which can be erroneously created by make from ./install.sh. echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 -echo "configure:4408: checking for a BSD compatible install" >&5 +echo "configure:4395: checking for a BSD compatible install" >&5 if test -z "$INSTALL"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -4487,7 +4474,7 @@ if test "x$cross_compiling" = "xno"; the EXEEXT_FOR_BUILD='$(EXEEXT)' else echo $ac_n "checking for build system executable suffix""... $ac_c" 1>&6 -echo "configure:4491: checking for build system executable suffix" >&5 +echo "configure:4478: checking for build system executable suffix" >&5 if eval "test \"`echo '$''{'bfd_cv_build_exeext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4515,17 +4502,17 @@ for ac_hdr in stddef.h string.h strings. do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:4519: checking for $ac_hdr" >&5 +echo "configure:4506: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4529: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4516: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4555,17 +4542,17 @@ for ac_hdr in fcntl.h sys/file.h sys/tim do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:4559: checking for $ac_hdr" >&5 +echo "configure:4546: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4569: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4556: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4592,12 +4579,12 @@ fi done echo $ac_n "checking whether time.h and sys/time.h may both be included""... $ac_c" 1>&6 -echo "configure:4596: checking whether time.h and sys/time.h may both be included" >&5 +echo "configure:4583: checking whether time.h and sys/time.h may both be included" >&5 if eval "test \"`echo '$''{'ac_cv_header_time'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < #include @@ -4606,7 +4593,7 @@ int main() { struct tm *tp; ; return 0; } EOF -if { (eval echo configure:4610: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:4597: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_header_time=yes else @@ -4631,12 +4618,12 @@ for ac_hdr in dirent.h sys/ndir.h sys/di do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr that defines DIR""... $ac_c" 1>&6 -echo "configure:4635: checking for $ac_hdr that defines DIR" >&5 +echo "configure:4622: checking for $ac_hdr that defines DIR" >&5 if eval "test \"`echo '$''{'ac_cv_header_dirent_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < #include <$ac_hdr> @@ -4644,7 +4631,7 @@ int main() { DIR *dirp = 0; ; return 0; } EOF -if { (eval echo configure:4648: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:4635: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* eval "ac_cv_header_dirent_$ac_safe=yes" else @@ -4669,7 +4656,7 @@ done # Two versions of opendir et al. are in -ldir and -lx on SCO Xenix. if test $ac_header_dirent = dirent.h; then echo $ac_n "checking for opendir in -ldir""... $ac_c" 1>&6 -echo "configure:4673: checking for opendir in -ldir" >&5 +echo "configure:4660: checking for opendir in -ldir" >&5 ac_lib_var=`echo dir'_'opendir | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -4677,7 +4664,7 @@ else ac_save_LIBS="$LIBS" LIBS="-ldir $LIBS" cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4679: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -4710,7 +4697,7 @@ fi else echo $ac_n "checking for opendir in -lx""... $ac_c" 1>&6 -echo "configure:4714: checking for opendir in -lx" >&5 +echo "configure:4701: checking for opendir in -lx" >&5 ac_lib_var=`echo x'_'opendir | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -4718,7 +4705,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lx $LIBS" cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4720: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -4754,12 +4741,12 @@ fi for ac_func in fcntl getpagesize setitimer sysconf fdopen getuid getgid do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:4758: checking for $ac_func" >&5 +echo "configure:4745: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4773: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -4817,12 +4804,12 @@ EOF esac echo $ac_n "checking whether strstr must be declared""... $ac_c" 1>&6 -echo "configure:4821: checking whether strstr must be declared" >&5 +echo "configure:4808: checking whether strstr must be declared" >&5 if eval "test \"`echo '$''{'bfd_cv_decl_needed_strstr'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < @@ -4843,7 +4830,7 @@ int main() { char *(*pfn) = (char *(*)) strstr ; return 0; } EOF -if { (eval echo configure:4847: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:4834: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_decl_needed_strstr=no else @@ -4864,12 +4851,12 @@ EOF fi echo $ac_n "checking whether malloc must be declared""... $ac_c" 1>&6 -echo "configure:4868: checking whether malloc must be declared" >&5 +echo "configure:4855: checking whether malloc must be declared" >&5 if eval "test \"`echo '$''{'bfd_cv_decl_needed_malloc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < @@ -4890,7 +4877,7 @@ int main() { char *(*pfn) = (char *(*)) malloc ; return 0; } EOF -if { (eval echo configure:4894: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:4881: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_decl_needed_malloc=no else @@ -4911,12 +4898,12 @@ EOF fi echo $ac_n "checking whether realloc must be declared""... $ac_c" 1>&6 -echo "configure:4915: checking whether realloc must be declared" >&5 +echo "configure:4902: checking whether realloc must be declared" >&5 if eval "test \"`echo '$''{'bfd_cv_decl_needed_realloc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < @@ -4937,7 +4924,7 @@ int main() { char *(*pfn) = (char *(*)) realloc ; return 0; } EOF -if { (eval echo configure:4941: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:4928: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_decl_needed_realloc=no else @@ -4958,12 +4945,12 @@ EOF fi echo $ac_n "checking whether free must be declared""... $ac_c" 1>&6 -echo "configure:4962: checking whether free must be declared" >&5 +echo "configure:4949: checking whether free must be declared" >&5 if eval "test \"`echo '$''{'bfd_cv_decl_needed_free'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < @@ -4984,7 +4971,7 @@ int main() { char *(*pfn) = (char *(*)) free ; return 0; } EOF -if { (eval echo configure:4988: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:4975: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_decl_needed_free=no else @@ -5005,12 +4992,12 @@ EOF fi echo $ac_n "checking whether getenv must be declared""... $ac_c" 1>&6 -echo "configure:5009: checking whether getenv must be declared" >&5 +echo "configure:4996: checking whether getenv must be declared" >&5 if eval "test \"`echo '$''{'bfd_cv_decl_needed_getenv'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < @@ -5031,7 +5018,7 @@ int main() { char *(*pfn) = (char *(*)) getenv ; return 0; } EOF -if { (eval echo configure:5035: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5022: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_decl_needed_getenv=no else @@ -5218,16 +5205,16 @@ if test "${target}" = "${host}"; then # Not all versions of AIX with -DAIX_CORE_DUMPX_CORE # have c_impl as a member of struct core_dumpx echo $ac_n "checking for c_impl in struct core_dumpx""... $ac_c" 1>&6 -echo "configure:5222: checking for c_impl in struct core_dumpx" >&5 +echo "configure:5209: checking for c_impl in struct core_dumpx" >&5 cat > conftest.$ac_ext < int main() { struct core_dumpx c; c.c_impl = 0; ; return 0; } EOF -if { (eval echo configure:5231: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5218: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* cat >> confdefs.h <<\EOF #define HAVE_ST_C_IMPL 1 @@ -5294,17 +5281,17 @@ rm -f conftest* do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:5298: checking for $ac_hdr" >&5 +echo "configure:5285: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:5308: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:5295: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -5332,12 +5319,12 @@ done if test "$ac_cv_header_sys_procfs_h" = yes; then echo $ac_n "checking for prstatus_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5336: checking for prstatus_t in sys/procfs.h" >&5 +echo "configure:5323: checking for prstatus_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_prstatus_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5337: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_prstatus_t=yes else @@ -5368,12 +5355,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_prstatus_t" 1>&6 echo $ac_n "checking for prstatus32_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5372: checking for prstatus32_t in sys/procfs.h" >&5 +echo "configure:5359: checking for prstatus32_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_prstatus32_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5373: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_prstatus32_t=yes else @@ -5404,12 +5391,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_prstatus32_t" 1>&6 echo $ac_n "checking for prstatus_t.pr_who in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5408: checking for prstatus_t.pr_who in sys/procfs.h" >&5 +echo "configure:5395: checking for prstatus_t.pr_who in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_member_prstatus_t_pr_who'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5409: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_member_prstatus_t_pr_who=yes else @@ -5440,12 +5427,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_member_prstatus_t_pr_who" 1>&6 echo $ac_n "checking for prstatus32_t.pr_who in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5444: checking for prstatus32_t.pr_who in sys/procfs.h" >&5 +echo "configure:5431: checking for prstatus32_t.pr_who in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_member_prstatus32_t_pr_who'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5445: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_member_prstatus32_t_pr_who=yes else @@ -5476,12 +5463,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_member_prstatus32_t_pr_who" 1>&6 echo $ac_n "checking for pstatus_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5480: checking for pstatus_t in sys/procfs.h" >&5 +echo "configure:5467: checking for pstatus_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_pstatus_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5481: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_pstatus_t=yes else @@ -5512,12 +5499,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_pstatus_t" 1>&6 echo $ac_n "checking for pxstatus_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5516: checking for pxstatus_t in sys/procfs.h" >&5 +echo "configure:5503: checking for pxstatus_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_pxstatus_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5517: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_pxstatus_t=yes else @@ -5548,12 +5535,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_pxstatus_t" 1>&6 echo $ac_n "checking for pstatus32_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5552: checking for pstatus32_t in sys/procfs.h" >&5 +echo "configure:5539: checking for pstatus32_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_pstatus32_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5553: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_pstatus32_t=yes else @@ -5584,12 +5571,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_pstatus32_t" 1>&6 echo $ac_n "checking for prpsinfo_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5588: checking for prpsinfo_t in sys/procfs.h" >&5 +echo "configure:5575: checking for prpsinfo_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_prpsinfo_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5589: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_prpsinfo_t=yes else @@ -5620,12 +5607,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_prpsinfo_t" 1>&6 echo $ac_n "checking for prpsinfo32_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5624: checking for prpsinfo32_t in sys/procfs.h" >&5 +echo "configure:5611: checking for prpsinfo32_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_prpsinfo32_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5625: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_prpsinfo32_t=yes else @@ -5656,12 +5643,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_prpsinfo32_t" 1>&6 echo $ac_n "checking for psinfo_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5660: checking for psinfo_t in sys/procfs.h" >&5 +echo "configure:5647: checking for psinfo_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_psinfo_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5661: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_psinfo_t=yes else @@ -5692,12 +5679,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_psinfo_t" 1>&6 echo $ac_n "checking for psinfo32_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5696: checking for psinfo32_t in sys/procfs.h" >&5 +echo "configure:5683: checking for psinfo32_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_psinfo32_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5697: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_psinfo32_t=yes else @@ -5728,12 +5715,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_psinfo32_t" 1>&6 echo $ac_n "checking for lwpstatus_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5732: checking for lwpstatus_t in sys/procfs.h" >&5 +echo "configure:5719: checking for lwpstatus_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_lwpstatus_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5733: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_lwpstatus_t=yes else @@ -5764,12 +5751,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_lwpstatus_t" 1>&6 echo $ac_n "checking for lwpxstatus_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5768: checking for lwpxstatus_t in sys/procfs.h" >&5 +echo "configure:5755: checking for lwpxstatus_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_lwpxstatus_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5769: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_lwpxstatus_t=yes else @@ -5800,12 +5787,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_lwpxstatus_t" 1>&6 echo $ac_n "checking for lwpstatus_t.pr_context in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5804: checking for lwpstatus_t.pr_context in sys/procfs.h" >&5 +echo "configure:5791: checking for lwpstatus_t.pr_context in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_member_lwpstatus_t_pr_context'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5805: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_member_lwpstatus_t_pr_context=yes else @@ -5836,12 +5823,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_member_lwpstatus_t_pr_context" 1>&6 echo $ac_n "checking for lwpstatus_t.pr_reg in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5840: checking for lwpstatus_t.pr_reg in sys/procfs.h" >&5 +echo "configure:5827: checking for lwpstatus_t.pr_reg in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_member_lwpstatus_t_pr_reg'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5841: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_member_lwpstatus_t_pr_reg=yes else @@ -5872,12 +5859,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_member_lwpstatus_t_pr_reg" 1>&6 echo $ac_n "checking for win32_pstatus_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5876: checking for win32_pstatus_t in sys/procfs.h" >&5 +echo "configure:5863: checking for win32_pstatus_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_win32_pstatus_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5877: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_win32_pstatus_t=yes else @@ -6029,6 +6016,7 @@ do # use one entry per line, even though this leads to long lines. a29kcoff_big_vec) tb="$tb coff-a29k.lo cofflink.lo" ;; a_out_adobe_vec) tb="$tb aout-adobe.lo aout32.lo" ;; + aix5coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;; aout0_big_vec) tb="$tb aout0.lo aout32.lo" ;; aout_arm_big_vec) tb="$tb aout-arm.lo aout32.lo" ;; aout_arm_little_vec) tb="$tb aout-arm.lo aout32.lo" ;; @@ -6061,6 +6049,7 @@ do bfd_elf32_d30v_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;; bfd_elf32_dlx_big_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;; bfd_elf32_fr30_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;; + bfd_elf32_frv_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;; bfd_elf32_h8300_vec) tb="$tb elf32-h8300.lo elf32.lo $elf" ;; bfd_elf32_hppa_linux_vec) tb="$tb elf32-hppa.lo elf32.lo $elf" ;; bfd_elf32_hppa_vec) tb="$tb elf32-hppa.lo elf32.lo $elf" ;; @@ -6093,23 +6082,19 @@ do bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf32.lo $elf" ;; bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf32.lo $elf" ;; bfd_elf32_s390_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; - bfd_elf32_sh_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; - bfd_elf32_shblin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; - bfd_elf32_shl_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; - bfd_elf32_shlin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; - bfd_elf32_shlnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; - bfd_elf32_shnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; # FIXME: We include cofflink.lo not because it's needed for # bfd_elf32_sh64[l]_vec, but because we include bfd_elf32_sh[l]_vec # which needs it but does not list it. Should be fixed in right place. bfd_elf32_sh64_vec) tb="$tb elf32-sh64.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" target_size=64 ;; bfd_elf32_sh64l_vec) tb="$tb elf32-sh64.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" target_size=64 ;; - bfd_elf64_sh64_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; - bfd_elf64_sh64l_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; - bfd_elf32_sh64nbsd_vec) tb="$tb elf32-sh64-nbsd.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" ;; bfd_elf32_sh64lnbsd_vec) tb="$tb elf32-sh64-nbsd.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" ;; - bfd_elf64_sh64nbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; - bfd_elf64_sh64lnbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; + bfd_elf32_sh64nbsd_vec) tb="$tb elf32-sh64-nbsd.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" ;; + bfd_elf32_sh_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; + bfd_elf32_shblin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; + bfd_elf32_shl_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; + bfd_elf32_shlin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; + bfd_elf32_shlnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; + bfd_elf32_shnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; bfd_elf32_sparc_vec) tb="$tb elf32-sparc.lo elf32.lo $elf" ;; bfd_elf32_tradbigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; @@ -6133,6 +6118,10 @@ do bfd_elf64_powerpc_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf"; target_size=64 ;; bfd_elf64_powerpcle_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;; bfd_elf64_s390_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;; + bfd_elf64_sh64_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; + bfd_elf64_sh64l_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; + bfd_elf64_sh64lnbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; + bfd_elf64_sh64nbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; bfd_elf64_sparc_vec) tb="$tb elf64-sparc.lo elf64.lo $elf"; target_size=64 ;; bfd_elf64_tradbigmips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; bfd_elf64_tradlittlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; @@ -6142,8 +6131,6 @@ do bfd_powerpc_pei_vec) tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;; bfd_powerpcle_pe_vec) tb="$tb pe-ppc.lo peigen.lo cofflink.lo" ;; bfd_powerpcle_pei_vec) tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;; - cisco_core_big_vec) tb="$tb cisco-core.lo" ;; - cisco_core_little_vec) tb="$tb cisco-core.lo" ;; cris_aout_vec) tb="$tb aout-cris.lo" ;; demo_64_vec) tb="$tb demo64.lo aout64.lo"; target_size=64 ;; ecoff_big_vec) tb="$tb coff-mips.lo ecoff.lo ecofflink.lo" ;; @@ -6185,6 +6172,7 @@ do m68knetbsd_vec) tb="$tb m68knetbsd.lo aout32.lo" ;; m68ksysvcoff_vec) tb="$tb coff-svm68k.lo cofflink.lo" ;; m88kbcs_vec) tb="$tb coff-m88k.lo" ;; + m88kmach3_vec) tb="$tb m88kmach3.lo aout32.lo" ;; mcore_pe_big_vec) tb="$tb pe-mcore.lo peigen.lo cofflink.lo" ;; mcore_pe_little_vec) tb="$tb pe-mcore.lo peigen.lo cofflink.lo" ;; mcore_pei_big_vec) tb="$tb pei-mcore.lo peigen.lo cofflink.lo" ;; @@ -6204,7 +6192,6 @@ do ppcboot_vec) tb="$tb ppcboot.lo" ;; riscix_vec) tb="$tb aout32.lo riscix.lo" ;; rs6000coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;; - aix5coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;; rs6000coff_vec) tb="$tb coff-rs6000.lo xcofflink.lo" ;; shcoff_small_vec) tb="$tb coff-sh.lo cofflink.lo" ;; shcoff_vec) tb="$tb coff-sh.lo cofflink.lo" ;; @@ -6219,10 +6206,7 @@ do sparclynx_aout_vec) tb="$tb sparclynx.lo lynx-core.lo aout32.lo" ;; sparclynx_coff_vec) tb="$tb cf-sparclynx.lo lynx-core.lo" ;; sparcnetbsd_vec) tb="$tb sparcnetbsd.lo aout32.lo" ;; - srec_vec) tb="$tb srec.lo" ;; sunos_big_vec) tb="$tb sunos.lo aout32.lo" ;; - symbolsrec_vec) tb="$tb srec.lo" ;; - tekhex_vec) tb="$tb tekhex.lo" ;; tic30_aout_vec) tb="$tb aout-tic30.lo" ;; tic30_coff_vec) tb="$tb coff-tic30.lo" ;; tic54x_coff0_beh_vec) tb="$tb coff-tic54x.lo" ;; @@ -6241,6 +6225,13 @@ do we32kcoff_vec) tb="$tb coff-we32k.lo" ;; z8kcoff_vec) tb="$tb coff-z8k.lo reloc16.lo" ;; + # These appear out of order in targets.c + srec_vec) tb="$tb srec.lo" ;; + symbolsrec_vec) tb="$tb srec.lo" ;; + tekhex_vec) tb="$tb tekhex.lo" ;; + cisco_core_big_vec) tb="$tb cisco-core.lo" ;; + cisco_core_little_vec) tb="$tb cisco-core.lo" ;; + "") ;; *) { echo "configure: error: *** unknown target vector $vec" 1>&2; exit 1; } ;; esac @@ -6309,10 +6300,10 @@ case ${host64}-${target64}-${want64} in if test -n "$GCC" ; then bad_64bit_gcc=no; echo $ac_n "checking for gcc version with buggy 64-bit support""... $ac_c" 1>&6 -echo "configure:6313: checking for gcc version with buggy 64-bit support" >&5 +echo "configure:6304: checking for gcc version with buggy 64-bit support" >&5 # Add more tests for gcc versions with non-working 64-bit support here. cat > conftest.$ac_ext <&6 -echo "configure:6361: checking for $ac_hdr" >&5 +echo "configure:6352: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:6371: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:6362: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -6396,12 +6387,12 @@ done for ac_func in getpagesize do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:6400: checking for $ac_func" >&5 +echo "configure:6391: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:6419: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -6449,7 +6440,7 @@ fi done echo $ac_n "checking for working mmap""... $ac_c" 1>&6 -echo "configure:6453: checking for working mmap" >&5 +echo "configure:6444: checking for working mmap" >&5 if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -6457,7 +6448,7 @@ else ac_cv_func_mmap_fixed_mapped=no else cat > conftest.$ac_ext < #include -#if HAVE_SYS_TYPES_H -# include -#endif - -#if HAVE_STDLIB_H -# include -#endif - -#if HAVE_SYS_STAT_H -# include -#endif - -#if HAVE_UNISTD_H -# include -#endif - /* This mess was copied from the GNU getpagesize.h. */ #ifndef HAVE_GETPAGESIZE +# ifdef HAVE_UNISTD_H +# include +# endif /* Assume that all systems that can run configure have sys/param.h. */ # ifndef HAVE_SYS_PARAM_H @@ -6610,7 +6588,7 @@ main() } EOF -if { (eval echo configure:6614: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:6592: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_func_mmap_fixed_mapped=yes else @@ -6635,12 +6613,12 @@ fi for ac_func in madvise mprotect do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:6639: checking for $ac_func" >&5 +echo "configure:6617: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:6645: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else diff -uprN binutils-2.12.90.0.11/bfd/configure.in binutils-2.12.90.0.12/bfd/configure.in --- binutils-2.12.90.0.11/bfd/configure.in Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/bfd/configure.in Tue Jun 18 21:41:58 2002 @@ -7,7 +7,7 @@ AC_INIT(libbfd.c) AC_CANONICAL_SYSTEM AC_ISC_POSIX -AM_INIT_AUTOMAKE(bfd, 2.12.90.0.11) +AM_INIT_AUTOMAKE(bfd, 2.12.90.0.12) # Uncomment the next line to remove the date from the reported bfd version #is_release=y @@ -536,6 +536,7 @@ do # use one entry per line, even though this leads to long lines. a29kcoff_big_vec) tb="$tb coff-a29k.lo cofflink.lo" ;; a_out_adobe_vec) tb="$tb aout-adobe.lo aout32.lo" ;; + aix5coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;; aout0_big_vec) tb="$tb aout0.lo aout32.lo" ;; aout_arm_big_vec) tb="$tb aout-arm.lo aout32.lo" ;; aout_arm_little_vec) tb="$tb aout-arm.lo aout32.lo" ;; @@ -568,6 +569,7 @@ do bfd_elf32_d30v_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;; bfd_elf32_dlx_big_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;; bfd_elf32_fr30_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;; + bfd_elf32_frv_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;; bfd_elf32_h8300_vec) tb="$tb elf32-h8300.lo elf32.lo $elf" ;; bfd_elf32_hppa_linux_vec) tb="$tb elf32-hppa.lo elf32.lo $elf" ;; bfd_elf32_hppa_vec) tb="$tb elf32-hppa.lo elf32.lo $elf" ;; @@ -600,23 +602,19 @@ do bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf32.lo $elf" ;; bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf32.lo $elf" ;; bfd_elf32_s390_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; - bfd_elf32_sh_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; - bfd_elf32_shblin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; - bfd_elf32_shl_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; - bfd_elf32_shlin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; - bfd_elf32_shlnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; - bfd_elf32_shnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; # FIXME: We include cofflink.lo not because it's needed for # bfd_elf32_sh64[l]_vec, but because we include bfd_elf32_sh[l]_vec # which needs it but does not list it. Should be fixed in right place. bfd_elf32_sh64_vec) tb="$tb elf32-sh64.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" target_size=64 ;; bfd_elf32_sh64l_vec) tb="$tb elf32-sh64.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" target_size=64 ;; - bfd_elf64_sh64_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; - bfd_elf64_sh64l_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; - bfd_elf32_sh64nbsd_vec) tb="$tb elf32-sh64-nbsd.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" ;; bfd_elf32_sh64lnbsd_vec) tb="$tb elf32-sh64-nbsd.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" ;; - bfd_elf64_sh64nbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; - bfd_elf64_sh64lnbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; + bfd_elf32_sh64nbsd_vec) tb="$tb elf32-sh64-nbsd.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" ;; + bfd_elf32_sh_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; + bfd_elf32_shblin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; + bfd_elf32_shl_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; + bfd_elf32_shlin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; + bfd_elf32_shlnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; + bfd_elf32_shnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; bfd_elf32_sparc_vec) tb="$tb elf32-sparc.lo elf32.lo $elf" ;; bfd_elf32_tradbigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; @@ -640,6 +638,10 @@ do bfd_elf64_powerpc_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf"; target_size=64 ;; bfd_elf64_powerpcle_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;; bfd_elf64_s390_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;; + bfd_elf64_sh64_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; + bfd_elf64_sh64l_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; + bfd_elf64_sh64lnbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; + bfd_elf64_sh64nbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; bfd_elf64_sparc_vec) tb="$tb elf64-sparc.lo elf64.lo $elf"; target_size=64 ;; bfd_elf64_tradbigmips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; bfd_elf64_tradlittlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; @@ -649,8 +651,6 @@ do bfd_powerpc_pei_vec) tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;; bfd_powerpcle_pe_vec) tb="$tb pe-ppc.lo peigen.lo cofflink.lo" ;; bfd_powerpcle_pei_vec) tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;; - cisco_core_big_vec) tb="$tb cisco-core.lo" ;; - cisco_core_little_vec) tb="$tb cisco-core.lo" ;; cris_aout_vec) tb="$tb aout-cris.lo" ;; demo_64_vec) tb="$tb demo64.lo aout64.lo"; target_size=64 ;; ecoff_big_vec) tb="$tb coff-mips.lo ecoff.lo ecofflink.lo" ;; @@ -692,6 +692,7 @@ do m68knetbsd_vec) tb="$tb m68knetbsd.lo aout32.lo" ;; m68ksysvcoff_vec) tb="$tb coff-svm68k.lo cofflink.lo" ;; m88kbcs_vec) tb="$tb coff-m88k.lo" ;; + m88kmach3_vec) tb="$tb m88kmach3.lo aout32.lo" ;; mcore_pe_big_vec) tb="$tb pe-mcore.lo peigen.lo cofflink.lo" ;; mcore_pe_little_vec) tb="$tb pe-mcore.lo peigen.lo cofflink.lo" ;; mcore_pei_big_vec) tb="$tb pei-mcore.lo peigen.lo cofflink.lo" ;; @@ -711,7 +712,6 @@ do ppcboot_vec) tb="$tb ppcboot.lo" ;; riscix_vec) tb="$tb aout32.lo riscix.lo" ;; rs6000coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;; - aix5coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;; rs6000coff_vec) tb="$tb coff-rs6000.lo xcofflink.lo" ;; shcoff_small_vec) tb="$tb coff-sh.lo cofflink.lo" ;; shcoff_vec) tb="$tb coff-sh.lo cofflink.lo" ;; @@ -726,10 +726,7 @@ do sparclynx_aout_vec) tb="$tb sparclynx.lo lynx-core.lo aout32.lo" ;; sparclynx_coff_vec) tb="$tb cf-sparclynx.lo lynx-core.lo" ;; sparcnetbsd_vec) tb="$tb sparcnetbsd.lo aout32.lo" ;; - srec_vec) tb="$tb srec.lo" ;; sunos_big_vec) tb="$tb sunos.lo aout32.lo" ;; - symbolsrec_vec) tb="$tb srec.lo" ;; - tekhex_vec) tb="$tb tekhex.lo" ;; tic30_aout_vec) tb="$tb aout-tic30.lo" ;; tic30_coff_vec) tb="$tb coff-tic30.lo" ;; tic54x_coff0_beh_vec) tb="$tb coff-tic54x.lo" ;; @@ -748,6 +745,13 @@ do we32kcoff_vec) tb="$tb coff-we32k.lo" ;; z8kcoff_vec) tb="$tb coff-z8k.lo reloc16.lo" ;; + # These appear out of order in targets.c + srec_vec) tb="$tb srec.lo" ;; + symbolsrec_vec) tb="$tb srec.lo" ;; + tekhex_vec) tb="$tb tekhex.lo" ;; + cisco_core_big_vec) tb="$tb cisco-core.lo" ;; + cisco_core_little_vec) tb="$tb cisco-core.lo" ;; + "") ;; *) AC_MSG_ERROR(*** unknown target vector $vec) ;; esac diff -uprN binutils-2.12.90.0.11/bfd/cpu-frv.c binutils-2.12.90.0.12/bfd/cpu-frv.c --- binutils-2.12.90.0.11/bfd/cpu-frv.c Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/bfd/cpu-frv.c Tue Jun 18 21:41:58 2002 @@ -0,0 +1,64 @@ +/* BFD support for the FRV processor. + Copyright (C) 2002 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + +enum { + I_frv_generic, + I_frv_simple, + I_frv_500, + I_frv_300, +}; + +#define FRV_ARCH(MACHINE, NAME, DEFAULT, NEXT) \ +{ \ + 32, /* 32 bits in a word */ \ + 32, /* 32 bits in an address */ \ + 8, /* 8 bits in a byte */ \ + bfd_arch_frv, /* architecture */ \ + MACHINE, /* which machine */ \ + "frv", /* architecture name */ \ + NAME, /* machine name */ \ + 4, /* default alignment */ \ + DEFAULT, /* is this the default? */ \ + bfd_default_compatible, /* architecture comparison fn */ \ + bfd_default_scan, /* string to architecture convert fn */ \ + NEXT /* next in list */ \ +} + +static const bfd_arch_info_type arch_info_300 + = FRV_ARCH (bfd_mach_fr300, "fr300", false, (bfd_arch_info_type *)0); + +static const bfd_arch_info_type arch_info_400 + = FRV_ARCH (bfd_mach_fr400, "fr400", false, &arch_info_300); + +static const bfd_arch_info_type arch_info_500 + = FRV_ARCH (bfd_mach_fr500, "fr500", false, &arch_info_400); + +static const bfd_arch_info_type arch_info_simple + = FRV_ARCH (bfd_mach_frvsimple, "simple", false, &arch_info_500); + +static const bfd_arch_info_type arch_info_tomcat + = FRV_ARCH (bfd_mach_frvtomcat, "tomcat", false, &arch_info_simple); + +const bfd_arch_info_type bfd_frv_arch + = FRV_ARCH (bfd_mach_frv, "frv", true, &arch_info_tomcat); + diff -uprN binutils-2.12.90.0.11/bfd/elf-hppa.h binutils-2.12.90.0.12/bfd/elf-hppa.h --- binutils-2.12.90.0.11/bfd/elf-hppa.h Mon Apr 8 10:37:22 2002 +++ binutils-2.12.90.0.12/bfd/elf-hppa.h Tue Jun 18 21:41:58 2002 @@ -1296,22 +1296,22 @@ elf_hppa_final_link (abfd, info) address of the .plt + gp_offset. If no .plt is found, then look for .dlt, .opd and .data (in - that order) and set __gp to the base address of whichever section - is found first. */ + that order) and set __gp to the base address of whichever + section is found first. */ sec = hppa_info->plt_sec; - if (sec) + if (sec && ! (sec->flags & SEC_EXCLUDE)) gp_val = (sec->output_offset + sec->output_section->vma + hppa_info->gp_offset); else { sec = hppa_info->dlt_sec; - if (!sec) + if (!sec || (sec->flags & SEC_EXCLUDE)) sec = hppa_info->opd_sec; - if (!sec) + if (!sec || (sec->flags & SEC_EXCLUDE)) sec = bfd_get_section_by_name (abfd, ".data"); - if (!sec) + if (!sec || (sec->flags & SEC_EXCLUDE)) return false; gp_val = sec->output_offset + sec->output_section->vma; @@ -2074,11 +2074,14 @@ elf_hppa_final_link_relocate (rel, input hppa_info->opd_sec->contents + dyn_h->opd_offset + 24); } - /* We want the value of the OPD offset for this symbol, not - the symbol's actual address. */ - value = (dyn_h->opd_offset - + hppa_info->opd_sec->output_offset - + hppa_info->opd_sec->output_section->vma); + if (dyn_h->want_opd) + /* We want the value of the OPD offset for this symbol. */ + value = (dyn_h->opd_offset + + hppa_info->opd_sec->output_offset + + hppa_info->opd_sec->output_section->vma); + else + /* We want the address of the symbol. */ + value += addend; bfd_put_64 (input_bfd, value, hit_data); return bfd_reloc_ok; diff -uprN binutils-2.12.90.0.11/bfd/elf-strtab.c binutils-2.12.90.0.12/bfd/elf-strtab.c --- binutils-2.12.90.0.11/bfd/elf-strtab.c Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/bfd/elf-strtab.c Tue Jun 18 21:41:58 2002 @@ -352,7 +352,7 @@ _bfd_elf_strtab_finalize (tab) qsort (array, size, sizeof (struct elf_strtab_hash_entry *), cmplengthentry); - last4tab = htab_create (size * 4, NULL, last4_eq, NULL); + last4tab = htab_create_alloc (size * 4, NULL, last4_eq, NULL, calloc, free); if (last4tab == NULL) goto alloc_failure; diff -uprN binutils-2.12.90.0.11/bfd/elf32-d10v.c binutils-2.12.90.0.12/bfd/elf32-d10v.c --- binutils-2.12.90.0.11/bfd/elf32-d10v.c Thu Mar 7 11:52:36 2002 +++ binutils-2.12.90.0.12/bfd/elf32-d10v.c Tue Jun 18 21:41:58 2002 @@ -1,5 +1,5 @@ /* D10V-specific support for 32-bit ELF - Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. Contributed by Martin Hunt (hunt@cygnus.com). This file is part of BFD, the Binary File Descriptor library. @@ -67,10 +67,10 @@ static reloc_howto_type elf_d10v_howto_t HOWTO (R_D10V_10_PCREL_R, /* type */ 2, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ - 8, /* bitsize */ + 7, /* bitsize */ true, /* pc_relative */ 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ + complain_overflow_bitfield, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ "R_D10V_10_PCREL_R", /* name */ false, /* partial_inplace */ @@ -83,10 +83,10 @@ static reloc_howto_type elf_d10v_howto_t HOWTO (R_D10V_10_PCREL_L, /* type */ 2, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ - 8, /* bitsize */ + 7, /* bitsize */ true, /* pc_relative */ 15, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ + complain_overflow_bitfield, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ "R_D10V_10_PCREL_L", /* name */ false, /* partial_inplace */ @@ -128,10 +128,10 @@ static reloc_howto_type elf_d10v_howto_t HOWTO (R_D10V_18_PCREL, /* type */ 2, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ + 15, /* bitsize */ true, /* pc_relative */ 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ + complain_overflow_bitfield, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ "R_D10V_18_PCREL", /* name */ false, /* partial_inplace */ diff -uprN binutils-2.12.90.0.11/bfd/elf32-frv.c binutils-2.12.90.0.12/bfd/elf32-frv.c --- binutils-2.12.90.0.11/bfd/elf32-frv.c Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/bfd/elf32-frv.c Tue Jun 18 21:41:58 2002 @@ -0,0 +1,1405 @@ +/* FRV-specific support for 32-bit ELF. + Copyright (C) 2002 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/frv.h" + +/* Forward declarations. */ +static bfd_reloc_status_type elf32_frv_relocate_lo16 + PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static bfd_reloc_status_type elf32_frv_relocate_hi16 + PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static bfd_reloc_status_type elf32_frv_relocate_label24 + PARAMS ((bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static bfd_reloc_status_type elf32_frv_relocate_gprel12 + PARAMS ((struct bfd_link_info *, bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static bfd_reloc_status_type elf32_frv_relocate_gprelu12 + PARAMS ((struct bfd_link_info *, bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static bfd_reloc_status_type elf32_frv_relocate_gprello + PARAMS ((struct bfd_link_info *, bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static bfd_reloc_status_type elf32_frv_relocate_gprelhi + PARAMS ((struct bfd_link_info *, bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static reloc_howto_type *frv_reloc_type_lookup + PARAMS ((bfd *, bfd_reloc_code_real_type)); +static void frv_info_to_howto_rela + PARAMS ((bfd *, arelent *, Elf32_Internal_Rela *)); +static boolean elf32_frv_relocate_section + PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, Elf_Internal_Sym *, asection **)); +static boolean elf32_frv_add_symbol_hook + PARAMS (( bfd *, struct bfd_link_info *, const Elf_Internal_Sym *, const char **, flagword *, asection **, bfd_vma *)); +static bfd_reloc_status_type frv_final_link_relocate + PARAMS ((reloc_howto_type *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, bfd_vma)); +static boolean elf32_frv_gc_sweep_hook + PARAMS ((bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *)); +static asection * elf32_frv_gc_mark_hook + PARAMS ((bfd *, struct bfd_link_info *, Elf_Internal_Rela *, struct elf_link_hash_entry *, Elf_Internal_Sym *)); +static boolean elf32_frv_check_relocs + PARAMS ((bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *)); +static int elf32_frv_machine PARAMS ((bfd *)); +static boolean elf32_frv_object_p PARAMS ((bfd *)); +static boolean frv_elf_set_private_flags PARAMS ((bfd *, flagword)); +static boolean frv_elf_copy_private_bfd_data PARAMS ((bfd *, bfd *)); +static boolean frv_elf_merge_private_bfd_data PARAMS ((bfd *, bfd *)); +static boolean frv_elf_print_private_bfd_data PARAMS ((bfd *, PTR)); + +static reloc_howto_type elf32_frv_howto_table [] = +{ + /* This reloc does nothing. */ + HOWTO (R_FRV_NONE, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_NONE", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 32 bit absolute relocation. */ + HOWTO (R_FRV_32, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_32", /* name */ + false, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 16 bit pc-relative relocation. */ + HOWTO (R_FRV_LABEL16, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_LABEL16", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + true), /* pcrel_offset */ + + /* A 24-bit pc-relative relocation. */ + HOWTO (R_FRV_LABEL24, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 26, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_LABEL24", /* name */ + false, /* partial_inplace */ + 0x7e03ffff, /* src_mask */ + 0x7e03ffff, /* dst_mask */ + true), /* pcrel_offset */ + + HOWTO (R_FRV_LO16, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_LO16", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_FRV_HI16, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_HI16", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_FRV_GPREL12, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 12, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_GPREL12", /* name */ + false, /* partial_inplace */ + 0xfff, /* src_mask */ + 0xfff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_FRV_GPRELU12, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 12, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_GPRELU12", /* name */ + false, /* partial_inplace */ + 0xfff, /* src_mask */ + 0x3f03f, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_FRV_GPREL32, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_GPREL32", /* name */ + false, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_FRV_GPRELHI, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_GPRELHI", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_FRV_GPRELLO, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_GPRELLO", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ +}; + +/* GNU extension to record C++ vtable hierarchy. */ +static reloc_howto_type elf32_frv_vtinherit_howto = + HOWTO (R_FRV_GNU_VTINHERIT, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_FRV_GNU_VTINHERIT", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false); /* pcrel_offset */ + + /* GNU extension to record C++ vtable member usage. */ +static reloc_howto_type elf32_frv_vtentry_howto = + HOWTO (R_FRV_GNU_VTENTRY, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_elf_rel_vtable_reloc_fn, /* special_function */ + "R_FRV_GNU_VTENTRY", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false); /* pcrel_offset */ + +/* Map BFD reloc types to FRV ELF reloc types. */ +#if 0 +struct frv_reloc_map +{ + unsigned int bfd_reloc_val; + unsigned int frv_reloc_val; +}; + +static const struct frv_reloc_map frv_reloc_map [] = +{ + { BFD_RELOC_NONE, R_FRV_NONE }, + { BFD_RELOC_32, R_FRV_32 }, + { BFD_RELOC_FRV_LABEL16, R_FRV_LABEL16 }, + { BFD_RELOC_FRV_LABEL24, R_FRV_LABEL24 }, + { BFD_RELOC_FRV_LO16, R_FRV_LO16 }, + { BFD_RELOC_FRV_HI16, R_FRV_HI16 }, + { BFD_RELOC_FRV_GPREL12, R_FRV_GPREL12 }, + { BFD_RELOC_FRV_GPRELU12, R_FRV_GPRELU12 }, + { BFD_RELOC_FRV_GPREL32, R_FRV_GPREL32 }, + { BFD_RELOC_FRV_GPRELHI, R_FRV_GPRELHI }, + { BFD_RELOC_FRV_GPRELLO, R_FRV_GPRELLO }, + { BFD_RELOC_VTABLE_INHERIT, R_FRV_GNU_VTINHERIT }, + { BFD_RELOC_VTABLE_ENTRY, R_FRV_GNU_VTENTRY }, +}; +#endif + +/* Handle an FRV small data reloc. */ + +static bfd_reloc_status_type +elf32_frv_relocate_gprel12 (info, input_bfd, input_section, relocation, contents, value) + struct bfd_link_info *info; + bfd *input_bfd; + asection *input_section; + Elf_Internal_Rela *relocation; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + bfd_vma gp; + struct bfd_link_hash_entry *h; + + h = bfd_link_hash_lookup (info->hash, "_gp", false, false, true); + + gp = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + value -= input_section->output_section->vma; + value -= (gp - input_section->output_section->vma); + + insn = bfd_get_32 (input_bfd, contents + relocation->r_offset); + + value += relocation->r_addend; + + if ((long) value > 0x7ff || (long) value < -0x800) + return bfd_reloc_overflow; + + bfd_put_32 (input_bfd, + (insn & 0xfffff000) | (value & 0xfff), + contents + relocation->r_offset); + + return bfd_reloc_ok; +} + +/* Handle an FRV small data reloc. for the u12 field. */ + +static bfd_reloc_status_type +elf32_frv_relocate_gprelu12 (info, input_bfd, input_section, relocation, contents, value) + struct bfd_link_info *info; + bfd *input_bfd; + asection *input_section; + Elf_Internal_Rela *relocation; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + bfd_vma gp; + struct bfd_link_hash_entry *h; + bfd_vma mask; + + h = bfd_link_hash_lookup (info->hash, "_gp", false, false, true); + + gp = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + value -= input_section->output_section->vma; + value -= (gp - input_section->output_section->vma); + + insn = bfd_get_32 (input_bfd, contents + relocation->r_offset); + + value += relocation->r_addend; + + if ((long) value > 0x7ff || (long) value < -0x800) + return bfd_reloc_overflow; + + /* The high 6 bits go into bits 17-12. The low 6 bits go into bits 5-0. */ + mask = 0x3f03f; + insn = (insn & ~mask) | ((value & 0xfc0) << 12) | (value & 0x3f); + + bfd_put_32 (input_bfd, insn, contents + relocation->r_offset); + + return bfd_reloc_ok; +} + +/* Handle an FRV ELF HI16 reloc. */ + +static bfd_reloc_status_type +elf32_frv_relocate_hi16 (input_bfd, relhi, contents, value) + bfd *input_bfd; + Elf_Internal_Rela *relhi; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + + insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); + + value += relhi->r_addend; + value = ((value >> 16) & 0xffff); + + insn = (insn & 0xffff0000) | value; + + if ((long) value > 0xffff || (long) value < -0x10000) + return bfd_reloc_overflow; + + bfd_put_32 (input_bfd, insn, contents + relhi->r_offset); + return bfd_reloc_ok; + +} +static bfd_reloc_status_type +elf32_frv_relocate_lo16 (input_bfd, rello, contents, value) + bfd *input_bfd; + Elf_Internal_Rela *rello; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + + insn = bfd_get_32 (input_bfd, contents + rello->r_offset); + + value += rello->r_addend; + value = value & 0xffff; + + insn = (insn & 0xffff0000) | value; + + if ((long) value > 0xffff || (long) value < -0x10000) + return bfd_reloc_overflow; + + bfd_put_32 (input_bfd, insn, contents + rello->r_offset); + return bfd_reloc_ok; +} + +/* Perform the relocation for the CALL label24 instruction. */ + +static bfd_reloc_status_type +elf32_frv_relocate_label24 (input_bfd, input_section, rello, contents, value) + bfd *input_bfd; + asection *input_section; + Elf_Internal_Rela *rello; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + bfd_vma label6; + bfd_vma label18; + + /* The format for the call instruction is: + + 0 000000 0001111 000000000000000000 + label6 opcode label18 + + The branch calculation is: pc + (4*label24) + where label24 is the concatenation of label6 and label18. */ + + /* Grab the instruction. */ + insn = bfd_get_32 (input_bfd, contents + rello->r_offset); + + value -= input_section->output_section->vma + input_section->output_offset; + value -= rello->r_offset; + value += rello->r_addend; + + value = value >> 2; + + label6 = value & 0xfc0000; + label6 = label6 << 7; + + label18 = value & 0x3ffff; + + insn = insn & 0x803c0000; + insn = insn | label6; + insn = insn | label18; + + bfd_put_32 (input_bfd, insn, contents + rello->r_offset); + + return bfd_reloc_ok; +} + +static bfd_reloc_status_type +elf32_frv_relocate_gprelhi (info, input_bfd, input_section, relocation, contents, value) + struct bfd_link_info *info; + bfd *input_bfd; + asection *input_section; + Elf_Internal_Rela *relocation; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + bfd_vma gp; + struct bfd_link_hash_entry *h; + + h = bfd_link_hash_lookup (info->hash, "_gp", false, false, true); + + gp = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + value -= input_section->output_section->vma; + value -= (gp - input_section->output_section->vma); + value += relocation->r_addend; + value = ((value >> 16) & 0xffff); + + if ((long) value > 0xffff || (long) value < -0x10000) + return bfd_reloc_overflow; + + insn = bfd_get_32 (input_bfd, contents + relocation->r_offset); + insn = (insn & 0xffff0000) | value; + + bfd_put_32 (input_bfd, insn, contents + relocation->r_offset); + return bfd_reloc_ok; +} + +static bfd_reloc_status_type +elf32_frv_relocate_gprello (info, input_bfd, input_section, relocation, contents, value) + struct bfd_link_info *info; + bfd *input_bfd; + asection *input_section; + Elf_Internal_Rela *relocation; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + bfd_vma gp; + struct bfd_link_hash_entry *h; + + h = bfd_link_hash_lookup (info->hash, "_gp", false, false, true); + + gp = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + value -= input_section->output_section->vma; + value -= (gp - input_section->output_section->vma); + value += relocation->r_addend; + value = value & 0xffff; + + if ((long) value > 0xffff || (long) value < -0x10000) + return bfd_reloc_overflow; + + insn = bfd_get_32 (input_bfd, contents + relocation->r_offset); + insn = (insn & 0xffff0000) | value; + + bfd_put_32 (input_bfd, insn, contents + relocation->r_offset); + + return bfd_reloc_ok; +} + +static reloc_howto_type * +frv_reloc_type_lookup (abfd, code) + bfd * abfd ATTRIBUTE_UNUSED; + bfd_reloc_code_real_type code; +{ + switch (code) + { + default: + break; + + case BFD_RELOC_NONE: + return &elf32_frv_howto_table[ (int) R_FRV_NONE]; + + case BFD_RELOC_32: + case BFD_RELOC_CTOR: + return &elf32_frv_howto_table[ (int) R_FRV_32]; + + case BFD_RELOC_FRV_LABEL16: + return &elf32_frv_howto_table[ (int) R_FRV_LABEL16]; + + case BFD_RELOC_FRV_LABEL24: + return &elf32_frv_howto_table[ (int) R_FRV_LABEL24]; + + case BFD_RELOC_FRV_LO16: + return &elf32_frv_howto_table[ (int) R_FRV_LO16]; + + case BFD_RELOC_FRV_HI16: + return &elf32_frv_howto_table[ (int) R_FRV_HI16]; + + case BFD_RELOC_FRV_GPREL12: + return &elf32_frv_howto_table[ (int) R_FRV_GPREL12]; + + case BFD_RELOC_FRV_GPRELU12: + return &elf32_frv_howto_table[ (int) R_FRV_GPRELU12]; + + case BFD_RELOC_FRV_GPREL32: + return &elf32_frv_howto_table[ (int) R_FRV_GPREL32]; + + case BFD_RELOC_FRV_GPRELHI: + return &elf32_frv_howto_table[ (int) R_FRV_GPRELHI]; + + case BFD_RELOC_FRV_GPRELLO: + return &elf32_frv_howto_table[ (int) R_FRV_GPRELLO]; + + case BFD_RELOC_VTABLE_INHERIT: + return &elf32_frv_vtinherit_howto; + + case BFD_RELOC_VTABLE_ENTRY: + return &elf32_frv_vtentry_howto; + } + + return NULL; +} + +/* Set the howto pointer for an FRV ELF reloc. */ + +static void +frv_info_to_howto_rela (abfd, cache_ptr, dst) + bfd * abfd ATTRIBUTE_UNUSED; + arelent * cache_ptr; + Elf32_Internal_Rela * dst; +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + switch (r_type) + { + case R_FRV_GNU_VTINHERIT: + cache_ptr->howto = &elf32_frv_vtinherit_howto; + break; + + case R_FRV_GNU_VTENTRY: + cache_ptr->howto = &elf32_frv_vtentry_howto; + break; + + default: + cache_ptr->howto = & elf32_frv_howto_table [r_type]; + break; + } +} + +/* Perform a single relocation. By default we use the standard BFD + routines, but a few relocs, we have to do them ourselves. */ + +static bfd_reloc_status_type +frv_final_link_relocate (howto, input_bfd, input_section, contents, rel, relocation) + reloc_howto_type * howto; + bfd * input_bfd; + asection * input_section; + bfd_byte * contents; + Elf_Internal_Rela * rel; + bfd_vma relocation; +{ + return _bfd_final_link_relocate (howto, input_bfd, input_section, + contents, rel->r_offset, relocation, + rel->r_addend); +} + + +/* Relocate an FRV ELF section. + There is some attempt to make this function usable for many architectures, + both USE_REL and USE_RELA ['twould be nice if such a critter existed], + if only to serve as a learning tool. + + The RELOCATE_SECTION function is called by the new ELF backend linker + to handle the relocations for a section. + + The relocs are always passed as Rela structures; if the section + actually uses Rel structures, the r_addend field will always be + zero. + + This function is responsible for adjusting the section contents as + necessary, and (if using Rela relocs and generating a relocateable + output file) adjusting the reloc addend as necessary. + + This function does not have to worry about setting the reloc + address or the reloc symbol index. + + LOCAL_SYMS is a pointer to the swapped in local symbols. + + LOCAL_SECTIONS is an array giving the section in the input file + corresponding to the st_shndx field of each local symbol. + + The global hash table entry for the global symbols can be found + via elf_sym_hashes (input_bfd). + + When generating relocateable output, this function must handle + STB_LOCAL/STT_SECTION symbols specially. The output symbol is + going to be the section symbol corresponding to the output + section, which means that the addend must be adjusted + accordingly. */ + +static boolean +elf32_frv_relocate_section (output_bfd, info, input_bfd, input_section, + contents, relocs, local_syms, local_sections) + bfd * output_bfd ATTRIBUTE_UNUSED; + struct bfd_link_info * info; + bfd * input_bfd; + asection * input_section; + bfd_byte * contents; + Elf_Internal_Rela * relocs; + Elf_Internal_Sym * local_syms; + asection ** local_sections; +{ + Elf_Internal_Shdr * symtab_hdr; + struct elf_link_hash_entry ** sym_hashes; + Elf_Internal_Rela * rel; + Elf_Internal_Rela * relend; + + symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (input_bfd); + relend = relocs + input_section->reloc_count; + + for (rel = relocs; rel < relend; rel ++) + { + reloc_howto_type * howto; + unsigned long r_symndx; + Elf_Internal_Sym * sym; + asection * sec; + struct elf_link_hash_entry * h; + bfd_vma relocation; + bfd_reloc_status_type r; + const char * name = NULL; + int r_type; + + r_type = ELF32_R_TYPE (rel->r_info); + + if ( r_type == R_FRV_GNU_VTINHERIT + || r_type == R_FRV_GNU_VTENTRY) + continue; + + r_symndx = ELF32_R_SYM (rel->r_info); + + if (info->relocateable) + { + /* This is a relocateable link. We don't have to change + anything, unless the reloc is against a section symbol, + in which case we have to adjust according to where the + section symbol winds up in the output section. */ + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + + if (ELF_ST_TYPE (sym->st_info) == STT_SECTION) + { + sec = local_sections [r_symndx]; + rel->r_addend += sec->output_offset + sym->st_value; + } + } + + continue; + } + + /* This is a final link. */ + howto = elf32_frv_howto_table + ELF32_R_TYPE (rel->r_info); + h = NULL; + sym = NULL; + sec = NULL; + + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections [r_symndx]; + relocation = (sec->output_section->vma + + sec->output_offset + + sym->st_value); + + name = bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name); + name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name; + } + else + { + h = sym_hashes [r_symndx - symtab_hdr->sh_info]; + + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + name = h->root.root.string; + + if (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak) + { + sec = h->root.u.def.section; + relocation = (h->root.u.def.value + + sec->output_section->vma + + sec->output_offset); + } + else if (h->root.type == bfd_link_hash_undefweak) + { + relocation = 0; + } + else + { + if (! ((*info->callbacks->undefined_symbol) + (info, h->root.root.string, input_bfd, + input_section, rel->r_offset, true))) + return false; + relocation = 0; + } + } + + if (r_type == R_FRV_HI16) + r = elf32_frv_relocate_hi16 (input_bfd, rel, contents, relocation); + + else if (r_type == R_FRV_LO16) + r = elf32_frv_relocate_lo16 (input_bfd, rel, contents, relocation); + + else if (r_type == R_FRV_LABEL24) + r = elf32_frv_relocate_label24 (input_bfd, input_section, rel, contents, relocation); + + else if (r_type == R_FRV_GPREL12) + r = elf32_frv_relocate_gprel12 (info, input_bfd, input_section, rel, contents, relocation); + + else if (r_type == R_FRV_GPRELU12) + r = elf32_frv_relocate_gprelu12 (info, input_bfd, input_section, rel, contents, relocation); + + else if (r_type == R_FRV_GPRELLO) + r = elf32_frv_relocate_gprello (info, input_bfd, input_section, rel, contents, relocation); + + else if (r_type == R_FRV_GPRELHI) + r = elf32_frv_relocate_gprelhi (info, input_bfd, input_section, rel, contents, relocation); + + else + r = frv_final_link_relocate (howto, input_bfd, input_section, contents, rel, relocation); + + if (r != bfd_reloc_ok) + { + const char * msg = (const char *) NULL; + + switch (r) + { + case bfd_reloc_overflow: + r = info->callbacks->reloc_overflow + (info, name, howto->name, (bfd_vma) 0, + input_bfd, input_section, rel->r_offset); + break; + + case bfd_reloc_undefined: + r = info->callbacks->undefined_symbol + (info, name, input_bfd, input_section, rel->r_offset, true); + break; + + case bfd_reloc_outofrange: + msg = _("internal error: out of range error"); + break; + + case bfd_reloc_notsupported: + msg = _("internal error: unsupported relocation error"); + break; + + case bfd_reloc_dangerous: + msg = _("internal error: dangerous relocation"); + break; + + default: + msg = _("internal error: unknown error"); + break; + } + + if (msg) + r = info->callbacks->warning + (info, msg, name, input_bfd, input_section, rel->r_offset); + + if (! r) + return false; + } + } + + return true; +} + +/* Return the section that should be marked against GC for a given + relocation. */ + +static asection * +elf32_frv_gc_mark_hook (abfd, info, rel, h, sym) + bfd * abfd; + struct bfd_link_info * info ATTRIBUTE_UNUSED; + Elf_Internal_Rela * rel; + struct elf_link_hash_entry * h; + Elf_Internal_Sym * sym; +{ + if (h != NULL) + { + switch (ELF32_R_TYPE (rel->r_info)) + { + case R_FRV_GNU_VTINHERIT: + case R_FRV_GNU_VTENTRY: + break; + + default: + switch (h->root.type) + { + default: + break; + + case bfd_link_hash_defined: + case bfd_link_hash_defweak: + return h->root.u.def.section; + + case bfd_link_hash_common: + return h->root.u.c.p->section; + } + } + } + else + { + if (!(elf_bad_symtab (abfd) + && ELF_ST_BIND (sym->st_info) != STB_LOCAL) + && ! ((sym->st_shndx <= 0 || sym->st_shndx >= SHN_LORESERVE) + && sym->st_shndx != SHN_COMMON)) + return bfd_section_from_elf_index (abfd, sym->st_shndx); + } + + return NULL; +} + +/* Update the got entry reference counts for the section being removed. */ + +static boolean +elf32_frv_gc_sweep_hook (abfd, info, sec, relocs) + bfd * abfd ATTRIBUTE_UNUSED; + struct bfd_link_info * info ATTRIBUTE_UNUSED; + asection * sec ATTRIBUTE_UNUSED; + const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED; +{ + return true; +} + + +/* Hook called by the linker routine which adds symbols from an object + file. We use it to put .comm items in .scomm, and not .comm. */ + +static boolean +elf32_frv_add_symbol_hook (abfd, info, sym, namep, flagsp, secp, valp) + bfd *abfd; + struct bfd_link_info *info; + const Elf_Internal_Sym *sym; + const char **namep ATTRIBUTE_UNUSED; + flagword *flagsp ATTRIBUTE_UNUSED; + asection **secp; + bfd_vma *valp; +{ + if (sym->st_shndx == SHN_COMMON + && !info->relocateable + && (int)sym->st_size <= (int)bfd_get_gp_size (abfd)) + { + /* Common symbols less than or equal to -G nn bytes are + automatically put into .sbss. */ + + asection *scomm = bfd_get_section_by_name (abfd, ".scommon"); + + if (scomm == NULL) + { + scomm = bfd_make_section (abfd, ".scommon"); + if (scomm == NULL + || !bfd_set_section_flags (abfd, scomm, (SEC_ALLOC + | SEC_IS_COMMON + | SEC_LINKER_CREATED))) + return false; + } + + *secp = scomm; + *valp = sym->st_size; + } + + return true; +} +/* Look through the relocs for a section during the first phase. + Since we don't do .gots or .plts, we just need to consider the + virtual table relocs for gc. */ + +static boolean +elf32_frv_check_relocs (abfd, info, sec, relocs) + bfd *abfd; + struct bfd_link_info *info; + asection *sec; + const Elf_Internal_Rela *relocs; +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; + const Elf_Internal_Rela *rel; + const Elf_Internal_Rela *rel_end; + + if (info->relocateable) + return true; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + sym_hashes_end = sym_hashes + symtab_hdr->sh_size/sizeof(Elf32_External_Sym); + if (!elf_bad_symtab (abfd)) + sym_hashes_end -= symtab_hdr->sh_info; + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + struct elf_link_hash_entry *h; + unsigned long r_symndx; + + r_symndx = ELF32_R_SYM (rel->r_info); + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + + switch (ELF32_R_TYPE (rel->r_info)) + { + /* This relocation describes the C++ object vtable hierarchy. + Reconstruct it for later use during GC. */ + case R_FRV_GNU_VTINHERIT: + if (!_bfd_elf32_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) + return false; + break; + + /* This relocation describes which C++ vtable entries are actually + used. Record for later use during GC. */ + case R_FRV_GNU_VTENTRY: + if (!_bfd_elf32_gc_record_vtentry (abfd, sec, h, rel->r_addend)) + return false; + break; + } + } + + return true; +} + + +/* Return the machine subcode from the ELF e_flags header. */ + +static int +elf32_frv_machine (abfd) + bfd *abfd; +{ + switch (elf_elfheader (abfd)->e_flags & EF_FRV_CPU_MASK) + { + default: break; + case EF_FRV_CPU_FR500: return bfd_mach_fr500; + case EF_FRV_CPU_FR400: return bfd_mach_fr400; + case EF_FRV_CPU_FR300: return bfd_mach_fr300; + case EF_FRV_CPU_SIMPLE: return bfd_mach_frvsimple; + case EF_FRV_CPU_TOMCAT: return bfd_mach_frvtomcat; + } + + return bfd_mach_frv; +} + +/* Set the right machine number for a FRV ELF file. */ + +static boolean +elf32_frv_object_p (abfd) + bfd *abfd; +{ + bfd_default_set_arch_mach (abfd, bfd_arch_frv, elf32_frv_machine (abfd)); + return true; +} + +/* Function to set the ELF flag bits. */ + +static boolean +frv_elf_set_private_flags (abfd, flags) + bfd *abfd; + flagword flags; +{ + elf_elfheader (abfd)->e_flags = flags; + elf_flags_init (abfd) = true; + return true; +} + +/* Copy backend specific data from one object module to another. */ + +static boolean +frv_elf_copy_private_bfd_data (ibfd, obfd) + bfd *ibfd; + bfd *obfd; +{ + if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour + || bfd_get_flavour (obfd) != bfd_target_elf_flavour) + return true; + + BFD_ASSERT (!elf_flags_init (obfd) + || elf_elfheader (obfd)->e_flags == elf_elfheader (ibfd)->e_flags); + + elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags; + elf_flags_init (obfd) = true; + return true; +} + +/* Merge backend specific data from an object file to the output + object file when linking. */ + +static boolean +frv_elf_merge_private_bfd_data (ibfd, obfd) + bfd *ibfd; + bfd *obfd; +{ + flagword old_flags, old_partial; + flagword new_flags, new_partial; + boolean error = false; + char new_opt[80]; + char old_opt[80]; + + new_opt[0] = old_opt[0] = '\0'; + new_flags = elf_elfheader (ibfd)->e_flags; + old_flags = elf_elfheader (obfd)->e_flags; + +#ifdef DEBUG + (*_bfd_error_handler) ("old_flags = 0x%.8lx, new_flags = 0x%.8lx, init = %s, filename = %s", + old_flags, new_flags, elf_flags_init (obfd) ? "yes" : "no", + bfd_get_filename (ibfd)); +#endif + + if (!elf_flags_init (obfd)) /* First call, no flags set. */ + { + elf_flags_init (obfd) = true; + old_flags = new_flags; + } + + else if (new_flags == old_flags) /* Compatible flags are ok. */ + ; + + else /* Possibly incompatible flags. */ + { + /* Warn if different # of gprs are used. Note, 0 means nothing is + said about the size of gprs. */ + new_partial = (new_flags & EF_FRV_GPR_MASK); + old_partial = (old_flags & EF_FRV_GPR_MASK); + if (new_partial == old_partial) + ; + + else if (new_partial == 0) + ; + + else if (old_partial == 0) + old_flags |= new_partial; + + else + { + switch (new_partial) + { + default: strcat (new_opt, " -mgpr-??"); break; + case EF_FRV_GPR_32: strcat (new_opt, " -mgpr-32"); break; + case EF_FRV_GPR_64: strcat (new_opt, " -mgpr-64"); break; + } + + switch (old_partial) + { + default: strcat (old_opt, " -mgpr-??"); break; + case EF_FRV_GPR_32: strcat (old_opt, " -mgpr-32"); break; + case EF_FRV_GPR_64: strcat (old_opt, " -mgpr-64"); break; + } + } + + /* Warn if different # of fprs are used. Note, 0 means nothing is + said about the size of fprs. */ + new_partial = (new_flags & EF_FRV_FPR_MASK); + old_partial = (old_flags & EF_FRV_FPR_MASK); + if (new_partial == old_partial) + ; + + else if (new_partial == 0) + ; + + else if (old_partial == 0) + old_flags |= new_partial; + + else + { + switch (new_partial) + { + default: strcat (new_opt, " -mfpr-?"); break; + case EF_FRV_FPR_32: strcat (new_opt, " -mfpr-32"); break; + case EF_FRV_FPR_64: strcat (new_opt, " -mfpr-64"); break; + case EF_FRV_FPR_NONE: strcat (new_opt, " -msoft-float"); break; + } + + switch (old_partial) + { + default: strcat (old_opt, " -mfpr-?"); break; + case EF_FRV_FPR_32: strcat (old_opt, " -mfpr-32"); break; + case EF_FRV_FPR_64: strcat (old_opt, " -mfpr-64"); break; + case EF_FRV_FPR_NONE: strcat (old_opt, " -msoft-float"); break; + } + } + + /* Warn if different dword support was used. Note, 0 means nothing is + said about the dword support. */ + new_partial = (new_flags & EF_FRV_DWORD_MASK); + old_partial = (old_flags & EF_FRV_DWORD_MASK); + if (new_partial == old_partial) + ; + + else if (new_partial == 0) + ; + + else if (old_partial == 0) + old_flags |= new_partial; + + else + { + switch (new_partial) + { + default: strcat (new_opt, " -mdword-?"); break; + case EF_FRV_DWORD_YES: strcat (new_opt, " -mdword"); break; + case EF_FRV_DWORD_NO: strcat (new_opt, " -mno-dword"); break; + } + + switch (old_partial) + { + default: strcat (old_opt, " -mdword-?"); break; + case EF_FRV_DWORD_YES: strcat (old_opt, " -mdword"); break; + case EF_FRV_DWORD_NO: strcat (old_opt, " -mno-dword"); break; + } + } + + /* Or in flags that accumulate (ie, if one module uses it, mark that the + feature is used. */ + old_flags |= new_flags & (EF_FRV_DOUBLE + | EF_FRV_MEDIA + | EF_FRV_MULADD + | EF_FRV_NON_PIC_RELOCS); + + /* If any module was compiled without -G0, clear the G0 bit. */ + old_flags = ((old_flags & ~ EF_FRV_G0) + | (old_flags & new_flags & EF_FRV_G0)); + + /* If any module was compiled without -mnopack, clear the mnopack bit. */ + old_flags = ((old_flags & ~ EF_FRV_NOPACK) + | (old_flags & new_flags & EF_FRV_NOPACK)); + + /* We don't have to do anything if the pic flags are the same, or the new + module(s) were compiled with -mlibrary-pic. */ + new_partial = (new_flags & EF_FRV_PIC_FLAGS); + old_partial = (old_flags & EF_FRV_PIC_FLAGS); + if ((new_partial == old_partial) || ((new_partial & EF_FRV_LIBPIC) != 0)) + ; + + /* If the old module(s) were compiled with -mlibrary-pic, copy in the pic + flags if any from the new module. */ + else if ((old_partial & EF_FRV_LIBPIC) != 0) + old_flags = (old_flags & ~ EF_FRV_PIC_FLAGS) | new_partial; + + /* If we have mixtures of -fpic and -fPIC, or in both bits. */ + else if (new_partial != 0 && old_partial != 0) + old_flags |= new_partial; + + /* One module was compiled for pic and the other was not, see if we have + had any relocations that are not pic-safe. */ + else + { + if ((old_flags & EF_FRV_NON_PIC_RELOCS) == 0) + old_flags |= new_partial; + else + { + old_flags &= ~ EF_FRV_PIC_FLAGS; +#ifndef FRV_NO_PIC_ERROR + error = true; + (*_bfd_error_handler) + (_("%s: compiled with %s and linked with modules that use non-pic relocations"), + bfd_get_filename (ibfd), + (new_flags & EF_FRV_BIGPIC) ? "-fPIC" : "-fpic"); +#endif + } + } + + /* Warn if different cpu is used (allow a specific cpu to override + the generic cpu). */ + new_partial = (new_flags & EF_FRV_CPU_MASK); + old_partial = (old_flags & EF_FRV_CPU_MASK); + if (new_partial == old_partial) + ; + + else if (new_partial == EF_FRV_CPU_GENERIC) + ; + + else if (old_partial == EF_FRV_CPU_GENERIC) + old_flags = (old_flags & ~EF_FRV_CPU_MASK) | new_partial; + + else + { + switch (new_partial) + { + default: strcat (new_opt, " -mcpu=?"); break; + case EF_FRV_CPU_GENERIC: strcat (new_opt, " -mcpu=frv"); break; + case EF_FRV_CPU_SIMPLE: strcat (new_opt, " -mcpu=simple"); break; + case EF_FRV_CPU_FR500: strcat (new_opt, " -mcpu=fr500"); break; + case EF_FRV_CPU_FR400: strcat (new_opt, " -mcpu=fr400"); break; + case EF_FRV_CPU_FR300: strcat (new_opt, " -mcpu=fr300"); break; + case EF_FRV_CPU_TOMCAT: strcat (new_opt, " -mcpu=tomcat"); break; + } + + switch (old_partial) + { + default: strcat (old_opt, " -mcpu=?"); break; + case EF_FRV_CPU_GENERIC: strcat (old_opt, " -mcpu=frv"); break; + case EF_FRV_CPU_SIMPLE: strcat (old_opt, " -mcpu=simple"); break; + case EF_FRV_CPU_FR500: strcat (old_opt, " -mcpu=fr500"); break; + case EF_FRV_CPU_FR400: strcat (old_opt, " -mcpu=fr400"); break; + case EF_FRV_CPU_FR300: strcat (old_opt, " -mcpu=fr300"); break; + case EF_FRV_CPU_TOMCAT: strcat (old_opt, " -mcpu=tomcat"); break; + } + } + + /* Print out any mismatches from above. */ + if (new_opt[0]) + { + error = true; + (*_bfd_error_handler) + (_("%s: compiled with %s and linked with modules compiled with %s"), + bfd_get_filename (ibfd), new_opt, old_opt); + } + + /* Warn about any other mismatches */ + new_partial = (new_flags & ~ EF_FRV_ALL_FLAGS); + old_partial = (old_flags & ~ EF_FRV_ALL_FLAGS); + if (new_partial != old_partial) + { + old_flags |= new_partial; + error = true; + (*_bfd_error_handler) + (_("%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)"), + bfd_get_filename (ibfd), (long)new_partial, (long)old_partial); + } + } + + /* If the cpu is -mcpu=simple, then set the -mnopack bit. */ + if ((old_flags & EF_FRV_CPU_MASK) == EF_FRV_CPU_SIMPLE) + old_flags |= EF_FRV_NOPACK; + + /* Update the old flags now with changes made above. */ + old_partial = elf_elfheader (obfd)->e_flags & EF_FRV_CPU_MASK; + elf_elfheader (obfd)->e_flags = old_flags; + if (old_partial != (old_flags & EF_FRV_CPU_MASK)) + bfd_default_set_arch_mach (obfd, bfd_arch_frv, elf32_frv_machine (obfd)); + + if (error) + bfd_set_error (bfd_error_bad_value); + + return !error; +} + + +boolean +frv_elf_print_private_bfd_data (abfd, ptr) + bfd *abfd; + PTR ptr; +{ + FILE *file = (FILE *) ptr; + flagword flags; + + BFD_ASSERT (abfd != NULL && ptr != NULL); + + /* Print normal ELF private data. */ + _bfd_elf_print_private_bfd_data (abfd, ptr); + + flags = elf_elfheader (abfd)->e_flags; + fprintf (file, _("private flags = 0x%lx:"), (long)flags); + + switch (flags & EF_FRV_CPU_MASK) + { + default: break; + case EF_FRV_CPU_SIMPLE: fprintf (file, " -mcpu=simple"); break; + case EF_FRV_CPU_FR500: fprintf (file, " -mcpu=fr500"); break; + case EF_FRV_CPU_FR400: fprintf (file, " -mcpu=fr400"); break; + case EF_FRV_CPU_FR300: fprintf (file, " -mcpu=fr300"); break; + case EF_FRV_CPU_TOMCAT: fprintf (file, " -mcpu=tomcat"); break; + } + + switch (flags & EF_FRV_GPR_MASK) + { + default: break; + case EF_FRV_GPR_32: fprintf (file, " -mgpr-32"); break; + case EF_FRV_GPR_64: fprintf (file, " -mgpr-64"); break; + } + + switch (flags & EF_FRV_FPR_MASK) + { + default: break; + case EF_FRV_FPR_32: fprintf (file, " -mfpr-32"); break; + case EF_FRV_FPR_64: fprintf (file, " -mfpr-64"); break; + case EF_FRV_FPR_NONE: fprintf (file, " -msoft-float"); break; + } + + switch (flags & EF_FRV_DWORD_MASK) + { + default: break; + case EF_FRV_DWORD_YES: fprintf (file, " -mdword"); break; + case EF_FRV_DWORD_NO: fprintf (file, " -mno-dword"); break; + } + + if (flags & EF_FRV_DOUBLE) + fprintf (file, " -mdouble"); + + if (flags & EF_FRV_MEDIA) + fprintf (file, " -mmedia"); + + if (flags & EF_FRV_MULADD) + fprintf (file, " -mmuladd"); + + if (flags & EF_FRV_PIC) + fprintf (file, " -fpic"); + + if (flags & EF_FRV_BIGPIC) + fprintf (file, " -fPIC"); + + if (flags & EF_FRV_NON_PIC_RELOCS) + fprintf (file, " non-pic relocations"); + + if (flags & EF_FRV_G0) + fprintf (file, " -G0"); + + fputc ('\n', file); + return true; +} + + +#define ELF_ARCH bfd_arch_frv +#define ELF_MACHINE_CODE EM_CYGNUS_FRV +#define ELF_MAXPAGESIZE 0x1000 + +#define TARGET_BIG_SYM bfd_elf32_frv_vec +#define TARGET_BIG_NAME "elf32-frv" + +#define elf_info_to_howto_rel NULL +#define elf_info_to_howto frv_info_to_howto_rela +#define elf_backend_relocate_section elf32_frv_relocate_section +#define elf_backend_gc_mark_hook elf32_frv_gc_mark_hook +#define elf_backend_gc_sweep_hook elf32_frv_gc_sweep_hook +#define elf_backend_check_relocs elf32_frv_check_relocs +#define elf_backend_object_p elf32_frv_object_p +#define elf_backend_add_symbol_hook elf32_frv_add_symbol_hook + +#define elf_backend_can_gc_sections 1 + +#define bfd_elf32_bfd_reloc_type_lookup frv_reloc_type_lookup +#define bfd_elf32_bfd_set_private_flags frv_elf_set_private_flags +#define bfd_elf32_bfd_copy_private_bfd_data frv_elf_copy_private_bfd_data +#define bfd_elf32_bfd_merge_private_bfd_data frv_elf_merge_private_bfd_data +#define bfd_elf32_bfd_print_private_bfd_data frv_elf_print_private_bfd_data + +#include "elf32-target.h" diff -uprN binutils-2.12.90.0.11/bfd/elf64-hppa.c binutils-2.12.90.0.12/bfd/elf64-hppa.c --- binutils-2.12.90.0.11/bfd/elf64-hppa.c Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/bfd/elf64-hppa.c Tue Jun 18 21:41:58 2002 @@ -1159,7 +1159,8 @@ allocate_global_data_opd (dyn_h, data) /* We never need an opd entry for a symbol which is not defined by this output file. */ - if (h && h->root.type == bfd_link_hash_undefined) + if (h && (h->root.type == bfd_link_hash_undefined + || h->root.u.def.section->output_section == NULL)) dyn_h->want_opd = 0; /* If we are creating a shared library, took the address of a local @@ -1168,9 +1169,8 @@ allocate_global_data_opd (dyn_h, data) else if (x->info->shared || h == NULL || h->dynindx == -1 - || ((h->root.type == bfd_link_hash_defined - || h->root.type == bfd_link_hash_defweak) - && h->root.u.def.section->output_section != NULL)) + || (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak)) { /* If we are creating a shared library, then we will have to create a runtime relocation for the symbol to properly @@ -1532,16 +1532,11 @@ allocate_dynrel_entries (dyn_h, data) for (rent = dyn_h->reloc_entries; rent; rent = rent->next) { - switch (rent->type) - { - case R_PARISC_FPTR64: - /* Allocate one iff we are not building a shared library and - !want_opd, which by this point will be true only if we're - actually allocating one statically in the main executable. */ - if (!x->info->shared && dyn_h->want_opd) - continue; - break; - } + /* Allocate one iff we are building a shared library, the relocation + isn't a R_PARISC_FPTR64, or we don't want an opd entry. */ + if (!shared && rent->type == R_PARISC_FPTR64 && dyn_h->want_opd) + continue; + hppa_info->other_rel_sec->_raw_size += sizeof (Elf64_External_Rela); /* Make sure this symbol gets into the dynamic symbol table if it is @@ -1723,10 +1718,9 @@ elf64_hppa_size_dynamic_sections (output if (strcmp (name, ".plt") == 0) { + /* Strip this section if we don't need it; see the comment below. */ if (s->_raw_size == 0) { - /* Strip this section if we don't need it; see the - comment below. */ strip = true; } else @@ -1737,24 +1731,29 @@ elf64_hppa_size_dynamic_sections (output } else if (strcmp (name, ".dlt") == 0) { + /* Strip this section if we don't need it; see the comment below. */ if (s->_raw_size == 0) { - /* Strip this section if we don't need it; see the - comment below. */ strip = true; } } else if (strcmp (name, ".opd") == 0) { + /* Strip this section if we don't need it; see the comment below. */ if (s->_raw_size == 0) { - /* Strip this section if we don't need it; see the - comment below. */ strip = true; } } - else if (strncmp (name, ".rela", 4) == 0) + else if (strncmp (name, ".rela", 5) == 0) { + /* If we don't need this section, strip it from the output file. + This is mostly to handle .rela.bss and .rela.plt. We must + create both sections in create_dynamic_sections, because they + must be created before the linker maps input sections to output + sections. The linker does that before adjust_dynamic_symbol + is called, and it is that function which decides whether + anything needs to go into these sections. */ if (s->_raw_size == 0) { /* If we don't need this section, strip it from the @@ -1952,9 +1951,6 @@ elf64_hppa_finish_dynamic_symbol (output spltrel = hppa_info->plt_rel_sec; sdltrel = hppa_info->dlt_rel_sec; - BFD_ASSERT (stub != NULL && splt != NULL - && sopd != NULL && sdlt != NULL) - /* Incredible. It is actually necessary to NOT use the symbol's real value when building the dynamic symbol table for a shared library. At least for symbols that refer to functions. @@ -1964,6 +1960,8 @@ elf64_hppa_finish_dynamic_symbol (output the original values (in elf64_hppa_link_output_symbol_hook). */ if (dyn_h && dyn_h->want_opd) { + BFD_ASSERT (sopd != NULL) + /* Save away the original value and section index so that we can restore them later. */ dyn_h->st_value = sym->st_value; @@ -1985,6 +1983,8 @@ elf64_hppa_finish_dynamic_symbol (output bfd_vma value; Elf_Internal_Rela rel; + BFD_ASSERT (splt != NULL && spltrel != NULL) + /* We do not actually care about the value in the PLT entry if we are creating a shared library and the symbol is still undefined, we create a dynamic relocation to fill @@ -2035,6 +2035,8 @@ elf64_hppa_finish_dynamic_symbol (output int insn; unsigned int max_offset; + BFD_ASSERT (stub != NULL) + /* Install the generic stub template. We are modifying the contents of the stub section, so we do not @@ -2115,7 +2117,7 @@ elf64_hppa_finalize_opd (dyn_h, data) { struct bfd_link_info *info = (struct bfd_link_info *)data; struct elf64_hppa_link_hash_table *hppa_info; - struct elf_link_hash_entry *h = dyn_h->h; + struct elf_link_hash_entry *h = dyn_h ? dyn_h->h : NULL; asection *sopd; asection *sopdrel; @@ -2123,7 +2125,7 @@ elf64_hppa_finalize_opd (dyn_h, data) sopd = hppa_info->opd_sec; sopdrel = hppa_info->opd_rel_sec; - if (h && dyn_h && dyn_h->want_opd) + if (h && dyn_h->want_opd) { bfd_vma value; @@ -2236,7 +2238,7 @@ elf64_hppa_finalize_dlt (dyn_h, data) struct bfd_link_info *info = (struct bfd_link_info *)data; struct elf64_hppa_link_hash_table *hppa_info; asection *sdlt, *sdltrel; - struct elf_link_hash_entry *h = dyn_h->h; + struct elf_link_hash_entry *h = dyn_h ? dyn_h->h : NULL; hppa_info = elf64_hppa_hash_table (info); @@ -2247,7 +2249,7 @@ elf64_hppa_finalize_dlt (dyn_h, data) address, so there is no need to create a relocation. Just install the proper value into the DLT, note this shortcut can not be skipped when building a shared library. */ - if (! info->shared && h && dyn_h && dyn_h->want_dlt) + if (! info->shared && h && dyn_h->want_dlt) { bfd_vma value; @@ -2263,16 +2265,17 @@ elf64_hppa_finalize_dlt (dyn_h, data) + hppa_info->opd_sec->output_offset + hppa_info->opd_sec->output_section->vma); } - else + else if (h->root.u.def.section) { - value = (h->root.u.def.value - + h->root.u.def.section->output_offset); - + value = h->root.u.def.value + h->root.u.def.section->output_offset; if (h->root.u.def.section->output_section) value += h->root.u.def.section->output_section->vma; else value += h->root.u.def.section->vma; } + else + /* We have an undefined function reference. */ + value = 0; /* We do not need to include the output offset of the DLT section here because we are modifying the in-memory contents. */ @@ -2357,16 +2360,10 @@ elf64_hppa_finalize_dynreloc (dyn_h, dat { Elf64_Internal_Rela rel; - switch (rent->type) - { - case R_PARISC_FPTR64: - /* Allocate one iff we are not building a shared library and - !want_opd, which by this point will be true only if we're - actually allocating one statically in the main executable. */ - if (!info->shared && dyn_h->want_opd) - continue; - break; - } + /* Allocate one iff we are building a shared library, the relocation + isn't a R_PARISC_FPTR64, or we don't want an opd entry. */ + if (!info->shared && rent->type == R_PARISC_FPTR64 && dyn_h->want_opd) + continue; /* Create a dynamic relocation for this entry. @@ -2395,7 +2392,7 @@ elf64_hppa_finalize_dynreloc (dyn_h, dat We use a section symbol recorded by check_relocs as the base symbol for the relocation. The addend is the difference between the section symbol and the address of the .opd entry. */ - if (info->shared && rent->type == R_PARISC_FPTR64) + if (info->shared && rent->type == R_PARISC_FPTR64 && dyn_h->want_opd) { bfd_vma value, value2; diff -uprN binutils-2.12.90.0.11/bfd/elf64-mmix.c binutils-2.12.90.0.12/bfd/elf64-mmix.c --- binutils-2.12.90.0.11/bfd/elf64-mmix.c Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/bfd/elf64-mmix.c Tue Jun 18 21:41:58 2002 @@ -2226,8 +2226,12 @@ bpo_reloc_request_sort_fn (p1, p2) if (r1->value != r2->value) return r1->value > r2->value ? 1 : -1; - /* As a last re-sort, use the address so we get a stable sort. */ - return r1 > r2 ? 1 : (r1 < r2 ? -1 : 0); + /* As a last re-sort, use the relocation number, so we get a stable + sort. The *addresses* aren't stable since items are swapped during + sorting. It depends on the qsort implementation if this actually + happens. */ + return r1->bpo_reloc_no > r2->bpo_reloc_no + ? 1 : (r1->bpo_reloc_no < r2->bpo_reloc_no ? -1 : 0); } /* For debug use only. Dumps the global register allocations resulting diff -uprN binutils-2.12.90.0.11/bfd/elfcode.h binutils-2.12.90.0.12/bfd/elfcode.h --- binutils-2.12.90.0.11/bfd/elfcode.h Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/bfd/elfcode.h Tue Jun 18 21:41:58 2002 @@ -624,6 +624,10 @@ elf_object_p (abfd) if (i_ehdrp->e_shentsize != sizeof (x_shdr) && i_ehdrp->e_shnum != 0) goto got_wrong_format_error; + /* Further sanity check. */ + if (i_ehdrp->e_shoff == 0 && i_ehdrp->e_shnum != 0) + goto got_wrong_format_error; + ebd = get_elf_backend_data (abfd); /* Check that the ELF e_machine field matches what this particular @@ -677,25 +681,28 @@ elf_object_p (abfd) /* Remember the entry point specified in the ELF file header. */ bfd_set_start_address (abfd, i_ehdrp->e_entry); - /* Seek to the section header table in the file. */ - if (bfd_seek (abfd, (file_ptr) i_ehdrp->e_shoff, SEEK_SET) != 0) - goto got_no_match; - - /* Read the first section header at index 0, and convert to internal - form. */ - if (bfd_bread ((PTR) & x_shdr, (bfd_size_type) sizeof x_shdr, abfd) - != sizeof (x_shdr)) - goto got_no_match; - elf_swap_shdr_in (abfd, &x_shdr, &i_shdr); - - /* If the section count is zero, the actual count is in the first - section header. */ - if (i_ehdrp->e_shnum == SHN_UNDEF) - i_ehdrp->e_shnum = i_shdr.sh_size; - - /* And similarly for the string table index. */ - if (i_ehdrp->e_shstrndx == SHN_XINDEX) - i_ehdrp->e_shstrndx = i_shdr.sh_link; + if (i_ehdrp->e_shoff != 0) + { + /* Seek to the section header table in the file. */ + if (bfd_seek (abfd, (file_ptr) i_ehdrp->e_shoff, SEEK_SET) != 0) + goto got_no_match; + + /* Read the first section header at index 0, and convert to internal + form. */ + if (bfd_bread ((PTR) & x_shdr, (bfd_size_type) sizeof x_shdr, abfd) + != sizeof (x_shdr)) + goto got_no_match; + elf_swap_shdr_in (abfd, &x_shdr, &i_shdr); + + /* If the section count is zero, the actual count is in the first + section header. */ + if (i_ehdrp->e_shnum == SHN_UNDEF) + i_ehdrp->e_shnum = i_shdr.sh_size; + + /* And similarly for the string table index. */ + if (i_ehdrp->e_shstrndx == SHN_XINDEX) + i_ehdrp->e_shstrndx = i_shdr.sh_link; + } /* Allocate space for a copy of the section header table in internal form. */ @@ -751,7 +758,7 @@ elf_object_p (abfd) } } - if (i_ehdrp->e_shstrndx) + if (i_ehdrp->e_shstrndx && i_ehdrp->e_shoff) { if (! bfd_section_from_shdr (abfd, i_ehdrp->e_shstrndx)) goto got_no_match; @@ -789,7 +796,7 @@ elf_object_p (abfd) bfd_section_from_shdr with it (since this particular strtab is used to find all of the ELF section names.) */ - if (i_ehdrp->e_shstrndx != 0) + if (i_ehdrp->e_shstrndx != 0 && i_ehdrp->e_shoff) { unsigned int num_sec; diff -uprN binutils-2.12.90.0.11/bfd/elflink.h binutils-2.12.90.0.12/bfd/elflink.h --- binutils-2.12.90.0.11/bfd/elflink.h Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/bfd/elflink.h Tue Jun 18 21:41:58 2002 @@ -5860,7 +5860,13 @@ elf_bfd_final_link (abfd, info) name = ".fini_array"; get_size: o = bfd_get_section_by_name (abfd, name); - BFD_ASSERT (o != NULL); + if (o == NULL) + { + (*_bfd_error_handler) + (_("%s: could not find output section %s"), + bfd_get_filename (abfd), name); + goto error_return; + } if (o->_raw_size == 0) (*_bfd_error_handler) (_("warning: %s section has zero size"), name); @@ -5897,7 +5903,13 @@ elf_bfd_final_link (abfd, info) name = ".gnu.version"; get_vma: o = bfd_get_section_by_name (abfd, name); - BFD_ASSERT (o != NULL); + if (o == NULL) + { + (*_bfd_error_handler) + (_("%s: could not find output section %s"), + bfd_get_filename (abfd), name); + goto error_return; + } dyn.d_un.d_ptr = o->vma; elf_swap_dyn_out (dynobj, &dyn, dyncon); break; diff -uprN binutils-2.12.90.0.11/bfd/merge.c binutils-2.12.90.0.12/bfd/merge.c --- binutils-2.12.90.0.11/bfd/merge.c Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/bfd/merge.c Tue Jun 18 21:41:58 2002 @@ -652,8 +652,10 @@ merge_strings (sinfo) qsort (array, (size_t) sinfo->htab->size, sizeof (struct sec_merge_hash_entry *), cmplengthentry); - last4tab = htab_create ((size_t) sinfo->htab->size * 4, NULL, last4_eq, NULL); - lasttab = htab_create ((size_t) sinfo->htab->size * 4, NULL, last_eq, NULL); + last4tab = htab_create_alloc ((size_t) sinfo->htab->size * 4, + NULL, last4_eq, NULL, calloc, free); + lasttab = htab_create_alloc ((size_t) sinfo->htab->size * 4, + NULL, last_eq, NULL, calloc, free); if (lasttab == NULL || last4tab == NULL) goto alloc_failure; diff -uprN binutils-2.12.90.0.11/bfd/opncls.c binutils-2.12.90.0.12/bfd/opncls.c --- binutils-2.12.90.0.11/bfd/opncls.c Thu May 23 15:10:10 2002 +++ binutils-2.12.90.0.12/bfd/opncls.c Tue Jun 18 21:41:58 2002 @@ -152,7 +152,6 @@ bfd_openr (filename, target) target_vec = bfd_find_target (target, nbfd); if (target_vec == NULL) { - bfd_set_error (bfd_error_invalid_target); _bfd_delete_bfd (nbfd); return NULL; } @@ -220,7 +219,8 @@ bfd_fdopenr (filename, target, fd) #else fdflags = fcntl (fd, F_GETFL, NULL); #endif - if (fdflags == -1) return NULL; + if (fdflags == -1) + return NULL; nbfd = _bfd_new_bfd (); if (nbfd == NULL) @@ -229,7 +229,6 @@ bfd_fdopenr (filename, target, fd) target_vec = bfd_find_target (target, nbfd); if (target_vec == NULL) { - bfd_set_error (bfd_error_invalid_target); _bfd_delete_bfd (nbfd); return NULL; } @@ -308,7 +307,6 @@ bfd_openstreamr (filename, target, strea target_vec = bfd_find_target (target, nbfd); if (target_vec == NULL) { - bfd_set_error (bfd_error_invalid_target); _bfd_delete_bfd (nbfd); return NULL; } @@ -354,8 +352,6 @@ bfd_openw (filename, target) bfd *nbfd; const bfd_target *target_vec; - bfd_set_error (bfd_error_system_call); - /* nbfd has to point to head of malloc'ed block so that bfd_close may reclaim it correctly. */ nbfd = _bfd_new_bfd (); diff -uprN binutils-2.12.90.0.11/bfd/pe-i386.c binutils-2.12.90.0.12/bfd/pe-i386.c --- binutils-2.12.90.0.11/bfd/pe-i386.c Fri Mar 9 11:38:00 2001 +++ binutils-2.12.90.0.12/bfd/pe-i386.c Tue Jun 18 21:41:58 2002 @@ -1,21 +1,21 @@ /* BFD back-end for Intel 386 PECOFF files. - Copyright 1995, 1996, 1999, 2001 Free Software Foundation, Inc. + Copyright 1995, 1996, 1999, 2001, 2002 Free Software Foundation, Inc. -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "bfd.h" #include "sysdep.h" @@ -29,6 +29,12 @@ Foundation, Inc., 59 Temple Place - Suit #define COFF_LONG_FILENAMES #define COFF_SECTION_ALIGNMENT_ENTRIES \ +{ COFF_SECTION_NAME_EXACT_MATCH (".bss"), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 4 }, \ +{ COFF_SECTION_NAME_EXACT_MATCH (".data"), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 4 }, \ +{ COFF_SECTION_NAME_EXACT_MATCH (".text"), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 4 }, \ { COFF_SECTION_NAME_PARTIAL_MATCH (".idata"), \ COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 2 }, \ { COFF_SECTION_NAME_EXACT_MATCH (".pdata"), \ diff -uprN binutils-2.12.90.0.11/bfd/pei-i386.c binutils-2.12.90.0.12/bfd/pei-i386.c --- binutils-2.12.90.0.11/bfd/pei-i386.c Mon Sep 13 09:36:54 1999 +++ binutils-2.12.90.0.12/bfd/pei-i386.c Tue Jun 18 21:41:58 2002 @@ -1,21 +1,21 @@ /* BFD back-end for Intel 386 PE IMAGE COFF files. - Copyright 1995, 1996, 1999 Free Software Foundation, Inc. + Copyright 1995, 1996, 1999, 2002 Free Software Foundation, Inc. -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "bfd.h" #include "sysdep.h" @@ -30,6 +30,12 @@ Foundation, Inc., 59 Temple Place - Suit #define COFF_LONG_FILENAMES #define COFF_SECTION_ALIGNMENT_ENTRIES \ +{ COFF_SECTION_NAME_EXACT_MATCH (".bss"), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 4 }, \ +{ COFF_SECTION_NAME_EXACT_MATCH (".data"), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 4 }, \ +{ COFF_SECTION_NAME_EXACT_MATCH (".text"), \ + COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 4 }, \ { COFF_SECTION_NAME_PARTIAL_MATCH (".idata"), \ COFF_ALIGNMENT_FIELD_EMPTY, COFF_ALIGNMENT_FIELD_EMPTY, 2 }, \ { COFF_SECTION_NAME_EXACT_MATCH (".pdata"), \ diff -uprN binutils-2.12.90.0.11/bfd/po/SRC-POTFILES.in binutils-2.12.90.0.12/bfd/po/SRC-POTFILES.in --- binutils-2.12.90.0.11/bfd/po/SRC-POTFILES.in Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/bfd/po/SRC-POTFILES.in Tue Jun 18 21:41:58 2002 @@ -67,6 +67,7 @@ cpu-d10v.c cpu-d30v.c cpu-dlx.c cpu-fr30.c +cpu-frv.c cpu-h8300.c cpu-h8500.c cpu-hppa.c @@ -127,6 +128,7 @@ elf32-d10v.c elf32-d30v.c elf32-dlx.c elf32-fr30.c +elf32-frv.c elf32-gen.c elf32-h8300.c elf32-hppa.c diff -uprN binutils-2.12.90.0.11/bfd/reloc.c binutils-2.12.90.0.12/bfd/reloc.c --- binutils-2.12.90.0.11/bfd/reloc.c Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/bfd/reloc.c Tue Jun 18 21:41:58 2002 @@ -2079,6 +2079,27 @@ ENUMX ENUMX BFD_RELOC_MIPS_JALR COMMENT +ENUM + BFD_RELOC_FRV_LABEL16 +ENUMX + BFD_RELOC_FRV_LABEL24 +ENUMX + BFD_RELOC_FRV_LO16 +ENUMX + BFD_RELOC_FRV_HI16 +ENUMX + BFD_RELOC_FRV_GPREL12 +ENUMX + BFD_RELOC_FRV_GPRELU12 +ENUMX + BFD_RELOC_FRV_GPREL32 +ENUMX + BFD_RELOC_FRV_GPRELHI +ENUMX + BFD_RELOC_FRV_GPRELLO +ENUMDOC + Fujitsu Frv Relocations. +COMMENT COMMENT ENUMDOC MIPS ELF relocations. diff -uprN binutils-2.12.90.0.11/bfd/section.c binutils-2.12.90.0.12/bfd/section.c --- binutils-2.12.90.0.11/bfd/section.c Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/bfd/section.c Tue Jun 18 21:41:58 2002 @@ -1368,6 +1368,7 @@ _bfd_strip_section_from_output (info, s) if (*spp == os) { bfd_section_list_remove (os->owner, spp); + os->flags |= SEC_EXCLUDE; os->owner->section_count--; break; } diff -uprN binutils-2.12.90.0.11/bfd/targets.c binutils-2.12.90.0.12/bfd/targets.c --- binutils-2.12.90.0.11/bfd/targets.c Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/bfd/targets.c Tue Jun 18 21:41:58 2002 @@ -481,6 +481,7 @@ to find an alternative output format tha we can't intermix extern's and initializers. */ extern const bfd_target a29kcoff_big_vec; extern const bfd_target a_out_adobe_vec; +extern const bfd_target aix5coff64_vec; extern const bfd_target aout0_big_vec; extern const bfd_target aout_arm_big_vec; extern const bfd_target aout_arm_little_vec; @@ -513,6 +514,7 @@ extern const bfd_target bfd_elf32_d10v_v extern const bfd_target bfd_elf32_d30v_vec; extern const bfd_target bfd_elf32_dlx_big_vec; extern const bfd_target bfd_elf32_fr30_vec; +extern const bfd_target bfd_elf32_frv_vec; extern const bfd_target bfd_elf32_h8300_vec; extern const bfd_target bfd_elf32_hppa_linux_vec; extern const bfd_target bfd_elf32_hppa_vec; @@ -545,6 +547,10 @@ extern const bfd_target bfd_elf32_pjl_ve extern const bfd_target bfd_elf32_powerpc_vec; extern const bfd_target bfd_elf32_powerpcle_vec; extern const bfd_target bfd_elf32_s390_vec; +extern const bfd_target bfd_elf32_sh64_vec; +extern const bfd_target bfd_elf32_sh64l_vec; +extern const bfd_target bfd_elf32_sh64lnbsd_vec; +extern const bfd_target bfd_elf32_sh64nbsd_vec; extern const bfd_target bfd_elf32_sh_vec; extern const bfd_target bfd_elf32_shblin_vec; extern const bfd_target bfd_elf32_shl_vec; @@ -574,6 +580,10 @@ extern const bfd_target bfd_elf64_mmix_v extern const bfd_target bfd_elf64_powerpc_vec; extern const bfd_target bfd_elf64_powerpcle_vec; extern const bfd_target bfd_elf64_s390_vec; +extern const bfd_target bfd_elf64_sh64_vec; +extern const bfd_target bfd_elf64_sh64l_vec; +extern const bfd_target bfd_elf64_sh64lnbsd_vec; +extern const bfd_target bfd_elf64_sh64nbsd_vec; extern const bfd_target bfd_elf64_sparc_vec; extern const bfd_target bfd_elf64_tradbigmips_vec; extern const bfd_target bfd_elf64_tradlittlemips_vec; @@ -646,7 +656,6 @@ extern const bfd_target ppcboot_vec; extern const bfd_target riscix_vec; extern const bfd_target rs6000coff64_vec; extern const bfd_target rs6000coff_vec; -extern const bfd_target aix5coff64_vec; extern const bfd_target shcoff_small_vec; extern const bfd_target shcoff_vec; extern const bfd_target shlcoff_small_vec; @@ -699,15 +708,6 @@ extern const bfd_target ptrace_core_vec; extern const bfd_target sco5_core_vec; extern const bfd_target trad_core_vec; -extern const bfd_target bfd_elf32_sh64_vec; -extern const bfd_target bfd_elf32_sh64l_vec; -extern const bfd_target bfd_elf64_sh64_vec; -extern const bfd_target bfd_elf64_sh64l_vec; - -extern const bfd_target bfd_elf32_sh64nbsd_vec; -extern const bfd_target bfd_elf32_sh64lnbsd_vec; -extern const bfd_target bfd_elf64_sh64nbsd_vec; -extern const bfd_target bfd_elf64_sh64lnbsd_vec; static const bfd_target * const _bfd_target_vector[] = { #ifdef SELECT_VECS @@ -727,6 +727,7 @@ static const bfd_target * const _bfd_tar it wasn't omitted by mistake. */ &a29kcoff_big_vec, &a_out_adobe_vec, + &aix5coff64_vec, &aout0_big_vec, #if 0 /* We have no way of distinguishing these from other a.out variants */ @@ -772,6 +773,7 @@ static const bfd_target * const _bfd_tar &bfd_elf32_d30v_vec, &bfd_elf32_dlx_big_vec, &bfd_elf32_fr30_vec, + &bfd_elf32_frv_vec, &bfd_elf32_h8300_vec, &bfd_elf32_hppa_linux_vec, &bfd_elf32_hppa_vec, @@ -812,6 +814,12 @@ static const bfd_target * const _bfd_tar &bfd_elf32_shlin_vec, &bfd_elf32_shlnbsd_vec, &bfd_elf32_shnbsd_vec, +#ifdef BFD64 + &bfd_elf32_sh64_vec, + &bfd_elf32_sh64l_vec, + &bfd_elf32_sh64lnbsd_vec, + &bfd_elf32_sh64nbsd_vec, +#endif &bfd_elf32_sparc_vec, &bfd_elf32_tradbigmips_vec, &bfd_elf32_tradlittlemips_vec, @@ -836,6 +844,10 @@ static const bfd_target * const _bfd_tar &bfd_elf64_powerpc_vec, &bfd_elf64_powerpcle_vec, &bfd_elf64_s390_vec, + &bfd_elf64_sh64_vec, + &bfd_elf64_sh64l_vec, + &bfd_elf64_sh64lnbsd_vec, + &bfd_elf64_sh64nbsd_vec, #if 0 &bfd_elf64_sparc_vec, #endif diff -uprN binutils-2.12.90.0.11/bfd/version.h binutils-2.12.90.0.12/bfd/version.h --- binutils-2.12.90.0.11/bfd/version.h Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/bfd/version.h Tue Jun 18 21:41:58 2002 @@ -1 +1 @@ -#define BFD_VERSION_DATE 20020609 +#define BFD_VERSION_DATE 20020619 diff -uprN binutils-2.12.90.0.11/binutils/ChangeLog binutils-2.12.90.0.12/binutils/ChangeLog --- binutils-2.12.90.0.11/binutils/ChangeLog Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/binutils/ChangeLog Tue Jun 18 21:41:58 2002 @@ -1,3 +1,65 @@ +2002-06-18 H.J. Lu (hjl@gnu.org) + + * nm.c: Include "elf/common.h". + (extended_symbol_info): Add elfinfo, a pointer to + elf_symbol_type. + (SYM_SIZE): Use elfinfo if it is not NULL. + (get_symbol_type): New function. + (display_archive): Set print_width for each archive member. + (display_file): Likewise. + (display_rel_file): Don't set print_width here. + (print_object_filename_sysv): Handle print_width. + (print_archive_member_sysv): Likewise. + (print_symbols): Pass (bfd_vma) 0 to print_symbol. + (print_symbol): Set the elfinfo field in extended_symbol_info + for ELF. + (print_object_filename_sysv): Fix the output format. + (print_symbol_info_sysv): Print type and section for ELF. + +2002-06-18 Elias Athanasopoulos + + * nm.c (print_size_symbols): Remove assignment, which makes + the symbol's size equal to its value when --size-sort is + used. + +2002-06-18 Dave Brolley + + From Catherine Moore: + * readelf.c (elf/frv.h): #include it. + (guess_is_rela): Support EM_CYGNUS_FRV. + (dump_relocations): Ditto. + (get_machine_name): Ditto. + * Makefile.am (readelf.o): add dependency on $(INCDIR)/elf/frv.h. + +2002-06-18 Jakub Jelinek + + * readelf.c (get_file_header): Only read the first section header if + e_shoff is non-zero. + +2002-06-15 H.J. Lu (hjl@gnu.org) + + * nm.c (print_size): New variable. Initialize to 0. + (long_options): Add 'S'/"print-size". + (main): Handle 'S'. + (print_symbol_info_bsd): Print size only if print_size is not + 0. + + * doc/binutils.texi: Document -S/--print-size. + +2002-6-13 Elias Athanasopoulos + + * nm.c (struct extended_symbol_info): New strcuture: Add the size + of the symbols to the information provided by the symbol_info + structure. + (print_symbols): Pass the symbol size to print_symbol. + (print_size_symbols): Pass the symbol size to print_symbol. + (print_symbol): Extra argument: The size of the symbol. Store + this in the extended_symbol_info structure. + (print_symbol_info): Change type of info parameter to + extended_symbol_info. Display the size, if known. + (print_symbol_info_posix): Likewise. + (print_symbol_info_sysv): Likewise. + 2002-06-08 Alan Modra * Makefile.am: Run "make dep-am". diff -uprN binutils-2.12.90.0.11/binutils/Makefile.am binutils-2.12.90.0.12/binutils/Makefile.am --- binutils-2.12.90.0.11/binutils/Makefile.am Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/binutils/Makefile.am Tue Jun 18 21:41:58 2002 @@ -501,6 +501,7 @@ readelf.o: readelf.c ../bfd/bfd.h $(INCD $(INCDIR)/elf/reloc-macros.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/arm.h \ $(INCDIR)/elf/avr.h $(INCDIR)/elf/cris.h $(INCDIR)/elf/d10v.h \ $(INCDIR)/elf/d30v.h $(INCDIR)/elf/dlx.h $(INCDIR)/elf/fr30.h \ + $(INCDIR)/elf/frv.h \ $(INCDIR)/elf/h8.h $(INCDIR)/elf/hppa.h $(INCDIR)/elf/i386.h \ $(INCDIR)/elf/i860.h $(INCDIR)/elf/i960.h $(INCDIR)/elf/ia64.h \ $(INCDIR)/elf/m32r.h $(INCDIR)/elf/m68k.h $(INCDIR)/elf/mcore.h \ diff -uprN binutils-2.12.90.0.11/binutils/Makefile.in binutils-2.12.90.0.12/binutils/Makefile.in --- binutils-2.12.90.0.11/binutils/Makefile.in Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/binutils/Makefile.in Tue Jun 18 21:41:58 2002 @@ -1229,6 +1229,7 @@ readelf.o: readelf.c ../bfd/bfd.h $(INCD $(INCDIR)/elf/reloc-macros.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/arm.h \ $(INCDIR)/elf/avr.h $(INCDIR)/elf/cris.h $(INCDIR)/elf/d10v.h \ $(INCDIR)/elf/d30v.h $(INCDIR)/elf/dlx.h $(INCDIR)/elf/fr30.h \ + $(INCDIR)/elf/frv.h \ $(INCDIR)/elf/h8.h $(INCDIR)/elf/hppa.h $(INCDIR)/elf/i386.h \ $(INCDIR)/elf/i860.h $(INCDIR)/elf/i960.h $(INCDIR)/elf/ia64.h \ $(INCDIR)/elf/m32r.h $(INCDIR)/elf/m68k.h $(INCDIR)/elf/mcore.h \ diff -uprN binutils-2.12.90.0.11/binutils/NEWS binutils-2.12.90.0.12/binutils/NEWS --- binutils-2.12.90.0.11/binutils/NEWS Thu Mar 7 11:52:37 2002 +++ binutils-2.12.90.0.12/binutils/NEWS Tue Jun 18 21:41:58 2002 @@ -1,4 +1,6 @@ -*- text -*- +Support for the Fujitsu FRV architecture added by Red Hat. Models for FR400 and +FR500 included. Changes in version 2.12: diff -uprN binutils-2.12.90.0.11/binutils/doc/binutils.texi binutils-2.12.90.0.12/binutils/doc/binutils.texi --- binutils-2.12.90.0.11/binutils/doc/binutils.texi Fri Mar 22 14:06:16 2002 +++ binutils-2.12.90.0.12/binutils/doc/binutils.texi Tue Jun 18 21:41:59 2002 @@ -659,7 +659,8 @@ The @sc{gnu} linker @command{ld} is now @c man begin SYNOPSIS nm nm [@option{-a}|@option{--debug-syms}] [@option{-g}|@option{--extern-only}] [@option{-B}] [@option{-C}|@option{--demangle}[=@var{style}]] [@option{-D}|@option{--dynamic}] - [@option{-s}|@option{--print-armap}] [@option{-A}|@option{-o}|@option{--print-file-name}] + [@option{-S}|@option{--print-size}] [@option{-s}|@option{--print-armap}] + [@option{-A}|@option{-o}|@option{--print-file-name}] [@option{-n}|@option{-v}|@option{--numeric-sort}] [@option{-p}|@option{--no-sort}] [@option{-r}|@option{--reverse-sort}] [@option{--size-sort}] [@option{-u}|@option{--undefined-only}] [@option{-t} @var{radix}|@option{--radix=}@var{radix}] [@option{-P}|@option{--portability}] @@ -851,6 +852,10 @@ encountered. Use the POSIX.2 standard output format instead of the default format. Equivalent to @samp{-f posix}. +@item -S +@itemx --print-size +Print size of defined symbols for the @code{bsd} output format. + @item -s @itemx --print-armap @cindex symbol index, listing diff -uprN binutils-2.12.90.0.11/binutils/nm.c binutils-2.12.90.0.12/binutils/nm.c --- binutils-2.12.90.0.11/binutils/nm.c Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/binutils/nm.c Tue Jun 18 21:41:58 2002 @@ -29,6 +29,7 @@ #include "demangle.h" #include "libiberty.h" #include "elf-bfd.h" +#include "elf/common.h" /* When sorting by size, we use this structure to hold the size and a pointer to the minisymbol. */ @@ -50,142 +51,84 @@ struct get_relocs_info asymbol **syms; }; -static void -usage PARAMS ((FILE *, int)); - -static void -set_print_radix PARAMS ((char *)); - -static void -set_output_format PARAMS ((char *)); - -static void -display_archive PARAMS ((bfd *)); - -static boolean -display_file PARAMS ((char *filename)); - -static void -display_rel_file PARAMS ((bfd * file, bfd * archive)); - -static long -filter_symbols PARAMS ((bfd *, boolean, PTR, long, unsigned int)); - -static long -sort_symbols_by_size PARAMS ((bfd *, boolean, PTR, long, unsigned int, - struct size_sym **)); - -static void -print_symbols PARAMS ((bfd *, boolean, PTR, long, unsigned int, bfd *)); - -static void -print_size_symbols PARAMS ((bfd *, boolean, struct size_sym *, long, bfd *)); - -static void -print_symname PARAMS ((const char *, const char *, bfd *)); - -static void -print_symbol PARAMS ((bfd *, asymbol *, bfd *)); - -static void -print_symdef_entry PARAMS ((bfd * abfd)); +struct extended_symbol_info +{ + symbol_info *sinfo; + bfd_vma ssize; + elf_symbol_type *elfinfo; + /* FIXME: We should add more fields for Type, Line, Section. */ +}; +#define SYM_NAME(sym) (sym->sinfo->name) +#define SYM_VALUE(sym) (sym->sinfo->value) +#define SYM_TYPE(sym) (sym->sinfo->type) +#define SYM_STAB_NAME(sym) (sym->sinfo->stab_name) +#define SYM_STAB_DESC(sym) (sym->sinfo->stab_desc) +#define SYM_STAB_OTHER(sym) (sym->sinfo->stab_other) +#define SYM_SIZE(sym) \ + (sym->elfinfo ? sym->elfinfo->internal_elf_sym.st_size: sym->ssize) + +static void usage PARAMS ((FILE *, int)); +static void set_print_radix PARAMS ((char *)); +static void set_output_format PARAMS ((char *)); +static void display_archive PARAMS ((bfd *)); +static boolean display_file PARAMS ((char *)); +static void display_rel_file PARAMS ((bfd *, bfd *)); +static long filter_symbols PARAMS ((bfd *, boolean, PTR, long, unsigned int)); +static long sort_symbols_by_size PARAMS ((bfd *, boolean, PTR, long, unsigned int, struct size_sym **)); +static void print_symbols PARAMS ((bfd *, boolean, PTR, long, unsigned int, bfd *)); +static void print_size_symbols PARAMS ((bfd *, boolean, struct size_sym *, long, bfd *)); +static void print_symname PARAMS ((const char *, const char *, bfd *)); +static void print_symbol PARAMS ((bfd *, asymbol *, bfd_vma ssize, bfd *)); +static void print_symdef_entry PARAMS ((bfd *)); /* The sorting functions. */ - -static int -numeric_forward PARAMS ((const PTR, const PTR)); - -static int -numeric_reverse PARAMS ((const PTR, const PTR)); - -static int -non_numeric_forward PARAMS ((const PTR, const PTR)); - -static int -non_numeric_reverse PARAMS ((const PTR, const PTR)); - -static int -size_forward1 PARAMS ((const PTR, const PTR)); - -static int -size_forward2 PARAMS ((const PTR, const PTR)); +static int numeric_forward PARAMS ((const PTR, const PTR)); +static int numeric_reverse PARAMS ((const PTR, const PTR)); +static int non_numeric_forward PARAMS ((const PTR, const PTR)); +static int non_numeric_reverse PARAMS ((const PTR, const PTR)); +static int size_forward1 PARAMS ((const PTR, const PTR)); +static int size_forward2 PARAMS ((const PTR, const PTR)); /* The output formatting functions. */ - -static void -print_object_filename_bsd PARAMS ((char *filename)); - -static void -print_object_filename_sysv PARAMS ((char *filename)); - -static void -print_object_filename_posix PARAMS ((char *filename)); - - -static void -print_archive_filename_bsd PARAMS ((char *filename)); - -static void -print_archive_filename_sysv PARAMS ((char *filename)); - -static void -print_archive_filename_posix PARAMS ((char *filename)); - - -static void -print_archive_member_bsd PARAMS ((char *archive, const char *filename)); - -static void -print_archive_member_sysv PARAMS ((char *archive, const char *filename)); - -static void -print_archive_member_posix PARAMS ((char *archive, const char *filename)); - - -static void -print_symbol_filename_bsd PARAMS ((bfd * archive_bfd, bfd * abfd)); - -static void -print_symbol_filename_sysv PARAMS ((bfd * archive_bfd, bfd * abfd)); - -static void -print_symbol_filename_posix PARAMS ((bfd * archive_bfd, bfd * abfd)); - - -static void -print_value PARAMS ((bfd *, bfd_vma)); - -static void -print_symbol_info_bsd PARAMS ((symbol_info * info, bfd * abfd)); - -static void -print_symbol_info_sysv PARAMS ((symbol_info * info, bfd * abfd)); - -static void -print_symbol_info_posix PARAMS ((symbol_info * info, bfd * abfd)); - -static void -get_relocs PARAMS ((bfd *, asection *, PTR)); +static void print_object_filename_bsd PARAMS ((char *)); +static void print_object_filename_sysv PARAMS ((char *)); +static void print_object_filename_posix PARAMS ((char *)); +static void print_archive_filename_bsd PARAMS ((char *)); +static void print_archive_filename_sysv PARAMS ((char *)); +static void print_archive_filename_posix PARAMS ((char *)); +static void print_archive_member_bsd PARAMS ((char *, const char *)); +static void print_archive_member_sysv PARAMS ((char *, const char *)); +static void print_archive_member_posix PARAMS ((char *, const char *)); +static void print_symbol_filename_bsd PARAMS ((bfd *, bfd *)); +static void print_symbol_filename_sysv PARAMS ((bfd *, bfd *)); +static void print_symbol_filename_posix PARAMS ((bfd *, bfd *)); +static void print_value PARAMS ((bfd *, bfd_vma)); +static void print_symbol_info_bsd PARAMS ((struct extended_symbol_info *, bfd *)); +static void print_symbol_info_sysv PARAMS ((struct extended_symbol_info *, bfd *)); +static void print_symbol_info_posix PARAMS ((struct extended_symbol_info *, bfd *)); +static void get_relocs PARAMS ((bfd *, asection *, PTR)); +static const char * get_symbol_type PARAMS ((unsigned int)); /* Support for different output formats. */ struct output_fns { /* Print the name of an object file given on the command line. */ - void (*print_object_filename) PARAMS ((char *filename)); + void (*print_object_filename) PARAMS ((char *)); /* Print the name of an archive file given on the command line. */ - void (*print_archive_filename) PARAMS ((char *filename)); + void (*print_archive_filename) PARAMS ((char *)); /* Print the name of an archive member file. */ - void (*print_archive_member) PARAMS ((char *archive, const char *filename)); + void (*print_archive_member) PARAMS ((char *, const char *)); /* Print the name of the file (and archive, if there is one) containing a symbol. */ - void (*print_symbol_filename) PARAMS ((bfd * archive_bfd, bfd * abfd)); + void (*print_symbol_filename) PARAMS ((bfd *, bfd *)); /* Print a line of information about a symbol. */ - void (*print_symbol_info) PARAMS ((symbol_info * info, bfd * abfd)); + void (*print_symbol_info) PARAMS ((struct extended_symbol_info *, bfd *)); }; + static struct output_fns formats[] = { {print_object_filename_bsd, @@ -214,23 +157,23 @@ static struct output_fns formats[] = /* The output format to use. */ static struct output_fns *format = &formats[FORMAT_DEFAULT]; - /* Command options. */ static int do_demangle = 0; /* Pretty print C++ symbol names. */ -static int external_only = 0; /* print external symbols only */ -static int defined_only = 0; /* Print defined symbols only */ -static int no_sort = 0; /* don't sort; print syms in order found */ -static int print_debug_syms = 0; /* print debugger-only symbols too */ -static int print_armap = 0; /* describe __.SYMDEF data in archive files. */ -static int reverse_sort = 0; /* sort in downward(alpha or numeric) order */ -static int sort_numerically = 0; /* sort in numeric rather than alpha order */ -static int sort_by_size = 0; /* sort by size of symbol */ -static int undefined_only = 0; /* print undefined symbols only */ -static int dynamic = 0; /* print dynamic symbols. */ -static int show_version = 0; /* show the version number */ -static int show_stats = 0; /* show statistics */ -static int line_numbers = 0; /* print line numbers for symbols */ +static int external_only = 0; /* Print external symbols only. */ +static int defined_only = 0; /* Print defined symbols only. */ +static int no_sort = 0; /* Don't sort; print syms in order found. */ +static int print_debug_syms = 0;/* Print debugger-only symbols too. */ +static int print_armap = 0; /* Describe __.SYMDEF data in archive files. */ +static int print_size = 0; /* Print size of defined symbols. */ +static int reverse_sort = 0; /* Sort in downward(alpha or numeric) order. */ +static int sort_numerically = 0;/* Sort in numeric rather than alpha order. */ +static int sort_by_size = 0; /* Sort by size of symbol. */ +static int undefined_only = 0; /* Print undefined symbols only. */ +static int dynamic = 0; /* Print dynamic symbols. */ +static int show_version = 0; /* Show the version number. */ +static int show_stats = 0; /* Show statistics. */ +static int line_numbers = 0; /* Print line numbers for symbols. */ /* When to print the names of files. Not mutually exclusive in SYSV format. */ static int filename_per_file = 0; /* Once per file, on its own line. */ @@ -282,6 +225,7 @@ static struct option long_options[] = {"portability", no_argument, 0, 'P'}, {"print-armap", no_argument, &print_armap, 1}, {"print-file-name", no_argument, 0, 'o'}, + {"print-size", no_argument, 0, 'S'}, {"radix", required_argument, 0, 't'}, {"reverse-sort", no_argument, &reverse_sort, 1}, {"size-sort", no_argument, &sort_by_size, 1}, @@ -293,7 +237,7 @@ static struct option long_options[] = {0, no_argument, 0, 0} }; -/* Some error-reporting functions */ +/* Some error-reporting functions. */ static void usage (stream, status) @@ -324,6 +268,7 @@ usage (stream, status) -p, --no-sort Do not sort the symbols\n\ -P, --portability Same as --format=posix\n\ -r, --reverse-sort Reverse the sense of the sort\n\ + -S, --print-size Print size of defined symbols\n\ -s, --print-armap Include index for symbols from archive members\n\ --size-sort Sort symbols by size\n\ -t, --radix=RADIX Use RADIX for printing symbol values\n\ @@ -426,7 +371,7 @@ main (argc, argv) bfd_init (); set_default_bfd_target (); - while ((c = getopt_long (argc, argv, "aABCDef:gHhlnopPrst:uvVvX:", + while ((c = getopt_long (argc, argv, "aABCDef:gHhlnopPrSst:uvVvX:", long_options, (int *) 0)) != EOF) { switch (c) @@ -480,6 +425,9 @@ main (argc, argv) case 's': print_armap = 1; break; + case 'S': + print_size = 1; + break; case 't': set_print_radix (optarg); break; @@ -554,6 +502,32 @@ main (argc, argv) return retval; } +static const char * +get_symbol_type (type) + unsigned int type; +{ + static char buff [32]; + + switch (type) + { + case STT_NOTYPE: return "NOTYPE"; + case STT_OBJECT: return "OBJECT"; + case STT_FUNC: return "FUNC"; + case STT_SECTION: return "SECTION"; + case STT_FILE: return "FILE"; + case STT_COMMON: return "COMMON"; + case STT_TLS: return "TLS"; + default: + if (type >= STT_LOPROC && type <= STT_HIPROC) + sprintf (buff, _(": %d"), type); + else if (type >= STT_LOOS && type <= STT_HIOS) + sprintf (buff, _(": %d"), type); + else + sprintf (buff, _(": %d"), type); + return buff; + } +} + static void display_archive (file) bfd *file; @@ -582,6 +556,10 @@ display_archive (file) if (bfd_check_format_matches (arfile, bfd_object, &matching)) { + char buf[30]; + + bfd_sprintf_vma (arfile, buf, (bfd_vma) -1); + print_width = strlen (buf); (*format->print_archive_member) (bfd_get_filename (file), bfd_get_filename (arfile)); display_rel_file (arfile, file); @@ -634,6 +612,10 @@ display_file (filename) } else if (bfd_check_format_matches (file, bfd_object, &matching)) { + char buf[30]; + + bfd_sprintf_vma (file, buf, (bfd_vma) -1); + print_width = strlen (buf); (*format->print_object_filename) (filename); display_rel_file (file, NULL); } @@ -870,7 +852,6 @@ sort_symbols_by_size (abfd, dynamic, min /* Note that filter_symbols has already removed all absolute and undefined symbols. Here we remove all symbols whose size winds up as zero. */ - from = (bfd_byte *) minisyms; fromend = from + symcount * size; @@ -954,7 +935,6 @@ display_rel_file (abfd, archive_bfd) PTR minisyms; unsigned int size; struct size_sym *symsizes; - char buf[30]; if (! dynamic) { @@ -975,9 +955,6 @@ display_rel_file (abfd, archive_bfd) return; } - bfd_sprintf_vma (abfd, buf, (bfd_vma) -1); - print_width = strlen (buf); - /* Discard the symbols we don't want to print. It's OK to do this in place; we'll free the storage anyway (after printing). */ @@ -1142,7 +1119,7 @@ print_symbols (abfd, dynamic, minisyms, if (sym == NULL) bfd_fatal (bfd_get_filename (abfd)); - print_symbol (abfd, sym, archive_bfd); + print_symbol (abfd, sym, (bfd_vma) 0, archive_bfd); } } @@ -1168,25 +1145,29 @@ print_size_symbols (abfd, dynamic, symsi for (; from < fromend; from++) { asymbol *sym; + bfd_vma ssize; sym = bfd_minisymbol_to_symbol (abfd, dynamic, from->minisym, store); if (sym == NULL) bfd_fatal (bfd_get_filename (abfd)); - /* Set the symbol value so that we actually display the symbol - size. */ - sym->value = from->size - bfd_section_vma (abfd, bfd_get_section (sym)); + /* For elf we have already computed the correct symbol size. */ + if (bfd_get_flavour (abfd) == bfd_target_elf_flavour) + ssize = from->size; + else + ssize = from->size - bfd_section_vma (abfd, bfd_get_section (sym)); - print_symbol (abfd, sym, archive_bfd); + print_symbol (abfd, sym, ssize, archive_bfd); } } /* Print a single symbol. */ static void -print_symbol (abfd, sym, archive_bfd) +print_symbol (abfd, sym, ssize, archive_bfd) bfd *abfd; asymbol *sym; + bfd_vma ssize; bfd *archive_bfd; { PROGRESS (1); @@ -1201,9 +1182,16 @@ print_symbol (abfd, sym, archive_bfd) else { symbol_info syminfo; + struct extended_symbol_info info; bfd_get_symbol_info (abfd, sym, &syminfo); - (*format->print_symbol_info) (&syminfo, abfd); + info.sinfo = &syminfo; + info.ssize = ssize; + if (bfd_get_flavour (abfd) == bfd_target_elf_flavour) + info.elfinfo = (elf_symbol_type *) sym; + else + info.elfinfo = NULL; + (*format->print_symbol_info) (&info, abfd); } if (line_numbers) @@ -1246,7 +1234,6 @@ print_symbol (abfd, sym, archive_bfd) /* For an undefined symbol, we try to find a reloc for the symbol, and print the line number of the reloc. */ - if (abfd != lineno_cache_rel_bfd && relocs != NULL) { for (i = 0; i < seccount; i++) @@ -1346,8 +1333,12 @@ print_object_filename_sysv (filename) printf (_("\n\nUndefined symbols from %s:\n\n"), filename); else printf (_("\n\nSymbols from %s:\n\n"), filename); - printf (_("\ -Name Value Class Type Size Line Section\n\n")); + if (print_width == 8) + printf (_("\ +Name Value Class Type Size Line Section\n\n")); + else + printf (_("\ +Name Value Class Type Size Line Section\n\n")); } static void @@ -1400,8 +1391,12 @@ print_archive_member_sysv (archive, file printf (_("\n\nUndefined symbols from %s[%s]:\n\n"), archive, filename); else printf (_("\n\nSymbols from %s[%s]:\n\n"), archive, filename); - printf (_("\ -Name Value Class Type Size Line Section\n\n")); + if (print_width == 8) + printf (_("\ +Name Value Class Type Size Line Section\n\n")); + else + printf (_("\ +Name Value Class Type Size Line Section\n\n")); } static void @@ -1490,66 +1485,109 @@ print_value (abfd, val) static void print_symbol_info_bsd (info, abfd) - symbol_info *info; + struct extended_symbol_info *info; bfd *abfd; { - if (bfd_is_undefined_symclass (info->type)) + if (bfd_is_undefined_symclass (SYM_TYPE (info))) { if (print_width == 16) printf (" "); printf (" "); } else - print_value (abfd, info->value); - printf (" %c", info->type); - if (info->type == '-') + { + print_value (abfd, SYM_VALUE (info)); + + if (print_size && SYM_SIZE (info)) + { + printf(" "); + print_value (abfd, SYM_SIZE (info)); + } + } + + printf (" %c", SYM_TYPE (info)); + + if (SYM_TYPE (info) == '-') { /* A stab. */ printf (" "); - printf (other_format, info->stab_other); + printf (other_format, SYM_STAB_OTHER (info)); printf (" "); - printf (desc_format, info->stab_desc); - printf (" %5s", info->stab_name); + printf (desc_format, SYM_STAB_DESC (info)); + printf (" %5s", SYM_STAB_NAME (info)); } - print_symname (" %s", info->name, abfd); + print_symname (" %s", SYM_NAME (info), abfd); } static void print_symbol_info_sysv (info, abfd) - symbol_info *info; + struct extended_symbol_info *info; bfd *abfd; { - print_symname ("%-20s|", info->name, abfd); /* Name */ - if (bfd_is_undefined_symclass (info->type)) - printf (" "); /* Value */ + print_symname ("%-20s|", SYM_NAME (info), abfd); + + if (bfd_is_undefined_symclass (SYM_TYPE (info))) + { + if (print_width == 8) + printf (" "); + else + printf (" "); + } else - print_value (abfd, info->value); - printf ("| %c |", info->type); /* Class */ - if (info->type == '-') + print_value (abfd, SYM_VALUE (info)); + + printf ("| %c |", SYM_TYPE (info)); + + if (SYM_TYPE (info) == '-') { /* A stab. */ - printf ("%18s| ", info->stab_name); /* (C) Type */ - printf (desc_format, info->stab_desc); /* Size */ - printf ("| |"); /* Line, Section */ + printf ("%18s| ", SYM_STAB_NAME (info)); /* (C) Type */ + printf (desc_format, SYM_STAB_DESC (info)); /* Size */ + printf ("| |"); /* Line, Section */ } else - printf (" | | |"); /* Type, Size, Line, Section */ + { + /* Type, Size, Line, Section */ + if (info->elfinfo) + printf ("%18s|", + get_symbol_type (ELF_ST_TYPE (info->elfinfo->internal_elf_sym.st_info))); + else + printf (" |"); + + if (SYM_SIZE (info)) + print_value (abfd, SYM_SIZE (info)); + else + { + if (print_width == 8) + printf (" "); + else + printf (" "); + } + + if (info->elfinfo) + printf("| |%s", info->elfinfo->symbol.section->name); + else + printf("| |"); + } } static void print_symbol_info_posix (info, abfd) - symbol_info *info; + struct extended_symbol_info *info; bfd *abfd; { - print_symname ("%s ", info->name, abfd); - printf ("%c ", info->type); - if (bfd_is_undefined_symclass (info->type)) + print_symname ("%s ", SYM_NAME (info), abfd); + printf ("%c ", SYM_TYPE (info)); + + if (bfd_is_undefined_symclass (SYM_TYPE (info))) printf (" "); else - print_value (abfd, info->value); - /* POSIX.2 wants the symbol size printed here, when applicable; - BFD currently doesn't provide it, so we take the easy way out by - considering it to never be applicable. */ + { + print_value (abfd, SYM_VALUE (info)); + printf (" "); + if (SYM_SIZE (info)) + print_value (abfd, SYM_SIZE (info)); + } } static void diff -uprN binutils-2.12.90.0.11/binutils/readelf.c binutils-2.12.90.0.12/binutils/readelf.c --- binutils-2.12.90.0.11/binutils/readelf.c Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/binutils/readelf.c Tue Jun 18 21:41:59 2002 @@ -58,6 +58,7 @@ #include "elf/d30v.h" #include "elf/dlx.h" #include "elf/fr30.h" +#include "elf/frv.h" #include "elf/h8.h" #include "elf/hppa.h" #include "elf/i386.h" @@ -633,6 +634,7 @@ guess_is_rela (e_machine) case EM_CYGNUS_MN10300: case EM_FR30: case EM_CYGNUS_FR30: + case EM_CYGNUS_FRV: case EM_SH: case EM_ALPHA: case EM_MCORE: @@ -1031,6 +1033,10 @@ dump_relocations (file, rel_offset, rel_ rtype = elf_fr30_reloc_type (type); break; + case EM_CYGNUS_FRV: + rtype = elf_frv_reloc_type (type); + break; + case EM_MCORE: rtype = elf_mcore_reloc_type (type); break; @@ -1508,6 +1514,7 @@ get_machine_name (e_machine) case EM_MN10200: return "mn10200"; case EM_CYGNUS_FR30: case EM_FR30: return "Fujitsu FR30"; + case EM_CYGNUS_FRV: return "Fujitsu FR-V"; case EM_PJ_OLD: case EM_PJ: return "picoJava"; case EM_MMA: return "Fujitsu Multimedia Accelerator"; @@ -9711,12 +9718,15 @@ get_file_header (file) elf_header.e_shstrndx = BYTE_GET (ehdr64.e_shstrndx); } - /* There may be some extensions in the first section header. Don't - bomb if we can't read it. */ - if (is_32bit_elf) - get_32bit_section_headers (file, 1); - else - get_64bit_section_headers (file, 1); + if (elf_header.e_shoff) + { + /* There may be some extensions in the first section header. Don't + bomb if we can't read it. */ + if (is_32bit_elf) + get_32bit_section_headers (file, 1); + else + get_64bit_section_headers (file, 1); + } return 1; } diff -uprN binutils-2.12.90.0.11/binutils.spec binutils-2.12.90.0.12/binutils.spec --- binutils-2.12.90.0.11/binutils.spec Sat Jun 8 20:39:08 2002 +++ binutils-2.12.90.0.12/binutils.spec Tue Jun 18 21:21:34 2002 @@ -9,7 +9,7 @@ Summary: A GNU collection of binary utilities. Name: binutils -Version: 2.12.90.0.11 +Version: 2.12.90.0.12 Release: 1 Copyright: GPL Group: Development/Tools diff -uprN binutils-2.12.90.0.11/config.sub binutils-2.12.90.0.12/config.sub --- binutils-2.12.90.0.11/config.sub Fri Jun 7 19:22:16 2002 +++ binutils-2.12.90.0.12/config.sub Tue Jun 18 21:41:58 2002 @@ -235,7 +235,7 @@ case $basic_machine in | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr \ | c4x | clipper \ | d10v | d30v | dlx | dsp16xx \ - | fr30 \ + | fr30 | frv \ | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ | i370 | i860 | i960 | ia64 \ | m32r | m68000 | m68k | m88k | mcore \ @@ -292,7 +292,7 @@ case $basic_machine in | clipper-* | cydra-* \ | d10v-* | d30v-* | dlx-* \ | elxsi-* \ - | f30[01]-* | f700-* | fr30-* | fx80-* \ + | f30[01]-* | f700-* | fr30-* | frv-* | fx80-* \ | h8300-* | h8500-* \ | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ | i*86-* | i860-* | i960-* | ia64-* \ diff -uprN binutils-2.12.90.0.11/configure.in binutils-2.12.90.0.12/configure.in --- binutils-2.12.90.0.11/configure.in Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/configure.in Tue Jun 18 21:41:58 2002 @@ -755,6 +755,12 @@ case "${target}" in target_configdirs="${target_configdirs} target-bsp target-libstub target-cygmon" fi ;; + frv-*-*) + noconfigdirs="$noconfigdirs ${libgcj}" + if test x${is_cross_compiler} != xno ; then + target_configdirs="${target_configdirs} target-bsp target-cygmon" + fi + ;; h8300*-*-*) noconfigdirs="$noconfigdirs target-libgloss" ;; diff -uprN binutils-2.12.90.0.11/etc/ChangeLog binutils-2.12.90.0.12/etc/ChangeLog --- binutils-2.12.90.0.11/etc/ChangeLog Thu Mar 7 11:52:37 2002 +++ binutils-2.12.90.0.12/etc/ChangeLog Tue Jun 18 21:41:59 2002 @@ -1,3 +1,31 @@ +2002-06-11 Nick Clifton + + Import the following patches from the FSF GCC sources: + 2002-03-25 Zack Weinberg + + * texi2pod.pl: Handle @end ftable and @end vtable. + + 2001-12-12 Matthias Klose + + * texi2pod.pl: Merge changes from binutils' texi2pod.pl. Allows + generation of more than one man page from one source. + Add '-' to set of valid chars for an identifier. + Let -D option accept flags of the form =. + Use \s+ for whitespace detection in '@c man' lines. + Handle @set and @clear independent of $output. + Substitute all @value{}'s in a line. + + 2001-11-14 Joseph S. Myers + + * texi2pod.pl: Handle @ifnottex, @iftex and @display. Handle @var + in verbatim blocks specially. Handle @unnumbered, @unnumberedsec + and @center. Allow [a-z] after @enumerate. Handle 0 and numbers + greater than 9 in enumerations. + + 2001-07-03 Joseph S. Myers + + * texi2pod.pl: Handle @r inside @item. + 2002-02-27 Andrew Cagney * fdl.texi: New file. @@ -19,7 +47,7 @@ * add-log.el, add-log.vi: New files. -Wed Jan 20 01:33:50 1999 Angela Marie Thomas (angela@cygnus.com) +1999-01-20 Angela Marie Thomas (angela@cygnus.com) * comp-tools-verify: Remove some checks that are no longer valid. @@ -27,16 +55,16 @@ Wed Jan 20 01:33:50 1999 Angela Marie T * targetdoc/fr30.texi: New document. -Thu Oct 1 21:15:59 1998 Angela Marie Thomas (angela@cygnus.com) +1998-10-01 Angela Marie Thomas (angela@cygnus.com) * comp-tools-fix, cross-tools-fix: Replace /usr/include with ${FIXINCDIR}. -Tue Aug 11 19:22:11 1998 Doug Evans +1998-08-11 Doug Evans * make-rel-sym-tree (version): Update calculation. -Fri Jun 12 21:34:01 1998 Ian Lance Taylor +1998-06-12 Ian Lance Taylor * configure.texi: Various additions. * Makefile.in (TEXI2HTML, DVIPS): New variables. @@ -51,7 +79,7 @@ Fri Jun 12 21:34:01 1998 Ian Lance Tayl * configbuild.ein: New file (EPS version of configbuild.fig). * configbuild.jin: New file (JPEG version of configbuild.fig). -Wed Jun 10 14:41:25 1998 Ian Lance Taylor +1998-06-10 Ian Lance Taylor * configure.texi: New file. * configdev.tin: New file. diff -uprN binutils-2.12.90.0.11/etc/texi2pod.pl binutils-2.12.90.0.12/etc/texi2pod.pl --- binutils-2.12.90.0.11/etc/texi2pod.pl Tue Mar 27 08:50:04 2001 +++ binutils-2.12.90.0.12/etc/texi2pod.pl Tue Jun 18 21:41:59 2002 @@ -1,6 +1,6 @@ #! /usr/bin/perl -w -# Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc. +# Copyright (C) 1999, 2000, 2001, 200 Free Software Foundation, Inc. # This file is part of GNU CC. @@ -30,9 +30,12 @@ $section = ""; @icstack = (); @endwstack = (); @skstack = (); +@instack = (); $shift = ""; %defs = (); $fnno = 1; +$inf = ""; +$ibase = ""; while ($_ = shift) { if (/^-D(.*)$/) { @@ -41,15 +44,13 @@ while ($_ = shift) { } else { $flag = shift; } - $value=$flag; - $value =~ s,^[a-zA-Z0-9_]+,,; - $value =~ s,.*=,,; - $flag =~ s,=.*$,,; + $value = ""; + ($flag, $value) = ($flag =~ /^([^=]+)(?:=(.+))?/); die "no flag specified for -D\n" unless $flag ne ""; - #print STDERR "FL = $flag, V = $value\n"; + die "flags may only contain letters, digits, hyphens, dashes and underscores\n" + unless $flag =~ /^[a-zA-Z0-9_-]+$/; $defs{$flag} = $value; - } elsif (/^-/) { usage(); } else { @@ -60,14 +61,19 @@ while ($_ = shift) { } if (defined $in) { - open(STDIN, $in) or die "opening \"$in\": $!\n"; + $inf = gensym(); + open($inf, "<$in") or die "opening \"$in\": $!\n"; + $ibase = $1 if $in =~ m|^(.+)/[^/]+$|; +} else { + $inf = \*STDIN; } + if (defined $out) { open(STDOUT, ">$out") or die "opening \"$out\": $!\n"; } -while() -{ +while(defined $inf) { +while(<$inf>) { # Certain commands are discarded without further processing. /^\@(?: [a-z]+index # @*index: useful only in complete manual @@ -75,8 +81,9 @@ while() |(?:end\s+)?group # @group .. @end group: ditto |page # @page: ditto |node # @node: useful only in .info file + |(?:end\s+)?ifnottex # @ifnottex .. @end ifnottex: use contents )\b/x and next; - + chomp; # Look for filename and title markers. @@ -84,7 +91,7 @@ while() /^\@settitle\s+([^.]+)/ and $tl = postprocess($1), next; # Identify a man title but keep only the one we are interested in. - /^\@c man title ([A-Za-z0-9]+) (.+)/ and do { + /^\@c\s+man\s+title\s+([A-Za-z0-9-]+)\s+(.+)/ and do { if (exists $defs{$1}) { $fn = $1; $tl = postprocess($2); @@ -95,19 +102,30 @@ while() # Look for blocks surrounded by @c man begin SECTION ... @c man end. # This really oughta be @ifman ... @end ifman and the like, but such # would require rev'ing all other Texinfo translators. - /^\@c man begin ([A-Z]+) ([A-Za-z0-9]+)/ and do { + /^\@c\s+man\s+begin\s+([A-Z]+)\s+([A-Za-z0-9-]+)/ and do { $output = 1 if exists $defs{$2}; $sect = $1; next; }; - /^\@c man begin ([A-Z]+)/ and $sect = $1, $output = 1, next; - /^\@c man end/ and do { + /^\@c\s+man\s+begin\s+([A-Z]+)/ and $sect = $1, $output = 1, next; + /^\@c\s+man\s+end/ and do { $sects{$sect} = "" unless exists $sects{$sect}; $sects{$sect} .= postprocess($section); $section = ""; $output = 0; next; }; + + # handle variables + /^\@set\s+([a-zA-Z0-9_-]+)\s*(.*)$/ and do { + $defs{$1} = $2; + next; + }; + /^\@clear\s+([a-zA-Z0-9_-]+)/ and do { + delete $defs{$1}; + next; + }; + next unless $output; # Discard comments. (Can't do it above, because then we'd never see @@ -120,20 +138,20 @@ while() # Ignore @end foo, where foo is not an operation which may # cause us to skip, if we are presently skipping. my $ended = $1; - next if $skipping && $ended !~ /^(?:ifset|ifclear|ignore|menu)$/; + next if $skipping && $ended !~ /^(?:ifset|ifclear|ignore|menu|iftex)$/; die "\@end $ended without \@$ended at line $.\n" unless defined $endw; die "\@$endw ended by \@end $ended at line $.\n" unless $ended eq $endw; $endw = pop @endwstack; - if ($ended =~ /^(?:ifset|ifclear|ignore|menu)$/) { + if ($ended =~ /^(?:ifset|ifclear|ignore|menu|iftex)$/) { $skipping = pop @skstack; next; - } elsif ($ended =~ /^(?:example|smallexample)$/) { + } elsif ($ended =~ /^(?:example|smallexample|display)$/) { $shift = ""; $_ = ""; # need a paragraph break - } elsif ($ended =~ /^(?:itemize|enumerate|table)$/) { + } elsif ($ended =~ /^(?:itemize|enumerate|[fv]?table)$/) { $_ = "\n=back\n"; $ic = pop @icstack; } else { @@ -160,7 +178,7 @@ while() next; }; - /^\@(ignore|menu)\b/ and do { + /^\@(ignore|menu|iftex)\b/ and do { push @endwstack, $endw; push @skstack, $skipping; $endw = $1; @@ -189,6 +207,12 @@ while() s/\@\{/{/g; s/\@\}/}/g; s/\@\@/&at;/g; + + # Inside a verbatim block, handle @var specially. + if ($shift ne "") { + s/\@var\{([^\}]*)\}/<$1>/g; + } + # POD doesn't interpret E<> inside a verbatim block. if ($shift eq "") { s/) } # Single line command handlers. - /^\@set\s+([a-zA-Z0-9_-]+)\s*(.*)$/ and $defs{$1} = $2, next; - /^\@clear\s+([a-zA-Z0-9_-]+)/ and delete $defs{$1}, next; - /^\@section\s+(.+)$/ and $_ = "\n=head2 $1\n"; - /^\@subsection\s+(.+)$/ and $_ = "\n=head3 $1\n"; + /^\@include\s+(.+)$/ and do { + push @instack, $inf; + $inf = gensym(); + + # Try cwd and $ibase. + open($inf, "<" . $1) + or open($inf, "<" . $ibase . "/" . $1) + or die "cannot open $1 or $ibase/$1: $!\n"; + next; + }; + + /^\@(?:section|unnumbered|unnumberedsec|center)\s+(.+)$/ + and $_ = "\n=head2 $1\n"; + /^\@subsection\s+(.+)$/ + and $_ = "\n=head3 $1\n"; # Block command handlers: /^\@itemize\s+(\@[a-z]+|\*|-)/ and do { @@ -214,7 +249,7 @@ while() $endw = "itemize"; }; - /^\@enumerate(?:\s+([A-Z0-9]+))?/ and do { + /^\@enumerate(?:\s+([a-zA-Z0-9]+))?/ and do { push @endwstack, $endw; push @icstack, $ic; if (defined $1) { @@ -226,19 +261,19 @@ while() $endw = "enumerate"; }; - /^\@table\s+(\@[a-z]+)/ and do { + /^\@([fv]?table)\s+(\@[a-z]+)/ and do { push @endwstack, $endw; push @icstack, $ic; - $ic = $1; + $endw = $1; + $ic = $2; $ic =~ s/\@(?:samp|strong|key|gcctabopt|env)/B/; $ic =~ s/\@(?:code|kbd)/C/; $ic =~ s/\@(?:dfn|var|emph|cite|i)/I/; $ic =~ s/\@(?:file)/F/; $_ = "\n=over 4\n"; - $endw = "table"; }; - /^\@((?:small)?example)/ and do { + /^\@((?:small)?example|display)/ and do { push @endwstack, $endw; $endw = $1; $shift = "\t"; @@ -251,12 +286,17 @@ while() $_ = "\n=item $ic\<$1\>\n"; } else { $_ = "\n=item $ic\n"; - $ic =~ y/A-Ya-y1-8/B-Zb-z2-9/; + $ic =~ y/A-Ya-y/B-Zb-z/; + $ic =~ s/(\d+)/$1 + 1/eg; } }; $section .= $shift.$_."\n"; } +# End of current file. +close($inf); +$inf = pop @instack; +} die "No filename or title\n" unless defined $fn && defined $tl; @@ -284,13 +324,15 @@ sub postprocess local $_ = $_[0]; # @value{foo} is replaced by whatever 'foo' is defined as. - if (/\@value\{([a-zA-Z0-9_-]+)\}/) { - if (! exists $defs{$1}) { - print STDERR "Option $1 not define\n"; + while (m/(\@value\{([a-zA-Z0-9_-]+)\})/g) { + if (! exists $defs{$2}) { + print STDERR "Option $2 not defined\n"; + s/\Q$1\E//; + } else { + $value = $defs{$2}; + s/\Q$1\E/$value/; } - } - s/\@value\{([a-zA-Z0-9_-]+)\}/$defs{$1}/g; # Formatting commands. # Temporary escape for @r. @@ -303,9 +345,6 @@ sub postprocess s/\@w\{([^\}]*)\}/S<$1>/g; s/\@(?:dmn|math)\{([^\}]*)\}/$1/g; - # Handle @r inside bold. - 1 while s/B<((?:[^<>]|I<[^<>]*>)*)R<([^>]*)>/B<$1>${2}B blah> into B I B to - # match Texinfo semantics of @emph inside @samp. + # match Texinfo semantics of @emph inside @samp. Also handle @r + # inside bold. s/<//g; + 1 while s/B<((?:[^<>]|I<[^<>]*>)*)R<([^>]*)>/B<$1>${2}B]*)I<([^>]+)>/B<$1>I<$2>B]*)B<([^>]+)>/I<$1>B<$2>I//g; @@ -372,4 +413,15 @@ sub add_footnote $sects{FOOTNOTES} .= $_[0]; $sects{FOOTNOTES} .= "\n\n"; } - + +# stolen from Symbol.pm +{ + my $genseq = 0; + sub gensym + { + my $name = "GEN" . $genseq++; + my $ref = \*{$name}; + delete $::{$name}; + return $ref; + } +} diff -uprN binutils-2.12.90.0.11/gas/ChangeLog binutils-2.12.90.0.12/gas/ChangeLog --- binutils-2.12.90.0.11/gas/ChangeLog Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/gas/ChangeLog Tue Jun 18 21:41:59 2002 @@ -1,3 +1,86 @@ +2002-06-18 Dave Brolley + + From Catherine Moore, Michael Meissner, Richard Sandiford, Dave Brolley: + * po/POTFILES.in: Add tc-frv.c, tc-frv.h. + * configure.in: Support frv-*-*. + * Makefile.am (CPU_TYPES): Add frv. + (TARGET_CPU_CFILES): Add tc-frv.c. + (TARGET_CPU_HFILES): Add tc-frv.h. + (DEPTC_frv_coff): New variable. + (DEPTC_frv_elf): New variable. + (DEPOBJ_frv_coff): New variable. + (DEPOBJ_frv_elf): New variable. + (DEP_frv_coff): New variable. + (DEP_frv_elf): New variable. + * tc-frv.c: New file. + * tc-frv.h: New file. + +2002-06-17 Catherine Moore + + * config/obj-elf.h (TARGET_SYMBOL_FIELDS): Conditionally define. + +Mon Jun 17 16:29:58 2002 J"orn Rennecke + + * config/tc-sh.c (assemble_ppi): Initialize reg_n. + +2002-06-17 Tom Rix + + * config/tc-i370.h (tc_comment_chars): Define for i370-elf. + +2002-06-14 H.J. Lu + Daniel Jacobowitz + + * dwarf2dbg.h (dwarf2_directive_file): Return char *. + * dwarf2dbg.c (dwarf2_directive_file): Return filename. + * config/tc-mips.c (s_mips_file): Call s_app_file_string + and new_logical_line for the first .file directive. + * read.c (s_app_file_string): New function. + (s_app_file): Call it. + * read.h (s_app_file_string): Add declaration. + +2002-06-14 Daniel Jacobowitz + + * configure.in: Remove MIPS_STABS_ELF. + * configure: Regenerated. + * config.in: Regenerated. + * config/obj-elf.h (ECOFF_DEBUGGING): Define to mips_flag_mdebug + for MIPS targets. + * config/tc-mips.c (mips_pseudo_table): Remove #ifdef around + ".extern". + (pdr_seg): Declare unconditionally. + (md_begin): Always generate .pdr unless ECOFF_DEBUGGING or not ELF. + (s_mips_end): Likewise. Generate stabs function markers. + (s_mips_ent): Generate stabs function markers. + (s_mips_frame): Always generate .pdr unless ECOFF_DEBUGGING or not + ELF. + (s_mips_mask): Likewise. + (mips_flag_mdebug): New. + (md_longopts): Add "mdebug" and "no-mdebug". + (md_parse_options): Add OPTION_MDEBUG and OPTION_NO_MDEBUG. + (mips_after_parse_args): Set mips_flag_mdebug. + * doc/as.texinfo: Add "-mdebug" and "-no-mdebug" for MIPS. + +2002-06-13 Maciej W. Rozycki + + * config/tc-mips.c (md_apply_fix3): Don't subtract the symbol's + value twice for RELA relocations. + +2002-06-12 Ben Elliston + + * symbols.c (resolve_symbol_value): Initialise final_val. + + * subsegs.c (subsegs_print_statistics): Cast frchp to void *. + +2002-06-11 Tom Rix + + * config/tc-ppc.c (ppc_subseg_align): Delete. + (ppc_change_csect): Default csect align is 2. + * config/tc-ppc.h (SUB_SEGMENT_ALIGN): Delete + +2002-06-09 Marek Michalkiewicz + + * config/tc-avr.c (mcu_types): Update. + 2002-06-08 Matt Thomas * configure.in (vax-*-netbsdelf*, vax-*-netbsdaout*) diff -uprN binutils-2.12.90.0.11/gas/ChangeLog.linux binutils-2.12.90.0.12/gas/ChangeLog.linux --- binutils-2.12.90.0.11/gas/ChangeLog.linux Fri Nov 16 14:05:52 2001 +++ binutils-2.12.90.0.12/gas/ChangeLog.linux Tue Jun 18 21:41:59 2002 @@ -1,3 +1,8 @@ +2002-06-18 H.J. Lu + + * dwarf2dbg.c (dwarf2_finish): Output dwarf debug info only + when needed. + 2001-10-21 H.J. Lu * configure: Rebuid for ../libtool.m4 change. diff -uprN binutils-2.12.90.0.11/gas/Makefile.am binutils-2.12.90.0.12/gas/Makefile.am --- binutils-2.12.90.0.11/gas/Makefile.am Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/gas/Makefile.am Tue Jun 18 21:41:59 2002 @@ -47,6 +47,7 @@ CPU_TYPES = \ d30v \ dlx \ fr30 \ + frv \ h8300 \ h8500 \ hppa \ @@ -236,6 +237,7 @@ TARGET_CPU_CFILES = \ config/tc-d30v.c \ config/tc-dlx.c \ config/tc-fr30.c \ + config/tc-frv.c \ config/tc-h8300.c \ config/tc-h8500.c \ config/tc-hppa.c \ @@ -284,6 +286,7 @@ TARGET_CPU_HFILES = \ config/tc-d30v.h \ config/tc-dlx.h \ config/tc-fr30.h \ + config/tc-frv.h \ config/tc-h8300.h \ config/tc-h8500.h \ config/tc-hppa.h \ @@ -1067,6 +1070,18 @@ DEPTC_fr30_elf = $(INCDIR)/symcat.h $(sr $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ $(srcdir)/../opcodes/fr30-desc.h $(INCDIR)/opcode/cgen.h \ $(srcdir)/../opcodes/fr30-opc.h cgen.h +DEPTC_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ + $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \ + $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \ + subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/frv-desc.h \ + $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/frv-opc.h \ + cgen.h +DEPTC_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \ + $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ + $(srcdir)/../opcodes/frv-desc.h $(INCDIR)/opcode/cgen.h \ + $(srcdir)/../opcodes/frv-opc.h cgen.h DEPTC_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \ $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \ @@ -1577,6 +1592,15 @@ DEPOBJ_fr30_elf = $(INCDIR)/symcat.h $(s $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \ $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ struc-symbol.h $(INCDIR)/aout/aout64.h +DEPOBJ_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ + $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \ + $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \ + subsegs.h +DEPOBJ_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \ + $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ + struc-symbol.h $(INCDIR)/aout/aout64.h DEPOBJ_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \ $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \ @@ -2015,6 +2039,12 @@ DEP_fr30_coff = $(srcdir)/config/obj-cof DEP_fr30_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \ $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h +DEP_frv_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-frv.h \ + $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \ + $(INCDIR)/bfdlink.h +DEP_frv_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h DEP_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \ $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h \ $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h diff -uprN binutils-2.12.90.0.11/gas/Makefile.in binutils-2.12.90.0.12/gas/Makefile.in --- binutils-2.12.90.0.11/gas/Makefile.in Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/gas/Makefile.in Tue Jun 18 21:41:59 2002 @@ -158,6 +158,7 @@ CPU_TYPES = \ d30v \ dlx \ fr30 \ + frv \ h8300 \ h8500 \ hppa \ @@ -353,6 +354,7 @@ TARGET_CPU_CFILES = \ config/tc-d30v.c \ config/tc-dlx.c \ config/tc-fr30.c \ + config/tc-frv.c \ config/tc-h8300.c \ config/tc-h8500.c \ config/tc-hppa.c \ @@ -402,6 +404,7 @@ TARGET_CPU_HFILES = \ config/tc-d30v.h \ config/tc-dlx.h \ config/tc-fr30.h \ + config/tc-frv.h \ config/tc-h8300.h \ config/tc-h8500.h \ config/tc-hppa.h \ @@ -795,6 +798,20 @@ DEPTC_fr30_elf = $(INCDIR)/symcat.h $(sr $(srcdir)/../opcodes/fr30-desc.h $(INCDIR)/opcode/cgen.h \ $(srcdir)/../opcodes/fr30-opc.h cgen.h +DEPTC_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ + $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \ + $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \ + subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/frv-desc.h \ + $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/frv-opc.h \ + cgen.h + +DEPTC_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \ + $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ + $(srcdir)/../opcodes/frv-desc.h $(INCDIR)/opcode/cgen.h \ + $(srcdir)/../opcodes/frv-opc.h cgen.h + DEPTC_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \ $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \ @@ -1414,6 +1431,17 @@ DEPOBJ_fr30_elf = $(INCDIR)/symcat.h $(s $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ struc-symbol.h $(INCDIR)/aout/aout64.h +DEPOBJ_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ + $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \ + $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \ + subsegs.h + +DEPOBJ_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \ + $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ + struc-symbol.h $(INCDIR)/aout/aout64.h + DEPOBJ_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \ $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \ @@ -1961,6 +1989,14 @@ DEP_fr30_elf = $(srcdir)/config/obj-elf. $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h +DEP_frv_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-frv.h \ + $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \ + $(INCDIR)/bfdlink.h + +DEP_frv_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h + DEP_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \ $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h \ $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h diff -uprN binutils-2.12.90.0.11/gas/NEWS binutils-2.12.90.0.12/gas/NEWS --- binutils-2.12.90.0.11/gas/NEWS Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/gas/NEWS Tue Jun 18 21:41:59 2002 @@ -1,4 +1,7 @@ -*- text -*- +Support for the Fujitsu FRV architecture added by Red Hat. Models for FR400 and +FR500 included. + Support for DLX processor added. GASP has now been deprecated and will be removed in a future release. Use the diff -uprN binutils-2.12.90.0.11/gas/config/obj-elf.h binutils-2.12.90.0.12/gas/config/obj-elf.h --- binutils-2.12.90.0.11/gas/config/obj-elf.h Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/gas/config/obj-elf.h Tue Jun 18 21:41:59 2002 @@ -1,5 +1,5 @@ /* ELF object file format. - Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 + Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. @@ -48,11 +48,8 @@ extern int alpha_flag_mdebug; /* For now, always set ECOFF_DEBUGGING for a MIPS target. */ #ifdef TC_MIPS -#ifdef MIPS_STABS_ELF -#define ECOFF_DEBUGGING 0 -#else -#define ECOFF_DEBUGGING (debug_type == DEBUG_ECOFF) -#endif /* MIPS_STABS_ELF */ +#define ECOFF_DEBUGGING mips_flag_mdebug +extern int mips_flag_mdebug; #endif /* TC_MIPS */ #ifdef OBJ_MAYBE_ECOFF @@ -89,7 +86,9 @@ struct elf_obj_sy #define ELF_TARGET_SYMBOL_FIELDS int local:1; /* Don't change this; change ELF_TARGET_SYMBOL_FIELDS instead. */ +#ifndef TARGET_SYMBOL_FIELDS #define TARGET_SYMBOL_FIELDS ELF_TARGET_SYMBOL_FIELDS +#endif /* #include "targ-cpu.h" */ diff -uprN binutils-2.12.90.0.11/gas/config/tc-avr.c binutils-2.12.90.0.12/gas/config/tc-avr.c --- binutils-2.12.90.0.11/gas/config/tc-avr.c Thu May 23 15:10:10 2002 +++ binutils-2.12.90.0.12/gas/config/tc-avr.c Tue Jun 18 21:41:59 2002 @@ -84,19 +84,22 @@ static struct mcu_type_s mcu_types[] = {"at90s8515", AVR_ISA_2xxx, bfd_mach_avr2}, {"at90s8535", AVR_ISA_2xxx, bfd_mach_avr2}, {"at90c8534", AVR_ISA_2xxx, bfd_mach_avr2}, + {"at86rf401", AVR_ISA_2xxx, bfd_mach_avr2}, {"atmega603", AVR_ISA_M603, bfd_mach_avr3}, /* XXX -> m103 */ {"atmega103", AVR_ISA_M103, bfd_mach_avr3}, {"at43usb320",AVR_ISA_M103, bfd_mach_avr3}, {"at43usb355",AVR_ISA_M603, bfd_mach_avr3}, {"at76c711", AVR_ISA_M603, bfd_mach_avr3}, {"atmega8", AVR_ISA_M8, bfd_mach_avr4}, - {"atmega83", AVR_ISA_M8, bfd_mach_avr4}, /* XXX -> m163 */ + {"atmega83", AVR_ISA_M8, bfd_mach_avr4}, /* XXX -> m8535 */ {"atmega85", AVR_ISA_M8, bfd_mach_avr4}, /* XXX -> m8 */ {"atmega8515",AVR_ISA_M8, bfd_mach_avr4}, + {"atmega8535",AVR_ISA_M8, bfd_mach_avr4}, {"atmega16", AVR_ISA_M323, bfd_mach_avr5}, {"atmega161", AVR_ISA_M161, bfd_mach_avr5}, {"atmega162", AVR_ISA_M323, bfd_mach_avr5}, {"atmega163", AVR_ISA_M161, bfd_mach_avr5}, + {"atmega169", AVR_ISA_M323, bfd_mach_avr5}, {"atmega32", AVR_ISA_M323, bfd_mach_avr5}, {"atmega323", AVR_ISA_M323, bfd_mach_avr5}, {"atmega64", AVR_ISA_M323, bfd_mach_avr5}, diff -uprN binutils-2.12.90.0.11/gas/config/tc-frv.c binutils-2.12.90.0.12/gas/config/tc-frv.c --- binutils-2.12.90.0.11/gas/config/tc-frv.c Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/gas/config/tc-frv.c Tue Jun 18 21:41:59 2002 @@ -0,0 +1,1606 @@ +/* tc-frv.c -- Assembler for the Fujitsu FRV. + Copyright (C) 2002 Free Software Foundation. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include +#include "as.h" +#include "dwarf2dbg.h" +#include "subsegs.h" +#include "symcat.h" +#include "opcodes/frv-desc.h" +#include "opcodes/frv-opc.h" +#include "cgen.h" +#include "libbfd.h" +#include "elf/common.h" +#include "elf/frv.h" + +/* Structure to hold all of the different components describing + an individual instruction. */ +typedef struct +{ + const CGEN_INSN * insn; + const CGEN_INSN * orig_insn; + CGEN_FIELDS fields; +#if CGEN_INT_INSN_P + CGEN_INSN_INT buffer [1]; +#define INSN_VALUE(buf) (*(buf)) +#else + unsigned char buffer [CGEN_MAX_INSN_SIZE]; +#define INSN_VALUE(buf) (buf) +#endif + char * addr; + fragS * frag; + int num_fixups; + fixS * fixups [GAS_CGEN_MAX_FIXUPS]; + int indices [MAX_OPERAND_INSTANCES]; +} +frv_insn; + +enum vliw_insn_type +{ + VLIW_GENERIC_TYPE, /* Don't care about this insn. */ + VLIW_BRANCH_TYPE, /* A Branch. */ + VLIW_LABEL_TYPE, /* A Label. */ + VLIW_NOP_TYPE, /* A NOP. */ + VLIW_BRANCH_HAS_NOPS /* A Branch that requires NOPS. */ +}; + +/* We're going to use these in the fr_subtype field to mark + whether to keep inserted nops. */ + +#define NOP_KEEP 1 /* Keep these NOPS. */ +#define NOP_DELETE 2 /* Delete these NOPS. */ + +#define DO_COUNT true +#define DONT_COUNT false + +/* A list of insns within a VLIW insn. */ +struct vliw_insn_list +{ + /* The type of this insn. */ + enum vliw_insn_type type; + + /* The corresponding gas insn information. */ + const CGEN_INSN *insn; + + /* For branches and labels, the symbol that is referenced. */ + symbolS *sym; + + /* For branches, the frag containing the single nop that was generated. */ + fragS *snop_frag; + + /* For branches, the frag containing the double nop that was generated. */ + fragS *dnop_frag; + + /* Pointer to raw data for this insn. */ + char *address; + + /* Next insn in list. */ + struct vliw_insn_list *next; +}; + +static struct vliw_insn_list single_nop_insn = { + VLIW_NOP_TYPE, NULL, NULL, NULL, NULL, NULL, NULL }; + +static struct vliw_insn_list double_nop_insn = { + VLIW_NOP_TYPE, NULL, NULL, NULL, NULL, NULL, NULL }; + +struct vliw_chain +{ + int num; + int insn_count; + struct vliw_insn_list *insn_list; + struct vliw_chain *next; +}; + +static struct vliw_chain *vliw_chain_top; +static struct vliw_chain *current_vliw_chain; +static struct vliw_chain *previous_vliw_chain; +static struct vliw_insn_list *current_vliw_insn; + +const char comment_chars[] = ";"; +const char line_comment_chars[] = "#"; +const char line_separator_chars[] = ""; +const char EXP_CHARS[] = "eE"; +const char FLT_CHARS[] = "dD"; + +static FRV_VLIW vliw; + +/* Default machine */ + +#ifdef DEFAULT_CPU_FRV +#define DEFAULT_MACHINE bfd_mach_frv +#define DEFAULT_FLAGS EF_FRV_CPU_GENERIC + +#else +#ifdef DEFAULT_CPU_FR300 +#define DEFAULT_MACHINE bfd_mach_fr300 +#define DEFAULT_FLAGS EF_FRV_CPU_FR300 + +#else +#ifdef DEFAULT_CPU_SIMPLE +#define DEFAULT_MACHINE bfd_mach_frvsimple +#define DEFAULT_FLAGS EF_FRV_CPU_SIMPLE + +#else +#ifdef DEFAULT_CPU_TOMCAT +#define DEFAULT_MACHINE bfd_mach_frvtomcat +#define DEFAULT_FLAGS EF_FRV_CPU_TOMCAT + +#else +#ifdef DEFAULT_CPU_FR400 +#define DEFAULT_MACHINE bfd_mach_fr400 +#define DEFAULT_FLAGS EF_FRV_CPU_FR400 + +#else +#define DEFAULT_MACHINE bfd_mach_fr500 +#define DEFAULT_FLAGS EF_FRV_CPU_FR500 +#endif +#endif +#endif +#endif +#endif + +static unsigned long frv_mach = bfd_mach_frv; + +/* Flags to set in the elf header */ +static flagword frv_flags = DEFAULT_FLAGS; + +static int frv_user_set_flags_p = 0; +static int frv_pic_p = 0; +static const char *frv_pic_flag = (const char *)0; + +/* Print tomcat-specific debugging info. */ +static int tomcat_debug = 0; + +/* Tomcat-specific NOP statistics. */ +static int tomcat_stats = 0; +static int tomcat_doubles = 0; +static int tomcat_singles = 0; + +/* Forward reference to static functions */ +static void frv_set_flags PARAMS ((int)); +static void frv_pic_ptr PARAMS ((int)); +static void frv_frob_file_section PARAMS ((bfd *, asection *, PTR)); + +/* The target specific pseudo-ops which we support. */ +const pseudo_typeS md_pseudo_table[] = +{ + { "eflags", frv_set_flags, 0 }, + { "word", cons, 4 }, + { "picptr", frv_pic_ptr, 4 }, + { "file", dwarf2_directive_file, 0 }, + { "loc", dwarf2_directive_loc, 0 }, + { NULL, NULL, 0 } +}; + + +#define FRV_SHORTOPTS "G:" +const char * md_shortopts = FRV_SHORTOPTS; + +#define OPTION_GPR_32 (OPTION_MD_BASE) +#define OPTION_GPR_64 (OPTION_MD_BASE + 1) +#define OPTION_FPR_32 (OPTION_MD_BASE + 2) +#define OPTION_FPR_64 (OPTION_MD_BASE + 3) +#define OPTION_SOFT_FLOAT (OPTION_MD_BASE + 4) +#define OPTION_DWORD_YES (OPTION_MD_BASE + 5) +#define OPTION_DWORD_NO (OPTION_MD_BASE + 6) +#define OPTION_DOUBLE (OPTION_MD_BASE + 7) +#define OPTION_NO_DOUBLE (OPTION_MD_BASE + 8) +#define OPTION_MEDIA (OPTION_MD_BASE + 9) +#define OPTION_NO_MEDIA (OPTION_MD_BASE + 10) +#define OPTION_CPU (OPTION_MD_BASE + 11) +#define OPTION_PIC (OPTION_MD_BASE + 12) +#define OPTION_BIGPIC (OPTION_MD_BASE + 13) +#define OPTION_LIBPIC (OPTION_MD_BASE + 14) +#define OPTION_MULADD (OPTION_MD_BASE + 15) +#define OPTION_NO_MULADD (OPTION_MD_BASE + 16) +#define OPTION_TOMCAT_DEBUG (OPTION_MD_BASE + 17) +#define OPTION_TOMCAT_STATS (OPTION_MD_BASE + 18) +#define OPTION_PACK (OPTION_MD_BASE + 19) +#define OPTION_NO_PACK (OPTION_MD_BASE + 20) + +struct option md_longopts[] = +{ + { "mgpr-32", no_argument, NULL, OPTION_GPR_32 }, + { "mgpr-64", no_argument, NULL, OPTION_GPR_64 }, + { "mfpr-32", no_argument, NULL, OPTION_FPR_32 }, + { "mfpr-64", no_argument, NULL, OPTION_FPR_64 }, + { "mhard-float", no_argument, NULL, OPTION_FPR_64 }, + { "msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT }, + { "mdword", no_argument, NULL, OPTION_DWORD_YES }, + { "mno-dword", no_argument, NULL, OPTION_DWORD_NO }, + { "mdouble", no_argument, NULL, OPTION_DOUBLE }, + { "mno-double", no_argument, NULL, OPTION_NO_DOUBLE }, + { "mmedia", no_argument, NULL, OPTION_MEDIA }, + { "mno-media", no_argument, NULL, OPTION_NO_MEDIA }, + { "mcpu", required_argument, NULL, OPTION_CPU }, + { "mpic", no_argument, NULL, OPTION_PIC }, + { "mPIC", no_argument, NULL, OPTION_BIGPIC }, + { "mlibrary-pic", no_argument, NULL, OPTION_LIBPIC }, + { "mmuladd", no_argument, NULL, OPTION_MULADD }, + { "mno-muladd", no_argument, NULL, OPTION_NO_MULADD }, + { "mtomcat-debug", no_argument, NULL, OPTION_TOMCAT_DEBUG }, + { "mtomcat-stats", no_argument, NULL, OPTION_TOMCAT_STATS }, + { "mpack", no_argument, NULL, OPTION_PACK }, + { "mno-pack", no_argument, NULL, OPTION_NO_PACK }, + { NULL, no_argument, NULL, 0 }, +}; + +size_t md_longopts_size = sizeof (md_longopts); + +/* What value to give to bfd_set_gp_size. */ +static int g_switch_value = 8; + +int +md_parse_option (c, arg) + int c; + char * arg; +{ + switch (c) + { + default: + return 0; + + case 'G': + g_switch_value = atoi (arg); + if (! g_switch_value) + frv_flags |= EF_FRV_G0; + break; + + case OPTION_GPR_32: + frv_flags = (frv_flags & ~EF_FRV_GPR_MASK) | EF_FRV_GPR_32; + break; + + case OPTION_GPR_64: + frv_flags = (frv_flags & ~EF_FRV_GPR_MASK) | EF_FRV_GPR_64; + break; + + case OPTION_FPR_32: + frv_flags = (frv_flags & ~EF_FRV_FPR_MASK) | EF_FRV_FPR_32; + break; + + case OPTION_FPR_64: + frv_flags = (frv_flags & ~EF_FRV_FPR_MASK) | EF_FRV_FPR_64; + break; + + case OPTION_SOFT_FLOAT: + frv_flags = (frv_flags & ~EF_FRV_FPR_MASK) | EF_FRV_FPR_NONE; + break; + + case OPTION_DWORD_YES: + frv_flags = (frv_flags & ~EF_FRV_DWORD_MASK) | EF_FRV_DWORD_YES; + break; + + case OPTION_DWORD_NO: + frv_flags = (frv_flags & ~EF_FRV_DWORD_MASK) | EF_FRV_DWORD_NO; + break; + + case OPTION_DOUBLE: + frv_flags |= EF_FRV_DOUBLE; + break; + + case OPTION_NO_DOUBLE: + frv_flags &= ~EF_FRV_DOUBLE; + break; + + case OPTION_MEDIA: + frv_flags |= EF_FRV_MEDIA; + break; + + case OPTION_NO_MEDIA: + frv_flags &= ~EF_FRV_MEDIA; + break; + + case OPTION_MULADD: + frv_flags |= EF_FRV_MULADD; + break; + + case OPTION_NO_MULADD: + frv_flags &= ~EF_FRV_MULADD; + break; + + case OPTION_PACK: + frv_flags &= ~EF_FRV_NOPACK; + break; + + case OPTION_NO_PACK: + frv_flags |= EF_FRV_NOPACK; + break; + + case OPTION_CPU: + { + char *p; + int cpu_flags = EF_FRV_CPU_GENERIC; + + /* Identify the processor type */ + p = arg; + if (strcmp (p, "frv") == 0) + { + cpu_flags = EF_FRV_CPU_GENERIC; + frv_mach = bfd_mach_frv; + } + + else if (strcmp (p, "fr500") == 0) + { + cpu_flags = EF_FRV_CPU_FR500; + frv_mach = bfd_mach_fr500; + } + + else if (strcmp (p, "fr400") == 0) + { + cpu_flags = EF_FRV_CPU_FR400; + frv_mach = bfd_mach_fr400; + } + + else if (strcmp (p, "fr300") == 0) + { + cpu_flags = EF_FRV_CPU_FR300; + frv_mach = bfd_mach_fr300; + } + + else if (strcmp (p, "simple") == 0) + { + cpu_flags = EF_FRV_CPU_SIMPLE; + frv_mach = bfd_mach_frvsimple; + frv_flags |= EF_FRV_NOPACK; + } + + else if (strcmp (p, "tomcat") == 0) + { + cpu_flags = EF_FRV_CPU_TOMCAT; + frv_mach = bfd_mach_frvtomcat; + } + + else + { + as_fatal ("Unknown cpu -mcpu=%s", arg); + return 0; + } + + frv_flags = (frv_flags & ~EF_FRV_CPU_MASK) | cpu_flags; + } + break; + + case OPTION_PIC: + frv_flags |= EF_FRV_PIC; + frv_pic_p = 1; + frv_pic_flag = "-fpic"; + break; + + case OPTION_BIGPIC: + frv_flags |= EF_FRV_BIGPIC; + frv_pic_p = 1; + frv_pic_flag = "-fPIC"; + break; + + case OPTION_LIBPIC: + frv_flags |= (EF_FRV_LIBPIC | EF_FRV_G0); + frv_pic_p = 1; + frv_pic_flag = "-mlibrary-pic"; + g_switch_value = 0; + break; + + case OPTION_TOMCAT_DEBUG: + tomcat_debug = 1; + break; + + case OPTION_TOMCAT_STATS: + tomcat_stats = 1; + break; + } + + return 1; +} + +void +md_show_usage (stream) + FILE * stream; +{ + fprintf (stream, _("FRV specific command line options:\n")); + fprintf (stream, _("-G n Data >= n bytes is in small data area\n")); + fprintf (stream, _("-mgpr-32 Note 32 gprs are used\n")); + fprintf (stream, _("-mgpr-64 Note 64 gprs are used\n")); + fprintf (stream, _("-mfpr-32 Note 32 fprs are used\n")); + fprintf (stream, _("-mfpr-64 Note 64 fprs are used\n")); + fprintf (stream, _("-msoft-float Note software fp is used\n")); + fprintf (stream, _("-mdword Note stack is aligned to a 8 byte boundary\n")); + fprintf (stream, _("-mno-dword Note stack is aligned to a 4 byte boundary\n")); + fprintf (stream, _("-mdouble Note fp double insns are used\n")); + fprintf (stream, _("-mmedia Note media insns are used\n")); + fprintf (stream, _("-mmuladd Note multiply add/subtract insns are used\n")); + fprintf (stream, _("-mpack Note instructions are packed\n")); + fprintf (stream, _("-mno-pack Do not allow instructions to be packed\n")); + fprintf (stream, _("-mpic Note small position independent code\n")); + fprintf (stream, _("-mPIC Note large position independent code\n")); + fprintf (stream, _("-mlibrary-pic Compile library for large position indepedent code\n")); + fprintf (stream, _("-mcpu={fr500|fr400|fr300|frv|simple|tomcat}\n")); + fprintf (stream, _(" Record the cpu type\n")); + fprintf (stream, _("-mtomcat-stats Print out stats for tomcat workarounds\n")); + fprintf (stream, _("-mtomcat-debug Debug tomcat workarounds\n")); +} + + +void +md_begin () +{ + /* Initialize the `cgen' interface. */ + + /* Set the machine number and endian. */ + gas_cgen_cpu_desc = frv_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, + CGEN_CPU_OPEN_ENDIAN, + CGEN_ENDIAN_BIG, + CGEN_CPU_OPEN_END); + frv_cgen_init_asm (gas_cgen_cpu_desc); + + /* This is a callback from cgen to gas to parse operands. */ + cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); + + /* Set the ELF flags if desired. */ + if (frv_flags) + bfd_set_private_flags (stdoutput, frv_flags); + + /* Set the machine type */ + bfd_default_set_arch_mach (stdoutput, bfd_arch_frv, frv_mach); + + /* Set up gp size so we can put local common items in .sbss */ + bfd_set_gp_size (stdoutput, g_switch_value); + + frv_vliw_reset (& vliw, frv_mach, frv_flags); +} + +int chain_num = 0; + +struct vliw_insn_list * +frv_insert_vliw_insn (count) + boolean count; +{ + struct vliw_insn_list *vliw_insn_list_entry; + struct vliw_chain *vliw_chain_entry; + + if (current_vliw_chain == NULL) + { + vliw_chain_entry = (struct vliw_chain *) xmalloc (sizeof (struct vliw_chain)); + vliw_chain_entry->insn_count = 0; + vliw_chain_entry->insn_list = NULL; + vliw_chain_entry->next = NULL; + vliw_chain_entry->num = chain_num++; + + if (!vliw_chain_top) + vliw_chain_top = vliw_chain_entry; + current_vliw_chain = vliw_chain_entry; + if (previous_vliw_chain) + previous_vliw_chain->next = vliw_chain_entry; + } + + vliw_insn_list_entry = (struct vliw_insn_list *) xmalloc (sizeof (struct vliw_insn_list)); + vliw_insn_list_entry->type = VLIW_GENERIC_TYPE; + vliw_insn_list_entry->insn = NULL; + vliw_insn_list_entry->sym = NULL; + vliw_insn_list_entry->snop_frag = NULL; + vliw_insn_list_entry->dnop_frag = NULL; + vliw_insn_list_entry->next = NULL; + + if (count) + current_vliw_chain->insn_count++; + + if (current_vliw_insn) + current_vliw_insn->next = vliw_insn_list_entry; + current_vliw_insn = vliw_insn_list_entry; + + if (!current_vliw_chain->insn_list) + current_vliw_chain->insn_list = current_vliw_insn; + + return vliw_insn_list_entry; +} + + /* Identify the following cases: + + 1) A VLIW insn that contains both a branch and the branch destination. + This requires the insertion of two vliw instructions before the + branch. The first consists of two nops. The second consists of + a single nop. + + 2) A single instruction VLIW insn which is the destination of a branch + that is in the next VLIW insn. This requires the insertion of a vliw + insn containing two nops before the branch. + + 3) A double instruction VLIW insn which contains the destination of a + branch that is in the next VLIW insn. This requires the insertion of + a VLIW insn containing a single nop before the branch. + + 4) A single instruction VLIW insn which contains branch destination (x), + followed by a single instruction VLIW insn which does not contain + the branch to (x), followed by a VLIW insn which does contain the branch + to (x). This requires the insertion of a VLIW insn containing a single + nop before the VLIW instruction containing the branch. + + */ +#define FRV_IS_NOP(insn) (insn.buffer[0] == FRV_NOP_PACK || insn.buffer[0] == FRV_NOP_NOPACK) +#define FRV_NOP_PACK 0x00880000 /* ori.p gr0,0,gr0 */ +#define FRV_NOP_NOPACK 0x80880000 /* ori gr0,0,gr0 */ + +/* Check a vliw insn for an insn of type containing the sym passed in label_sym. */ + +static struct vliw_insn_list * +frv_find_in_vliw (vliw_insn_type, this_chain, label_sym) + enum vliw_insn_type vliw_insn_type; + struct vliw_chain *this_chain; + symbolS *label_sym; +{ + + struct vliw_insn_list *the_insn; + + if (!this_chain) + return NULL; + + for (the_insn = this_chain->insn_list; the_insn; the_insn = the_insn->next) + { + if (the_insn->type == vliw_insn_type + && the_insn->sym == label_sym) + return the_insn; + } + + return NULL; +} + +enum vliw_nop_type +{ + /* A Vliw insn containing a single nop insn. */ + VLIW_SINGLE_NOP, + + /* A Vliw insn containing two nop insns. */ + VLIW_DOUBLE_NOP, + + /* Two vliw insns. The first containing two nop insns. + The second contain a single nop insn. */ + VLIW_DOUBLE_THEN_SINGLE_NOP +}; + +static void +frv_debug_tomcat (start_chain) + struct vliw_chain *start_chain; +{ + struct vliw_chain *this_chain; + struct vliw_insn_list *this_insn; + int i = 1; + + for (this_chain = start_chain; this_chain; this_chain = this_chain->next, i++) + { + fprintf (stderr, "\nVliw Insn #%d, #insns: %d\n", i, this_chain->insn_count); + + for (this_insn = this_chain->insn_list; this_insn; this_insn = this_insn->next) + { + if (this_insn->type == VLIW_LABEL_TYPE) + fprintf (stderr, "Label Value: %d\n", (int) this_insn->sym); + else if (this_insn->type == VLIW_BRANCH_TYPE) + fprintf (stderr, "%s to %d\n", this_insn->insn->base->name, (int) this_insn->sym); + else if (this_insn->type == VLIW_BRANCH_HAS_NOPS) + fprintf (stderr, "nop'd %s to %d\n", this_insn->insn->base->name, (int) this_insn->sym); + else if (this_insn->type == VLIW_NOP_TYPE) + fprintf (stderr, "Nop\n"); + else + fprintf (stderr, " %s\n", this_insn->insn->base->name); + } + } +} + + +static void +frv_adjust_vliw_count (this_chain) + struct vliw_chain *this_chain; +{ + struct vliw_insn_list *this_insn; + + this_chain->insn_count = 0; + + for (this_insn = this_chain->insn_list; + this_insn; + this_insn = this_insn->next) + { + if (this_insn->type != VLIW_LABEL_TYPE) + this_chain->insn_count++; + } + +} + +/* Insert the desired nop combination in the vliw chain before insert_before_insn. + Rechain the vliw insn. */ + + +static struct vliw_chain * +frv_tomcat_shuffle (this_nop_type, vliw_to_split, insert_before_insn) + enum vliw_nop_type this_nop_type; + struct vliw_chain *vliw_to_split; + struct vliw_insn_list *insert_before_insn; +{ + + boolean pack_prev = false; + struct vliw_chain *return_me = NULL; + struct vliw_insn_list *prev_insn = NULL; + struct vliw_insn_list *curr_insn = vliw_to_split->insn_list; + + struct vliw_chain *double_nop = (struct vliw_chain *) xmalloc (sizeof (struct vliw_chain)); + struct vliw_chain *single_nop = (struct vliw_chain *) xmalloc (sizeof (struct vliw_chain)); + struct vliw_chain *second_part = (struct vliw_chain *) xmalloc (sizeof (struct vliw_chain)); + struct vliw_chain *curr_vliw = vliw_chain_top; + struct vliw_chain *prev_vliw = NULL; + + while (curr_insn && curr_insn != insert_before_insn) + { + /* We can't set the packing bit on a label. If we have the case + label 1: + label 2: + label 3: + branch that needs nops + Then don't set pack bit later. */ + + if (curr_insn->type != VLIW_LABEL_TYPE) + pack_prev = true; + prev_insn = curr_insn; + curr_insn = curr_insn->next; + } + + while (curr_vliw && curr_vliw != vliw_to_split) + { + prev_vliw = curr_vliw; + curr_vliw = curr_vliw->next; + } + + switch (this_nop_type) + { + case VLIW_SINGLE_NOP: + if (!prev_insn) + { + /* Branch is first, Insert the NOP prior to this vliw insn. */ + if (prev_vliw) + prev_vliw->next = single_nop; + else + vliw_chain_top = single_nop; + single_nop->next = vliw_to_split; + vliw_to_split->insn_list->type = VLIW_BRANCH_HAS_NOPS; + return_me = vliw_to_split; + } + else + { + /* Set the packing bit on the previous insn. */ + if (pack_prev) + { + unsigned char *buffer = prev_insn->address; + buffer[0] |= 0x80; + } + /* The branch is in the middle. Split this vliw insn into first + and second parts. Insert the NOP inbetween. */ + + second_part->insn_list = insert_before_insn; + second_part->insn_list->type = VLIW_BRANCH_HAS_NOPS; + second_part->next = vliw_to_split->next; + frv_adjust_vliw_count (second_part); + + single_nop->next = second_part; + + vliw_to_split->next = single_nop; + prev_insn->next = NULL; + + return_me = second_part; + frv_adjust_vliw_count (vliw_to_split); + } + break; + + case VLIW_DOUBLE_NOP: + if (!prev_insn) + { + /* Branch is first, Insert the NOP prior to this vliw insn. */ + if (prev_vliw) + prev_vliw->next = double_nop; + else + vliw_chain_top = double_nop; + + double_nop->next = vliw_to_split; + return_me = vliw_to_split; + vliw_to_split->insn_list->type = VLIW_BRANCH_HAS_NOPS; + } + else + { + /* Set the packing bit on the previous insn. */ + if (pack_prev) + { + unsigned char *buffer = prev_insn->address; + buffer[0] |= 0x80; + } + + /* The branch is in the middle. Split this vliw insn into first + and second parts. Insert the NOP inbetween. */ + second_part->insn_list = insert_before_insn; + second_part->insn_list->type = VLIW_BRANCH_HAS_NOPS; + second_part->next = vliw_to_split->next; + frv_adjust_vliw_count (second_part); + + double_nop->next = second_part; + + vliw_to_split->next = single_nop; + prev_insn->next = NULL; + frv_adjust_vliw_count (vliw_to_split); + + return_me = second_part; + } + break; + + case VLIW_DOUBLE_THEN_SINGLE_NOP: + double_nop->next = single_nop; + double_nop->insn_count = 2; + double_nop->insn_list = &double_nop_insn; + single_nop->insn_count = 1; + single_nop->insn_list = &single_nop_insn; + + if (!prev_insn) + { + /* The branch is the first insn in this vliw. Don't split the vliw. Insert + the nops prior to this vliw. */ + if (prev_vliw) + prev_vliw->next = double_nop; + else + vliw_chain_top = double_nop; + + single_nop->next = vliw_to_split; + return_me = vliw_to_split; + vliw_to_split->insn_list->type = VLIW_BRANCH_HAS_NOPS; + } + else + { + /* Set the packing bit on the previous insn. */ + if (pack_prev) + { + unsigned char *buffer = prev_insn->address; + buffer[0] |= 0x80; + } + + /* The branch is in the middle of this vliw insn. Split into first and + second parts. Insert the nop vliws in between. */ + second_part->insn_list = insert_before_insn; + second_part->insn_list->type = VLIW_BRANCH_HAS_NOPS; + second_part->next = vliw_to_split->next; + frv_adjust_vliw_count (second_part); + + single_nop->next = second_part; + + vliw_to_split->next = double_nop; + prev_insn->next = NULL; + frv_adjust_vliw_count (vliw_to_split); + + return_me = second_part; + } + break; + } + + return return_me; +} + +static void +frv_tomcat_analyze_vliw_chains () +{ + struct vliw_chain *vliw1 = NULL; + struct vliw_chain *vliw2 = NULL; + struct vliw_chain *vliw3 = NULL; + + struct vliw_insn_list *this_insn = NULL; + struct vliw_insn_list *temp_insn = NULL; + + /* We potentially need to look at three VLIW insns to determine if the + workaround is required. Set them up. Ignore existing nops during analysis. */ + +#define FRV_SET_VLIW_WINDOW(VLIW1, VLIW2, VLIW3) \ + if (VLIW1 && VLIW1->next) \ + VLIW2 = VLIW1->next; \ + else \ + VLIW2 = NULL; \ + if (VLIW2 && VLIW2->next) \ + VLIW3 = VLIW2->next; \ + else \ + VLIW3 = NULL + + vliw1 = vliw_chain_top; + +workaround_top: + + FRV_SET_VLIW_WINDOW (vliw1, vliw2, vliw3); + + if (!vliw1) + return; + + if (vliw1->insn_count == 1) + { + /* check vliw1 for a label. */ + if (vliw1->insn_list->type == VLIW_LABEL_TYPE) + { + temp_insn = frv_find_in_vliw (VLIW_BRANCH_TYPE, vliw2, vliw1->insn_list->sym); + if (temp_insn) + { + vliw1 = frv_tomcat_shuffle (VLIW_DOUBLE_NOP, vliw2, vliw1->insn_list); + temp_insn->dnop_frag->fr_subtype = NOP_KEEP; + vliw1 = vliw1->next; + if (tomcat_stats) + tomcat_doubles++; + goto workaround_top; + } + else if (vliw2 + && vliw2->insn_count == 1 + && (temp_insn = frv_find_in_vliw (VLIW_BRANCH_TYPE, vliw3, vliw1->insn_list->sym)) != NULL) + { + temp_insn->snop_frag->fr_subtype = NOP_KEEP; + vliw1 = frv_tomcat_shuffle (VLIW_SINGLE_NOP, vliw3, vliw3->insn_list); + if (tomcat_stats) + tomcat_singles++; + goto workaround_top; + } + } + } + + if (vliw1->insn_count == 2) + { + struct vliw_insn_list *this_insn; + + /* check vliw1 for a label. */ + for (this_insn = vliw1->insn_list; this_insn; this_insn = this_insn->next) + { + if (this_insn->type == VLIW_LABEL_TYPE) + { + if ((temp_insn = frv_find_in_vliw (VLIW_BRANCH_TYPE, vliw2, this_insn->sym, temp_insn)) != NULL) + { + temp_insn->snop_frag->fr_subtype = NOP_KEEP; + vliw1 = frv_tomcat_shuffle (VLIW_SINGLE_NOP, vliw2, this_insn); + if (tomcat_stats) + tomcat_singles++; + } + else + vliw1 = vliw1->next; + goto workaround_top; + } + } + } + /* Examine each insn in this VLIW. Look for the workaround criteria. */ + for (this_insn = vliw1->insn_list; this_insn; this_insn = this_insn->next) + { + /* Don't look at labels or nops. */ + while (this_insn + && (this_insn->type == VLIW_LABEL_TYPE + || this_insn->type == VLIW_NOP_TYPE + || this_insn->type == VLIW_BRANCH_HAS_NOPS)) + this_insn = this_insn->next; + + if (!this_insn) + { + vliw1 = vliw2; + goto workaround_top; + } + + if (frv_is_branch_insn (this_insn->insn)) + { + if ((temp_insn = frv_find_in_vliw (VLIW_LABEL_TYPE, vliw1, this_insn->sym, temp_insn)) != NULL) + { + /* Insert [nop/nop] [nop] before branch. */ + this_insn->snop_frag->fr_subtype = NOP_KEEP; + this_insn->dnop_frag->fr_subtype = NOP_KEEP; + vliw1 = frv_tomcat_shuffle (VLIW_DOUBLE_THEN_SINGLE_NOP, vliw1, this_insn); + goto workaround_top; + } + } + + + } + /* This vliw insn checks out okay. Take a look at the next one. */ + vliw1 = vliw1->next; + goto workaround_top; +} + +void +frv_tomcat_workaround () +{ + if (frv_mach != bfd_mach_frvtomcat) + return; + + if (tomcat_debug) + frv_debug_tomcat (vliw_chain_top); + + frv_tomcat_analyze_vliw_chains (); + + if (tomcat_stats) + { + fprintf (stderr, "Inserted %d Single Nops\n", tomcat_singles); + fprintf (stderr, "Inserted %d Double Nops\n", tomcat_doubles); + } +} + +void +md_assemble (str) + char * str; +{ + frv_insn insn; + char *errmsg; + int packing_constraint; + finished_insnS finished_insn; + fragS *double_nop_frag = NULL; + fragS *single_nop_frag = NULL; + struct vliw_insn_list *vliw_insn_list_entry = NULL; + + /* Initialize GAS's cgen interface for a new instruction. */ + gas_cgen_init_parse (); + + insn.insn = frv_cgen_assemble_insn + (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, &errmsg); + + if (!insn.insn) + { + as_bad (errmsg); + return; + } + + /* If the cpu is tomcat, then we need to insert nops to workaround + hardware limitations. We need to keep track of each vliw unit + and examine the length of the unit and the individual insns + within the unit to determine the number and location of the + required nops. */ + if (frv_mach == bfd_mach_frvtomcat) + { + /* If we've just finished a VLIW insn OR this is a branch, + then start up a new frag. Fill it with nops. We will get rid + of those that are not required after we've seen all of the + instructions but before we start resolving fixups. */ + if ( !FRV_IS_NOP (insn) + && (frv_is_branch_insn (insn.insn) || insn.fields.f_pack)) + { + char *buffer; + + frag_wane (frag_now); + frag_new (0); + double_nop_frag = frag_now; + buffer = frag_var (rs_machine_dependent, 8, 8, NOP_DELETE, NULL, 0, 0); + md_number_to_chars (buffer, FRV_NOP_PACK, 4); + md_number_to_chars (buffer+4, FRV_NOP_NOPACK, 4); + + frag_wane (frag_now); + frag_new (0); + single_nop_frag = frag_now; + buffer = frag_var (rs_machine_dependent, 4, 4, NOP_DELETE, NULL, 0, 0); + md_number_to_chars (buffer, FRV_NOP_NOPACK, 4); + } + + vliw_insn_list_entry = frv_insert_vliw_insn (DO_COUNT); + vliw_insn_list_entry->insn = insn.insn; + if (frv_is_branch_insn (insn.insn)) + vliw_insn_list_entry->type = VLIW_BRANCH_TYPE; + + if ( !FRV_IS_NOP (insn) + && (frv_is_branch_insn (insn.insn) || insn.fields.f_pack)) + { + vliw_insn_list_entry->snop_frag = single_nop_frag; + vliw_insn_list_entry->dnop_frag = double_nop_frag; + } + } + + /* Make sure that this insn does not violate the VLIW packing constraints. */ + /* -mno-pack disallows any packing whatsoever. */ + if (frv_flags & EF_FRV_NOPACK) + { + if (! insn.fields.f_pack) + { + as_bad (_("VLIW packing used for -mno-pack")); + return; + } + } + /* -mcpu=FRV is an idealized FR-V implementation that supports all of the + instructions, don't do vliw checking. */ + else if (frv_mach != bfd_mach_frv) + { + packing_constraint = frv_vliw_add_insn (& vliw, insn.insn); + if (insn.fields.f_pack) + frv_vliw_reset (& vliw, frv_mach, frv_flags); + if (packing_constraint) + { + as_bad (_("VLIW packing constraint violation")); + return; + } + } + + /* Doesn't really matter what we pass for RELAX_P here. */ + gas_cgen_finish_insn (insn.insn, insn.buffer, + CGEN_FIELDS_BITSIZE (& insn.fields), 1, &finished_insn); + + + /* If the cpu is tomcat, then we need to insert nops to workaround + hardware limitations. We need to keep track of each vliw unit + and examine the length of the unit and the individual insns + within the unit to determine the number and location of the + required nops. */ + if (frv_mach == bfd_mach_frvtomcat) + { + if (vliw_insn_list_entry) + vliw_insn_list_entry->address = finished_insn.addr; + else + abort(); + + if (insn.fields.f_pack) + { + /* We've completed a VLIW insn. */ + previous_vliw_chain = current_vliw_chain; + current_vliw_chain = NULL; + current_vliw_insn = NULL; + } + } +} + +/* The syntax in the manual says constants begin with '#'. + We just ignore it. */ + +void +md_operand (expressionP) + expressionS * expressionP; +{ + if (* input_line_pointer == '#') + { + input_line_pointer ++; + expression (expressionP); + } +} + +valueT +md_section_align (segment, size) + segT segment; + valueT size; +{ + int align = bfd_get_section_alignment (stdoutput, segment); + return ((size + (1 << align) - 1) & (-1 << align)); +} + +symbolS * +md_undefined_symbol (name) + char * name ATTRIBUTE_UNUSED; +{ + return 0; +} + +/* Interface to relax_segment. */ + +/* FIXME: Build table by hand, get it working, then machine generate. */ +const relax_typeS md_relax_table[] = +{ + {1, 1, 0, 0}, + {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, + {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, + {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } +}; + +long +frv_relax_frag (fragP, stretch) + fragS *fragP ATTRIBUTE_UNUSED; + long stretch ATTRIBUTE_UNUSED; +{ + return 0; +} + +/* Return an initial guess of the length by which a fragment must grow to + hold a branch to reach its destination. + Also updates fr_type/fr_subtype as necessary. + + Called just before doing relaxation. + Any symbol that is now undefined will not become defined. + The guess for fr_var is ACTUALLY the growth beyond fr_fix. + Whatever we do to grow fr_fix or fr_var contributes to our returned value. + Although it may not be explicit in the frag, pretend fr_var starts with a + 0 value. */ + +int +md_estimate_size_before_relax (fragP, segment) + fragS * fragP; + segT segment ATTRIBUTE_UNUSED; +{ + switch (fragP->fr_subtype) + { + case NOP_KEEP: + return fragP->fr_var; + + default: + case NOP_DELETE: + return 0; + } +} + +/* *fragP has been relaxed to its final size, and now needs to have + the bytes inside it modified to conform to the new size. + + Called after relaxation is finished. + fragP->fr_type == rs_machine_dependent. + fragP->fr_subtype is the subtype of what the address relaxed to. */ + +void +md_convert_frag (abfd, sec, fragP) + bfd * abfd ATTRIBUTE_UNUSED; + segT sec ATTRIBUTE_UNUSED; + fragS * fragP; +{ + switch (fragP->fr_subtype) + { + default: + case NOP_DELETE: + return; + + case NOP_KEEP: + fragP->fr_fix = fragP->fr_var; + fragP->fr_var = 0; + return; + } +} + +/* Functions concerning relocs. */ + +/* The location from which a PC relative jump should be calculated, + given a PC relative reloc. */ + +long +md_pcrel_from_section (fixP, sec) + fixS * fixP; + segT sec; +{ + if (fixP->fx_addsy != (symbolS *) NULL + && (! S_IS_DEFINED (fixP->fx_addsy) + || S_GET_SEGMENT (fixP->fx_addsy) != sec)) + { + /* The symbol is undefined (or is defined but not in this section). + Let the linker figure it out. */ + return 0; + } + + return (fixP->fx_frag->fr_address + fixP->fx_where) & ~1; +} + +/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. + Returns BFD_RELOC_NONE if no reloc type can be found. + *FIXP may be modified if desired. */ + +bfd_reloc_code_real_type +md_cgen_lookup_reloc (insn, operand, fixP) + const CGEN_INSN * insn ATTRIBUTE_UNUSED; + const CGEN_OPERAND * operand; + fixS * fixP; +{ + switch (operand->type) + { + case FRV_OPERAND_LABEL16: + fixP->fx_pcrel = true; + return BFD_RELOC_FRV_LABEL16; + + case FRV_OPERAND_LABEL24: + fixP->fx_pcrel = true; + return BFD_RELOC_FRV_LABEL24; + + case FRV_OPERAND_UHI16: + case FRV_OPERAND_ULO16: + case FRV_OPERAND_SLO16: + + /* The relocation type should be recorded in opinfo */ + if (fixP->fx_cgen.opinfo != 0) + return fixP->fx_cgen.opinfo; + break; + + case FRV_OPERAND_D12: + case FRV_OPERAND_S12: + return BFD_RELOC_FRV_GPREL12; + + case FRV_OPERAND_U12: + return BFD_RELOC_FRV_GPRELU12; + + default: + break; + } + return BFD_RELOC_NONE; +} + + +/* See whether we need to force a relocation into the output file. + This is used to force out switch and PC relative relocations when + relaxing. */ + +int +frv_force_relocation (fix) + fixS * fix; +{ + if (fix->fx_r_type == BFD_RELOC_VTABLE_INHERIT + || fix->fx_r_type == BFD_RELOC_VTABLE_ENTRY + || fix->fx_r_type == BFD_RELOC_FRV_GPREL12 + || fix->fx_r_type == BFD_RELOC_FRV_GPRELU12) + return 1; + + return 0; +} + +/* Write a value out to the object file, using the appropriate endianness. */ + +void +frv_md_number_to_chars (buf, val, n) + char * buf; + valueT val; + int n; +{ + number_to_chars_bigendian (buf, val, n); +} + +/* Turn a string in input_line_pointer into a floating point constant of type + type, and store the appropriate bytes in *litP. The number of LITTLENUMS + emitted is stored in *sizeP . An error message is returned, or NULL on OK. +*/ + +/* Equal to MAX_PRECISION in atof-ieee.c */ +#define MAX_LITTLENUMS 6 + +char * +md_atof (type, litP, sizeP) + char type; + char * litP; + int * sizeP; +{ + int i; + int prec; + LITTLENUM_TYPE words [MAX_LITTLENUMS]; + char * t; + char * atof_ieee (); + + switch (type) + { + case 'f': + case 'F': + case 's': + case 'S': + prec = 2; + break; + + case 'd': + case 'D': + case 'r': + case 'R': + prec = 4; + break; + + /* FIXME: Some targets allow other format chars for bigger sizes here. */ + + default: + * sizeP = 0; + return _("Bad call to md_atof()"); + } + + t = atof_ieee (input_line_pointer, type, words); + if (t) + input_line_pointer = t; + * sizeP = prec * sizeof (LITTLENUM_TYPE); + + for (i = 0; i < prec; i++) + { + md_number_to_chars (litP, (valueT) words[i], + sizeof (LITTLENUM_TYPE)); + litP += sizeof (LITTLENUM_TYPE); + } + + return 0; +} + +boolean +frv_fix_adjustable (fixP) + fixS * fixP; +{ + bfd_reloc_code_real_type reloc_type; + + if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) + { + const CGEN_INSN *insn = NULL; + int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; + const CGEN_OPERAND *operand = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); + reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); + } + else + reloc_type = fixP->fx_r_type; + + if (fixP->fx_addsy == NULL) + return 1; + + /* Prevent all adjustments to global symbols. */ + if (S_IS_EXTERN (fixP->fx_addsy)) + return 0; + + if (S_IS_WEAK (fixP->fx_addsy)) + return 0; + + /* We need the symbol name for the VTABLE entries */ + if ( reloc_type == BFD_RELOC_VTABLE_INHERIT + || reloc_type == BFD_RELOC_VTABLE_ENTRY + || reloc_type == BFD_RELOC_FRV_GPREL12 + || reloc_type == BFD_RELOC_FRV_GPRELU12) + return 0; + + return 1; +} + +/* Allow user to set flags bits. */ +void +frv_set_flags (arg) + int arg ATTRIBUTE_UNUSED; +{ + flagword new_flags = get_absolute_expression (); + flagword new_mask = ~ (flagword)0; + + frv_user_set_flags_p = 1; + if (*input_line_pointer == ',') + { + ++input_line_pointer; + new_mask = get_absolute_expression (); + } + + frv_flags = (frv_flags & ~new_mask) | (new_flags & new_mask); + bfd_set_private_flags (stdoutput, frv_flags); +} + +/* Frv specific function to handle 4 byte initializations for pointers that are + considered 'safe' for use with pic support. Until frv_frob_file{,_section} + is run, we encode it a BFD_RELOC_CTOR, and it is turned back into a normal + BFD_RELOC_32 at that time. */ + +void +frv_pic_ptr (nbytes) + int nbytes; +{ + expressionS exp; + char *p; + + if (nbytes != 4) + abort (); + +#ifdef md_flush_pending_output + md_flush_pending_output (); +#endif + + if (is_it_end_of_statement ()) + { + demand_empty_rest_of_line (); + return; + } + +#ifdef md_cons_align + md_cons_align (nbytes); +#endif + + do + { + expression (&exp); + + p = frag_more (4); + memset (p, 0, 4); + fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &exp, 0, + BFD_RELOC_CTOR); + } + while (*input_line_pointer++ == ','); + + input_line_pointer--; /* Put terminator back into stream. */ + demand_empty_rest_of_line (); +} + + + +#ifdef DEBUG +#define DPRINTF1(A) fprintf (stderr, A) +#define DPRINTF2(A,B) fprintf (stderr, A, B) +#define DPRINTF3(A,B,C) fprintf (stderr, A, B, C) + +#else +#define DPRINTF1(A) +#define DPRINTF2(A,B) +#define DPRINTF3(A,B,C) +#endif + +/* Go through a the sections looking for relocations that are problematical for + pic. If not pic, just note that this object can't be linked with pic. If + it is pic, see if it needs to be marked so that it will be fixed up, or if + not possible, issue an error. */ + +static void +frv_frob_file_section (abfd, sec, ptr) + bfd *abfd; + asection *sec; + PTR ptr ATTRIBUTE_UNUSED; +{ + segment_info_type *seginfo = seg_info (sec); + fixS *fixp; + CGEN_CPU_DESC cd = gas_cgen_cpu_desc; + flagword flags = bfd_get_section_flags (abfd, sec); + + /* Skip relocations in known sections (.ctors, .dtors, and .gcc_except_table) + since we can fix those up by hand. */ + int known_section_p = (sec->name + && sec->name[0] == '.' + && ((sec->name[1] == 'c' + && strcmp (sec->name, ".ctor") == 0) + || (sec->name[1] == 'd' + && strcmp (sec->name, ".dtor") == 0) + || (sec->name[1] == 'g' + && strcmp (sec->name, ".gcc_except_table") == 0))); + + DPRINTF3 ("\nFrv section %s%s\n", sec->name, (known_section_p) ? ", known section" : ""); + if ((flags & SEC_ALLOC) == 0) + { + DPRINTF1 ("\tSkipping non-loaded section\n"); + return; + } + + for (fixp = seginfo->fix_root; fixp; fixp = fixp->fx_next) + { + symbolS *s = fixp->fx_addsy; + bfd_reloc_code_real_type reloc; + int non_pic_p; + int opindex; + const CGEN_OPERAND *operand; + const CGEN_INSN *insn = fixp->fx_cgen.insn; + + if (fixp->fx_done) + { + DPRINTF1 ("\tSkipping reloc that has already been done\n"); + continue; + } + + if (fixp->fx_pcrel) + { + DPRINTF1 ("\tSkipping reloc that is PC relative\n"); + continue; + } + + if (! s) + { + DPRINTF1 ("\tSkipping reloc without symbol\n"); + continue; + } + + if (fixp->fx_r_type < BFD_RELOC_UNUSED) + { + opindex = -1; + reloc = fixp->fx_r_type; + } + else + { + opindex = (int) fixp->fx_r_type - (int) BFD_RELOC_UNUSED; + operand = cgen_operand_lookup_by_num (cd, opindex); + reloc = md_cgen_lookup_reloc (insn, operand, fixp); + } + + DPRINTF3 ("\treloc %s\t%s", bfd_get_reloc_code_name (reloc), S_GET_NAME (s)); + + non_pic_p = 0; + switch (reloc) + { + default: + break; + + case BFD_RELOC_32: + /* Skip relocations in known sections (.ctors, .dtors, and + .gcc_except_table) since we can fix those up by hand. Also + skip forward references to constants. Also skip a difference + of two symbols, which still uses the BFD_RELOC_32 at this + point. */ + if (! known_section_p + && S_GET_SEGMENT (s) != absolute_section + && !fixp->fx_subsy + && (flags & (SEC_READONLY | SEC_CODE)) == 0) + { + non_pic_p = 1; + } + break; + + /* FIXME -- should determine if any of the GP relocation really uses + gr16 (which is not pic safe) or not. Right now, assume if we + aren't being compiled with -mpic, the usage is non pic safe, but + is safe with -mpic. */ + case BFD_RELOC_FRV_GPREL12: + case BFD_RELOC_FRV_GPRELU12: + case BFD_RELOC_FRV_GPREL32: + case BFD_RELOC_FRV_GPRELHI: + case BFD_RELOC_FRV_GPRELLO: + non_pic_p = ! frv_pic_p; + break; + + case BFD_RELOC_FRV_LO16: + case BFD_RELOC_FRV_HI16: + if (S_GET_SEGMENT (s) != absolute_section) + non_pic_p = 1; + break; + + case BFD_RELOC_VTABLE_INHERIT: + case BFD_RELOC_VTABLE_ENTRY: + non_pic_p = 1; + break; + + /* If this is a blessed BFD_RELOC_32, convert it back to the normal + relocation. */ + case BFD_RELOC_CTOR: + fixp->fx_r_type = BFD_RELOC_32; + break; + } + + if (non_pic_p) + { + DPRINTF1 (" (Non-pic relocation)\n"); + if (frv_pic_p) + as_warn_where (fixp->fx_file, fixp->fx_line, + _("Relocation %s is not safe for %s"), + bfd_get_reloc_code_name (reloc), frv_pic_flag); + + else if ((frv_flags & EF_FRV_NON_PIC_RELOCS) == 0) + { + frv_flags |= EF_FRV_NON_PIC_RELOCS; + bfd_set_private_flags (abfd, frv_flags); + } + } +#ifdef DEBUG + else + DPRINTF1 ("\n"); +#endif + } +} + +/* After all of the symbols have been adjusted, go over the file looking + for any relocations that pic won't support. */ + +void +frv_frob_file () +{ + bfd_map_over_sections (stdoutput, frv_frob_file_section, (PTR)0); +} + +void +frv_frob_label (this_label) + symbolS *this_label; +{ + struct vliw_insn_list *vliw_insn_list_entry; + + if (frv_mach != bfd_mach_frvtomcat) + return; + + if (now_seg != text_section) + return; + + vliw_insn_list_entry = frv_insert_vliw_insn(DONT_COUNT); + vliw_insn_list_entry->type = VLIW_LABEL_TYPE; + vliw_insn_list_entry->sym = this_label; +} + +fixS * +frv_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) + fragS * frag; + int where; + const CGEN_INSN * insn; + int length; + const CGEN_OPERAND * operand; + int opinfo; + expressionS * exp; +{ + fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, + operand, opinfo, exp); + + if (frv_mach == bfd_mach_frvtomcat + && current_vliw_insn + && current_vliw_insn->type == VLIW_BRANCH_TYPE + && exp != NULL) + current_vliw_insn->sym = exp->X_add_symbol; + + return fixP; +} diff -uprN binutils-2.12.90.0.11/gas/config/tc-frv.h binutils-2.12.90.0.12/gas/config/tc-frv.h --- binutils-2.12.90.0.11/gas/config/tc-frv.h Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/gas/config/tc-frv.h Tue Jun 18 21:41:59 2002 @@ -0,0 +1,89 @@ +/* tc-frv.h -- Header file for tc-frv.c. + Copyright (C) 2002 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#define TC_FRV + +#ifndef BFD_ASSEMBLER +/* leading space so will compile with cc */ + #error FRV support requires BFD_ASSEMBLER +#endif + +#define LISTING_HEADER "FRV GAS " + +/* The target BFD architecture. */ +#define TARGET_ARCH bfd_arch_frv + +#define TARGET_FORMAT "elf32-frv" + +#define TARGET_BYTES_BIG_ENDIAN 1 + +/* call md_pcrel_from_section, not md_pcrel_from */ +long md_pcrel_from_section PARAMS ((struct fix *, segT)); +#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC) + +/* Permit temporary numeric labels. */ +#define LOCAL_LABELS_FB 1 + +#define DIFF_EXPR_OK /* .-foo gets turned into PC relative relocs */ + +/* We don't need to handle .word strangely. */ +#define WORKING_DOT_WORD + +#define md_apply_fix3 gas_cgen_md_apply_fix3 + +extern void frv_tomcat_workaround PARAMS ((void)); +#define md_cleanup frv_tomcat_workaround + +#define md_number_to_chars frv_md_number_to_chars + +extern long frv_relax_frag PARAMS ((fragS *, long)); +#define md_relax_frag(segment, fragP, stretch) frv_relax_frag(fragP, stretch) + +#define obj_fix_adjustable(fixP) frv_fix_adjustable (fixP) +extern boolean frv_fix_adjustable PARAMS ((struct fix *)); + +#ifdef OBJ_ELF +/* This arranges for gas/write.c to not apply a relocation if + obj_fix_adjustable() says it is not adjustable. */ +#define TC_FIX_ADJUSTABLE(fixP) obj_fix_adjustable (fixP) +#endif + +/* When relaxing, we need to emit various relocs we otherwise wouldn't. */ +#define TC_FORCE_RELOCATION(fix) frv_force_relocation (fix) +extern int frv_force_relocation PARAMS ((struct fix *)); + +#undef GAS_CGEN_MAX_FIXUPS +#define GAS_CGEN_MAX_FIXUPS 1 + +void frv_frob_label PARAMS ((symbolS *)); +#define tc_frob_label(sym) frv_frob_label(sym) + +#define tc_gen_reloc gas_cgen_tc_gen_reloc + +#define md_cgen_record_fixup_exp frv_cgen_record_fixup_exp + +/* Call md_pcrel_from_section(), not md_pcrel_from(). */ +#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC) +extern long md_pcrel_from_section PARAMS ((struct fix *, segT)); + +/* After all of the symbols have been adjusted, go over the file looking + for any relocations that pic won't support. */ +#define tc_frob_file() frv_frob_file () +extern void frv_frob_file PARAMS ((void)); diff -uprN binutils-2.12.90.0.11/gas/config/tc-i370.h binutils-2.12.90.0.12/gas/config/tc-i370.h --- binutils-2.12.90.0.11/gas/config/tc-i370.h Fri Nov 16 14:05:52 2001 +++ binutils-2.12.90.0.12/gas/config/tc-i370.h Tue Jun 18 21:41:59 2002 @@ -65,3 +65,6 @@ extern int target_big_endian; extern long md_pcrel_from_section PARAMS ((struct fix *, segT)); #define md_operand(x) + +#define tc_comment_chars i370_comment_chars +extern const char *i370_comment_chars; diff -uprN binutils-2.12.90.0.11/gas/config/tc-mips.c binutils-2.12.90.0.12/gas/config/tc-mips.c --- binutils-2.12.90.0.11/gas/config/tc-mips.c Sat Jun 8 20:44:53 2002 +++ binutils-2.12.90.0.12/gas/config/tc-mips.c Tue Jun 18 21:41:59 2002 @@ -77,6 +77,8 @@ static int mips_output_flavor () { retur #define ECOFF_DEBUGGING 0 #endif +int mips_flag_mdebug = -1; + #include "ecoff.h" #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) @@ -885,9 +887,7 @@ static const pseudo_typeS mips_pseudo_ta {"text", s_change_sec, 't'}, {"word", s_cons, 2}, -#ifdef MIPS_STABS_ELF { "extern", ecoff_directive_extern, 0}, -#endif { NULL, NULL, 0 }, }; @@ -967,11 +967,10 @@ static boolean imm_unmatched_hi; static boolean mips16_small, mips16_ext; -#ifdef MIPS_STABS_ELF -/* The pdr segment for per procedure frame/regmask info */ +/* The pdr segment for per procedure frame/regmask info. Not used for + ECOFF debugging. */ static segT pdr_seg; -#endif static const char * mips_isa_to_str (isa) @@ -1224,12 +1223,15 @@ md_begin () SEC_HAS_CONTENTS | SEC_READONLY); (void) bfd_set_section_alignment (stdoutput, sec, 2); } - -#ifdef MIPS_STABS_ELF - pdr_seg = subseg_new (".pdr", (subsegT) 0); - (void) bfd_set_section_flags (stdoutput, pdr_seg, - SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); - (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); +#ifdef OBJ_ELF + else if (OUTPUT_FLAVOR == bfd_target_elf_flavour) + { + pdr_seg = subseg_new (".pdr", (subsegT) 0); + (void) bfd_set_section_flags (stdoutput, pdr_seg, + SEC_READONLY | SEC_RELOC + | SEC_DEBUGGING); + (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); + } #endif subseg_set (seg, subseg); @@ -9929,6 +9931,10 @@ struct option md_longopts[] = {"n32", no_argument, NULL, OPTION_N32}, #define OPTION_64 (OPTION_ELF_BASE + 6) {"64", no_argument, NULL, OPTION_64}, +#define OPTION_MDEBUG (OPTION_ELF_BASE + 7) + {"mdebug", no_argument, NULL, OPTION_MDEBUG}, +#define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) + {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, #endif /* OBJ_ELF */ {NULL, no_argument, NULL, 0} }; @@ -10295,6 +10301,16 @@ md_parse_option (c, arg) mips_7000_hilo_fix = false; break; +#ifdef OBJ_ELF + case OPTION_MDEBUG: + mips_flag_mdebug = true; + break; + + case OPTION_NO_MDEBUG: + mips_flag_mdebug = false; + break; +#endif /* OBJ_ELF */ + default: return 0; } @@ -10650,6 +10666,16 @@ mips_after_parse_args () if (HAVE_NEWABI) mips_big_got = 1; + + if (mips_flag_mdebug < 0) + { +#ifdef OBJ_MAYBE_ECOFF + if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) + mips_flag_mdebug = 1; + else +#endif /* OBJ_MAYBE_ECOFF */ + mips_flag_mdebug = 0; + } } void @@ -10892,10 +10918,13 @@ md_apply_fix3 (fixP, valP, seg) { if (mips_need_elf_addend_fixup (fixP)) { + reloc_howto_type *howto; valueT symval = S_GET_VALUE (fixP->fx_addsy); value -= symval; - if (value != 0 && ! fixP->fx_pcrel) + + howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); + if (value != 0 && howto->partial_inplace && ! fixP->fx_pcrel) { /* In this case, the bfd_install_relocation routine will incorrectly add the symbol value back in. We just want @@ -10913,12 +10942,8 @@ md_apply_fix3 (fixP, valP, seg) leave the matching HI16 in-place addends as zero. */ if (fixP->fx_r_type != BFD_RELOC_HI16_S) { - reloc_howto_type *howto; bfd_vma contents, mask, field; - howto = bfd_reloc_type_lookup (stdoutput, - fixP->fx_r_type); - contents = bfd_get_bits (fixP->fx_frag->fr_literal + fixP->fx_where, fixP->fx_size * 8, @@ -13366,13 +13391,30 @@ static void s_mips_file (x) int x ATTRIBUTE_UNUSED; { + static int first_file_directive = 0; + if (ECOFF_DEBUGGING) { get_number (); s_app_file (0); } else - dwarf2_directive_file (0); + { + char *filename; + + filename = dwarf2_directive_file (0); + + /* Versions of GCC up to 3.1 start files with a ".file" + directive even for stabs output. Make sure that this + ".file" is handled. Note that you need a version of GCC + after 3.1 in order to support DWARF-2 on MIPS. */ + if (filename != NULL && ! first_file_directive) + { + (void) new_logical_line (filename, -1); + s_app_file_string (filename); + } + first_file_directive = 1; + } } /* The .loc directive, implying DWARF-2. */ @@ -13433,46 +13475,52 @@ s_mips_end (x) assert (S_GET_NAME (p)); if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) as_warn (_(".end symbol does not match .ent symbol.")); + + if (debug_type == DEBUG_STABS) + stabs_generate_asm_endfunc (S_GET_NAME (p), + S_GET_NAME (p)); } else as_warn (_(".end directive missing or unknown symbol")); -#ifdef MIPS_STABS_ELF - { - segT saved_seg = now_seg; - subsegT saved_subseg = now_subseg; - valueT dot; - expressionS exp; - char *fragp; +#ifdef OBJ_ELF + /* Generate a .pdr section. */ + if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) + { + segT saved_seg = now_seg; + subsegT saved_subseg = now_subseg; + valueT dot; + expressionS exp; + char *fragp; - dot = frag_now_fix (); + dot = frag_now_fix (); #ifdef md_flush_pending_output - md_flush_pending_output (); + md_flush_pending_output (); #endif - assert (pdr_seg); - subseg_set (pdr_seg, 0); + assert (pdr_seg); + subseg_set (pdr_seg, 0); - /* Write the symbol. */ - exp.X_op = O_symbol; - exp.X_add_symbol = p; - exp.X_add_number = 0; - emit_expr (&exp, 4); - - fragp = frag_more (7 * 4); - - md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); - md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); - md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); - md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); - md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); - md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); - md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); - - subseg_set (saved_seg, saved_subseg); - } -#endif /* MIPS_STABS_ELF */ + /* Write the symbol. */ + exp.X_op = O_symbol; + exp.X_add_symbol = p; + exp.X_add_number = 0; + emit_expr (&exp, 4); + + fragp = frag_more (7 * 4); + + md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); + md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); + md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); + md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); + md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); + md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); + md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); + + subseg_set (saved_seg, saved_subseg); + } +#endif /* OBJ_ELF */ cur_proc_ptr = NULL; } @@ -13526,6 +13574,10 @@ s_mips_ent (aent) symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; ++numprocs; + + if (debug_type == DEBUG_STABS) + stabs_generate_asm_func (S_GET_NAME (symbolP), + S_GET_NAME (symbolP)); } demand_empty_rest_of_line (); @@ -13541,36 +13593,38 @@ static void s_mips_frame (ignore) int ignore ATTRIBUTE_UNUSED; { -#ifdef MIPS_STABS_ELF +#ifdef OBJ_ELF + if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) + { + long val; - long val; + if (cur_proc_ptr == (procS *) NULL) + { + as_warn (_(".frame outside of .ent")); + demand_empty_rest_of_line (); + return; + } - if (cur_proc_ptr == (procS *) NULL) - { - as_warn (_(".frame outside of .ent")); - demand_empty_rest_of_line (); - return; - } + cur_proc_ptr->frame_reg = tc_get_register (1); - cur_proc_ptr->frame_reg = tc_get_register (1); + SKIP_WHITESPACE (); + if (*input_line_pointer++ != ',' + || get_absolute_expression_and_terminator (&val) != ',') + { + as_warn (_("Bad .frame directive")); + --input_line_pointer; + demand_empty_rest_of_line (); + return; + } + + cur_proc_ptr->frame_offset = val; + cur_proc_ptr->pc_reg = tc_get_register (0); - SKIP_WHITESPACE (); - if (*input_line_pointer++ != ',' - || get_absolute_expression_and_terminator (&val) != ',') - { - as_warn (_("Bad .frame directive")); - --input_line_pointer; demand_empty_rest_of_line (); - return; } - - cur_proc_ptr->frame_offset = val; - cur_proc_ptr->pc_reg = tc_get_register (0); - - demand_empty_rest_of_line (); -#else - s_ignore (ignore); -#endif /* MIPS_STABS_ELF */ + else +#endif /* OBJ_ELF */ + s_ignore (ignore); } /* The .fmask and .mask directives. If the mdebug section is present @@ -13583,41 +13637,44 @@ static void s_mips_mask (reg_type) char reg_type; { -#ifdef MIPS_STABS_ELF - long mask, off; - - if (cur_proc_ptr == (procS *) NULL) +#ifdef OBJ_ELF + if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) { - as_warn (_(".mask/.fmask outside of .ent")); - demand_empty_rest_of_line (); - return; - } + long mask, off; - if (get_absolute_expression_and_terminator (&mask) != ',') - { - as_warn (_("Bad .mask/.fmask directive")); - --input_line_pointer; - demand_empty_rest_of_line (); - return; - } + if (cur_proc_ptr == (procS *) NULL) + { + as_warn (_(".mask/.fmask outside of .ent")); + demand_empty_rest_of_line (); + return; + } - off = get_absolute_expression (); + if (get_absolute_expression_and_terminator (&mask) != ',') + { + as_warn (_("Bad .mask/.fmask directive")); + --input_line_pointer; + demand_empty_rest_of_line (); + return; + } - if (reg_type == 'F') - { - cur_proc_ptr->fpreg_mask = mask; - cur_proc_ptr->fpreg_offset = off; + off = get_absolute_expression (); + + if (reg_type == 'F') + { + cur_proc_ptr->fpreg_mask = mask; + cur_proc_ptr->fpreg_offset = off; + } + else + { + cur_proc_ptr->reg_mask = mask; + cur_proc_ptr->reg_offset = off; + } + + demand_empty_rest_of_line (); } else - { - cur_proc_ptr->reg_mask = mask; - cur_proc_ptr->reg_offset = off; - } - - demand_empty_rest_of_line (); -#else - s_ignore (reg_type); -#endif /* MIPS_STABS_ELF */ +#endif /* OBJ_ELF */ + s_ignore (reg_type); } /* The .loc directive. */ diff -uprN binutils-2.12.90.0.11/gas/config/tc-ppc.c binutils-2.12.90.0.12/gas/config/tc-ppc.c --- binutils-2.12.90.0.11/gas/config/tc-ppc.c Thu May 23 15:10:10 2002 +++ binutils-2.12.90.0.12/gas/config/tc-ppc.c Tue Jun 18 21:41:59 2002 @@ -1120,14 +1120,6 @@ ppc_mach () return ppc_size == PPC_OPCODE_64 ? 620 : 0; } -#ifdef OBJ_XCOFF -int -ppc_subseg_align () -{ - return ppc_xcoff64 ? 3 : 2; -} -#endif - extern char* ppc_target_format () { @@ -2836,7 +2828,7 @@ ppc_change_csect (sym) symbol_set_frag (sym, frag_now); S_SET_VALUE (sym, (valueT) frag_now_fix ()); - symbol_get_tc (sym)->align = (ppc_xcoff64) ? 3 : 2; + symbol_get_tc (sym)->align = 2; symbol_get_tc (sym)->output = 1; symbol_get_tc (sym)->within = sym; diff -uprN binutils-2.12.90.0.11/gas/config/tc-ppc.h binutils-2.12.90.0.12/gas/config/tc-ppc.h --- binutils-2.12.90.0.11/gas/config/tc-ppc.h Thu May 23 15:10:10 2002 +++ binutils-2.12.90.0.12/gas/config/tc-ppc.h Tue Jun 18 21:41:59 2002 @@ -196,10 +196,6 @@ extern int ppc_frob_symbol PARAMS ((symb #define tc_adjust_symtab() ppc_adjust_symtab () extern void ppc_adjust_symtab PARAMS ((void)); -/* Niclas Andersson says this is needed. */ -extern int ppc_subseg_align PARAMS ((void)); -#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) ppc_subseg_align () - /* We also need to copy, in particular, the class of the symbol, over what obj-coff would otherwise have copied. */ #define OBJ_COPY_SYMBOL_ATTRIBUTES(dest,src) \ diff -uprN binutils-2.12.90.0.11/gas/config/tc-sh.c binutils-2.12.90.0.12/gas/config/tc-sh.c --- binutils-2.12.90.0.11/gas/config/tc-sh.c Sat Jun 8 20:44:53 2002 +++ binutils-2.12.90.0.12/gas/config/tc-sh.c Tue Jun 18 21:41:59 2002 @@ -2147,6 +2147,7 @@ assemble_ppi (op_end, opcode) Make sure we encode a defined insn pattern. */ reg_x = 0; reg_y = 0; + reg_n = 0; for (;;) { diff -uprN binutils-2.12.90.0.11/gas/config.in binutils-2.12.90.0.12/gas/config.in --- binutils-2.12.90.0.11/gas/config.in Thu Mar 7 11:52:37 2002 +++ binutils-2.12.90.0.12/gas/config.in Tue Jun 18 21:41:59 2002 @@ -130,9 +130,6 @@ /* Define if you have the header file. */ #undef HAVE_SYS_PARAM_H -/* Define if you have the header file. */ -#undef HAVE_SYS_STAT_H - /* Define if you have the header file. */ #undef HAVE_SYS_TYPES_H @@ -163,9 +160,6 @@ /* Define as 1 if big endian. */ #undef TARGET_BYTES_BIG_ENDIAN -/* Use ELF stabs for MIPS, not ECOFF stabs */ -#undef MIPS_STABS_ELF - /* Default architecture. */ #undef DEFAULT_ARCH diff -uprN binutils-2.12.90.0.11/gas/configure binutils-2.12.90.0.12/gas/configure --- binutils-2.12.90.0.11/gas/configure Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/gas/configure Tue Jun 18 21:41:59 2002 @@ -2314,7 +2314,6 @@ for this_target in $target $canon_target dev=no bfd_gas=no em=generic - mips_stabs_elf= # assign object format case ${generic_target} in @@ -2362,6 +2361,7 @@ for this_target in $target $canon_target fr30-*-*) fmt=elf bfd_gas=yes ;; + frv-*-*) fmt=elf bfd_gas=yes ;; hppa-*-linux-gnu*) case ${cpu} in hppa*64*) @@ -2520,13 +2520,13 @@ EOF mips-*-irix*) fmt=ecoff ;; mips-*-lnews*) fmt=ecoff em=lnews ;; mips-*-riscos*) fmt=ecoff ;; - mips*-*-linux*) fmt=elf em=tmips mips_stabs_elf=y ;; + mips*-*-linux*) fmt=elf em=tmips ;; mips-*-sysv4*MP* | mips-*-gnu*) fmt=elf em=tmips ;; mips-*-sysv*) fmt=ecoff ;; mips-*-elf* | mips-*-rtems* | mips-*-netbsd* | mips-*-openbsd*) fmt=elf ;; - mips-*-vxworks*) fmt=elf mips_stabs_elf=y ;; + mips-*-vxworks*) fmt=elf ;; mmix-*-*) fmt=elf bfd_gas=yes ;; mn10200-*-*) fmt=elf bfd_gas=yes ;; mn10300-*-*) fmt=elf bfd_gas=yes ;; @@ -2675,13 +2675,6 @@ EOF fi fi - if test x${mips_stabs_elf} != x; then - cat >> confdefs.h <<\EOF -#define MIPS_STABS_ELF 1 -EOF - - fi - case ${cpu_type}-${fmt} in alpha*-*) bfd_gas=yes ;; arm-*) bfd_gas=yes ;; @@ -2733,6 +2726,9 @@ EOF using_cgen=yes ;; + frv) + using_cgen=yes + ;; m68k) case ${extra_objects} in *m68k-parse.o*) ;; @@ -3147,7 +3143,7 @@ EOF # Extract the first word of "gcc", so it can be a program name with args. set dummy gcc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3151: checking for $ac_word" >&5 +echo "configure:3147: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3177,7 +3173,7 @@ if test -z "$CC"; then # Extract the first word of "cc", so it can be a program name with args. set dummy cc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3181: checking for $ac_word" >&5 +echo "configure:3177: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3228,7 +3224,7 @@ fi # Extract the first word of "cl", so it can be a program name with args. set dummy cl; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3232: checking for $ac_word" >&5 +echo "configure:3228: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3260,7 +3256,7 @@ fi fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 -echo "configure:3264: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 +echo "configure:3260: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 ac_ext=c # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. @@ -3271,12 +3267,12 @@ cross_compiling=$ac_cv_prog_cc_cross cat > conftest.$ac_ext << EOF -#line 3275 "configure" +#line 3271 "configure" #include "confdefs.h" main(){return(0);} EOF -if { (eval echo configure:3280: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3276: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then ac_cv_prog_cc_works=yes # If we can't run a trivial program, we are probably using a cross compiler. if (./conftest; exit) 2>/dev/null; then @@ -3302,12 +3298,12 @@ if test $ac_cv_prog_cc_works = no; then { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 -echo "configure:3306: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "configure:3302: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 cross_compiling=$ac_cv_prog_cc_cross echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 -echo "configure:3311: checking whether we are using GNU C" >&5 +echo "configure:3307: checking whether we are using GNU C" >&5 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3316,7 +3312,7 @@ else yes; #endif EOF -if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:3320: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then +if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:3316: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then ac_cv_prog_gcc=yes else ac_cv_prog_gcc=no @@ -3335,7 +3331,7 @@ ac_test_CFLAGS="${CFLAGS+set}" ac_save_CFLAGS="$CFLAGS" CFLAGS= echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 -echo "configure:3339: checking whether ${CC-cc} accepts -g" >&5 +echo "configure:3335: checking whether ${CC-cc} accepts -g" >&5 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3372,7 +3368,7 @@ do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3376: checking for $ac_word" >&5 +echo "configure:3372: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_YACC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3403,7 +3399,7 @@ done test -n "$YACC" || YACC="yacc" echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 -echo "configure:3407: checking how to run the C preprocessor" >&5 +echo "configure:3403: checking how to run the C preprocessor" >&5 # On Suns, sometimes $CPP names a directory. if test -n "$CPP" && test -d "$CPP"; then CPP= @@ -3418,13 +3414,13 @@ else # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. cat > conftest.$ac_ext < Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3428: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3424: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -3435,13 +3431,13 @@ else rm -rf conftest* CPP="${CC-cc} -E -traditional-cpp" cat > conftest.$ac_ext < Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3445: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3441: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -3452,13 +3448,13 @@ else rm -rf conftest* CPP="${CC-cc} -nologo -E" cat > conftest.$ac_ext < Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3462: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3458: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -3488,7 +3484,7 @@ do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3492: checking for $ac_word" >&5 +echo "configure:3488: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_LEX'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3521,7 +3517,7 @@ test -n "$LEX" || LEX="$missing_dir/miss # Extract the first word of "flex", so it can be a program name with args. set dummy flex; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3525: checking for $ac_word" >&5 +echo "configure:3521: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_LEX'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3555,7 +3551,7 @@ then *) ac_lib=l ;; esac echo $ac_n "checking for yywrap in -l$ac_lib""... $ac_c" 1>&6 -echo "configure:3559: checking for yywrap in -l$ac_lib" >&5 +echo "configure:3555: checking for yywrap in -l$ac_lib" >&5 ac_lib_var=`echo $ac_lib'_'yywrap | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -3563,7 +3559,7 @@ else ac_save_LIBS="$LIBS" LIBS="-l$ac_lib $LIBS" cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3574: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -3597,7 +3593,7 @@ fi fi echo $ac_n "checking lex output file root""... $ac_c" 1>&6 -echo "configure:3601: checking lex output file root" >&5 +echo "configure:3597: checking lex output file root" >&5 if eval "test \"`echo '$''{'ac_cv_prog_lex_root'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3618,7 +3614,7 @@ echo "$ac_t""$ac_cv_prog_lex_root" 1>&6 LEX_OUTPUT_ROOT=$ac_cv_prog_lex_root echo $ac_n "checking whether yytext is a pointer""... $ac_c" 1>&6 -echo "configure:3622: checking whether yytext is a pointer" >&5 +echo "configure:3618: checking whether yytext is a pointer" >&5 if eval "test \"`echo '$''{'ac_cv_prog_lex_yytext_pointer'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3630,14 +3626,14 @@ echo 'extern char *yytext;' >>$LEX_OUTPU ac_save_LIBS="$LIBS" LIBS="$LIBS $LEXLIB" cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3637: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* ac_cv_prog_lex_yytext_pointer=yes else @@ -3663,7 +3659,7 @@ ALL_LINGUAS="fr tr es" # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3667: checking for $ac_word" >&5 +echo "configure:3663: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3691,12 +3687,12 @@ else fi echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6 -echo "configure:3695: checking for ANSI C header files" >&5 +echo "configure:3691: checking for ANSI C header files" >&5 if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < #include @@ -3704,7 +3700,7 @@ else #include EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3708: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3704: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3721,7 +3717,7 @@ rm -f conftest* if test $ac_cv_header_stdc = yes; then # SunOS 4.x string.h does not declare mem*, contrary to ANSI. cat > conftest.$ac_ext < EOF @@ -3739,7 +3735,7 @@ fi if test $ac_cv_header_stdc = yes; then # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. cat > conftest.$ac_ext < EOF @@ -3760,7 +3756,7 @@ if test "$cross_compiling" = yes; then : else cat > conftest.$ac_ext < #define ISLOWER(c) ('a' <= (c) && (c) <= 'z') @@ -3771,7 +3767,7 @@ if (XOR (islower (i), ISLOWER (i)) || to exit (0); } EOF -if { (eval echo configure:3775: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:3771: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then : else @@ -3795,12 +3791,12 @@ EOF fi echo $ac_n "checking for working const""... $ac_c" 1>&6 -echo "configure:3799: checking for working const" >&5 +echo "configure:3795: checking for working const" >&5 if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:3849: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_c_const=yes else @@ -3870,21 +3866,21 @@ EOF fi echo $ac_n "checking for inline""... $ac_c" 1>&6 -echo "configure:3874: checking for inline" >&5 +echo "configure:3870: checking for inline" >&5 if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else ac_cv_c_inline=no for ac_kw in inline __inline__ __inline; do cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:3884: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_c_inline=$ac_kw; break else @@ -3910,12 +3906,12 @@ EOF esac echo $ac_n "checking for off_t""... $ac_c" 1>&6 -echo "configure:3914: checking for off_t" >&5 +echo "configure:3910: checking for off_t" >&5 if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < #if STDC_HEADERS @@ -3943,12 +3939,12 @@ EOF fi echo $ac_n "checking for size_t""... $ac_c" 1>&6 -echo "configure:3947: checking for size_t" >&5 +echo "configure:3943: checking for size_t" >&5 if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < #if STDC_HEADERS @@ -3978,19 +3974,19 @@ fi # The Ultrix 4.2 mips builtin alloca declared by alloca.h only works # for constant arguments. Useless! echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6 -echo "configure:3982: checking for working alloca.h" >&5 +echo "configure:3978: checking for working alloca.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < int main() { char *p = alloca(2 * sizeof(int)); ; return 0; } EOF -if { (eval echo configure:3994: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3990: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* ac_cv_header_alloca_h=yes else @@ -4011,12 +4007,12 @@ EOF fi echo $ac_n "checking for alloca""... $ac_c" 1>&6 -echo "configure:4015: checking for alloca" >&5 +echo "configure:4011: checking for alloca" >&5 if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4044: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* ac_cv_func_alloca_works=yes else @@ -4076,12 +4072,12 @@ EOF echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6 -echo "configure:4080: checking whether alloca needs Cray hooks" >&5 +echo "configure:4076: checking whether alloca needs Cray hooks" >&5 if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&6 if test $ac_cv_os_cray = yes; then for ac_func in _getb67 GETB67 getb67; do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:4110: checking for $ac_func" >&5 +echo "configure:4106: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4134: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -4161,7 +4157,7 @@ done fi echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6 -echo "configure:4165: checking stack direction for C alloca" >&5 +echo "configure:4161: checking stack direction for C alloca" >&5 if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4169,7 +4165,7 @@ else ac_cv_c_stack_direction=0 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:4188: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_c_stack_direction=1 else @@ -4213,17 +4209,17 @@ for ac_hdr in unistd.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:4217: checking for $ac_hdr" >&5 +echo "configure:4213: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4227: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4223: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4252,12 +4248,12 @@ done for ac_func in getpagesize do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:4256: checking for $ac_func" >&5 +echo "configure:4252: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4280: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -4305,7 +4301,7 @@ fi done echo $ac_n "checking for working mmap""... $ac_c" 1>&6 -echo "configure:4309: checking for working mmap" >&5 +echo "configure:4305: checking for working mmap" >&5 if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4313,7 +4309,7 @@ else ac_cv_func_mmap_fixed_mapped=no else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:4453: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_func_mmap_fixed_mapped=yes else @@ -4481,17 +4477,17 @@ unistd.h values.h sys/param.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:4485: checking for $ac_hdr" >&5 +echo "configure:4481: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4495: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4491: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4521,12 +4517,12 @@ done __argz_count __argz_stringify __argz_next do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:4525: checking for $ac_func" >&5 +echo "configure:4521: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4549: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -4578,12 +4574,12 @@ done for ac_func in stpcpy do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:4582: checking for $ac_func" >&5 +echo "configure:4578: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4606: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -4640,19 +4636,19 @@ EOF if test $ac_cv_header_locale_h = yes; then echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6 -echo "configure:4644: checking for LC_MESSAGES" >&5 +echo "configure:4640: checking for LC_MESSAGES" >&5 if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < int main() { return LC_MESSAGES ; return 0; } EOF -if { (eval echo configure:4656: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4652: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* am_cv_val_LC_MESSAGES=yes else @@ -4673,7 +4669,7 @@ EOF fi fi echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6 -echo "configure:4677: checking whether NLS is requested" >&5 +echo "configure:4673: checking whether NLS is requested" >&5 # Check whether --enable-nls or --disable-nls was given. if test "${enable_nls+set}" = set; then enableval="$enable_nls" @@ -4693,7 +4689,7 @@ fi EOF echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6 -echo "configure:4697: checking whether included gettext is requested" >&5 +echo "configure:4693: checking whether included gettext is requested" >&5 # Check whether --with-included-gettext or --without-included-gettext was given. if test "${with_included_gettext+set}" = set; then withval="$with_included_gettext" @@ -4712,17 +4708,17 @@ fi ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for libintl.h""... $ac_c" 1>&6 -echo "configure:4716: checking for libintl.h" >&5 +echo "configure:4712: checking for libintl.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4726: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4722: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4739,19 +4735,19 @@ fi if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6 -echo "configure:4743: checking for gettext in libc" >&5 +echo "configure:4739: checking for gettext in libc" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:4755: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4751: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libc=yes else @@ -4767,7 +4763,7 @@ echo "$ac_t""$gt_cv_func_gettext_libc" 1 if test "$gt_cv_func_gettext_libc" != "yes"; then echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6 -echo "configure:4771: checking for bindtextdomain in -lintl" >&5 +echo "configure:4767: checking for bindtextdomain in -lintl" >&5 ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -4775,7 +4771,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lintl $LIBS" cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4786: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -4802,19 +4798,19 @@ fi if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6 -echo "configure:4806: checking for gettext in libintl" >&5 +echo "configure:4802: checking for gettext in libintl" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4814: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libintl=yes else @@ -4842,7 +4838,7 @@ EOF # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4846: checking for $ac_word" >&5 +echo "configure:4842: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4876,12 +4872,12 @@ fi for ac_func in dcgettext do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:4880: checking for $ac_func" >&5 +echo "configure:4876: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4904: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -4931,7 +4927,7 @@ done # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4935: checking for $ac_word" >&5 +echo "configure:4931: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4967,7 +4963,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4971: checking for $ac_word" >&5 +echo "configure:4967: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4999,7 +4995,7 @@ else fi cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5007: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* CATOBJEXT=.gmo DATADIRNAME=share @@ -5039,7 +5035,7 @@ fi # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:5043: checking for $ac_word" >&5 +echo "configure:5039: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -5073,7 +5069,7 @@ fi # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:5077: checking for $ac_word" >&5 +echo "configure:5073: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -5109,7 +5105,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:5113: checking for $ac_word" >&5 +echo "configure:5109: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -5199,7 +5195,7 @@ fi LINGUAS= else echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6 -echo "configure:5203: checking for catalogs to be installed" >&5 +echo "configure:5199: checking for catalogs to be installed" >&5 NEW_LINGUAS= for lang in ${LINGUAS=$ALL_LINGUAS}; do case "$ALL_LINGUAS" in @@ -5227,17 +5223,17 @@ echo "configure:5203: checking for catal if test "$CATOBJEXT" = ".cat"; then ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6 -echo "configure:5231: checking for linux/version.h" >&5 +echo "configure:5227: checking for linux/version.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:5241: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:5237: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -5300,7 +5296,7 @@ fi echo $ac_n "checking whether to enable maintainer-specific portions of Makefiles""... $ac_c" 1>&6 -echo "configure:5304: checking whether to enable maintainer-specific portions of Makefiles" >&5 +echo "configure:5300: checking whether to enable maintainer-specific portions of Makefiles" >&5 # Check whether --enable-maintainer-mode or --disable-maintainer-mode was given. if test "${enable_maintainer_mode+set}" = set; then enableval="$enable_maintainer_mode" @@ -5325,7 +5321,7 @@ fi echo $ac_n "checking for executable suffix""... $ac_c" 1>&6 -echo "configure:5329: checking for executable suffix" >&5 +echo "configure:5325: checking for executable suffix" >&5 if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -5335,7 +5331,7 @@ else rm -f conftest* echo 'int main () { return 0; }' > conftest.$ac_ext ac_cv_exeext= - if { (eval echo configure:5339: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then + if { (eval echo configure:5335: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then for file in conftest.*; do case $file in *.c | *.o | *.obj) ;; @@ -5360,17 +5356,17 @@ for ac_hdr in string.h stdlib.h memory.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:5364: checking for $ac_hdr" >&5 +echo "configure:5360: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:5374: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:5370: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -5400,7 +5396,7 @@ done # Put this here so that autoconf's "cross-compiling" message doesn't confuse # people who are not cross-compiling but are compiling cross-assemblers. echo $ac_n "checking whether compiling a cross-assembler""... $ac_c" 1>&6 -echo "configure:5404: checking whether compiling a cross-assembler" >&5 +echo "configure:5400: checking whether compiling a cross-assembler" >&5 if test "${host}" = "${target}"; then cross_gas=no else @@ -5415,19 +5411,19 @@ echo "$ac_t""$cross_gas" 1>&6 # The Ultrix 4.2 mips builtin alloca declared by alloca.h only works # for constant arguments. Useless! echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6 -echo "configure:5419: checking for working alloca.h" >&5 +echo "configure:5415: checking for working alloca.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < int main() { char *p = alloca(2 * sizeof(int)); ; return 0; } EOF -if { (eval echo configure:5431: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5427: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* ac_cv_header_alloca_h=yes else @@ -5448,12 +5444,12 @@ EOF fi echo $ac_n "checking for alloca""... $ac_c" 1>&6 -echo "configure:5452: checking for alloca" >&5 +echo "configure:5448: checking for alloca" >&5 if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5481: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* ac_cv_func_alloca_works=yes else @@ -5513,12 +5509,12 @@ EOF echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6 -echo "configure:5517: checking whether alloca needs Cray hooks" >&5 +echo "configure:5513: checking whether alloca needs Cray hooks" >&5 if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&6 if test $ac_cv_os_cray = yes; then for ac_func in _getb67 GETB67 getb67; do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:5547: checking for $ac_func" >&5 +echo "configure:5543: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5571: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -5598,7 +5594,7 @@ done fi echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6 -echo "configure:5602: checking stack direction for C alloca" >&5 +echo "configure:5598: checking stack direction for C alloca" >&5 if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -5606,7 +5602,7 @@ else ac_cv_c_stack_direction=0 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:5625: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_c_stack_direction=1 else @@ -5647,21 +5643,21 @@ EOF fi echo $ac_n "checking for inline""... $ac_c" 1>&6 -echo "configure:5651: checking for inline" >&5 +echo "configure:5647: checking for inline" >&5 if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else ac_cv_c_inline=no for ac_kw in inline __inline__ __inline; do cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5661: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_c_inline=$ac_kw; break else @@ -5691,12 +5687,12 @@ esac for ac_func in unlink remove do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:5695: checking for $ac_func" >&5 +echo "configure:5691: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5719: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -5748,12 +5744,12 @@ done for ac_func in sbrk do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:5752: checking for $ac_func" >&5 +echo "configure:5748: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5776: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -5811,7 +5807,7 @@ case $host in ;; *-ncr-sysv4.3*) echo $ac_n "checking for _mwvalidcheckl in -lmw""... $ac_c" 1>&6 -echo "configure:5815: checking for _mwvalidcheckl in -lmw" >&5 +echo "configure:5811: checking for _mwvalidcheckl in -lmw" >&5 ac_lib_var=`echo mw'_'_mwvalidcheckl | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -5819,7 +5815,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lmw $LIBS" cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5830: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -5851,7 +5847,7 @@ else fi echo $ac_n "checking for main in -lm""... $ac_c" 1>&6 -echo "configure:5855: checking for main in -lm" >&5 +echo "configure:5851: checking for main in -lm" >&5 ac_lib_var=`echo m'_'main | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -5859,14 +5855,14 @@ else ac_save_LIBS="$LIBS" LIBS="-lm $LIBS" cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5866: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -5889,7 +5885,7 @@ fi ;; *) echo $ac_n "checking for main in -lm""... $ac_c" 1>&6 -echo "configure:5893: checking for main in -lm" >&5 +echo "configure:5889: checking for main in -lm" >&5 ac_lib_var=`echo m'_'main | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -5897,14 +5893,14 @@ else ac_save_LIBS="$LIBS" LIBS="-lm $LIBS" cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5904: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -5935,12 +5931,12 @@ esac # enough, but on some of those systems, the assert macro relies on requoting # working properly! echo $ac_n "checking for working assert macro""... $ac_c" 1>&6 -echo "configure:5939: checking for working assert macro" >&5 +echo "configure:5935: checking for working assert macro" >&5 if eval "test \"`echo '$''{'gas_cv_assert_ok'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < #include @@ -5956,7 +5952,7 @@ assert (a == b ; return 0; } EOF -if { (eval echo configure:5960: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5956: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gas_cv_assert_ok=yes else @@ -5997,12 +5993,12 @@ gas_test_headers=" " echo $ac_n "checking whether declaration is required for strstr""... $ac_c" 1>&6 -echo "configure:6001: checking whether declaration is required for strstr" >&5 +echo "configure:5997: checking whether declaration is required for strstr" >&5 if eval "test \"`echo '$''{'gas_cv_decl_needed_strstr'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:6013: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gas_cv_decl_needed_strstr=no else @@ -6034,12 +6030,12 @@ fi echo $ac_n "checking whether declaration is required for malloc""... $ac_c" 1>&6 -echo "configure:6038: checking whether declaration is required for malloc" >&5 +echo "configure:6034: checking whether declaration is required for malloc" >&5 if eval "test \"`echo '$''{'gas_cv_decl_needed_malloc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:6050: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gas_cv_decl_needed_malloc=no else @@ -6071,12 +6067,12 @@ fi echo $ac_n "checking whether declaration is required for free""... $ac_c" 1>&6 -echo "configure:6075: checking whether declaration is required for free" >&5 +echo "configure:6071: checking whether declaration is required for free" >&5 if eval "test \"`echo '$''{'gas_cv_decl_needed_free'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:6087: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gas_cv_decl_needed_free=no else @@ -6108,12 +6104,12 @@ fi echo $ac_n "checking whether declaration is required for sbrk""... $ac_c" 1>&6 -echo "configure:6112: checking whether declaration is required for sbrk" >&5 +echo "configure:6108: checking whether declaration is required for sbrk" >&5 if eval "test \"`echo '$''{'gas_cv_decl_needed_sbrk'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:6124: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gas_cv_decl_needed_sbrk=no else @@ -6145,12 +6141,12 @@ fi echo $ac_n "checking whether declaration is required for environ""... $ac_c" 1>&6 -echo "configure:6149: checking whether declaration is required for environ" >&5 +echo "configure:6145: checking whether declaration is required for environ" >&5 if eval "test \"`echo '$''{'gas_cv_decl_needed_environ'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:6161: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gas_cv_decl_needed_environ=no else @@ -6185,12 +6181,12 @@ fi # for it? echo $ac_n "checking whether declaration is required for errno""... $ac_c" 1>&6 -echo "configure:6189: checking whether declaration is required for errno" >&5 +echo "configure:6185: checking whether declaration is required for errno" >&5 if eval "test \"`echo '$''{'gas_cv_decl_needed_errno'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:6205: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gas_cv_decl_needed_errno=no else diff -uprN binutils-2.12.90.0.11/gas/configure.in binutils-2.12.90.0.12/gas/configure.in --- binutils-2.12.90.0.11/gas/configure.in Sat Jun 8 20:44:52 2002 +++ binutils-2.12.90.0.12/gas/configure.in Tue Jun 18 21:41:59 2002 @@ -170,7 +170,6 @@ changequote([,])dnl dev=no bfd_gas=no em=generic - mips_stabs_elf= # assign object format case ${generic_target} in @@ -218,6 +217,7 @@ changequote([,])dnl fr30-*-*) fmt=elf bfd_gas=yes ;; + frv-*-*) fmt=elf bfd_gas=yes ;; hppa-*-linux-gnu*) case ${cpu} in hppa*64*) @@ -373,13 +373,13 @@ changequote([,])dnl mips-*-irix*) fmt=ecoff ;; mips-*-lnews*) fmt=ecoff em=lnews ;; mips-*-riscos*) fmt=ecoff ;; - mips*-*-linux*) fmt=elf em=tmips mips_stabs_elf=y ;; + mips*-*-linux*) fmt=elf em=tmips ;; mips-*-sysv4*MP* | mips-*-gnu*) fmt=elf em=tmips ;; mips-*-sysv*) fmt=ecoff ;; mips-*-elf* | mips-*-rtems* | mips-*-netbsd* | mips-*-openbsd*) fmt=elf ;; - mips-*-vxworks*) fmt=elf mips_stabs_elf=y ;; + mips-*-vxworks*) fmt=elf ;; mmix-*-*) fmt=elf bfd_gas=yes ;; mn10200-*-*) fmt=elf bfd_gas=yes ;; mn10300-*-*) fmt=elf bfd_gas=yes ;; @@ -524,11 +524,6 @@ changequote([,])dnl fi fi - if test x${mips_stabs_elf} != x; then - AC_DEFINE(MIPS_STABS_ELF, 1, - [Use ELF stabs for MIPS, not ECOFF stabs]) - fi - case ${cpu_type}-${fmt} in alpha*-*) bfd_gas=yes ;; arm-*) bfd_gas=yes ;; @@ -580,6 +575,9 @@ changequote([,])dnl using_cgen=yes ;; + frv) + using_cgen=yes + ;; m68k) case ${extra_objects} in *m68k-parse.o*) ;; diff -uprN binutils-2.12.90.0.11/gas/doc/as.texinfo binutils-2.12.90.0.12/gas/doc/as.texinfo --- binutils-2.12.90.0.11/gas/doc/as.texinfo Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/gas/doc/as.texinfo Tue Jun 18 21:41:59 2002 @@ -382,6 +382,7 @@ gcc(1), ld(1), and the Info entries for [@b{-mips16}] [@b{-no-mips16}] [@b{-mips3d}] [@b{-no-mips3d}] [@b{-mdmx}] [@b{-no-mdmx}] + [@b{-mdebug}] [@b{-no-mdebug}] @end ifset @ifset MMIX @@ -892,6 +893,11 @@ Schedule and tune for a particular @sc{m Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. +@item -mdebug +@itemx -no-mdebug +Cause stabs-style debugging output to go into an ECOFF-style .mdebug +section instead of the standard ELF .stabs sections. + @item -mgp32 @itemx -mfp32 The register sizes are normally inferred from the ISA and ABI, but these diff -uprN binutils-2.12.90.0.11/gas/dwarf2dbg.c binutils-2.12.90.0.12/gas/dwarf2dbg.c --- binutils-2.12.90.0.11/gas/dwarf2dbg.c Thu May 23 15:10:10 2002 +++ binutils-2.12.90.0.12/gas/dwarf2dbg.c Tue Jun 18 21:41:59 2002 @@ -344,9 +344,13 @@ get_filenum (filename) return i; } -/* Handle the .file directive. */ +/* Handle two forms of .file directive: + - Pass .file "source.c" to s_app_file + - Handle .file 1 "source.c" by adding an entry to the DWARF-2 file table -void + If an entry is added to the file table, return a pointer to the filename. */ + +char * dwarf2_directive_file (dummy) int dummy ATTRIBUTE_UNUSED; { @@ -359,7 +363,7 @@ dwarf2_directive_file (dummy) if (*input_line_pointer == '"') { s_app_file (0); - return; + return NULL; } num = get_absolute_expression (); @@ -369,13 +373,13 @@ dwarf2_directive_file (dummy) if (num < 1) { as_bad (_("file number less than one")); - return; + return NULL; } if (num < (int) files_in_use && files[num].filename != 0) { as_bad (_("file number %ld already allocated"), (long) num); - return; + return NULL; } if (num >= (int) files_allocated) @@ -393,6 +397,8 @@ dwarf2_directive_file (dummy) files[num].filename = filename; files[num].dir = 0; files_in_use = num + 1; + + return filename; } void @@ -1242,8 +1248,11 @@ dwarf2_finish () segT line_seg; struct line_seg *s; - /* If no debug information was recorded, nothing to do. */ - if (all_segs == NULL && files_in_use <= 1) + /* If no debug information was recorded, nothing to do. Don't + emit dwarf debug info for one ".file" directive only unless + we are generating DWARF2 debugging info. */ + if (debug_type != DEBUG_DWARF2 && all_segs == NULL + && files_in_use <= 2) return; /* Calculate the size of an address for the target machine. */ diff -uprN binutils-2.12.90.0.11/gas/dwarf2dbg.h binutils-2.12.90.0.12/gas/dwarf2dbg.h --- binutils-2.12.90.0.11/gas/dwarf2dbg.h Fri Mar 9 11:16:40 2001 +++ binutils-2.12.90.0.12/gas/dwarf2dbg.h Tue Jun 18 21:41:59 2002 @@ -36,7 +36,7 @@ struct dwarf2_line_info { /* Implements the .file FILENO "FILENAME" directive. FILENO can be 0 to indicate that no file number has been assigned. All real file number must be >0. */ -extern void dwarf2_directive_file PARAMS ((int dummy)); +extern char *dwarf2_directive_file PARAMS ((int dummy)); /* Implements the .loc FILENO LINENO [COLUMN] directive. FILENO is the file number, LINENO the line number and the (optional) COLUMN diff -uprN binutils-2.12.90.0.11/gas/po/POTFILES.in binutils-2.12.90.0.12/gas/po/POTFILES.in --- binutils-2.12.90.0.11/gas/po/POTFILES.in Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/gas/po/POTFILES.in Tue Jun 18 21:41:59 2002 @@ -60,6 +60,8 @@ config/tc-dlx.c config/tc-dlx.h config/tc-fr30.c config/tc-fr30.h +config/tc-frv.c +config/tc-frv.h config/tc-h8300.c config/tc-h8300.h config/tc-h8500.c diff -uprN binutils-2.12.90.0.11/gas/read.c binutils-2.12.90.0.12/gas/read.c --- binutils-2.12.90.0.11/gas/read.c Thu May 23 15:10:10 2002 +++ binutils-2.12.90.0.12/gas/read.c Tue Jun 18 21:41:59 2002 @@ -1572,6 +1572,20 @@ s_data (ignore) .file. */ void +s_app_file_string (file) + char *file; +{ +#ifdef LISTING + if (listing) + listing_source_file (file); +#endif + register_dependency (file); +#ifdef obj_app_file + obj_app_file (file); +#endif +} + +void s_app_file (appfile) int appfile; { @@ -1596,16 +1610,7 @@ s_app_file (appfile) demand_empty_rest_of_line (); if (!may_omit) - { -#ifdef LISTING - if (listing) - listing_source_file (s); -#endif - register_dependency (s); -#ifdef obj_app_file - obj_app_file (s); -#endif - } + s_app_file_string (s); } } diff -uprN binutils-2.12.90.0.11/gas/read.h binutils-2.12.90.0.12/gas/read.h --- binutils-2.12.90.0.11/gas/read.h Mon Oct 15 21:27:23 2001 +++ binutils-2.12.90.0.12/gas/read.h Tue Jun 18 21:41:59 2002 @@ -137,6 +137,7 @@ extern void generate_lineno_debug PARAMS extern void s_abort PARAMS ((int)) ATTRIBUTE_NORETURN; extern void s_align_bytes PARAMS ((int arg)); extern void s_align_ptwo PARAMS ((int)); +extern void s_app_file_string PARAMS ((char *)); extern void s_app_file PARAMS ((int)); extern void s_app_line PARAMS ((int)); extern void s_bad_endr PARAMS ((int)); diff -uprN binutils-2.12.90.0.11/gas/subsegs.c binutils-2.12.90.0.12/gas/subsegs.c --- binutils-2.12.90.0.11/gas/subsegs.c Fri Oct 5 14:11:21 2001 +++ binutils-2.12.90.0.12/gas/subsegs.c Tue Jun 18 21:41:59 2002 @@ -652,7 +652,7 @@ subsegs_print_statistics (file) count++; } fprintf (file, "\n"); - fprintf (file, "\t%p %-10s\t%10d frags\n", frchp, + fprintf (file, "\t%p %-10s\t%10d frags\n", (void *) frchp, segment_name (frchp->frch_seg), count); } } diff -uprN binutils-2.12.90.0.11/gas/symbols.c binutils-2.12.90.0.12/gas/symbols.c --- binutils-2.12.90.0.11/gas/symbols.c Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/gas/symbols.c Tue Jun 18 21:41:59 2002 @@ -839,7 +839,7 @@ resolve_symbol_value (symp) symbolS *symp; { int resolved; - valueT final_val; + valueT final_val = 0; segT final_seg; #ifdef BFD_ASSEMBLER diff -uprN binutils-2.12.90.0.11/gas/testsuite/ChangeLog binutils-2.12.90.0.12/gas/testsuite/ChangeLog --- binutils-2.12.90.0.11/gas/testsuite/ChangeLog Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/gas/testsuite/ChangeLog Tue Jun 18 21:41:59 2002 @@ -1,3 +1,26 @@ +2002-06-18 Dave Brolley + + * gas/frv: New testsuite. + +Mon Jun 17 16:23:59 2002 J"orn Rennecke + + * gas/sh/dsp.s: Add three more instructions. + * gas/sh/dsp.d: Update. + +2002-06-14 Daniel Jacobowitz + + * gas/mips/lineno.d: Use --gstabs. + * gas/mips/mips.exp (lineno.s): Remove XFAIL. + +2002-06-12 Tom Rix + + * gas/ppc/aix.exp: Run tests for all versions of powerpc AIX. Add + text alignment tests. + * gas/ppc/textalign-xcoff-001.d: New Test. + * gas/ppc/textalign-xcoff-002.d: New Test. + * gas/ppc/test1xcoff32.d : Change text section alignment. + * gas/ppc/booke_xcoff.d: Remove invalid pad. + 2002-06-06 John David Anglin * gas/hppa/basic/add.s: Set code level to 1.1. diff -uprN binutils-2.12.90.0.11/gas/testsuite/gas/frv/allinsn.d binutils-2.12.90.0.12/gas/testsuite/gas/frv/allinsn.d --- binutils-2.12.90.0.11/gas/testsuite/gas/frv/allinsn.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/gas/testsuite/gas/frv/allinsn.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,1660 @@ +#as: +#objdump: -dr +#name: + +.*: +file format .* + +Disassembly of section .text: + +00000000 : + 0: 82 00 10 01 add sp,sp,sp + +00000004 : + 4: 82 00 11 01 sub sp,sp,sp + +00000008 : + 8: 82 00 13 c1 udiv sp,sp,sp + +0000000c : + c: 82 04 10 01 and sp,sp,sp + +00000010 : + 10: 82 04 10 81 or sp,sp,sp + +00000014 : + 14: 82 04 11 01 xor sp,sp,sp + +00000018 : + 18: 82 04 01 81 not sp,sp + +0000001c : + 1c: 82 00 13 81 sdiv sp,sp,sp + +00000020 : + 20: 82 04 13 81 nsdiv sp,sp,sp + +00000024 : + 24: 82 04 13 c1 nudiv sp,sp,sp + +00000028 : + 28: 82 00 12 01 smul sp,sp,sp + +0000002c : + 2c: 82 00 12 81 umul sp,sp,sp + +00000030 : + 30: 82 04 12 01 sll sp,sp,sp + +00000034 : + 34: 82 04 12 81 srl sp,sp,sp + +00000038 : + 38: 82 04 13 01 sra sp,sp,sp + +0000003c : + 3c: 82 2c 10 01 scan sp,sp,sp + +00000040 : + 40: 83 60 10 01 cadd sp,sp,sp,cc0,0x0 + +00000044 : + 44: 83 60 10 41 csub sp,sp,sp,cc0,0x0 + +00000048 : + 48: 83 64 10 c1 cudiv sp,sp,sp,cc0,0x0 + +0000004c : + 4c: 83 68 10 01 cand sp,sp,sp,cc0,0x0 + +00000050 : + 50: 83 68 10 41 cor sp,sp,sp,cc0,0x0 + +00000054 : + 54: 83 68 10 81 cxor sp,sp,sp,cc0,0x0 + +00000058 : + 58: 83 68 00 c1 cnot sp,sp,cc0,0x0 + +0000005c : + 5c: 83 60 10 81 csmul sp,sp,sp,cc0,0x0 + +00000060 : + 60: 83 60 10 c1 csdiv sp,sp,sp,cc0,0x0 + +00000064 : + 64: 83 70 10 01 csll sp,sp,sp,cc0,0x0 + +00000068 : + 68: 83 70 10 41 csrl sp,sp,sp,cc0,0x0 + +0000006c : + 6c: 83 70 10 81 csra sp,sp,sp,cc0,0x0 + +00000070 : + 70: 83 94 10 c1 cscan sp,sp,sp,cc0,0x0 + +00000074 : + 74: 82 00 10 41 addcc sp,sp,sp,icc0 + +00000078 : + 78: 82 00 11 41 subcc sp,sp,sp,icc0 + +0000007c : + 7c: 82 04 10 41 andcc sp,sp,sp,icc0 + +00000080 : + 80: 82 04 10 c1 orcc sp,sp,sp,icc0 + +00000084 : + 84: 82 04 11 41 xorcc sp,sp,sp,icc0 + +00000088 : + 88: 82 04 12 41 sllcc sp,sp,sp,icc0 + +0000008c : + 8c: 82 04 12 c1 srlcc sp,sp,sp,icc0 + +00000090 : + 90: 82 04 13 41 sracc sp,sp,sp,icc0 + +00000094 : + 94: 82 00 12 41 smulcc sp,sp,sp,icc0 + +00000098 : + 98: 82 00 12 c1 umulcc sp,sp,sp,icc0 + +0000009c : + 9c: 83 64 10 01 caddcc sp,sp,sp,cc0,0x0 + +000000a0 : + a0: 83 64 10 41 csubcc sp,sp,sp,cc0,0x0 + +000000a4 : + a4: 83 64 10 81 csmulcc sp,sp,sp,cc0,0x0 + +000000a8 : + a8: 83 6c 10 01 candcc sp,sp,sp,cc0,0x0 + +000000ac : + ac: 83 6c 10 41 corcc sp,sp,sp,cc0,0x0 + +000000b0 : + b0: 83 6c 10 81 cxorcc sp,sp,sp,cc0,0x0 + +000000b4 : + b4: 83 74 10 01 csllcc sp,sp,sp,cc0,0x0 + +000000b8 : + b8: 83 74 10 41 csrlcc sp,sp,sp,cc0,0x0 + +000000bc : + bc: 83 74 10 81 csracc sp,sp,sp,cc0,0x0 + +000000c0 : + c0: 82 00 10 81 addx sp,sp,sp,icc0 + +000000c4 : + c4: 82 00 11 81 subx sp,sp,sp,icc0 + +000000c8 : + c8: 82 00 10 c1 addxcc sp,sp,sp,icc0 + +000000cc : + cc: 82 00 11 c1 subxcc sp,sp,sp,icc0 + +000000d0 : + d0: 82 40 10 00 addi sp,0,sp + +000000d4 : + d4: 82 50 10 00 subi sp,0,sp + +000000d8 : + d8: 82 7c 10 00 udivi sp,0,sp + +000000dc : + dc: 82 80 10 00 andi sp,0,sp + +000000e0 : + e0: 82 88 10 00 ori sp,0,sp + +000000e4 : + e4: 82 90 10 00 xori sp,0,sp + +000000e8 : + e8: 82 78 10 00 sdivi sp,0,sp + +000000ec : + ec: 82 b8 10 00 nsdivi sp,0,sp + +000000f0 : + f0: 82 bc 10 00 nudivi sp,0,sp + +000000f4 : + f4: 82 60 10 00 smuli sp,0,sp + +000000f8 : + f8: 82 68 10 00 umuli sp,0,sp + +000000fc : + fc: 82 a0 10 00 slli sp,0,sp + +00000100 : + 100: 82 a8 10 00 srli sp,0,sp + +00000104 : + 104: 82 b0 10 00 srai sp,0,sp + +00000108 : + 108: 83 1c 10 00 scani sp,0,sp + +0000010c : + 10c: 82 44 10 00 addicc sp,0,sp,icc0 + +00000110 : + 110: 82 54 10 00 subicc sp,0,sp,icc0 + +00000114 : + 114: 82 84 10 00 andicc sp,0,sp,icc0 + +00000118 : + 118: 82 8c 10 00 oricc sp,0,sp,icc0 + +0000011c : + 11c: 82 94 10 00 xoricc sp,0,sp,icc0 + +00000120 : + 120: 82 64 10 00 smulicc sp,0,sp,icc0 + +00000124 : + 124: 82 6c 10 00 umulicc sp,0,sp,icc0 + +00000128 : + 128: 82 a4 10 00 sllicc sp,0,sp,icc0 + +0000012c : + 12c: 82 ac 10 00 srlicc sp,0,sp,icc0 + +00000130 : + 130: 82 b4 10 00 sraicc sp,0,sp,icc0 + +00000134 : + 134: 82 48 10 00 addxi sp,0,sp,icc0 + +00000138 : + 138: 82 58 10 00 subxi sp,0,sp,icc0 + +0000013c : + 13c: 82 4c 10 00 addxicc sp,0,sp,icc0 + +00000140 : + 140: 82 5c 10 00 subxicc sp,0,sp,icc0 + +00000144 : + 144: 82 f4 00 00 setlo lo\(0x0\),sp + +00000148 : + 148: 82 f8 00 00 sethi hi\(0x0\),sp + +0000014c : + 14c: 82 fc 00 00 setlos lo\(0x0\),sp + +00000150 : + 150: 82 08 10 01 ldsb @\(sp,sp\),sp + +00000154 : + 154: 82 08 10 41 ldub @\(sp,sp\),sp + +00000158 : + 158: 82 08 10 81 ldsh @\(sp,sp\),sp + +0000015c : + 15c: 82 08 10 c1 lduh @\(sp,sp\),sp + +00000160 : + 160: 82 08 11 01 ld @\(sp,sp\),sp + +00000164 : + 164: 80 08 12 01 ldbf @\(sp,sp\),fr0 + +00000168 : + 168: 80 08 12 41 ldhf @\(sp,sp\),fr0 + +0000016c : + 16c: 80 08 12 81 ldf @\(sp,sp\),fr0 + +00000170 : + 170: 80 08 13 41 ldc @\(sp,sp\),cpr0 + +00000174 : + 174: 82 08 18 01 nldsb @\(sp,sp\),sp + +00000178 : + 178: 82 08 18 41 nldub @\(sp,sp\),sp + +0000017c : + 17c: 82 08 18 81 nldsh @\(sp,sp\),sp + +00000180 : + 180: 82 08 18 c1 nlduh @\(sp,sp\),sp + +00000184 : + 184: 82 08 19 01 nld @\(sp,sp\),sp + +00000188 : + 188: 80 08 1a 01 nldbf @\(sp,sp\),fr0 + +0000018c : + 18c: 80 08 1a 41 nldhf @\(sp,sp\),fr0 + +00000190 : + 190: 80 08 1a 81 nldf @\(sp,sp\),fr0 + +00000194 : + 194: 82 08 11 41 ldd @\(sp,sp\),sp + +00000198 : + 198: 80 08 12 c1 lddf @\(sp,sp\),fr0 + +0000019c : + 19c: 80 08 13 81 lddc @\(sp,sp\),cpr0 + +000001a0 : + 1a0: 82 08 19 41 nldd @\(sp,sp\),sp + +000001a4 : + 1a4: 80 08 1a c1 nlddf @\(sp,sp\),fr0 + +000001a8 : + 1a8: 82 08 11 81 ldq @\(sp,sp\),sp + +000001ac : + 1ac: 80 08 13 01 ldqf @\(sp,sp\),fr0 + +000001b0 : + 1b0: 80 08 13 c1 ldqc @\(sp,sp\),cpr0 + +000001b4 : + 1b4: 82 08 19 81 nldq @\(sp,sp\),sp + +000001b8 : + 1b8: 80 08 1b 01 nldqf @\(sp,sp\),fr0 + +000001bc : + 1bc: 82 08 14 01 ldsbu @\(sp,sp\),sp + +000001c0 : + 1c0: 82 08 14 41 ldubu @\(sp,sp\),sp + +000001c4 : + 1c4: 82 08 14 81 ldshu @\(sp,sp\),sp + +000001c8 : + 1c8: 82 08 14 c1 lduhu @\(sp,sp\),sp + +000001cc : + 1cc: 82 08 15 01 ldu @\(sp,sp\),sp + +000001d0 : + 1d0: 82 08 1c 01 nldsbu @\(sp,sp\),sp + +000001d4 : + 1d4: 82 08 1c 41 nldubu @\(sp,sp\),sp + +000001d8 : + 1d8: 82 08 1c 81 nldshu @\(sp,sp\),sp + +000001dc : + 1dc: 82 08 1c c1 nlduhu @\(sp,sp\),sp + +000001e0 : + 1e0: 82 08 1d 01 nldu @\(sp,sp\),sp + +000001e4 : + 1e4: 80 08 16 01 ldbfu @\(sp,sp\),fr0 + +000001e8 : + 1e8: 80 08 16 41 ldhfu @\(sp,sp\),fr0 + +000001ec : + 1ec: 80 08 16 81 ldfu @\(sp,sp\),fr0 + +000001f0 : + 1f0: 80 08 17 41 ldcu @\(sp,sp\),cpr0 + +000001f4 : + 1f4: 80 08 1e 01 nldbfu @\(sp,sp\),fr0 + +000001f8 : + 1f8: 80 08 1e 41 nldhfu @\(sp,sp\),fr0 + +000001fc : + 1fc: 80 08 1e 81 nldfu @\(sp,sp\),fr0 + +00000200 : + 200: 82 08 15 41 lddu @\(sp,sp\),sp + +00000204 : + 204: 82 08 1d 41 nlddu @\(sp,sp\),sp + +00000208 : + 208: 80 08 16 c1 lddfu @\(sp,sp\),fr0 + +0000020c : + 20c: 80 08 17 81 lddcu @\(sp,sp\),cpr0 + +00000210 : + 210: 80 08 1e c1 nlddfu @\(sp,sp\),fr0 + +00000214 : + 214: 82 08 15 81 ldqu @\(sp,sp\),sp + +00000218 : + 218: 82 08 1d 81 nldqu @\(sp,sp\),sp + +0000021c : + 21c: 80 08 17 01 ldqfu @\(sp,sp\),fr0 + +00000220 : + 220: 80 08 17 c1 ldqcu @\(sp,sp\),cpr0 + +00000224 : + 224: 80 08 1f 01 nldqfu @\(sp,sp\),fr0 + +00000228 : + 228: 82 c0 10 00 ldsbi @\(sp,0\),sp + +0000022c : + 22c: 82 c4 10 00 ldshi @\(sp,0\),sp + +00000230 : + 230: 82 c8 10 00 ldi @\(sp,0\),sp + +00000234 : + 234: 82 d4 10 00 ldubi @\(sp,0\),sp + +00000238 : + 238: 82 d8 10 00 lduhi @\(sp,0\),sp + +0000023c : + 23c: 80 e0 10 00 ldbfi @\(sp,0\),fr0 + +00000240 : + 240: 80 e4 10 00 ldhfi @\(sp,0\),fr0 + +00000244 : + 244: 80 e8 10 00 ldfi @\(sp,0\),fr0 + +00000248 : + 248: 83 00 10 00 nldsbi @\(sp,0\),sp + +0000024c : + 24c: 83 04 10 00 nldubi @\(sp,0\),sp + +00000250 : + 250: 83 08 10 00 nldshi @\(sp,0\),sp + +00000254 : + 254: 83 0c 10 00 nlduhi @\(sp,0\),sp + +00000258 : + 258: 83 10 10 00 nldi @\(sp,0\),sp + +0000025c : + 25c: 81 20 10 00 nldbfi @\(sp,0\),fr0 + +00000260 : + 260: 81 24 10 00 nldhfi @\(sp,0\),fr0 + +00000264 : + 264: 81 28 10 00 nldfi @\(sp,0\),fr0 + +00000268 : + 268: 82 cc 10 00 lddi @\(sp,0\),sp + +0000026c : + 26c: 80 ec 10 00 lddfi @\(sp,0\),fr0 + +00000270 : + 270: 83 14 10 00 nlddi @\(sp,0\),sp + +00000274 : + 274: 81 2c 10 00 nlddfi @\(sp,0\),fr0 + +00000278 : + 278: 82 d0 10 00 ldqi @\(sp,0\),sp + +0000027c : + 27c: 80 f0 10 00 ldqfi @\(sp,0\),fr0 + +00000280 : + 280: 83 18 10 00 nldqi @\(sp,0\),sp + +00000284 : + 284: 81 30 10 00 nldqfi @\(sp,0\),fr0 + +00000288 : + 288: 82 0c 10 01 stb sp,@\(sp,sp\) + +0000028c : + 28c: 82 0c 10 41 sth sp,@\(sp,sp\) + +00000290 : + 290: 82 0c 10 81 st sp,@\(sp,sp\) + +00000294 : + 294: 80 0c 12 01 stbf fr0,@\(sp,sp\) + +00000298 : + 298: 80 0c 12 41 sthf fr0,@\(sp,sp\) + +0000029c : + 29c: 80 0c 12 81 stf fr0,@\(sp,sp\) + +000002a0 : + 2a0: 80 0c 19 41 stc cpr0,@\(sp,sp\) + +000002a4 : + 2a4: 82 0c 18 01 rstb sp,@\(sp,sp\) + +000002a8 : + 2a8: 82 0c 18 41 rsth sp,@\(sp,sp\) + +000002ac : + 2ac: 82 0c 18 81 rst sp,@\(sp,sp\) + +000002b0 : + 2b0: 80 0c 1a 01 rstbf fr0,@\(sp,sp\) + +000002b4 : + 2b4: 80 0c 1a 41 rsthf fr0,@\(sp,sp\) + +000002b8 : + 2b8: 80 0c 1a 81 rstf fr0,@\(sp,sp\) + +000002bc : + 2bc: 82 0c 10 c1 std sp,@\(sp,sp\) + +000002c0 : + 2c0: 80 0c 12 c1 stdf fr0,@\(sp,sp\) + +000002c4 : + 2c4: 80 0c 19 81 stdc cpr0,@\(sp,sp\) + +000002c8 : + 2c8: 82 0c 18 c1 rstd sp,@\(sp,sp\) + +000002cc : + 2cc: 80 0c 1a c1 rstdf fr0,@\(sp,sp\) + +000002d0 : + 2d0: 82 0c 11 01 stq sp,@\(sp,sp\) + +000002d4 : + 2d4: 80 0c 13 01 stqf fr0,@\(sp,sp\) + +000002d8 : + 2d8: 80 0c 19 c1 stqc cpr0,@\(sp,sp\) + +000002dc : + 2dc: 82 0c 19 01 rstq sp,@\(sp,sp\) + +000002e0 : + 2e0: 80 0c 1b 01 rstqf fr0,@\(sp,sp\) + +000002e4 : + 2e4: 82 0c 14 01 stbu sp,@\(sp,sp\) + +000002e8 : + 2e8: 82 0c 14 41 sthu sp,@\(sp,sp\) + +000002ec : + 2ec: 82 0c 14 81 stu sp,@\(sp,sp\) + +000002f0 : + 2f0: 80 0c 16 01 stbfu fr0,@\(sp,sp\) + +000002f4 : + 2f4: 80 0c 16 41 sthfu fr0,@\(sp,sp\) + +000002f8 : + 2f8: 80 0c 16 81 stfu fr0,@\(sp,sp\) + +000002fc : + 2fc: 80 0c 1b 41 stcu cpr0,@\(sp,sp\) + +00000300 : + 300: 82 0c 14 c1 stdu sp,@\(sp,sp\) + +00000304 : + 304: 80 0c 16 c1 stdfu fr0,@\(sp,sp\) + +00000308 : + 308: 80 0c 1b 81 stdcu cpr0,@\(sp,sp\) + +0000030c : + 30c: 82 0c 15 01 stqu sp,@\(sp,sp\) + +00000310 : + 310: 80 0c 17 01 stqfu fr0,@\(sp,sp\) + +00000314 : + 314: 80 0c 1b c1 stqcu cpr0,@\(sp,sp\) + +00000318 : + 318: 83 78 10 01 cldsb @\(sp,sp\),sp,cc0,0x0 + +0000031c : + 31c: 83 78 10 41 cldub @\(sp,sp\),sp,cc0,0x0 + +00000320 : + 320: 83 78 10 81 cldsh @\(sp,sp\),sp,cc0,0x0 + +00000324 : + 324: 83 78 10 c1 clduh @\(sp,sp\),sp,cc0,0x0 + +00000328 : + 328: 83 7c 10 01 cld @\(sp,sp\),sp,cc0,0x0 + +0000032c : + 32c: 81 80 10 01 cldbf @\(sp,sp\),fr0,cc0,0x0 + +00000330 : + 330: 81 80 10 41 cldhf @\(sp,sp\),fr0,cc0,0x0 + +00000334 : + 334: 81 80 10 81 cldf @\(sp,sp\),fr0,cc0,0x0 + +00000338 : + 338: 83 7c 10 41 cldd @\(sp,sp\),sp,cc0,0x0 + +0000033c : + 33c: 81 80 10 c1 clddf @\(sp,sp\),fr0,cc0,0x0 + +00000340 : + 340: 83 7c 10 81 cldq @\(sp,sp\),sp,cc0,0x0 + +00000344 : + 344: 83 84 10 01 cldsbu @\(sp,sp\),sp,cc0,0x0 + +00000348 : + 348: 83 84 10 41 cldubu @\(sp,sp\),sp,cc0,0x0 + +0000034c : + 34c: 83 84 10 81 cldshu @\(sp,sp\),sp,cc0,0x0 + +00000350 : + 350: 83 84 10 c1 clduhu @\(sp,sp\),sp,cc0,0x0 + +00000354 : + 354: 83 88 10 01 cldu @\(sp,sp\),sp,cc0,0x0 + +00000358 : + 358: 81 8c 10 01 cldbfu @\(sp,sp\),fr0,cc0,0x0 + +0000035c : + 35c: 81 8c 10 41 cldhfu @\(sp,sp\),fr0,cc0,0x0 + +00000360 : + 360: 81 8c 10 81 cldfu @\(sp,sp\),fr0,cc0,0x0 + +00000364 : + 364: 83 88 10 41 clddu @\(sp,sp\),sp,cc0,0x0 + +00000368 : + 368: 81 8c 10 c1 clddfu @\(sp,sp\),fr0,cc0,0x0 + +0000036c : + 36c: 83 88 10 81 cldqu @\(sp,sp\),sp,cc0,0x0 + +00000370 : + 370: 83 90 10 01 cstb sp,@\(sp,sp\),cc0,0x0 + +00000374 : + 374: 83 90 10 41 csth sp,@\(sp,sp\),cc0,0x0 + +00000378 : + 378: 83 90 10 81 cst sp,@\(sp,sp\),cc0,0x0 + +0000037c : + 37c: 81 98 10 01 cstbf fr0,@\(sp,sp\),cc0,0x0 + +00000380 : + 380: 81 98 10 41 csthf fr0,@\(sp,sp\),cc0,0x0 + +00000384 : + 384: 81 98 10 81 cstf fr0,@\(sp,sp\),cc0,0x0 + +00000388 : + 388: 83 90 10 c1 cstd sp,@\(sp,sp\),cc0,0x0 + +0000038c : + 38c: 81 98 10 c1 cstdf fr0,@\(sp,sp\),cc0,0x0 + +00000390 : + 390: 83 94 10 01 cstq sp,@\(sp,sp\),cc0,0x0 + +00000394 : + 394: 83 9c 10 01 cstbu sp,@\(sp,sp\),cc0,0x0 + +00000398 : + 398: 83 9c 10 41 csthu sp,@\(sp,sp\),cc0,0x0 + +0000039c : + 39c: 83 9c 10 81 cstu sp,@\(sp,sp\),cc0,0x0 + +000003a0 : + 3a0: 81 a0 10 01 cstbfu fr0,@\(sp,sp\),cc0,0x0 + +000003a4 : + 3a4: 81 a0 10 41 csthfu fr0,@\(sp,sp\),cc0,0x0 + +000003a8 : + 3a8: 81 a0 10 81 cstfu fr0,@\(sp,sp\),cc0,0x0 + +000003ac : + 3ac: 83 9c 10 c1 cstdu sp,@\(sp,sp\),cc0,0x0 + +000003b0 : + 3b0: 81 a0 10 c1 cstdfu fr0,@\(sp,sp\),cc0,0x0 + +000003b4 : + 3b4: 83 40 10 00 stbi sp,@\(sp,0\) + +000003b8 : + 3b8: 83 44 10 00 sthi sp,@\(sp,0\) + +000003bc : + 3bc: 83 48 10 00 sti sp,@\(sp,0\) + +000003c0 : + 3c0: 81 38 10 00 stbfi fr0,@\(sp,0\) + +000003c4 : + 3c4: 81 3c 10 00 sthfi fr0,@\(sp,0\) + +000003c8 : + 3c8: 81 54 10 00 stfi fr0,@\(sp,0\) + +000003cc : + 3cc: 83 4c 10 00 stdi sp,@\(sp,0\) + +000003d0 : + 3d0: 81 58 10 00 stdfi fr0,@\(sp,0\) + +000003d4 : + 3d4: 83 50 10 00 stqi sp,@\(sp,0\) + +000003d8 : + 3d8: 81 5c 10 00 stqfi fr0,@\(sp,0\) + +000003dc : + 3dc: 82 0c 11 41 swap @\(sp,sp\),sp + +000003e0 : + 3e0: 83 34 10 00 swapi @\(sp,0\),sp + +000003e4 : + 3e4: 83 94 10 81 cswap @\(sp,sp\),sp,cc0,0x0 + +000003e8 : + 3e8: 80 0c 05 41 movgf sp,fr0 + +000003ec : + 3ec: 80 0c 03 41 movfg fr0,sp + +000003f0 : + 3f0: 80 0c 05 81 movgfd sp,fr0 + +000003f4 : + 3f4: 80 0c 03 81 movfgd fr0,sp + +000003f8 : + 3f8: 80 0c 05 c1 movgfq sp,fr0 + +000003fc : + 3fc: 80 0c 03 c1 movfgq fr0,sp + +00000400 : + 400: 81 a4 00 01 cmovgf sp,fr0,cc0,0x0 + +00000404 : + 404: 81 a4 00 81 cmovfg fr0,sp,cc0,0x0 + +00000408 : + 408: 81 a4 00 41 cmovgfd sp,fr0,cc0,0x0 + +0000040c : + 40c: 81 a4 00 c1 cmovfgd fr0,sp,cc0,0x0 + +00000410 : + 410: 80 0c 01 81 movgs sp,psr + +00000414 : + 414: 80 0c 01 c1 movsg psr,sp + +00000418 : + 418: 80 18 00 00 bno + +0000041c : + 41c: c0 1a fe f9 bra 0 + +00000420 : + 420: a0 18 fe f8 beq icc0,0x0,0 + +00000424 : + 424: e0 18 fe f7 bne icc0,0x0,0 + +00000428 : + 428: b8 18 fe f6 ble icc0,0x0,0 + +0000042c : + 42c: f8 18 fe f5 bgt icc0,0x0,0 + +00000430 : + 430: 98 18 fe f4 blt icc0,0x0,0 + +00000434 : + 434: d8 18 fe f3 bge icc0,0x0,0 + +00000438 : + 438: a8 18 fe f2 bls icc0,0x0,0 + +0000043c : + 43c: e8 18 fe f1 bhi icc0,0x0,0 + +00000440 : + 440: 88 18 fe f0 bc icc0,0x0,0 + +00000444 : + 444: c8 18 fe ef bnc icc0,0x0,0 + +00000448 : + 448: b0 18 fe ee bn icc0,0x0,0 + +0000044c : + 44c: f0 18 fe ed bp icc0,0x0,0 + +00000450 : + 450: 90 18 fe ec bv icc0,0x0,0 + +00000454 : + 454: d0 18 fe eb bnv icc0,0x0,0 + +00000458 : + 458: 80 1c 00 00 fbno + +0000045c : + 45c: f8 1e fe e9 fbra 0 + +00000460 : + 460: b8 1c fe e8 fbne fcc0,0x0,0 + +00000464 : + 464: c0 1c fe e7 fbeq fcc0,0x0,0 + +00000468 : + 468: b0 1c fe e6 fblg fcc0,0x0,0 + +0000046c : + 46c: c8 1c fe e5 fbue fcc0,0x0,0 + +00000470 : + 470: a8 1c fe e4 fbul fcc0,0x0,0 + +00000474 : + 474: d0 1c fe e3 fbge fcc0,0x0,0 + +00000478 : + 478: a0 1c fe e2 fblt fcc0,0x0,0 + +0000047c : + 47c: d8 1c fe e1 fbuge fcc0,0x0,0 + +00000480 : + 480: 98 1c fe e0 fbug fcc0,0x0,0 + +00000484 : + 484: e0 1c fe df fble fcc0,0x0,0 + +00000488 : + 488: 90 1c fe de fbgt fcc0,0x0,0 + +0000048c : + 48c: e8 1c fe dd fbule fcc0,0x0,0 + +00000490 : + 490: 88 1c fe dc fbu fcc0,0x0,0 + +00000494 : + 494: f0 1c fe db fbo fcc0,0x0,0 + +00000498 : + 498: 80 38 20 00 bctrlr 0x0,0x0 + +0000049c : + 49c: 80 38 40 00 bnolr + +000004a0 : + 4a0: c0 3a 40 00 bralr + +000004a4 : + 4a4: a0 38 40 00 beqlr icc0,0x0 + +000004a8 : + 4a8: e0 38 40 00 bnelr icc0,0x0 + +000004ac : + 4ac: b8 38 40 00 blelr icc0,0x0 + +000004b0 : + 4b0: f8 38 40 00 bgtlr icc0,0x0 + +000004b4 : + 4b4: 98 38 40 00 bltlr icc0,0x0 + +000004b8 : + 4b8: d8 38 40 00 bgelr icc0,0x0 + +000004bc : + 4bc: a8 38 40 00 blslr icc0,0x0 + +000004c0 : + 4c0: e8 38 40 00 bhilr icc0,0x0 + +000004c4 : + 4c4: 88 38 40 00 bclr icc0,0x0 + +000004c8 : + 4c8: c8 38 40 00 bnclr icc0,0x0 + +000004cc : + 4cc: b0 38 40 00 bnlr icc0,0x0 + +000004d0 : + 4d0: f0 38 40 00 bplr icc0,0x0 + +000004d4 : + 4d4: 90 38 40 00 bvlr icc0,0x0 + +000004d8 : + 4d8: d0 38 40 00 bnvlr icc0,0x0 + +000004dc : + 4dc: 80 38 c0 00 fbnolr + +000004e0 : + 4e0: f8 3a c0 00 fbralr + +000004e4 : + 4e4: c0 38 c0 00 fbeqlr fcc0,0x0 + +000004e8 : + 4e8: b8 38 c0 00 fbnelr fcc0,0x0 + +000004ec : + 4ec: b0 38 c0 00 fblglr fcc0,0x0 + +000004f0 : + 4f0: c8 38 c0 00 fbuelr fcc0,0x0 + +000004f4 : + 4f4: a8 38 c0 00 fbullr fcc0,0x0 + +000004f8 : + 4f8: d0 38 c0 00 fbgelr fcc0,0x0 + +000004fc : + 4fc: a0 38 c0 00 fbltlr fcc0,0x0 + +00000500 : + 500: d8 38 c0 00 fbugelr fcc0,0x0 + +00000504 : + 504: 98 38 c0 00 fbuglr fcc0,0x0 + +00000508 : + 508: e0 38 c0 00 fblelr fcc0,0x0 + +0000050c : + 50c: 90 38 c0 00 fbgtlr fcc0,0x0 + +00000510 : + 510: e8 38 c0 00 fbulelr fcc0,0x0 + +00000514 : + 514: 88 38 c0 00 fbulr fcc0,0x0 + +00000518 : + 518: f0 38 c0 00 fbolr fcc0,0x0 + +0000051c : + 51c: 80 38 60 00 bcnolr + +00000520 : + 520: c0 3a 60 00 bcralr 0x0 + +00000524 : + 524: a0 38 60 00 bceqlr icc0,0x0,0x0 + +00000528 : + 528: e0 38 60 00 bcnelr icc0,0x0,0x0 + +0000052c : + 52c: b8 38 60 00 bclelr icc0,0x0,0x0 + +00000530 : + 530: f8 38 60 00 bcgtlr icc0,0x0,0x0 + +00000534 : + 534: 98 38 60 00 bcltlr icc0,0x0,0x0 + +00000538 : + 538: d8 38 60 00 bcgelr icc0,0x0,0x0 + +0000053c : + 53c: a8 38 60 00 bclslr icc0,0x0,0x0 + +00000540 : + 540: e8 38 60 00 bchilr icc0,0x0,0x0 + +00000544 : + 544: 88 38 60 00 bcclr icc0,0x0,0x0 + +00000548 : + 548: c8 38 60 00 bcnclr icc0,0x0,0x0 + +0000054c : + 54c: b0 38 60 00 bcnlr icc0,0x0,0x0 + +00000550 : + 550: f0 38 60 00 bcplr icc0,0x0,0x0 + +00000554 : + 554: 90 38 60 00 bcvlr icc0,0x0,0x0 + +00000558 : + 558: d0 38 60 00 bcnvlr icc0,0x0,0x0 + +0000055c : + 55c: 80 38 e0 00 fcbnolr + +00000560 : + 560: f8 3a e0 00 fcbralr 0x0 + +00000564 : + 564: c0 38 e0 00 fcbeqlr fcc0,0x0,0x0 + +00000568 : + 568: b8 38 e0 00 fcbnelr fcc0,0x0,0x0 + +0000056c : + 56c: b0 38 e0 00 fcblglr fcc0,0x0,0x0 + +00000570 : + 570: c8 38 e0 00 fcbuelr fcc0,0x0,0x0 + +00000574 : + 574: a8 38 e0 00 fcbullr fcc0,0x0,0x0 + +00000578 : + 578: d0 38 e0 00 fcbgelr fcc0,0x0,0x0 + +0000057c : + 57c: a0 38 e0 00 fcbltlr fcc0,0x0,0x0 + +00000580 : + 580: d8 38 e0 00 fcbugelr fcc0,0x0,0x0 + +00000584 : + 584: 98 38 e0 00 fcbuglr fcc0,0x0,0x0 + +00000588 : + 588: e0 38 e0 00 fcblelr fcc0,0x0,0x0 + +0000058c : + 58c: 90 38 e0 00 fcbgtlr fcc0,0x0,0x0 + +00000590 : + 590: e8 38 e0 00 fcbulelr fcc0,0x0,0x0 + +00000594 : + 594: 88 38 e0 00 fcbulr fcc0,0x0,0x0 + +00000598 : + 598: f0 38 e0 00 fcbolr fcc0,0x0,0x0 + +0000059c : + 59c: 80 30 10 01 jmpl @\(sp,sp\) + +000005a0 : + 5a0: 80 34 10 00 jmpil @\(sp,0\) + +000005a4 : + 5a4: fe 3f fe 97 call 0 + +000005a8 : + 5a8: 80 dc 00 00 rei 0x0 + +000005ac : + 5ac: 80 10 00 00 tno + +000005b0 : + 5b0: c0 10 10 01 tra sp,sp + +000005b4 : + 5b4: a0 10 10 01 teq icc0,sp,sp + +000005b8 : + 5b8: e0 10 10 01 tne icc0,sp,sp + +000005bc : + 5bc: b8 10 10 01 tle icc0,sp,sp + +000005c0 : + 5c0: f8 10 10 01 tgt icc0,sp,sp + +000005c4 : + 5c4: 98 10 10 01 tlt icc0,sp,sp + +000005c8 : + 5c8: d8 10 10 01 tge icc0,sp,sp + +000005cc : + 5cc: a8 10 10 01 tls icc0,sp,sp + +000005d0 : + 5d0: e8 10 10 01 thi icc0,sp,sp + +000005d4 : + 5d4: 88 10 10 01 tc icc0,sp,sp + +000005d8 : + 5d8: c8 10 10 01 tnc icc0,sp,sp + +000005dc : + 5dc: b0 10 10 01 tn icc0,sp,sp + +000005e0 : + 5e0: f0 10 10 01 tp icc0,sp,sp + +000005e4 : + 5e4: 90 10 10 01 tv icc0,sp,sp + +000005e8 : + 5e8: d0 10 10 01 tnv icc0,sp,sp + +000005ec : + 5ec: 80 10 00 40 ftno + +000005f0 : + 5f0: f8 10 10 41 ftra sp,sp + +000005f4 : + 5f4: b8 10 10 41 ftne fcc0,sp,sp + +000005f8 : + 5f8: c0 10 10 41 fteq fcc0,sp,sp + +000005fc : + 5fc: b0 10 10 41 ftlg fcc0,sp,sp + +00000600 : + 600: c8 10 10 41 ftue fcc0,sp,sp + +00000604 : + 604: a8 10 10 41 ftul fcc0,sp,sp + +00000608 : + 608: d0 10 10 41 ftge fcc0,sp,sp + +0000060c : + 60c: a0 10 10 41 ftlt fcc0,sp,sp + +00000610 : + 610: d8 10 10 41 ftuge fcc0,sp,sp + +00000614 : + 614: 98 10 10 41 ftug fcc0,sp,sp + +00000618 : + 618: e0 10 10 41 ftle fcc0,sp,sp + +0000061c : + 61c: 90 10 10 41 ftgt fcc0,sp,sp + +00000620 : + 620: e8 10 10 41 ftule fcc0,sp,sp + +00000624 : + 624: 88 10 10 41 ftu fcc0,sp,sp + +00000628 : + 628: f0 10 10 41 fto fcc0,sp,sp + +0000062c : + 62c: 80 70 00 00 tino + +00000630 : + 630: c0 70 10 00 tira sp,0 + +00000634 : + 634: a0 70 10 00 tieq icc0,sp,0 + +00000638 : + 638: e0 70 10 00 tine icc0,sp,0 + +0000063c : + 63c: b8 70 10 00 tile icc0,sp,0 + +00000640 : + 640: f8 70 10 00 tigt icc0,sp,0 + +00000644 : + 644: 98 70 10 00 tilt icc0,sp,0 + +00000648 : + 648: d8 70 10 00 tige icc0,sp,0 + +0000064c : + 64c: a8 70 10 00 tils icc0,sp,0 + +00000650 : + 650: e8 70 10 00 tihi icc0,sp,0 + +00000654 : + 654: 88 70 10 00 tic icc0,sp,0 + +00000658 : + 658: c8 70 10 00 tinc icc0,sp,0 + +0000065c : + 65c: b0 70 10 00 tin icc0,sp,0 + +00000660 : + 660: f0 70 10 00 tip icc0,sp,0 + +00000664 : + 664: 90 70 10 00 tiv icc0,sp,0 + +00000668 : + 668: d0 70 10 00 tinv icc0,sp,0 + +0000066c : + 66c: 80 74 00 00 ftino + +00000670 : + 670: f8 74 10 00 ftira sp,0 + +00000674 : + 674: b8 74 10 00 ftine fcc0,sp,0 + +00000678 : + 678: c0 74 10 00 ftieq fcc0,sp,0 + +0000067c : + 67c: b0 74 10 00 ftilg fcc0,sp,0 + +00000680 : + 680: c8 74 10 00 ftiue fcc0,sp,0 + +00000684 : + 684: a8 74 10 00 ftiul fcc0,sp,0 + +00000688 : + 688: d0 74 10 00 ftige fcc0,sp,0 + +0000068c : + 68c: a0 74 10 00 ftilt fcc0,sp,0 + +00000690 : + 690: d8 74 10 00 ftiuge fcc0,sp,0 + +00000694 : + 694: 98 74 10 00 ftiug fcc0,sp,0 + +00000698 : + 698: e0 74 10 00 ftile fcc0,sp,0 + +0000069c : + 69c: 90 74 10 00 ftigt fcc0,sp,0 + +000006a0 : + 6a0: e8 74 10 00 ftiule fcc0,sp,0 + +000006a4 : + 6a4: 88 74 10 00 ftiu fcc0,sp,0 + +000006a8 : + 6a8: f0 74 10 00 ftio fcc0,sp,0 + +000006ac : + 6ac: 80 28 02 00 andcr cc0,cc0,cc0 + +000006b0 : + 6b0: 80 28 02 40 orcr cc0,cc0,cc0 + +000006b4 : + 6b4: 80 28 02 80 xorcr cc0,cc0,cc0 + +000006b8 : + 6b8: 80 28 03 00 nandcr cc0,cc0,cc0 + +000006bc : + 6bc: 80 28 03 40 norcr cc0,cc0,cc0 + +000006c0 : + 6c0: 80 28 04 00 andncr cc0,cc0,cc0 + +000006c4 : + 6c4: 80 28 04 40 orncr cc0,cc0,cc0 + +000006c8 : + 6c8: 80 28 05 00 nandncr cc0,cc0,cc0 + +000006cc : + 6cc: 80 28 05 40 norncr cc0,cc0,cc0 + +000006d0 : + 6d0: 80 28 02 c0 notcr cc0,cc0 + +000006d4 : + 6d4: 86 20 00 00 ckno cc7 + +000006d8 : + 6d8: c6 20 00 00 ckra cc7 + +000006dc : + 6dc: a6 20 00 00 ckeq icc0,cc7 + +000006e0 : + 6e0: e6 20 00 00 ckne icc0,cc7 + +000006e4 : + 6e4: be 20 00 00 ckle icc0,cc7 + +000006e8 : + 6e8: fe 20 00 00 ckgt icc0,cc7 + +000006ec : + 6ec: 9e 20 00 00 cklt icc0,cc7 + +000006f0 : + 6f0: de 20 00 00 ckge icc0,cc7 + +000006f4 : + 6f4: ae 20 00 00 ckls icc0,cc7 + +000006f8 : + 6f8: ee 20 00 00 ckhi icc0,cc7 + +000006fc : + 6fc: 8e 20 00 00 ckc icc0,cc7 + +00000700 : + 700: ce 20 00 00 cknc icc0,cc7 + +00000704 : + 704: b6 20 00 00 ckn icc0,cc7 + +00000708 : + 708: f6 20 00 00 ckp icc0,cc7 + +0000070c : + 70c: 96 20 00 00 ckv icc0,cc7 + +00000710 : + 710: d6 20 00 00 cknv icc0,cc7 + +00000714 : + 714: 80 24 00 00 fckno cc0 + +00000718 : + 718: f8 24 00 00 fckra cc0 + +0000071c : + 71c: b8 24 00 00 fckne fcc0,cc0 + +00000720 : + 720: c0 24 00 00 fckeq fcc0,cc0 + +00000724 : + 724: b0 24 00 00 fcklg fcc0,cc0 + +00000728 : + 728: c8 24 00 00 fckue fcc0,cc0 + +0000072c : + 72c: a8 24 00 00 fckul fcc0,cc0 + +00000730 : + 730: d0 24 00 00 fckge fcc0,cc0 + +00000734 : + 734: a0 24 00 00 fcklt fcc0,cc0 + +00000738 : + 738: d8 24 00 00 fckuge fcc0,cc0 + +0000073c : + 73c: 98 24 00 00 fckug fcc0,cc0 + +00000740 : + 740: e0 24 00 00 fckle fcc0,cc0 + +00000744 : + 744: 90 24 00 00 fckgt fcc0,cc0 + +00000748 : + 748: e8 24 00 00 fckule fcc0,cc0 + +0000074c : + 74c: 88 24 00 00 fcku fcc0,cc0 + +00000750 : + 750: f0 24 00 00 fcko fcc0,cc0 + +00000754 : + 754: 87 a8 06 00 cckno cc7,cc3,0x0 + +00000758 : + 758: c7 a8 06 00 cckra cc7,cc3,0x0 + +0000075c : + 75c: a7 a8 06 00 cckeq icc0,cc7,cc3,0x0 + +00000760 : + 760: e7 a8 06 00 cckne icc0,cc7,cc3,0x0 + +00000764 : + 764: bf a8 06 00 cckle icc0,cc7,cc3,0x0 + +00000768 : + 768: ff a8 06 00 cckgt icc0,cc7,cc3,0x0 + +0000076c : + 76c: 9f a8 06 00 ccklt icc0,cc7,cc3,0x0 + +00000770 : + 770: df a8 06 00 cckge icc0,cc7,cc3,0x0 + +00000774 : + 774: af a8 06 00 cckls icc0,cc7,cc3,0x0 + +00000778 : + 778: ef a8 06 00 cckhi icc0,cc7,cc3,0x0 + +0000077c : + 77c: 8f a8 06 00 cckc icc0,cc7,cc3,0x0 + +00000780 : + 780: cf a8 06 00 ccknc icc0,cc7,cc3,0x0 + +00000784 : + 784: b7 a8 06 00 cckn icc0,cc7,cc3,0x0 + +00000788 : + 788: f7 a8 06 00 cckp icc0,cc7,cc3,0x0 + +0000078c : + 78c: 97 a8 06 00 cckv icc0,cc7,cc3,0x0 + +00000790 : + 790: d7 a8 06 00 ccknv icc0,cc7,cc3,0x0 + +00000794 : + 794: 81 a8 00 40 cfckno cc0,cc0,0x0 + +00000798 : + 798: f9 a8 00 40 cfckra cc0,cc0,0x0 + +0000079c : + 79c: b9 a8 00 40 cfckne fcc0,cc0,cc0,0x0 + +000007a0 : + 7a0: c1 a8 00 40 cfckeq fcc0,cc0,cc0,0x0 + +000007a4 : + 7a4: b1 a8 00 40 cfcklg fcc0,cc0,cc0,0x0 + +000007a8 : + 7a8: c9 a8 00 40 cfckue fcc0,cc0,cc0,0x0 + +000007ac : + 7ac: a9 a8 00 40 cfckul fcc0,cc0,cc0,0x0 + +000007b0 : + 7b0: d1 a8 00 40 cfckge fcc0,cc0,cc0,0x0 + +000007b4 : + 7b4: a1 a8 00 40 cfcklt fcc0,cc0,cc0,0x0 + +000007b8 : + 7b8: d9 a8 00 40 cfckuge fcc0,cc0,cc0,0x0 + +000007bc : + 7bc: 99 a8 00 40 cfckug fcc0,cc0,cc0,0x0 + +000007c0 : + 7c0: e1 a8 00 40 cfckle fcc0,cc0,cc0,0x0 + +000007c4 : + 7c4: 91 a8 00 40 cfckgt fcc0,cc0,cc0,0x0 + +000007c8 : + 7c8: e9 a8 00 40 cfckule fcc0,cc0,cc0,0x0 + +000007cc : + 7cc: 89 a8 00 40 cfcku fcc0,cc0,cc0,0x0 + +000007d0 : + 7d0: f1 a8 00 40 cfcko fcc0,cc0,cc0,0x0 + +000007d4 : + 7d4: 81 a8 10 81 cjmpl @\(sp,sp\),cc0,0x0 + +000007d8 : + 7d8: 80 0c 1e 01 ici @\(sp,sp\) + +000007dc : + 7dc: 80 0c 1f 01 dci @\(sp,sp\) + +000007e0 : + 7e0: 80 0c 1f 41 dcf @\(sp,sp\) + +000007e4 : + 7e4: 82 0c 1c 81 witlb sp,@\(sp,sp\) + +000007e8 : + 7e8: 82 0c 1d 81 wdtlb sp,@\(sp,sp\) + +000007ec : + 7ec: 80 0c 1c c1 itlbi @\(sp,sp\) + +000007f0 : + 7f0: 80 0c 1d c1 dtlbi @\(sp,sp\) + +000007f4 : + 7f4: 80 0c 1c 01 icpl sp,sp,0x0 + +000007f8 : + 7f8: 80 0c 1d 01 dcpl sp,sp,0x0 + +000007fc : + 7fc: 80 0c 1c 40 icul sp + +00000800 : + 800: 80 0c 1d 40 dcul sp + +00000804 : + 804: 82 28 00 00 clrgr sp + +00000808 : + 808: 80 28 00 80 clrfr fr0 + +0000080c : + 80c: 82 28 01 00 commitgr sp + +00000810 : + 810: 80 28 01 80 commitfr fr0 + +00000814 : + 814: 81 e4 00 00 fitos fr0,fr0 + +00000818 : + 818: 81 e4 00 40 fstoi fr0,fr0 + +0000081c : + 81c: 81 e8 00 00 fitod fr0,fr0 + +00000820 : + 820: 81 e8 00 40 fdtoi fr0,fr0 + +00000824 : + 824: 81 e4 00 80 fmovs fr0,fr0 + +00000828 : + 828: 81 e8 00 80 fmovd fr0,fr0 + +0000082c : + 82c: 81 e4 00 c0 fnegs fr0,fr0 + +00000830 : + 830: 81 e8 00 c0 fnegd fr0,fr0 + +00000834 : + 834: 81 e4 01 00 fabss fr0,fr0 + +00000838 : + 838: 81 e8 01 00 fabsd fr0,fr0 + +0000083c : + 83c: 81 e4 01 40 fsqrts fr0,fr0 + +00000840 : + 840: 81 e8 01 40 fsqrtd fr0,fr0 + +00000844 : + 844: 81 e4 01 80 fadds fr0,fr0,fr0 + +00000848 : + 848: 81 e4 01 c0 fsubs fr0,fr0,fr0 + +0000084c : + 84c: 81 e4 02 00 fmuls fr0,fr0,fr0 + +00000850 : + 850: 81 e4 02 40 fdivs fr0,fr0,fr0 + +00000854 : + 854: 81 e8 01 80 faddd fr0,fr0,fr0 + +00000858 : + 858: 81 e8 01 c0 fsubd fr0,fr0,fr0 + +0000085c : + 85c: 81 e8 02 00 fmuld fr0,fr0,fr0 + +00000860 : + 860: 81 e8 02 40 fdivd fr0,fr0,fr0 + +00000864 : + 864: 81 e4 02 80 fcmps fr0,fr0,fcc0 + +00000868 : + 868: 81 e8 02 80 fcmpd fr0,fr0,fcc0 + +0000086c : + 86c: 81 e4 02 c0 fmadds fr0,fr0,fr0 + +00000870 : + 870: 81 e4 03 00 fmsubs fr0,fr0,fr0 + +00000874 : + 874: 81 e8 02 c0 fmaddd fr0,fr0,fr0 + +00000878 : + 878: 81 e8 03 00 fmsubd fr0,fr0,fr0 + +0000087c : + 87c: 81 ec 00 00 mand fr0,fr0,fr0 + +00000880 : + 880: 81 ec 00 40 mor fr0,fr0,fr0 + +00000884 : + 884: 81 ec 00 80 mxor fr0,fr0,fr0 + +00000888 : + 888: 81 ec 00 c0 mnot fr0,fr0 + +0000088c : + 88c: 81 ec 01 00 mrotli fr0,0x0,fr0 + +00000890 : + 890: 81 ec 01 40 mrotri fr0,0x0,fr0 + +00000894 : + 894: 81 ec 01 80 mwcut fr0,fr0,fr0 + +00000898 : + 898: 81 ec 01 c0 mwcuti fr0,0x0,fr0 diff -uprN binutils-2.12.90.0.11/gas/testsuite/gas/frv/allinsn.exp binutils-2.12.90.0.12/gas/testsuite/gas/frv/allinsn.exp --- binutils-2.12.90.0.11/gas/testsuite/gas/frv/allinsn.exp Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/gas/testsuite/gas/frv/allinsn.exp Tue Jun 18 21:41:59 2002 @@ -0,0 +1,5 @@ +# FRV assembler testsuite. + +if [istarget frv*-*-*] { + run_dump_test "allinsn" +} diff -uprN binutils-2.12.90.0.11/gas/testsuite/gas/frv/allinsn.s binutils-2.12.90.0.12/gas/testsuite/gas/frv/allinsn.s --- binutils-2.12.90.0.11/gas/testsuite/gas/frv/allinsn.s Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/gas/testsuite/gas/frv/allinsn.s Tue Jun 18 21:41:59 2002 @@ -0,0 +1,2235 @@ + .data +foodata: .word 42 + .text +footext: + .text + .global add +add: + ADD sp,sp,sp + .text + .global sub +sub: + sub sp,sp,sp + .text + .global udiv +udiv: + udiv sp,sp,sp + .text + .global and +and: + and sp,sp,sp + .text + .global or +or: + or sp,sp,sp + .text + .global xor +xor: + xor sp,sp,sp + .text + .global not +not: + not sp,sp + .text + .global sdiv +sdiv: + sdiv sp,sp,sp + .text + .global nsdiv +nsdiv: + nsdiv sp,sp,sp + .text + .global nudiv +nudiv: + nudiv sp,sp,sp + .text + .global smul +smul: + smul sp,sp,sp + .text + .global umul +umul: + umul sp,sp,sp + .text + .global sll +sll: + sll sp,sp,sp + .text + .global srl +srl: + srl sp,sp,sp + .text + .global sra +sra: + sra sp,sp,sp + .text + .global scan +scan: + scan sp,sp,sp + .text + .global cadd +cadd: + cadd sp,sp,sp,cc0,0 + .text + .global csub +csub: + csub sp,sp,sp,cc0,0 + .text + .global cudiv +cudiv: + cudiv sp,sp,sp,cc0,0 + .text + .global cand +cand: + cand sp,sp,sp,cc0,0 + .text + .global cor +cor: + cor sp,sp,sp,cc0,0 + .text + .global cxor +cxor: + cxor sp,sp,sp,cc0,0 + .text + .global cnot +cnot: + cnot sp,sp,cc0,0 + .text + .global csmul +csmul: + csmul sp,sp,sp,cc0,0 + .text + .global csdiv +csdiv: + csdiv sp,sp,sp,cc0,0 + .text + .global csll +csll: + csll sp,sp,sp,cc0,0 + .text + .global csrl +csrl: + csrl sp,sp,sp,cc0,0 + .text + .global csra +csra: + csra sp,sp,sp,cc0,0 + .text + .global cscan +cscan: + cscan sp,sp,sp,cc0,0 + .text + .global addcc +addcc: + addcc sp,sp,sp,icc0 + .text + .global subcc +subcc: + subcc sp,sp,sp,icc0 + .text + .global andcc +andcc: + andcc sp,sp,sp,icc0 + .text + .global orcc +orcc: + orcc sp,sp,sp,icc0 + .text + .global xorcc +xorcc: + xorcc sp,sp,sp,icc0 + .text + .global sllcc +sllcc: + sllcc sp,sp,sp,icc0 + .text + .global srlcc +srlcc: + srlcc sp,sp,sp,icc0 + .text + .global sracc +sracc: + sracc sp,sp,sp,icc0 + .text + .global smulcc +smulcc: + smulcc sp,sp,sp,icc0 + .text + .global umulcc +umulcc: + umulcc sp,sp,sp,icc0 + .text + .global caddcc +caddcc: + caddcc sp,sp,sp,cc0,0 + .text + .global csubcc +csubcc: + csubcc sp,sp,sp,cc0,0 + .text + .global csmulcc +csmulcc: + csmulcc sp,sp,sp,cc0,0 + .text + .global candcc +candcc: + candcc sp,sp,sp,cc0,0 + .text + .global corcc +corcc: + corcc sp,sp,sp,cc0,0 + .text + .global cxorcc +cxorcc: + cxorcc sp,sp,sp,cc0,0 + .text + .global csllcc +csllcc: + csllcc sp,sp,sp,cc0,0 + .text + .global csrlcc +csrlcc: + csrlcc sp,sp,sp,cc0,0 + .text + .global csracc +csracc: + csracc sp,sp,sp,cc0,0 + .text + .global addx +addx: + addx sp,sp,sp,icc0 + .text + .global subx +subx: + subx sp,sp,sp,icc0 + .text + .global addxcc +addxcc: + addxcc sp,sp,sp,icc0 + .text + .global subxcc +subxcc: + subxcc sp,sp,sp,icc0 + .text + .global addi +addi: + addi sp,0,sp + .text + .global subi +subi: + subi sp,0,sp + .text + .global udivi +udivi: + udivi sp,0,sp + .text + .global andi +andi: + andi sp,0,sp + .text + .global ori +ori: + ori sp,0,sp + .text + .global xori +xori: + xori sp,0,sp + .text + .global sdivi +sdivi: + sdivi sp,0,sp + .text + .global nsdivi +nsdivi: + nsdivi sp,0,sp + .text + .global nudivi +nudivi: + nudivi sp,0,sp + .text + .global smuli +smuli: + smuli sp,0,sp + .text + .global umuli +umuli: + umuli sp,0,sp + .text + .global slli +slli: + slli sp,0,sp + .text + .global srli +srli: + srli sp,0,sp + .text + .global srai +srai: + srai sp,0,sp + .text + .global scani +scani: + scani sp,0,sp + .text + .global addicc +addicc: + addicc sp,0,sp,icc0 + .text + .global subicc +subicc: + subicc sp,0,sp,icc0 + .text + .global andicc +andicc: + andicc sp,0,sp,icc0 + .text + .global oricc +oricc: + oricc sp,0,sp,icc0 + .text + .global xoricc +xoricc: + xoricc sp,0,sp,icc0 + .text + .global smulicc +smulicc: + smulicc sp,0,sp,icc0 + .text + .global umulicc +umulicc: + umulicc sp,0,sp,icc0 + .text + .global sllicc +sllicc: + sllicc sp,0,sp,icc0 + .text + .global srlicc +srlicc: + srlicc sp,0,sp,icc0 + .text + .global sraicc +sraicc: + sraicc sp,0,sp,icc0 + .text + .global addxi +addxi: + addxi sp,0,sp,icc0 + .text + .global subxi +subxi: + subxi sp,0,sp,icc0 + .text + .global addxicc +addxicc: + addxicc sp,0,sp,icc0 + .text + .global subxicc +subxicc: + subxicc sp,0,sp,icc0 + .text + .global setlo +setlo: + setlo 0,sp + .text + .global sethi +sethi: + sethi 0,sp + .text + .global setlos +setlos: + setlos 0,sp + .text + .global ldsb +ldsb: + ldsb @(sp,sp),sp + .text + .global ldub +ldub: + ldub @(sp,sp),sp + .text + .global ldsh +ldsh: + ldsh @(sp,sp),sp + .text + .global lduh +lduh: + lduh @(sp,sp),sp + .text + .global ld +ld: + ld @(sp,sp),sp + .text + .global ldbf +ldbf: + ldbf @(sp,sp),fr0 + .text + .global ldhf +ldhf: + ldhf @(sp,sp),fr0 + .text + .global ldf +ldf: + ldf @(sp,sp),fr0 + .text + .global ldc +ldc: + ldc @(sp,sp),cpr0 + .text + .global nldsb +nldsb: + nldsb @(sp,sp),sp + .text + .global nldub +nldub: + nldub @(sp,sp),sp + .text + .global nldsh +nldsh: + nldsh @(sp,sp),sp + .text + .global nlduh +nlduh: + nlduh @(sp,sp),sp + .text + .global nld +nld: + nld @(sp,sp),sp + .text + .global nldbf +nldbf: + nldbf @(sp,sp),fr0 + .text + .global nldhf +nldhf: + nldhf @(sp,sp),fr0 + .text + .global nldf +nldf: + nldf @(sp,sp),fr0 + .text + .global ldd +ldd: + ldd @(sp,sp),sp + .text + .global lddf +lddf: + lddf @(sp,sp),fr0 + .text + .global lddc +lddc: + lddc @(sp,sp),cpr0 + .text + .global nldd +nldd: + nldd @(sp,sp),sp + .text + .global nlddf +nlddf: + nlddf @(sp,sp),fr0 + .text + .global ldq +ldq: + ldq @(sp,sp),sp + .text + .global ldqf +ldqf: + ldqf @(sp,sp),fr0 + .text + .global ldqc +ldqc: + ldqc @(sp,sp),cpr0 + .text + .global nldq +nldq: + nldq @(sp,sp),sp + .text + .global nldqf +nldqf: + nldqf @(sp,sp),fr0 + .text + .global ldsbu +ldsbu: + ldsbu @(sp,sp),sp + .text + .global ldubu +ldubu: + ldubu @(sp,sp),sp + .text + .global ldshu +ldshu: + ldshu @(sp,sp),sp + .text + .global lduhu +lduhu: + lduhu @(sp,sp),sp + .text + .global ldu +ldu: + ldu @(sp,sp),sp + .text + .global nldsbu +nldsbu: + nldsbu @(sp,sp),sp + .text + .global nldubu +nldubu: + nldubu @(sp,sp),sp + .text + .global nldshu +nldshu: + nldshu @(sp,sp),sp + .text + .global nlduhu +nlduhu: + nlduhu @(sp,sp),sp + .text + .global nldu +nldu: + nldu @(sp,sp),sp + .text + .global ldbfu +ldbfu: + ldbfu @(sp,sp),fr0 + .text + .global ldhfu +ldhfu: + ldhfu @(sp,sp),fr0 + .text + .global ldfu +ldfu: + ldfu @(sp,sp),fr0 + .text + .global ldcu +ldcu: + ldcu @(sp,sp),cpr0 + .text + .global nldbfu +nldbfu: + nldbfu @(sp,sp),fr0 + .text + .global nldhfu +nldhfu: + nldhfu @(sp,sp),fr0 + .text + .global nldfu +nldfu: + nldfu @(sp,sp),fr0 + .text + .global lddu +lddu: + lddu @(sp,sp),sp + .text + .global nlddu +nlddu: + nlddu @(sp,sp),sp + .text + .global lddfu +lddfu: + lddfu @(sp,sp),fr0 + .text + .global lddcu +lddcu: + lddcu @(sp,sp),cpr0 + .text + .global nlddfu +nlddfu: + nlddfu @(sp,sp),fr0 + .text + .global ldqu +ldqu: + ldqu @(sp,sp),sp + .text + .global nldqu +nldqu: + nldqu @(sp,sp),sp + .text + .global ldqfu +ldqfu: + ldqfu @(sp,sp),fr0 + .text + .global ldqcu +ldqcu: + ldqcu @(sp,sp),cpr0 + .text + .global nldqfu +nldqfu: + nldqfu @(sp,sp),fr0 + .text + .global ldsbi +ldsbi: + ldsbi @(sp,0),sp + .text + .global ldshi +ldshi: + ldshi @(sp,0),sp + .text + .global ldi +ldi: + ldi @(sp,0),sp + .text + .global ldubi +ldubi: + ldubi @(sp,0),sp + .text + .global lduhi +lduhi: + lduhi @(sp,0),sp + .text + .global ldbfi +ldbfi: + ldbfi @(sp,0),fr0 + .text + .global ldhfi +ldhfi: + ldhfi @(sp,0),fr0 + .text + .global ldfi +ldfi: + ldfi @(sp,0),fr0 + .text + .global nldsbi +nldsbi: + nldsbi @(sp,0),sp + .text + .global nldubi +nldubi: + nldubi @(sp,0),sp + .text + .global nldshi +nldshi: + nldshi @(sp,0),sp + .text + .global nlduhi +nlduhi: + nlduhi @(sp,0),sp + .text + .global nldi +nldi: + nldi @(sp,0),sp + .text + .global nldbfi +nldbfi: + nldbfi @(sp,0),fr0 + .text + .global nldhfi +nldhfi: + nldhfi @(sp,0),fr0 + .text + .global nldfi +nldfi: + nldfi @(sp,0),fr0 + .text + .global lddi +lddi: + lddi @(sp,0),sp + .text + .global lddfi +lddfi: + lddfi @(sp,0),fr0 + .text + .global nlddi +nlddi: + nlddi @(sp,0),sp + .text + .global nlddfi +nlddfi: + nlddfi @(sp,0),fr0 + .text + .global ldqi +ldqi: + ldqi @(sp,0),sp + .text + .global ldqfi +ldqfi: + ldqfi @(sp,0),fr0 + .text + .global nldqi +nldqi: + nldqi @(sp,0),sp + .text + .global nldqfi +nldqfi: + nldqfi @(sp,0),fr0 + .text + .global stb +stb: + stb sp,@(sp,sp) + .text + .global sth +sth: + sth sp,@(sp,sp) + .text + .global st +st: + st sp,@(sp,sp) + .text + .global stbf +stbf: + stbf fr0,@(sp,sp) + .text + .global sthf +sthf: + sthf fr0,@(sp,sp) + .text + .global stf +stf: + stf fr0,@(sp,sp) + .text + .global stc +stc: + stc cpr0,@(sp,sp) + .text + .global rstb +rstb: + rstb sp,@(sp,sp) + .text + .global rsth +rsth: + rsth sp,@(sp,sp) + .text + .global rst +rst: + rst sp,@(sp,sp) + .text + .global rstbf +rstbf: + rstbf fr0,@(sp,sp) + .text + .global rsthf +rsthf: + rsthf fr0,@(sp,sp) + .text + .global rstf +rstf: + rstf fr0,@(sp,sp) + .text + .global std +std: + std sp,@(sp,sp) + .text + .global stdf +stdf: + stdf fr0,@(sp,sp) + .text + .global stdc +stdc: + stdc cpr0,@(sp,sp) + .text + .global rstd +rstd: + rstd sp,@(sp,sp) + .text + .global rstdf +rstdf: + rstdf fr0,@(sp,sp) + .text + .global stq +stq: + stq sp,@(sp,sp) + .text + .global stqf +stqf: + stqf fr0,@(sp,sp) + .text + .global stqc +stqc: + stqc cpr0,@(sp,sp) + .text + .global rstq +rstq: + rstq sp,@(sp,sp) + .text + .global rstqf +rstqf: + rstqf fr0,@(sp,sp) + .text + .global stbu +stbu: + stbu sp,@(sp,sp) + .text + .global sthu +sthu: + sthu sp,@(sp,sp) + .text + .global stu +stu: + stu sp,@(sp,sp) + .text + .global stbfu +stbfu: + stbfu fr0,@(sp,sp) + .text + .global sthfu +sthfu: + sthfu fr0,@(sp,sp) + .text + .global stfu +stfu: + stfu fr0,@(sp,sp) + .text + .global stcu +stcu: + stcu cpr0,@(sp,sp) + .text + .global stdu +stdu: + stdu sp,@(sp,sp) + .text + .global stdfu +stdfu: + stdfu fr0,@(sp,sp) + .text + .global stdcu +stdcu: + stdcu cpr0,@(sp,sp) + .text + .global stqu +stqu: + stqu sp,@(sp,sp) + .text + .global stqfu +stqfu: + stqfu fr0,@(sp,sp) + .text + .global stqcu +stqcu: + stqcu cpr0,@(sp,sp) + .text + .global cldsb +cldsb: + cldsb @(sp,sp),sp,cc0,0 + .text + .global cldub +cldub: + cldub @(sp,sp),sp,cc0,0 + .text + .global cldsh +cldsh: + cldsh @(sp,sp),sp,cc0,0 + .text + .global clduh +clduh: + clduh @(sp,sp),sp,cc0,0 + .text + .global cld +cld: + cld @(sp,sp),sp,cc0,0 + .text + .global cldbf +cldbf: + cldbf @(sp,sp),fr0,cc0,0 + .text + .global cldhf +cldhf: + cldhf @(sp,sp),fr0,cc0,0 + .text + .global cldf +cldf: + cldf @(sp,sp),fr0,cc0,0 + .text + .global cldd +cldd: + cldd @(sp,sp),sp,cc0,0 + .text + .global clddf +clddf: + clddf @(sp,sp),fr0,cc0,0 + .text + .global cldq +cldq: + cldq @(sp,sp),sp,cc0,0 + .text + .global cldsbu +cldsbu: + cldsbu @(sp,sp),sp,cc0,0 + .text + .global cldubu +cldubu: + cldubu @(sp,sp),sp,cc0,0 + .text + .global cldshu +cldshu: + cldshu @(sp,sp),sp,cc0,0 + .text + .global clduhu +clduhu: + clduhu @(sp,sp),sp,cc0,0 + .text + .global cldu +cldu: + cldu @(sp,sp),sp,cc0,0 + .text + .global cldbfu +cldbfu: + cldbfu @(sp,sp),fr0,cc0,0 + .text + .global cldhfu +cldhfu: + cldhfu @(sp,sp),fr0,cc0,0 + .text + .global cldfu +cldfu: + cldfu @(sp,sp),fr0,cc0,0 + .text + .global clddu +clddu: + clddu @(sp,sp),sp,cc0,0 + .text + .global clddfu +clddfu: + clddfu @(sp,sp),fr0,cc0,0 + .text + .global cldqu +cldqu: + cldqu @(sp,sp),sp,cc0,0 + .text + .global cstb +cstb: + cstb sp,@(sp,sp),cc0,0 + .text + .global csth +csth: + csth sp,@(sp,sp),cc0,0 + .text + .global cst +cst: + cst sp,@(sp,sp),cc0,0 + .text + .global cstbf +cstbf: + cstbf fr0,@(sp,sp),cc0,0 + .text + .global csthf +csthf: + csthf fr0,@(sp,sp),cc0,0 + .text + .global cstf +cstf: + cstf fr0,@(sp,sp),cc0,0 + .text + .global cstd +cstd: + cstd sp,@(sp,sp),cc0,0 + .text + .global cstdf +cstdf: + cstdf fr0,@(sp,sp),cc0,0 + .text + .global cstq +cstq: + cstq sp,@(sp,sp),cc0,0 + .text + .global cstbu +cstbu: + cstbu sp,@(sp,sp),cc0,0 + .text + .global csthu +csthu: + csthu sp,@(sp,sp),cc0,0 + .text + .global cstu +cstu: + cstu sp,@(sp,sp),cc0,0 + .text + .global cstbfu +cstbfu: + cstbfu fr0,@(sp,sp),cc0,0 + .text + .global csthfu +csthfu: + csthfu fr0,@(sp,sp),cc0,0 + .text + .global cstfu +cstfu: + cstfu fr0,@(sp,sp),cc0,0 + .text + .global cstdu +cstdu: + cstdu sp,@(sp,sp),cc0,0 + .text + .global cstdfu +cstdfu: + cstdfu fr0,@(sp,sp),cc0,0 + .text + .global stbi +stbi: + stbi sp,@(sp,0) + .text + .global sthi +sthi: + sthi sp,@(sp,0) + .text + .global sti +sti: + sti sp,@(sp,0) + .text + .global stbfi +stbfi: + stbfi fr0,@(sp,0) + .text + .global sthfi +sthfi: + sthfi fr0,@(sp,0) + .text + .global stfi +stfi: + stfi fr0,@(sp,0) + .text + .global stdi +stdi: + stdi sp,@(sp,0) + .text + .global stdfi +stdfi: + stdfi fr0,@(sp,0) + .text + .global stqi +stqi: + stqi sp,@(sp,0) + .text + .global stqfi +stqfi: + stqfi fr0,@(sp,0) + .text + .global swap +swap: + swap @(sp,sp),sp + .text + .global swapi +swapi: + swapi @(sp,0),sp + .text + .global cswap +cswap: + cswap @(sp,sp),sp,cc0,0 + .text + .global movgf +movgf: + movgf sp,fr0 + .text + .global movfg +movfg: + movfg fr0,sp + .text + .global movgfd +movgfd: + movgfd sp,fr0 + .text + .global movfgd +movfgd: + movfgd fr0,sp + .text + .global movgfq +movgfq: + movgfq sp,fr0 + .text + .global movfgq +movfgq: + movfgq fr0,sp + .text + .global cmovgf +cmovgf: + cmovgf sp,fr0,cc0,0 + .text + .global cmovfg +cmovfg: + cmovfg fr0,sp,cc0,0 + .text + .global cmovgfd +cmovgfd: + cmovgfd sp,fr0,cc0,0 + .text + .global cmovfgd +cmovfgd: + cmovfgd fr0,sp,cc0,0 + .text + .global movgs +movgs: + movgs sp,psr + .text + .global movsg +movsg: + movsg psr,sp + .text + .global bno +bno: + bno + .text + .global bra +bra: + bra footext + .text + .global beq +beq: + beq icc0,0,footext + .text + .global bne +bne: + bne icc0,0,footext + .text + .global ble +ble: + ble icc0,0,footext + .text + .global bgt +bgt: + bgt icc0,0,footext + .text + .global blt +blt: + blt icc0,0,footext + .text + .global bge +bge: + bge icc0,0,footext + .text + .global bls +bls: + bls icc0,0,footext + .text + .global bhi +bhi: + bhi icc0,0,footext + .text + .global bc +bc: + bc icc0,0,footext + .text + .global bnc +bnc: + bnc icc0,0,footext + .text + .global bn +bn: + bn icc0,0,footext + .text + .global bp +bp: + bp icc0,0,footext + .text + .global bv +bv: + bv icc0,0,footext + .text + .global bnv +bnv: + bnv icc0,0,footext + .text + .global fbno +fbno: + fbno + .text + .global fbra +fbra: + fbra footext + .text + .global fbne +fbne: + fbne fcc0,0,footext + .text + .global fbeq +fbeq: + fbeq fcc0,0,footext + .text + .global fblg +fblg: + fblg fcc0,0,footext + .text + .global fbue +fbue: + fbue fcc0,0,footext + .text + .global fbul +fbul: + fbul fcc0,0,footext + .text + .global fbge +fbge: + fbge fcc0,0,footext + .text + .global fblt +fblt: + fblt fcc0,0,footext + .text + .global fbuge +fbuge: + fbuge fcc0,0,footext + .text + .global fbug +fbug: + fbug fcc0,0,footext + .text + .global fble +fble: + fble fcc0,0,footext + .text + .global fbgt +fbgt: + fbgt fcc0,0,footext + .text + .global fbule +fbule: + fbule fcc0,0,footext + .text + .global fbu +fbu: + fbu fcc0,0,footext + .text + .global fbo +fbo: + fbo fcc0,0,footext + .text + .global bctrlr +bctrlr: + bctrlr 0,0 + .text + .global bnolr +bnolr: + bnolr + .text + .global bralr +bralr: + bralr + .text + .global beqlr +beqlr: + beqlr icc0,0 + .text + .global bnelr +bnelr: + bnelr icc0,0 + .text + .global blelr +blelr: + blelr icc0,0 + .text + .global bgtlr +bgtlr: + bgtlr icc0,0 + .text + .global bltlr +bltlr: + bltlr icc0,0 + .text + .global bgelr +bgelr: + bgelr icc0,0 + .text + .global blslr +blslr: + blslr icc0,0 + .text + .global bhilr +bhilr: + bhilr icc0,0 + .text + .global bclr +bclr: + bclr icc0,0 + .text + .global bnclr +bnclr: + bnclr icc0,0 + .text + .global bnlr +bnlr: + bnlr icc0,0 + .text + .global bplr +bplr: + bplr icc0,0 + .text + .global bvlr +bvlr: + bvlr icc0,0 + .text + .global bnvlr +bnvlr: + bnvlr icc0,0 + .text + .global fbnolr +fbnolr: + fbnolr + .text + .global fbralr +fbralr: + fbralr + .text + .global fbeqlr +fbeqlr: + fbeqlr fcc0,0 + .text + .global fbnelr +fbnelr: + fbnelr fcc0,0 + .text + .global fblglr +fblglr: + fblglr fcc0,0 + .text + .global fbuelr +fbuelr: + fbuelr fcc0,0 + .text + .global fbullr +fbullr: + fbullr fcc0,0 + .text + .global fbgelr +fbgelr: + fbgelr fcc0,0 + .text + .global fbltlr +fbltlr: + fbltlr fcc0,0 + .text + .global fbugelr +fbugelr: + fbugelr fcc0,0 + .text + .global fbuglr +fbuglr: + fbuglr fcc0,0 + .text + .global fblelr +fblelr: + fblelr fcc0,0 + .text + .global fbgtlr +fbgtlr: + fbgtlr fcc0,0 + .text + .global fbulelr +fbulelr: + fbulelr fcc0,0 + .text + .global fbulr +fbulr: + fbulr fcc0,0 + .text + .global fbolr +fbolr: + fbolr fcc0,0 + .text + .global bcnolr +bcnolr: + bcnolr + .text + .global bcralr +bcralr: + bcralr 0 + .text + .global bceqlr +bceqlr: + bceqlr icc0,0,0 + .text + .global bcnelr +bcnelr: + bcnelr icc0,0,0 + .text + .global bclelr +bclelr: + bclelr icc0,0,0 + .text + .global bcgtlr +bcgtlr: + bcgtlr icc0,0,0 + .text + .global bcltlr +bcltlr: + bcltlr icc0,0,0 + .text + .global bcgelr +bcgelr: + bcgelr icc0,0,0 + .text + .global bclslr +bclslr: + bclslr icc0,0,0 + .text + .global bchilr +bchilr: + bchilr icc0,0,0 + .text + .global bcclr +bcclr: + bcclr icc0,0,0 + .text + .global bcnclr +bcnclr: + bcnclr icc0,0,0 + .text + .global bcnlr +bcnlr: + bcnlr icc0,0,0 + .text + .global bcplr +bcplr: + bcplr icc0,0,0 + .text + .global bcvlr +bcvlr: + bcvlr icc0,0,0 + .text + .global bcnvlr +bcnvlr: + bcnvlr icc0,0,0 + .text + .global fcbnolr +fcbnolr: + fcbnolr + .text + .global fcbralr +fcbralr: + fcbralr 0 + .text + .global fcbeqlr +fcbeqlr: + fcbeqlr fcc0,0,0 + .text + .global fcbnelr +fcbnelr: + fcbnelr fcc0,0,0 + .text + .global fcblglr +fcblglr: + fcblglr fcc0,0,0 + .text + .global fcbuelr +fcbuelr: + fcbuelr fcc0,0,0 + .text + .global fcbullr +fcbullr: + fcbullr fcc0,0,0 + .text + .global fcbgelr +fcbgelr: + fcbgelr fcc0,0,0 + .text + .global fcbltlr +fcbltlr: + fcbltlr fcc0,0,0 + .text + .global fcbugelr +fcbugelr: + fcbugelr fcc0,0,0 + .text + .global fcbuglr +fcbuglr: + fcbuglr fcc0,0,0 + .text + .global fcblelr +fcblelr: + fcblelr fcc0,0,0 + .text + .global fcbgtlr +fcbgtlr: + fcbgtlr fcc0,0,0 + .text + .global fcbulelr +fcbulelr: + fcbulelr fcc0,0,0 + .text + .global fcbulr +fcbulr: + fcbulr fcc0,0,0 + .text + .global fcbolr +fcbolr: + fcbolr fcc0,0,0 + .text + .global jmpl +jmpl: + jmpl @(sp,sp) + .text + .global jmpil +jmpil: + jmpil @(sp,0) + .text + .global call +call: + call footext + .text + .global rett +rett: + .text + .global rei +rei: + rei 0 + .text + .global tno +tno: + tno + .text + .global tra +tra: + tra sp,sp + .text + .global teq +teq: + teq icc0,sp,sp + .text + .global tne +tne: + tne icc0,sp,sp + .text + .global tle +tle: + tle icc0,sp,sp + .text + .global tgt +tgt: + tgt icc0,sp,sp + .text + .global tlt +tlt: + tlt icc0,sp,sp + .text + .global tge +tge: + tge icc0,sp,sp + .text + .global tls +tls: + tls icc0,sp,sp + .text + .global thi +thi: + thi icc0,sp,sp + .text + .global tc +tc: + tc icc0,sp,sp + .text + .global tnc +tnc: + tnc icc0,sp,sp + .text + .global tn +tn: + tn icc0,sp,sp + .text + .global tp +tp: + tp icc0,sp,sp + .text + .global tv +tv: + tv icc0,sp,sp + .text + .global tnv +tnv: + tnv icc0,sp,sp + .text + .global ftno +ftno: + ftno + .text + .global ftra +ftra: + ftra sp,sp + .text + .global ftne +ftne: + ftne fcc0,sp,sp + .text + .global fteq +fteq: + fteq fcc0,sp,sp + .text + .global ftlg +ftlg: + ftlg fcc0,sp,sp + .text + .global ftue +ftue: + ftue fcc0,sp,sp + .text + .global ftul +ftul: + ftul fcc0,sp,sp + .text + .global ftge +ftge: + ftge fcc0,sp,sp + .text + .global ftlt +ftlt: + ftlt fcc0,sp,sp + .text + .global ftuge +ftuge: + ftuge fcc0,sp,sp + .text + .global ftug +ftug: + ftug fcc0,sp,sp + .text + .global ftle +ftle: + ftle fcc0,sp,sp + .text + .global ftgt +ftgt: + ftgt fcc0,sp,sp + .text + .global ftule +ftule: + ftule fcc0,sp,sp + .text + .global ftu +ftu: + ftu fcc0,sp,sp + .text + .global fto +fto: + fto fcc0,sp,sp + .text + .global tino +tino: + tino + .text + .global tira +tira: + tira sp,0 + .text + .global tieq +tieq: + tieq icc0,sp,0 + .text + .global tine +tine: + tine icc0,sp,0 + .text + .global tile +tile: + tile icc0,sp,0 + .text + .global tigt +tigt: + tigt icc0,sp,0 + .text + .global tilt +tilt: + tilt icc0,sp,0 + .text + .global tige +tige: + tige icc0,sp,0 + .text + .global tils +tils: + tils icc0,sp,0 + .text + .global tihi +tihi: + tihi icc0,sp,0 + .text + .global tic +tic: + tic icc0,sp,0 + .text + .global tinc +tinc: + tinc icc0,sp,0 + .text + .global tin +tin: + tin icc0,sp,0 + .text + .global tip +tip: + tip icc0,sp,0 + .text + .global tiv +tiv: + tiv icc0,sp,0 + .text + .global tinv +tinv: + tinv icc0,sp,0 + .text + .global ftino +ftino: + ftino + .text + .global ftira +ftira: + ftira sp,0 + .text + .global ftine +ftine: + ftine fcc0,sp,0 + .text + .global ftieq +ftieq: + ftieq fcc0,sp,0 + .text + .global ftilg +ftilg: + ftilg fcc0,sp,0 + .text + .global ftiue +ftiue: + ftiue fcc0,sp,0 + .text + .global ftiul +ftiul: + ftiul fcc0,sp,0 + .text + .global ftige +ftige: + ftige fcc0,sp,0 + .text + .global ftilt +ftilt: + ftilt fcc0,sp,0 + .text + .global ftiuge +ftiuge: + ftiuge fcc0,sp,0 + .text + .global ftiug +ftiug: + ftiug fcc0,sp,0 + .text + .global ftile +ftile: + ftile fcc0,sp,0 + .text + .global ftigt +ftigt: + ftigt fcc0,sp,0 + .text + .global ftiule +ftiule: + ftiule fcc0,sp,0 + .text + .global ftiu +ftiu: + ftiu fcc0,sp,0 + .text + .global ftio +ftio: + ftio fcc0,sp,0 + .text + .global break +break: + .text + .global mtrap +mtrap: + .text + .global andcr +andcr: + andcr cc0,cc0,cc0 + .text + .global orcr +orcr: + orcr cc0,cc0,cc0 + .text + .global xorcr +xorcr: + xorcr cc0,cc0,cc0 + .text + .global nandcr +nandcr: + nandcr cc0,cc0,cc0 + .text + .global norcr +norcr: + norcr cc0,cc0,cc0 + .text + .global andncr +andncr: + andncr cc0,cc0,cc0 + .text + .global orncr +orncr: + orncr cc0,cc0,cc0 + .text + .global nandncr +nandncr: + nandncr cc0,cc0,cc0 + .text + .global norncr +norncr: + norncr cc0,cc0,cc0 + .text + .global notcr +notcr: + notcr cc0,cc0 + .text + .global ckno +ckno: + ckno cc7 + .text + .global ckra +ckra: + ckra cc7 + .text + .global ckeq +ckeq: + ckeq icc0,cc7 + .text + .global ckne +ckne: + ckne icc0,cc7 + .text + .global ckle +ckle: + ckle icc0,cc7 + .text + .global ckgt +ckgt: + ckgt icc0,cc7 + .text + .global cklt +cklt: + cklt icc0,cc7 + .text + .global ckge +ckge: + ckge icc0,cc7 + .text + .global ckls +ckls: + ckls icc0,cc7 + .text + .global ckhi +ckhi: + ckhi icc0,cc7 + .text + .global ckc +ckc: + ckc icc0,cc7 + .text + .global cknc +cknc: + cknc icc0,cc7 + .text + .global ckn +ckn: + ckn icc0,cc7 + .text + .global ckp +ckp: + ckp icc0,cc7 + .text + .global ckv +ckv: + ckv icc0,cc7 + .text + .global cknv +cknv: + cknv icc0,cc7 + .text + .global fckno +fckno: + fckno cc0 + .text + .global fckra +fckra: + fckra cc0 + .text + .global fckne +fckne: + fckne fcc0,cc0 + .text + .global fckeq +fckeq: + fckeq fcc0,cc0 + .text + .global fcklg +fcklg: + fcklg fcc0,cc0 + .text + .global fckue +fckue: + fckue fcc0,cc0 + .text + .global fckul +fckul: + fckul fcc0,cc0 + .text + .global fckge +fckge: + fckge fcc0,cc0 + .text + .global fcklt +fcklt: + fcklt fcc0,cc0 + .text + .global fckuge +fckuge: + fckuge fcc0,cc0 + .text + .global fckug +fckug: + fckug fcc0,cc0 + .text + .global fckle +fckle: + fckle fcc0,cc0 + .text + .global fckgt +fckgt: + fckgt fcc0,cc0 + .text + .global fckule +fckule: + fckule fcc0,cc0 + .text + .global fcku +fcku: + fcku fcc0,cc0 + .text + .global fcko +fcko: + fcko fcc0,cc0 + .text + .global cckno +cckno: + cckno cc7,cc3,0 + .text + .global cckra +cckra: + cckra cc7,cc3,0 + .text + .global cckeq +cckeq: + cckeq icc0,cc7,cc3,0 + .text + .global cckne +cckne: + cckne icc0,cc7,cc3,0 + .text + .global cckle +cckle: + cckle icc0,cc7,cc3,0 + .text + .global cckgt +cckgt: + cckgt icc0,cc7,cc3,0 + .text + .global ccklt +ccklt: + ccklt icc0,cc7,cc3,0 + .text + .global cckge +cckge: + cckge icc0,cc7,cc3,0 + .text + .global cckls +cckls: + cckls icc0,cc7,cc3,0 + .text + .global cckhi +cckhi: + cckhi icc0,cc7,cc3,0 + .text + .global cckc +cckc: + cckc icc0,cc7,cc3,0 + .text + .global ccknc +ccknc: + ccknc icc0,cc7,cc3,0 + .text + .global cckn +cckn: + cckn icc0,cc7,cc3,0 + .text + .global cckp +cckp: + cckp icc0,cc7,cc3,0 + .text + .global cckv +cckv: + cckv icc0,cc7,cc3,0 + .text + .global ccknv +ccknv: + ccknv icc0,cc7,cc3,0 + .text + .global cfckno +cfckno: + cfckno cc0,cc0,0 + .text + .global cfckra +cfckra: + cfckra cc0,cc0,0 + .text + .global cfckne +cfckne: + cfckne fcc0,cc0,cc0,0 + .text + .global cfckeq +cfckeq: + cfckeq fcc0,cc0,cc0,0 + .text + .global cfcklg +cfcklg: + cfcklg fcc0,cc0,cc0,0 + .text + .global cfckue +cfckue: + cfckue fcc0,cc0,cc0,0 + .text + .global cfckul +cfckul: + cfckul fcc0,cc0,cc0,0 + .text + .global cfckge +cfckge: + cfckge fcc0,cc0,cc0,0 + .text + .global cfcklt +cfcklt: + cfcklt fcc0,cc0,cc0,0 + .text + .global cfckuge +cfckuge: + cfckuge fcc0,cc0,cc0,0 + .text + .global cfckug +cfckug: + cfckug fcc0,cc0,cc0,0 + .text + .global cfckle +cfckle: + cfckle fcc0,cc0,cc0,0 + .text + .global cfckgt +cfckgt: + cfckgt fcc0,cc0,cc0,0 + .text + .global cfckule +cfckule: + cfckule fcc0,cc0,cc0,0 + .text + .global cfcku +cfcku: + cfcku fcc0,cc0,cc0,0 + .text + .global cfcko +cfcko: + cfcko fcc0,cc0,cc0,0 + .text + .global cjmpl +cjmpl: + cjmpl @(sp,sp),cc0,0 + .text + .global ici +ici: + ici @(sp,sp) + .text + .global dci +dci: + dci @(sp,sp) + .text + .global dcf +dcf: + dcf @(sp,sp) + .text + .global witlb +witlb: + witlb sp,@(sp,sp) + .text + .global wdtlb +wdtlb: + wdtlb sp,@(sp,sp) + .text + .global itlbi +itlbi: + itlbi @(sp,sp) + .text + .global dtlbi +dtlbi: + dtlbi @(sp,sp) + .text + .global icpl +icpl: + icpl sp,sp,0 + .text + .global dcpl +dcpl: + dcpl sp,sp,0 + .text + .global icul +icul: + icul sp + .text + .global dcul +dcul: + dcul sp + .text + .global bar +bar: + .text + .global membar +membar: + .text + .global clrgr +clrgr: + clrgr sp + .text + .global clrfr +clrfr: + clrfr fr0 + .text + .global clrga +clrga: + .text + .global clrfa +clrfa: + .text + .global commitgr +commitgr: + commitgr sp + .text + .global commitfr +commitfr: + commitfr fr0 + .text + .global commitgra +commitgra: + .text + .global commitfra +commitfra: + .text + .global fitos +fitos: + fitos fr0,fr0 + .text + .global fstoi +fstoi: + fstoi fr0,fr0 + .text + .global fitod +fitod: + fitod fr0,fr0 + .text + .global fdtoi +fdtoi: + fdtoi fr0,fr0 + .text + .global fmovs +fmovs: + fmovs fr0,fr0 + .text + .global fmovd +fmovd: + fmovd fr0,fr0 + .text + .global fnegs +fnegs: + fnegs fr0,fr0 + .text + .global fnegd +fnegd: + fnegd fr0,fr0 + .text + .global fabss +fabss: + fabss fr0,fr0 + .text + .global fabsd +fabsd: + fabsd fr0,fr0 + .text + .global fsqrts +fsqrts: + fsqrts fr0,fr0 + .text + .global fsqrtd +fsqrtd: + fsqrtd fr0,fr0 + .text + .global fadds +fadds: + fadds fr0,fr0,fr0 + .text + .global fsubs +fsubs: + fsubs fr0,fr0,fr0 + .text + .global fmuls +fmuls: + fmuls fr0,fr0,fr0 + .text + .global fdivs +fdivs: + fdivs fr0,fr0,fr0 + .text + .global faddd +faddd: + faddd fr0,fr0,fr0 + .text + .global fsubd +fsubd: + fsubd fr0,fr0,fr0 + .text + .global fmuld +fmuld: + fmuld fr0,fr0,fr0 + .text + .global fdivd +fdivd: + fdivd fr0,fr0,fr0 + .text + .global fcmps +fcmps: + fcmps fr0,fr0,fcc0 + .text + .global fcmpd +fcmpd: + fcmpd fr0,fr0,fcc0 + .text + .global fmadds +fmadds: + fmadds fr0,fr0,fr0 + .text + .global fmsubs +fmsubs: + fmsubs fr0,fr0,fr0 + .text + .global fmaddd +fmaddd: + fmaddd fr0,fr0,fr0 + .text + .global fmsubd +fmsubd: + fmsubd fr0,fr0,fr0 + .text + .global mand +mand: + mand fr0,fr0,fr0 + .text + .global mor +mor: + mor fr0,fr0,fr0 + .text + .global mxor +mxor: + mxor fr0,fr0,fr0 + .text + .global mnot +mnot: + mnot fr0,fr0 + .text + .global mrotli +mrotli: + mrotli fr0,0,fr0 + .text + .global mrotri +mrotri: + mrotri fr0,0,fr0 + .text + .global mwcut +mwcut: + mwcut fr0,fr0,fr0 + .text + .global mwcuti +mwcuti: + mwcuti fr0,0,fr0 diff -uprN binutils-2.12.90.0.11/gas/testsuite/gas/mips/lineno.d binutils-2.12.90.0.12/gas/testsuite/gas/mips/lineno.d --- binutils-2.12.90.0.11/gas/testsuite/gas/mips/lineno.d Fri Jul 6 09:26:11 2001 +++ binutils-2.12.90.0.12/gas/testsuite/gas/mips/lineno.d Tue Jun 18 21:41:59 2002 @@ -1,6 +1,6 @@ #objdump: -d -l -mmips:4000 #name: assembly line numbers -#as: -g -march=r4000 +#as: --gstabs -march=r4000 .*: +file format .*mips.* diff -uprN binutils-2.12.90.0.11/gas/testsuite/gas/mips/mips.exp binutils-2.12.90.0.12/gas/testsuite/gas/mips/mips.exp --- binutils-2.12.90.0.11/gas/testsuite/gas/mips/mips.exp Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/gas/testsuite/gas/mips/mips.exp Tue Jun 18 21:41:59 2002 @@ -145,8 +145,6 @@ if { [istarget mips*-*-*] } then { run_dump_test "mips4650" run_dump_test "mips4100" run_dump_test "perfcount" - # Linux uses ELF stabs, which doesn't support line number. - setup_xfail "mips*-*-*linux*" run_dump_test "lineno" run_dump_test "sync" run_dump_test "mips32" diff -uprN binutils-2.12.90.0.11/gas/testsuite/gas/ppc/aix.exp binutils-2.12.90.0.12/gas/testsuite/gas/ppc/aix.exp --- binutils-2.12.90.0.11/gas/testsuite/gas/ppc/aix.exp Wed Jun 20 12:19:37 2001 +++ binutils-2.12.90.0.12/gas/testsuite/gas/ppc/aix.exp Tue Jun 18 21:41:59 2002 @@ -1,4 +1,4 @@ -# Copyright (C) 2001 Free Software Foundation, Inc. +# Copyright (C) 2001, 2002 Free Software Foundation, Inc. # Contributed by Red Hat # This program is free software; you can redistribute it and/or modify @@ -56,8 +56,11 @@ proc do_align_test {} { } -if [istarget powerpc*-*-aix4.3*] then { +if [istarget powerpc-ibm-aix*] then { # Make sure that symbols are correctly aligned do_align_test + + run_dump_test "textalign-xcoff-001" + run_dump_test "textalign-xcoff-002" } diff -uprN binutils-2.12.90.0.11/gas/testsuite/gas/ppc/booke_xcoff.d binutils-2.12.90.0.12/gas/testsuite/gas/ppc/booke_xcoff.d --- binutils-2.12.90.0.11/gas/testsuite/gas/ppc/booke_xcoff.d Thu Mar 7 11:52:38 2002 +++ binutils-2.12.90.0.12/gas/testsuite/gas/ppc/booke_xcoff.d Tue Jun 18 21:41:59 2002 @@ -26,5 +26,4 @@ Disassembly of section .text: 40: 7c 00 04 ac sync 44: 7c 09 55 ec dcba r9,r10 48: 7c 00 06 ac eieio - 4c: 00 00 00 00 .long 0x0 Disassembly of section .data: diff -uprN binutils-2.12.90.0.11/gas/testsuite/gas/ppc/test1xcoff32.d binutils-2.12.90.0.12/gas/testsuite/gas/ppc/test1xcoff32.d --- binutils-2.12.90.0.11/gas/testsuite/gas/ppc/test1xcoff32.d Mon Aug 27 11:44:52 2001 +++ binutils-2.12.90.0.12/gas/testsuite/gas/ppc/test1xcoff32.d Tue Jun 18 21:41:59 2002 @@ -10,7 +10,7 @@ start address 0x0+0000 Sections: Idx Name +Size +VMA +LMA +File off +Algn - 0 \.text +00000068 0+0000 0+0000 000000a8 2\*\*3 + 0 \.text +00000068 0+0000 0+0000 000000a8 2\*\*2 +CONTENTS, ALLOC, LOAD, RELOC, CODE 1 \.data +00000028 0+0068 0+0068 00000110 2\*\*3 +CONTENTS, ALLOC, LOAD, RELOC, DATA diff -uprN binutils-2.12.90.0.11/gas/testsuite/gas/ppc/textalign-xcoff-001.d binutils-2.12.90.0.12/gas/testsuite/gas/ppc/textalign-xcoff-001.d --- binutils-2.12.90.0.11/gas/testsuite/gas/ppc/textalign-xcoff-001.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/gas/testsuite/gas/ppc/textalign-xcoff-001.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,14 @@ +#objdump: -h +#source: textalign-xcoff-001.s +#as: + +.*: file format aixcoff-rs6000 + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.text 00000004 0000000000000000 0000000000000000 000000a8 2\*\*2 + CONTENTS, ALLOC, LOAD, CODE + 1 \.data 00000008 0000000000000004 0000000000000004 000000ac 2\*\*3 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 2 \.bss 00000000 000000000000000c 000000000000000c 00000000 2\*\*3 + ALLOC diff -uprN binutils-2.12.90.0.11/gas/testsuite/gas/ppc/textalign-xcoff-001.s binutils-2.12.90.0.12/gas/testsuite/gas/ppc/textalign-xcoff-001.s --- binutils-2.12.90.0.11/gas/testsuite/gas/ppc/textalign-xcoff-001.s Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/gas/testsuite/gas/ppc/textalign-xcoff-001.s Tue Jun 18 21:41:59 2002 @@ -0,0 +1,11 @@ + .globl __start + .globl .__start + +__start: + .csect .data[DS] + .long .__start + + .csect .text[pr] +.__start: + nop + \ No newline at end of file diff -uprN binutils-2.12.90.0.11/gas/testsuite/gas/ppc/textalign-xcoff-002.d binutils-2.12.90.0.12/gas/testsuite/gas/ppc/textalign-xcoff-002.d --- binutils-2.12.90.0.11/gas/testsuite/gas/ppc/textalign-xcoff-002.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/gas/testsuite/gas/ppc/textalign-xcoff-002.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,14 @@ +#objdump: -h +#source: textalign-xcoff-001.s +#as: -mppc64 -a64 + +.*: file format .*coff64-rs6000 + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.text 00000004 0000000000000000 0000000000000000 000000f0 2\*\*2 + CONTENTS, ALLOC, LOAD, CODE + 1 \.data 00000008 0000000000000004 0000000000000004 000000f4 2\*\*3 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 2 \.bss 00000000 000000000000000c 000000000000000c 00000000 2\*\*3 + ALLOC diff -uprN binutils-2.12.90.0.11/gas/testsuite/gas/sh/dsp.d binutils-2.12.90.0.12/gas/testsuite/gas/sh/dsp.d --- binutils-2.12.90.0.11/gas/testsuite/gas/sh/dsp.d Sun Feb 3 11:22:32 2002 +++ binutils-2.12.90.0.12/gas/testsuite/gas/sh/dsp.d Tue Jun 18 21:41:59 2002 @@ -22,3 +22,6 @@ Disassembly of section .text: 0+01a <[^>]*> f4 b7 [ ]*movs.l y1,@r4 0+01c <[^>]*> f7 cb [ ]*movs.l m0,@r3\+ 0+01e <[^>]*> f6 ef [ ]*movs.l m1,@r2\+r8 +0+020 <[^>]*> f8 00 b1 07 [ ]padd x0,y0,a0 +0+024 <[^>]*> f8 00 ed 07 [ ]plds a0,mach +0+028 <[^>]*> f8 00 b1 07 [ ]padd x0,y0,a0 diff -uprN binutils-2.12.90.0.11/gas/testsuite/gas/sh/dsp.s binutils-2.12.90.0.12/gas/testsuite/gas/sh/dsp.s --- binutils-2.12.90.0.11/gas/testsuite/gas/sh/dsp.s Mon Oct 15 21:27:23 2001 +++ binutils-2.12.90.0.12/gas/testsuite/gas/sh/dsp.s Tue Jun 18 21:41:59 2002 @@ -1,4 +1,4 @@ -# Test file for ARM/GAS -- basic instructions +# Test file for SH/GAS -- dsp instructions .text .align @@ -21,4 +21,7 @@ dsp_tests: movs.l y1, @r4 movs.l m0, @r3+ movs.l m1, @r2+r8 - \ No newline at end of file + + padd x0,y0,a0 + plds a0,mach + padd x0,y0,a0 diff -uprN binutils-2.12.90.0.11/include/ChangeLog binutils-2.12.90.0.12/include/ChangeLog --- binutils-2.12.90.0.11/include/ChangeLog Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/include/ChangeLog Tue Jun 18 21:41:59 2002 @@ -1,3 +1,13 @@ +2002-06-18 Dave Brolley + + From Catherine Moore: + * dis-asm.h (print_insn_frv): New prototype. + +2002-06-09 Andrew Cagney + + * remote-sim.h: Move to directory gdb/. + * callback.h: Move to directory gdb/. + 2002-06-07 Charles Wilson * bfdlink.h (struct bfd_link_info): Change type of diff -uprN binutils-2.12.90.0.11/include/callback.h binutils-2.12.90.0.12/include/callback.h --- binutils-2.12.90.0.11/include/callback.h Thu Jun 3 11:02:08 1999 +++ binutils-2.12.90.0.12/include/callback.h Wed Dec 31 16:00:00 1969 @@ -1,270 +0,0 @@ -/* Remote target system call callback support. - Copyright 1997 Free Software Foundation, Inc. - Contributed by Cygnus Solutions. - -This file is part of GDB. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* This interface isn't intended to be specific to any particular kind - of remote (hardware, simulator, whatever). As such, support for it - (e.g. sim/common/callback.c) should *not* live in the simulator source - tree, nor should it live in the gdb source tree. */ - -/* There are various ways to handle system calls: - - 1) Have a simulator intercept the appropriate trap instruction and - directly perform the system call on behalf of the target program. - This is the typical way of handling system calls for embedded targets. - [Handling system calls for embedded targets isn't that much of an - oxymoron as running compiler testsuites make use of the capability.] - - This method of system call handling is done when STATE_ENVIRONMENT - is ENVIRONMENT_USER. - - 2) Have a simulator emulate the hardware as much as possible. - If the program running on the real hardware communicates with some sort - of target manager, one would want to be able to run this program on the - simulator as well. - - This method of system call handling is done when STATE_ENVIRONMENT - is ENVIRONMENT_OPERATING. -*/ - -#ifndef CALLBACK_H -#define CALLBACK_H - -/* ??? The reason why we check for va_start here should be documented. */ - -#ifndef va_start -#include -#ifdef ANSI_PROTOTYPES -#include -#else -#include -#endif -#endif - -/* Mapping of host/target values. */ -/* ??? For debugging purposes, one might want to add a string of the - name of the symbol. */ - -typedef struct { - int host_val; - int target_val; -} CB_TARGET_DEFS_MAP; - -#define MAX_CALLBACK_FDS 10 - -/* Forward decl for stat/fstat. */ -struct stat; - -typedef struct host_callback_struct host_callback; - -struct host_callback_struct -{ - int (*close) PARAMS ((host_callback *,int)); - int (*get_errno) PARAMS ((host_callback *)); - int (*isatty) PARAMS ((host_callback *, int)); - int (*lseek) PARAMS ((host_callback *, int, long , int)); - int (*open) PARAMS ((host_callback *, const char*, int mode)); - int (*read) PARAMS ((host_callback *,int, char *, int)); - int (*read_stdin) PARAMS (( host_callback *, char *, int)); - int (*rename) PARAMS ((host_callback *, const char *, const char *)); - int (*system) PARAMS ((host_callback *, const char *)); - long (*time) PARAMS ((host_callback *, long *)); - int (*unlink) PARAMS ((host_callback *, const char *)); - int (*write) PARAMS ((host_callback *,int, const char *, int)); - int (*write_stdout) PARAMS ((host_callback *, const char *, int)); - void (*flush_stdout) PARAMS ((host_callback *)); - int (*write_stderr) PARAMS ((host_callback *, const char *, int)); - void (*flush_stderr) PARAMS ((host_callback *)); - int (*stat) PARAMS ((host_callback *, const char *, struct stat *)); - int (*fstat) PARAMS ((host_callback *, int, struct stat *)); - - /* When present, call to the client to give it the oportunity to - poll any io devices for a request to quit (indicated by a nonzero - return value). */ - int (*poll_quit) PARAMS ((host_callback *)); - - /* Used when the target has gone away, so we can close open - handles and free memory etc etc. */ - int (*shutdown) PARAMS ((host_callback *)); - int (*init) PARAMS ((host_callback *)); - - /* depreciated, use vprintf_filtered - Talk to the user on a console. */ - void (*printf_filtered) PARAMS ((host_callback *, const char *, ...)); - - /* Talk to the user on a console. */ - void (*vprintf_filtered) PARAMS ((host_callback *, const char *, va_list)); - - /* Same as vprintf_filtered but to stderr. */ - void (*evprintf_filtered) PARAMS ((host_callback *, const char *, va_list)); - - /* Print an error message and "exit". - In the case of gdb "exiting" means doing a longjmp back to the main - command loop. */ - void (*error) PARAMS ((host_callback *, const char *, ...)); - - int last_errno; /* host format */ - - int fdmap[MAX_CALLBACK_FDS]; - char fdopen[MAX_CALLBACK_FDS]; - char alwaysopen[MAX_CALLBACK_FDS]; - - /* System call numbers. */ - CB_TARGET_DEFS_MAP *syscall_map; - /* Errno values. */ - CB_TARGET_DEFS_MAP *errno_map; - /* Flags to the open system call. */ - CB_TARGET_DEFS_MAP *open_map; - /* Signal numbers. */ - CB_TARGET_DEFS_MAP *signal_map; - /* Layout of `stat' struct. - The format is a series of "name,length" pairs separated by colons. - Empty space is indicated with a `name' of "space". - All padding must be explicitly mentioned. - Lengths are in bytes. If this needs to be extended to bits, - use "name.bits". - Example: "st_dev,4:st_ino,4:st_mode,4:..." */ - const char *stat_map; - - /* Marker for those wanting to do sanity checks. - This should remain the last member of this struct to help catch - miscompilation errors. */ -#define HOST_CALLBACK_MAGIC 4705 /* teds constant */ - int magic; -}; - -extern host_callback default_callback; - -/* Canonical versions of system call numbers. - It's not intended to willy-nilly throw every system call ever heard - of in here. Only include those that have an important use. - ??? One can certainly start a discussion over the ones that are currently - here, but that will always be true. */ - -/* These are used by the ANSI C support of libc. */ -#define CB_SYS_exit 1 -#define CB_SYS_open 2 -#define CB_SYS_close 3 -#define CB_SYS_read 4 -#define CB_SYS_write 5 -#define CB_SYS_lseek 6 -#define CB_SYS_unlink 7 -#define CB_SYS_getpid 8 -#define CB_SYS_kill 9 -#define CB_SYS_fstat 10 -/*#define CB_SYS_sbrk 11 - not currently a system call, but reserved. */ - -/* ARGV support. */ -#define CB_SYS_argvlen 12 -#define CB_SYS_argv 13 - -/* These are extras added for one reason or another. */ -#define CB_SYS_chdir 14 -#define CB_SYS_stat 15 -#define CB_SYS_chmod 16 -#define CB_SYS_utime 17 -#define CB_SYS_time 18 - -/* Struct use to pass and return information necessary to perform a - system call. */ -/* FIXME: Need to consider target word size. */ - -typedef struct cb_syscall { - /* The target's value of what system call to perform. */ - int func; - /* The arguments to the syscall. */ - long arg1, arg2, arg3, arg4; - - /* The result. */ - long result; - /* Some system calls have two results. */ - long result2; - /* The target's errno value, or 0 if success. - This is converted to the target's value with host_to_target_errno. */ - int errcode; - - /* Working space to be used by memory read/write callbacks. */ - PTR p1; - PTR p2; - long x1,x2; - - /* Callbacks for reading/writing memory (e.g. for read/write syscalls). - ??? long or unsigned long might be better to use for the `count' - argument here. We mimic sim_{read,write} for now. Be careful to - test any changes with -Wall -Werror, mixed signed comparisons - will get you. */ - int (*read_mem) PARAMS ((host_callback * /*cb*/, struct cb_syscall * /*sc*/, - unsigned long /*taddr*/, char * /*buf*/, - int /*bytes*/)); - int (*write_mem) PARAMS ((host_callback * /*cb*/, struct cb_syscall * /*sc*/, - unsigned long /*taddr*/, const char * /*buf*/, - int /*bytes*/)); - - /* For sanity checking, should be last entry. */ - int magic; -} CB_SYSCALL; - -/* Magic number sanity checker. */ -#define CB_SYSCALL_MAGIC 0x12344321 - -/* Macro to initialize CB_SYSCALL. Called first, before filling in - any fields. */ -#define CB_SYSCALL_INIT(sc) \ -do { \ - memset ((sc), 0, sizeof (*(sc))); \ - (sc)->magic = CB_SYSCALL_MAGIC; \ -} while (0) - -/* Return codes for various interface routines. */ - -typedef enum { - CB_RC_OK = 0, - /* generic error */ - CB_RC_ERR, - /* either file not found or no read access */ - CB_RC_ACCESS, - CB_RC_NO_MEM -} CB_RC; - -/* Read in target values for system call numbers, errno values, signals. */ -CB_RC cb_read_target_syscall_maps PARAMS ((host_callback *, const char *)); - -/* Translate target to host syscall function numbers. */ -int cb_target_to_host_syscall PARAMS ((host_callback *, int)); - -/* Translate host to target errno value. */ -int cb_host_to_target_errno PARAMS ((host_callback *, int)); - -/* Translate target to host open flags. */ -int cb_target_to_host_open PARAMS ((host_callback *, int)); - -/* Translate target signal number to host. */ -int cb_target_to_host_signal PARAMS ((host_callback *, int)); - -/* Translate host signal number to target. */ -int cb_host_to_target_signal PARAMS ((host_callback *, int)); - -/* Translate host stat struct to target. - If stat struct ptr is NULL, just compute target stat struct size. - Result is size of target stat struct or 0 if error. */ -int cb_host_to_target_stat PARAMS ((host_callback *, const struct stat *, PTR)); - -/* Perform a system call. */ -CB_RC cb_syscall PARAMS ((host_callback *, CB_SYSCALL *)); - -#endif diff -uprN binutils-2.12.90.0.11/include/dis-asm.h binutils-2.12.90.0.12/include/dis-asm.h --- binutils-2.12.90.0.11/include/dis-asm.h Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/include/dis-asm.h Tue Jun 18 21:41:59 2002 @@ -236,6 +236,7 @@ extern int print_insn_w65 PARAMS ((bfd_ extern int print_insn_xstormy16 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_sh64 PARAMS ((bfd_vma, disassemble_info *)); extern int print_insn_sh64x_media PARAMS ((bfd_vma, disassemble_info *)); +extern int print_insn_frv PARAMS ((bfd_vma, disassemble_info *)); extern disassembler_ftype arc_get_disassembler PARAMS ((void *)); extern disassembler_ftype cris_get_disassembler PARAMS ((bfd *)); diff -uprN binutils-2.12.90.0.11/include/elf/ChangeLog binutils-2.12.90.0.12/include/elf/ChangeLog --- binutils-2.12.90.0.11/include/elf/ChangeLog Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/include/elf/ChangeLog Tue Jun 18 21:41:59 2002 @@ -1,3 +1,9 @@ +2002-06-18 Dave Brolley + + From Catherine Moore, Michael Meissner, Dave Brolley: + * common.h (EM_CYGNUS_FRV): New macro. + * frv.h: New file. + 2002-06-06 Lars Brinkhoff * common.h: Change registry@sco.com to registry@caldera.com. diff -uprN binutils-2.12.90.0.11/include/elf/common.h binutils-2.12.90.0.12/include/elf/common.h --- binutils-2.12.90.0.11/include/elf/common.h Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/include/elf/common.h Tue Jun 18 21:41:59 2002 @@ -244,6 +244,8 @@ Foundation, Inc., 59 Temple Place - Suit #define EM_XSTORMY16 0xad45 +/* FRV magic number - no EABI available??. */ +#define EM_CYGNUS_FRV 0x5441 /* See the above comment before you add a new EM_* value here. */ /* Values for e_version. */ diff -uprN binutils-2.12.90.0.11/include/elf/frv.h binutils-2.12.90.0.12/include/elf/frv.h --- binutils-2.12.90.0.11/include/elf/frv.h Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/include/elf/frv.h Tue Jun 18 21:41:59 2002 @@ -0,0 +1,95 @@ +/* FRV ELF support for BFD. + Copyright (C) 2002 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_FRV_H +#define _ELF_FRV_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_frv_reloc_type) + RELOC_NUMBER (R_FRV_NONE, 0) + RELOC_NUMBER (R_FRV_32, 1) + RELOC_NUMBER (R_FRV_LABEL16, 2) + RELOC_NUMBER (R_FRV_LABEL24, 3) + RELOC_NUMBER (R_FRV_LO16, 4) + RELOC_NUMBER (R_FRV_HI16, 5) + RELOC_NUMBER (R_FRV_GPREL12, 6) + RELOC_NUMBER (R_FRV_GPRELU12, 7) + RELOC_NUMBER (R_FRV_GPREL32, 8) + RELOC_NUMBER (R_FRV_GPRELHI, 9) + RELOC_NUMBER (R_FRV_GPRELLO, 10) + RELOC_NUMBER (R_FRV_GNU_VTINHERIT, 200) + RELOC_NUMBER (R_FRV_GNU_VTENTRY, 201) +END_RELOC_NUMBERS(R_FRV_max) + +/* Processor specific flags for the ELF header e_flags field. */ + /* gpr support */ +#define EF_FRV_GPR_MASK 0x00000003 /* mask for # of gprs */ +#define EF_FRV_GPR_32 0x00000001 /* -mgpr-32 */ +#define EF_FRV_GPR_64 0x00000002 /* -mgpr-64 */ + + /* fpr support */ +#define EF_FRV_FPR_MASK 0x0000000c /* mask for # of fprs */ +#define EF_FRV_FPR_32 0x00000004 /* -mfpr-32 */ +#define EF_FRV_FPR_64 0x00000008 /* -mfpr-64 */ +#define EF_FRV_FPR_NONE 0x0000000c /* -msoft-float */ + + /* double word support */ +#define EF_FRV_DWORD_MASK 0x00000030 /* mask for dword support */ +#define EF_FRV_DWORD_YES 0x00000010 /* use double word insns */ +#define EF_FRV_DWORD_NO 0x00000020 /* don't use double word insn*/ + +#define EF_FRV_DOUBLE 0x00000040 /* -mdouble */ +#define EF_FRV_MEDIA 0x00000080 /* -mmedia */ + +#define EF_FRV_PIC 0x00000100 /* -fpic */ +#define EF_FRV_NON_PIC_RELOCS 0x00000200 /* used non pic safe relocs */ + +#define EF_FRV_MULADD 0x00000400 /* -mmuladd */ +#define EF_FRV_BIGPIC 0x00000800 /* -fPIC */ +#define EF_FRV_LIBPIC 0x00001000 /* -mlibrary-pic */ +#define EF_FRV_G0 0x00002000 /* -G 0, no small data ptr */ +#define EF_FRV_NOPACK 0x00004000 /* -mnopack */ + +#define EF_FRV_CPU_MASK 0xff000000 /* specific cpu bits */ +#define EF_FRV_CPU_GENERIC 0x00000000 /* generic FRV */ +#define EF_FRV_CPU_FR500 0x01000000 /* FRV500 */ +#define EF_FRV_CPU_FR300 0x02000000 /* FRV300 */ +#define EF_FRV_CPU_SIMPLE 0x03000000 /* SIMPLE */ +#define EF_FRV_CPU_TOMCAT 0x04000000 /* Tomcat, FR500 prototype */ +#define EF_FRV_CPU_FR400 0x05000000 /* FRV400 */ + + /* Mask of PIC related bits */ +#define EF_FRV_PIC_FLAGS (EF_FRV_PIC | EF_FRV_LIBPIC | EF_FRV_BIGPIC) + + /* Mask of all flags */ +#define EF_FRV_ALL_FLAGS (EF_FRV_GPR_MASK | \ + EF_FRV_FPR_MASK | \ + EF_FRV_DWORD_MASK | \ + EF_FRV_DOUBLE | \ + EF_FRV_MEDIA | \ + EF_FRV_PIC_FLAGS | \ + EF_FRV_NON_PIC_RELOCS | \ + EF_FRV_MULADD | \ + EF_FRV_G0 | \ + EF_FRV_NOPACK | \ + EF_FRV_CPU_MASK) + +#endif /* _ELF_FRV_H */ diff -uprN binutils-2.12.90.0.11/include/gdb/ChangeLog binutils-2.12.90.0.12/include/gdb/ChangeLog --- binutils-2.12.90.0.11/include/gdb/ChangeLog Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/include/gdb/ChangeLog Tue Jun 18 21:41:59 2002 @@ -1,3 +1,16 @@ +2002-06-15 Andrew Cagney + + * sim-arm.h (enum sim_arm_regs): Rename sim_arm_regnum. + +2002-06-12 Andrew Cagney + + * sim-arm.h: New file. + +2002-06-08 Andrew Cagney + + * callback.h: Copy to here from directory above. + * remote-sim.h: Copy to here from directory above. + 2002-06-01 Andrew Cagney * sim-d10v.h (sim_d10v_regs): Expand to include all registers. diff -uprN binutils-2.12.90.0.11/include/gdb/callback.h binutils-2.12.90.0.12/include/gdb/callback.h --- binutils-2.12.90.0.11/include/gdb/callback.h Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/include/gdb/callback.h Tue Jun 18 21:41:59 2002 @@ -0,0 +1,270 @@ +/* Remote target system call callback support. + Copyright 1997 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This interface isn't intended to be specific to any particular kind + of remote (hardware, simulator, whatever). As such, support for it + (e.g. sim/common/callback.c) should *not* live in the simulator source + tree, nor should it live in the gdb source tree. */ + +/* There are various ways to handle system calls: + + 1) Have a simulator intercept the appropriate trap instruction and + directly perform the system call on behalf of the target program. + This is the typical way of handling system calls for embedded targets. + [Handling system calls for embedded targets isn't that much of an + oxymoron as running compiler testsuites make use of the capability.] + + This method of system call handling is done when STATE_ENVIRONMENT + is ENVIRONMENT_USER. + + 2) Have a simulator emulate the hardware as much as possible. + If the program running on the real hardware communicates with some sort + of target manager, one would want to be able to run this program on the + simulator as well. + + This method of system call handling is done when STATE_ENVIRONMENT + is ENVIRONMENT_OPERATING. +*/ + +#ifndef CALLBACK_H +#define CALLBACK_H + +/* ??? The reason why we check for va_start here should be documented. */ + +#ifndef va_start +#include +#ifdef ANSI_PROTOTYPES +#include +#else +#include +#endif +#endif + +/* Mapping of host/target values. */ +/* ??? For debugging purposes, one might want to add a string of the + name of the symbol. */ + +typedef struct { + int host_val; + int target_val; +} CB_TARGET_DEFS_MAP; + +#define MAX_CALLBACK_FDS 10 + +/* Forward decl for stat/fstat. */ +struct stat; + +typedef struct host_callback_struct host_callback; + +struct host_callback_struct +{ + int (*close) PARAMS ((host_callback *,int)); + int (*get_errno) PARAMS ((host_callback *)); + int (*isatty) PARAMS ((host_callback *, int)); + int (*lseek) PARAMS ((host_callback *, int, long , int)); + int (*open) PARAMS ((host_callback *, const char*, int mode)); + int (*read) PARAMS ((host_callback *,int, char *, int)); + int (*read_stdin) PARAMS (( host_callback *, char *, int)); + int (*rename) PARAMS ((host_callback *, const char *, const char *)); + int (*system) PARAMS ((host_callback *, const char *)); + long (*time) PARAMS ((host_callback *, long *)); + int (*unlink) PARAMS ((host_callback *, const char *)); + int (*write) PARAMS ((host_callback *,int, const char *, int)); + int (*write_stdout) PARAMS ((host_callback *, const char *, int)); + void (*flush_stdout) PARAMS ((host_callback *)); + int (*write_stderr) PARAMS ((host_callback *, const char *, int)); + void (*flush_stderr) PARAMS ((host_callback *)); + int (*stat) PARAMS ((host_callback *, const char *, struct stat *)); + int (*fstat) PARAMS ((host_callback *, int, struct stat *)); + + /* When present, call to the client to give it the oportunity to + poll any io devices for a request to quit (indicated by a nonzero + return value). */ + int (*poll_quit) PARAMS ((host_callback *)); + + /* Used when the target has gone away, so we can close open + handles and free memory etc etc. */ + int (*shutdown) PARAMS ((host_callback *)); + int (*init) PARAMS ((host_callback *)); + + /* depreciated, use vprintf_filtered - Talk to the user on a console. */ + void (*printf_filtered) PARAMS ((host_callback *, const char *, ...)); + + /* Talk to the user on a console. */ + void (*vprintf_filtered) PARAMS ((host_callback *, const char *, va_list)); + + /* Same as vprintf_filtered but to stderr. */ + void (*evprintf_filtered) PARAMS ((host_callback *, const char *, va_list)); + + /* Print an error message and "exit". + In the case of gdb "exiting" means doing a longjmp back to the main + command loop. */ + void (*error) PARAMS ((host_callback *, const char *, ...)); + + int last_errno; /* host format */ + + int fdmap[MAX_CALLBACK_FDS]; + char fdopen[MAX_CALLBACK_FDS]; + char alwaysopen[MAX_CALLBACK_FDS]; + + /* System call numbers. */ + CB_TARGET_DEFS_MAP *syscall_map; + /* Errno values. */ + CB_TARGET_DEFS_MAP *errno_map; + /* Flags to the open system call. */ + CB_TARGET_DEFS_MAP *open_map; + /* Signal numbers. */ + CB_TARGET_DEFS_MAP *signal_map; + /* Layout of `stat' struct. + The format is a series of "name,length" pairs separated by colons. + Empty space is indicated with a `name' of "space". + All padding must be explicitly mentioned. + Lengths are in bytes. If this needs to be extended to bits, + use "name.bits". + Example: "st_dev,4:st_ino,4:st_mode,4:..." */ + const char *stat_map; + + /* Marker for those wanting to do sanity checks. + This should remain the last member of this struct to help catch + miscompilation errors. */ +#define HOST_CALLBACK_MAGIC 4705 /* teds constant */ + int magic; +}; + +extern host_callback default_callback; + +/* Canonical versions of system call numbers. + It's not intended to willy-nilly throw every system call ever heard + of in here. Only include those that have an important use. + ??? One can certainly start a discussion over the ones that are currently + here, but that will always be true. */ + +/* These are used by the ANSI C support of libc. */ +#define CB_SYS_exit 1 +#define CB_SYS_open 2 +#define CB_SYS_close 3 +#define CB_SYS_read 4 +#define CB_SYS_write 5 +#define CB_SYS_lseek 6 +#define CB_SYS_unlink 7 +#define CB_SYS_getpid 8 +#define CB_SYS_kill 9 +#define CB_SYS_fstat 10 +/*#define CB_SYS_sbrk 11 - not currently a system call, but reserved. */ + +/* ARGV support. */ +#define CB_SYS_argvlen 12 +#define CB_SYS_argv 13 + +/* These are extras added for one reason or another. */ +#define CB_SYS_chdir 14 +#define CB_SYS_stat 15 +#define CB_SYS_chmod 16 +#define CB_SYS_utime 17 +#define CB_SYS_time 18 + +/* Struct use to pass and return information necessary to perform a + system call. */ +/* FIXME: Need to consider target word size. */ + +typedef struct cb_syscall { + /* The target's value of what system call to perform. */ + int func; + /* The arguments to the syscall. */ + long arg1, arg2, arg3, arg4; + + /* The result. */ + long result; + /* Some system calls have two results. */ + long result2; + /* The target's errno value, or 0 if success. + This is converted to the target's value with host_to_target_errno. */ + int errcode; + + /* Working space to be used by memory read/write callbacks. */ + PTR p1; + PTR p2; + long x1,x2; + + /* Callbacks for reading/writing memory (e.g. for read/write syscalls). + ??? long or unsigned long might be better to use for the `count' + argument here. We mimic sim_{read,write} for now. Be careful to + test any changes with -Wall -Werror, mixed signed comparisons + will get you. */ + int (*read_mem) PARAMS ((host_callback * /*cb*/, struct cb_syscall * /*sc*/, + unsigned long /*taddr*/, char * /*buf*/, + int /*bytes*/)); + int (*write_mem) PARAMS ((host_callback * /*cb*/, struct cb_syscall * /*sc*/, + unsigned long /*taddr*/, const char * /*buf*/, + int /*bytes*/)); + + /* For sanity checking, should be last entry. */ + int magic; +} CB_SYSCALL; + +/* Magic number sanity checker. */ +#define CB_SYSCALL_MAGIC 0x12344321 + +/* Macro to initialize CB_SYSCALL. Called first, before filling in + any fields. */ +#define CB_SYSCALL_INIT(sc) \ +do { \ + memset ((sc), 0, sizeof (*(sc))); \ + (sc)->magic = CB_SYSCALL_MAGIC; \ +} while (0) + +/* Return codes for various interface routines. */ + +typedef enum { + CB_RC_OK = 0, + /* generic error */ + CB_RC_ERR, + /* either file not found or no read access */ + CB_RC_ACCESS, + CB_RC_NO_MEM +} CB_RC; + +/* Read in target values for system call numbers, errno values, signals. */ +CB_RC cb_read_target_syscall_maps PARAMS ((host_callback *, const char *)); + +/* Translate target to host syscall function numbers. */ +int cb_target_to_host_syscall PARAMS ((host_callback *, int)); + +/* Translate host to target errno value. */ +int cb_host_to_target_errno PARAMS ((host_callback *, int)); + +/* Translate target to host open flags. */ +int cb_target_to_host_open PARAMS ((host_callback *, int)); + +/* Translate target signal number to host. */ +int cb_target_to_host_signal PARAMS ((host_callback *, int)); + +/* Translate host signal number to target. */ +int cb_host_to_target_signal PARAMS ((host_callback *, int)); + +/* Translate host stat struct to target. + If stat struct ptr is NULL, just compute target stat struct size. + Result is size of target stat struct or 0 if error. */ +int cb_host_to_target_stat PARAMS ((host_callback *, const struct stat *, PTR)); + +/* Perform a system call. */ +CB_RC cb_syscall PARAMS ((host_callback *, CB_SYSCALL *)); + +#endif diff -uprN binutils-2.12.90.0.11/include/gdb/remote-sim.h binutils-2.12.90.0.12/include/gdb/remote-sim.h --- binutils-2.12.90.0.11/include/gdb/remote-sim.h Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/include/gdb/remote-sim.h Tue Jun 18 21:41:59 2002 @@ -0,0 +1,354 @@ +/* This file defines the interface between the simulator and gdb. + Copyright 1993, 1994, 1996, 1997, 1998, 2000 + Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#if !defined (REMOTE_SIM_H) +#define REMOTE_SIM_H 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/* This file is used when building stand-alone simulators, so isolate this + file from gdb. */ + +/* Pick up CORE_ADDR_TYPE if defined (from gdb), otherwise use same value as + gdb does (unsigned int - from defs.h). */ + +#ifndef CORE_ADDR_TYPE +typedef unsigned int SIM_ADDR; +#else +typedef CORE_ADDR_TYPE SIM_ADDR; +#endif + + +/* Semi-opaque type used as result of sim_open and passed back to all + other routines. "desc" is short for "descriptor". + It is up to each simulator to define `sim_state'. */ + +typedef struct sim_state *SIM_DESC; + + +/* Values for `kind' arg to sim_open. */ + +typedef enum { + SIM_OPEN_STANDALONE, /* simulator used standalone (run.c) */ + SIM_OPEN_DEBUG /* simulator used by debugger (gdb) */ +} SIM_OPEN_KIND; + + +/* Return codes from various functions. */ + +typedef enum { + SIM_RC_FAIL = 0, + SIM_RC_OK = 1, + SIM_RC_UNKNOWN_BREAKPOINT = 2, + SIM_RC_INSUFFICIENT_RESOURCES = 3, + SIM_RC_DUPLICATE_BREAKPOINT = 4 +} SIM_RC; + + +/* The bfd struct, as an opaque type. */ + +struct _bfd; + + +/* Main simulator entry points. */ + + +/* Create a fully initialized simulator instance. + + (This function is called when the simulator is selected from the + gdb command line.) + + KIND specifies how the simulator shall be used. Currently there + are only two kinds: stand-alone and debug. + + CALLBACK specifies a standard host callback (defined in callback.h). + + ABFD, when non NULL, designates a target program. The program is + not loaded. + + ARGV is a standard ARGV pointer such as that passed from the + command line. The syntax of the argument list is is assumed to be + ``SIM-PROG { SIM-OPTION } [ TARGET-PROGRAM { TARGET-OPTION } ]''. + The trailing TARGET-PROGRAM and args are only valid for a + stand-alone simulator. + + On success, the result is a non NULL descriptor that shall be + passed to the other sim_foo functions. While the simulator + configuration can be parameterized by (in decreasing precedence) + ARGV's SIM-OPTION, ARGV's TARGET-PROGRAM and the ABFD argument, the + successful creation of the simulator shall not dependent on the + presence of any of these arguments/options. + + Hardware simulator: The created simulator shall be sufficiently + initialized to handle, with out restrictions any client requests + (including memory reads/writes, register fetch/stores and a + resume). + + Process simulator: that process is not created until a call to + sim_create_inferior. FIXME: What should the state of the simulator + be? */ + +SIM_DESC sim_open PARAMS ((SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct _bfd *abfd, char **argv)); + + +/* Destory a simulator instance. + + QUITTING is non-zero if we cannot hang on errors. + + This may involve freeing target memory and closing any open files + and mmap'd areas. You cannot assume sim_kill has already been + called. */ + +void sim_close PARAMS ((SIM_DESC sd, int quitting)); + + +/* Load program PROG into the simulators memory. + + If ABFD is non-NULL, the bfd for the file has already been opened. + The result is a return code indicating success. + + Hardware simulator: Normally, each program section is written into + memory according to that sections LMA using physical (direct) + addressing. The exception being systems, such as PPC/CHRP, which + support more complicated program loaders. A call to this function + should not effect the state of the processor registers. Multiple + calls to this function are permitted and have an accumulative + effect. + + Process simulator: Calls to this function may be ignored. + + FIXME: Most hardware simulators load the image at the VMA using + virtual addressing. + + FIXME: For some hardware targets, before a loaded program can be + executed, it requires the manipulation of VM registers and tables. + Such manipulation should probably (?) occure in + sim_create_inferior. */ + +SIM_RC sim_load PARAMS ((SIM_DESC sd, char *prog, struct _bfd *abfd, int from_tty)); + + +/* Prepare to run the simulated program. + + ABFD, if not NULL, provides initial processor state information. + ARGV and ENV, if non NULL, are NULL terminated lists of pointers. + + Hardware simulator: This function shall initialize the processor + registers to a known value. The program counter and possibly stack + pointer shall be set using information obtained from ABFD (or + hardware reset defaults). ARGV and ENV, dependant on the target + ABI, may be written to memory. + + Process simulator: After a call to this function, a new process + instance shall exist. The TEXT, DATA, BSS and stack regions shall + all be initialized, ARGV and ENV shall be written to process + address space (according to the applicable ABI) and the program + counter and stack pointer set accordingly. */ + +SIM_RC sim_create_inferior PARAMS ((SIM_DESC sd, struct _bfd *abfd, char **argv, char **env)); + + +/* Fetch LENGTH bytes of the simulated program's memory. Start fetch + at virtual address MEM and store in BUF. Result is number of bytes + read, or zero if error. */ + +int sim_read PARAMS ((SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)); + + +/* Store LENGTH bytes from BUF into the simulated program's + memory. Store bytes starting at virtual address MEM. Result is + number of bytes write, or zero if error. */ + +int sim_write PARAMS ((SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)); + + +/* Fetch register REGNO storing its raw (target endian) value in the + LENGTH byte buffer BUF. Return the actual size of the register or + zero if REGNO is not applicable. + + Legacy implementations ignore LENGTH and always return -1. + + If LENGTH does not match the size of REGNO no data is transfered + (the actual register size is still returned). */ + +int sim_fetch_register PARAMS ((SIM_DESC sd, int regno, unsigned char *buf, int length)); + + +/* Store register REGNO from the raw (target endian) value in BUF. + Return the actual size of the register or zero if REGNO is not + applicable. + + Legacy implementations ignore LENGTH and always return -1. + + If LENGTH does not match the size of REGNO no data is transfered + (the actual register size is still returned). */ + +int sim_store_register PARAMS ((SIM_DESC sd, int regno, unsigned char *buf, int length)); + + +/* Print whatever statistics the simulator has collected. + + VERBOSE is currently unused and must always be zero. */ + +void sim_info PARAMS ((SIM_DESC sd, int verbose)); + + +/* Run (or resume) the simulated program. + + STEP, when non-zero indicates that only a single simulator cycle + should be emulated. + + SIGGNAL, if non-zero is a (HOST) SIGRC value indicating the type of + event (hardware interrupt, signal) to be delivered to the simulated + program. + + Hardware simulator: If the SIGRC value returned by + sim_stop_reason() is passed back to the simulator via SIGGNAL then + the hardware simulator shall correctly deliver the hardware event + indicated by that signal. If a value of zero is passed in then the + simulation will continue as if there were no outstanding signal. + The effect of any other SIGGNAL value is is implementation + dependant. + + Process simulator: If SIGRC is non-zero then the corresponding + signal is delivered to the simulated program and execution is then + continued. A zero SIGRC value indicates that the program should + continue as normal. */ + +void sim_resume PARAMS ((SIM_DESC sd, int step, int siggnal)); + + +/* Asynchronous request to stop the simulation. + A nonzero return indicates that the simulator is able to handle + the request */ + +int sim_stop PARAMS ((SIM_DESC sd)); + + +/* Fetch the REASON why the program stopped. + + SIM_EXITED: The program has terminated. SIGRC indicates the target + dependant exit status. + + SIM_STOPPED: The program has stopped. SIGRC uses the host's signal + numbering as a way of identifying the reaon: program interrupted by + user via a sim_stop request (SIGINT); a breakpoint instruction + (SIGTRAP); a completed single step (SIGTRAP); an internal error + condition (SIGABRT); an illegal instruction (SIGILL); Access to an + undefined memory region (SIGSEGV); Mis-aligned memory access + (SIGBUS). For some signals information in addition to the signal + number may be retained by the simulator (e.g. offending address), + that information is not directly accessable via this interface. + + SIM_SIGNALLED: The program has been terminated by a signal. The + simulator has encountered target code that causes the the program + to exit with signal SIGRC. + + SIM_RUNNING, SIM_POLLING: The return of one of these values + indicates a problem internal to the simulator. */ + +enum sim_stop { sim_running, sim_polling, sim_exited, sim_stopped, sim_signalled }; + +void sim_stop_reason PARAMS ((SIM_DESC sd, enum sim_stop *reason, int *sigrc)); + + +/* Passthru for other commands that the simulator might support. + Simulators should be prepared to deal with any combination of NULL + or empty CMD. */ + +void sim_do_command PARAMS ((SIM_DESC sd, char *cmd)); + +/* Call these functions to set and clear breakpoints at ADDR. */ + +SIM_RC sim_set_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr)); +SIM_RC sim_clear_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr)); +SIM_RC sim_clear_all_breakpoints PARAMS ((SIM_DESC sd)); + +/* These functions are used to enable and disable breakpoints. */ + +SIM_RC sim_enable_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr)); +SIM_RC sim_disable_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr)); +SIM_RC sim_enable_all_breakpoints PARAMS ((SIM_DESC sd)); +SIM_RC sim_disable_all_breakpoints PARAMS ((SIM_DESC sd)); + + +/* Provide simulator with a default (global) host_callback_struct. + THIS PROCEDURE IS DEPRECIATED. + GDB and NRUN do not use this interface. + This procedure does not take a SIM_DESC argument as it is + used before sim_open. */ + +void sim_set_callbacks PARAMS ((struct host_callback_struct *)); + + +/* Set the size of the simulator memory array. + THIS PROCEDURE IS DEPRECIATED. + GDB and NRUN do not use this interface. + This procedure does not take a SIM_DESC argument as it is + used before sim_open. */ + +void sim_size PARAMS ((int i)); + + +/* Single-step simulator with tracing enabled. + THIS PROCEDURE IS DEPRECIATED. + THIS PROCEDURE IS EVEN MORE DEPRECATED THAN SIM_SET_TRACE + GDB and NRUN do not use this interface. + This procedure returns: ``0'' indicating that the simulator should + be continued using sim_trace() calls; ``1'' indicating that the + simulation has finished. */ + +int sim_trace PARAMS ((SIM_DESC sd)); + + +/* Enable tracing. + THIS PROCEDURE IS DEPRECIATED. + GDB and NRUN do not use this interface. + This procedure returns: ``0'' indicating that the simulator should + be continued using sim_trace() calls; ``1'' indicating that the + simulation has finished. */ + +void sim_set_trace PARAMS ((void)); + + +/* Configure the size of the profile buffer. + THIS PROCEDURE IS DEPRECIATED. + GDB and NRUN do not use this interface. + This procedure does not take a SIM_DESC argument as it is + used before sim_open. */ + +void sim_set_profile_size PARAMS ((int n)); + + +/* Kill the running program. + THIS PROCEDURE IS DEPRECIATED. + GDB and NRUN do not use this interface. + This procedure will be replaced as part of the introduction of + multi-cpu simulators. */ + +void sim_kill PARAMS ((SIM_DESC sd)); + +#ifdef __cplusplus +} +#endif + +#endif /* !defined (REMOTE_SIM_H) */ diff -uprN binutils-2.12.90.0.11/include/gdb/sim-arm.h binutils-2.12.90.0.12/include/gdb/sim-arm.h --- binutils-2.12.90.0.11/include/gdb/sim-arm.h Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/include/gdb/sim-arm.h Tue Jun 18 21:41:59 2002 @@ -0,0 +1,65 @@ +/* This file defines the interface between the Arm simulator and GDB. + + Copyright 2002 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#if !defined (SIM_ARM_H) +#define SIM_ARM_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +enum sim_arm_regs +{ + SIM_ARM_R0_REGNUM, + SIM_ARM_R1_REGNUM, + SIM_ARM_R2_REGNUM, + SIM_ARM_R3_REGNUM, + SIM_ARM_R4_REGNUM, + SIM_ARM_R5_REGNUM, + SIM_ARM_R6_REGNUM, + SIM_ARM_R7_REGNUM, + SIM_ARM_R8_REGNUM, + SIM_ARM_R9_REGNUM, + SIM_ARM_R10_REGNUM, + SIM_ARM_R11_REGNUM, + SIM_ARM_R12_REGNUM, + SIM_ARM_R13_REGNUM, + SIM_ARM_R14_REGNUM, + SIM_ARM_R15_REGNUM, /* PC */ + SIM_ARM_FP0_REGNUM, + SIM_ARM_FP1_REGNUM, + SIM_ARM_FP2_REGNUM, + SIM_ARM_FP3_REGNUM, + SIM_ARM_FP4_REGNUM, + SIM_ARM_FP5_REGNUM, + SIM_ARM_FP6_REGNUM, + SIM_ARM_FP7_REGNUM, + SIM_ARM_FPS_REGNUM, + SIM_ARM_PS_REGNUM +}; + +#ifdef __cplusplus +} +#endif + +#endif diff -uprN binutils-2.12.90.0.11/include/remote-sim.h binutils-2.12.90.0.12/include/remote-sim.h --- binutils-2.12.90.0.11/include/remote-sim.h Thu Mar 15 14:53:01 2001 +++ binutils-2.12.90.0.12/include/remote-sim.h Wed Dec 31 16:00:00 1969 @@ -1,354 +0,0 @@ -/* This file defines the interface between the simulator and gdb. - Copyright 1993, 1994, 1996, 1997, 1998, 2000 - Free Software Foundation, Inc. - -This file is part of GDB. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#if !defined (REMOTE_SIM_H) -#define REMOTE_SIM_H 1 - -#ifdef __cplusplus -extern "C" { -#endif - -/* This file is used when building stand-alone simulators, so isolate this - file from gdb. */ - -/* Pick up CORE_ADDR_TYPE if defined (from gdb), otherwise use same value as - gdb does (unsigned int - from defs.h). */ - -#ifndef CORE_ADDR_TYPE -typedef unsigned int SIM_ADDR; -#else -typedef CORE_ADDR_TYPE SIM_ADDR; -#endif - - -/* Semi-opaque type used as result of sim_open and passed back to all - other routines. "desc" is short for "descriptor". - It is up to each simulator to define `sim_state'. */ - -typedef struct sim_state *SIM_DESC; - - -/* Values for `kind' arg to sim_open. */ - -typedef enum { - SIM_OPEN_STANDALONE, /* simulator used standalone (run.c) */ - SIM_OPEN_DEBUG /* simulator used by debugger (gdb) */ -} SIM_OPEN_KIND; - - -/* Return codes from various functions. */ - -typedef enum { - SIM_RC_FAIL = 0, - SIM_RC_OK = 1, - SIM_RC_UNKNOWN_BREAKPOINT = 2, - SIM_RC_INSUFFICIENT_RESOURCES = 3, - SIM_RC_DUPLICATE_BREAKPOINT = 4 -} SIM_RC; - - -/* The bfd struct, as an opaque type. */ - -struct _bfd; - - -/* Main simulator entry points. */ - - -/* Create a fully initialized simulator instance. - - (This function is called when the simulator is selected from the - gdb command line.) - - KIND specifies how the simulator shall be used. Currently there - are only two kinds: stand-alone and debug. - - CALLBACK specifies a standard host callback (defined in callback.h). - - ABFD, when non NULL, designates a target program. The program is - not loaded. - - ARGV is a standard ARGV pointer such as that passed from the - command line. The syntax of the argument list is is assumed to be - ``SIM-PROG { SIM-OPTION } [ TARGET-PROGRAM { TARGET-OPTION } ]''. - The trailing TARGET-PROGRAM and args are only valid for a - stand-alone simulator. - - On success, the result is a non NULL descriptor that shall be - passed to the other sim_foo functions. While the simulator - configuration can be parameterized by (in decreasing precedence) - ARGV's SIM-OPTION, ARGV's TARGET-PROGRAM and the ABFD argument, the - successful creation of the simulator shall not dependent on the - presence of any of these arguments/options. - - Hardware simulator: The created simulator shall be sufficiently - initialized to handle, with out restrictions any client requests - (including memory reads/writes, register fetch/stores and a - resume). - - Process simulator: that process is not created until a call to - sim_create_inferior. FIXME: What should the state of the simulator - be? */ - -SIM_DESC sim_open PARAMS ((SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct _bfd *abfd, char **argv)); - - -/* Destory a simulator instance. - - QUITTING is non-zero if we cannot hang on errors. - - This may involve freeing target memory and closing any open files - and mmap'd areas. You cannot assume sim_kill has already been - called. */ - -void sim_close PARAMS ((SIM_DESC sd, int quitting)); - - -/* Load program PROG into the simulators memory. - - If ABFD is non-NULL, the bfd for the file has already been opened. - The result is a return code indicating success. - - Hardware simulator: Normally, each program section is written into - memory according to that sections LMA using physical (direct) - addressing. The exception being systems, such as PPC/CHRP, which - support more complicated program loaders. A call to this function - should not effect the state of the processor registers. Multiple - calls to this function are permitted and have an accumulative - effect. - - Process simulator: Calls to this function may be ignored. - - FIXME: Most hardware simulators load the image at the VMA using - virtual addressing. - - FIXME: For some hardware targets, before a loaded program can be - executed, it requires the manipulation of VM registers and tables. - Such manipulation should probably (?) occure in - sim_create_inferior. */ - -SIM_RC sim_load PARAMS ((SIM_DESC sd, char *prog, struct _bfd *abfd, int from_tty)); - - -/* Prepare to run the simulated program. - - ABFD, if not NULL, provides initial processor state information. - ARGV and ENV, if non NULL, are NULL terminated lists of pointers. - - Hardware simulator: This function shall initialize the processor - registers to a known value. The program counter and possibly stack - pointer shall be set using information obtained from ABFD (or - hardware reset defaults). ARGV and ENV, dependant on the target - ABI, may be written to memory. - - Process simulator: After a call to this function, a new process - instance shall exist. The TEXT, DATA, BSS and stack regions shall - all be initialized, ARGV and ENV shall be written to process - address space (according to the applicable ABI) and the program - counter and stack pointer set accordingly. */ - -SIM_RC sim_create_inferior PARAMS ((SIM_DESC sd, struct _bfd *abfd, char **argv, char **env)); - - -/* Fetch LENGTH bytes of the simulated program's memory. Start fetch - at virtual address MEM and store in BUF. Result is number of bytes - read, or zero if error. */ - -int sim_read PARAMS ((SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)); - - -/* Store LENGTH bytes from BUF into the simulated program's - memory. Store bytes starting at virtual address MEM. Result is - number of bytes write, or zero if error. */ - -int sim_write PARAMS ((SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)); - - -/* Fetch register REGNO storing its raw (target endian) value in the - LENGTH byte buffer BUF. Return the actual size of the register or - zero if REGNO is not applicable. - - Legacy implementations ignore LENGTH and always return -1. - - If LENGTH does not match the size of REGNO no data is transfered - (the actual register size is still returned). */ - -int sim_fetch_register PARAMS ((SIM_DESC sd, int regno, unsigned char *buf, int length)); - - -/* Store register REGNO from the raw (target endian) value in BUF. - Return the actual size of the register or zero if REGNO is not - applicable. - - Legacy implementations ignore LENGTH and always return -1. - - If LENGTH does not match the size of REGNO no data is transfered - (the actual register size is still returned). */ - -int sim_store_register PARAMS ((SIM_DESC sd, int regno, unsigned char *buf, int length)); - - -/* Print whatever statistics the simulator has collected. - - VERBOSE is currently unused and must always be zero. */ - -void sim_info PARAMS ((SIM_DESC sd, int verbose)); - - -/* Run (or resume) the simulated program. - - STEP, when non-zero indicates that only a single simulator cycle - should be emulated. - - SIGGNAL, if non-zero is a (HOST) SIGRC value indicating the type of - event (hardware interrupt, signal) to be delivered to the simulated - program. - - Hardware simulator: If the SIGRC value returned by - sim_stop_reason() is passed back to the simulator via SIGGNAL then - the hardware simulator shall correctly deliver the hardware event - indicated by that signal. If a value of zero is passed in then the - simulation will continue as if there were no outstanding signal. - The effect of any other SIGGNAL value is is implementation - dependant. - - Process simulator: If SIGRC is non-zero then the corresponding - signal is delivered to the simulated program and execution is then - continued. A zero SIGRC value indicates that the program should - continue as normal. */ - -void sim_resume PARAMS ((SIM_DESC sd, int step, int siggnal)); - - -/* Asynchronous request to stop the simulation. - A nonzero return indicates that the simulator is able to handle - the request */ - -int sim_stop PARAMS ((SIM_DESC sd)); - - -/* Fetch the REASON why the program stopped. - - SIM_EXITED: The program has terminated. SIGRC indicates the target - dependant exit status. - - SIM_STOPPED: The program has stopped. SIGRC uses the host's signal - numbering as a way of identifying the reaon: program interrupted by - user via a sim_stop request (SIGINT); a breakpoint instruction - (SIGTRAP); a completed single step (SIGTRAP); an internal error - condition (SIGABRT); an illegal instruction (SIGILL); Access to an - undefined memory region (SIGSEGV); Mis-aligned memory access - (SIGBUS). For some signals information in addition to the signal - number may be retained by the simulator (e.g. offending address), - that information is not directly accessable via this interface. - - SIM_SIGNALLED: The program has been terminated by a signal. The - simulator has encountered target code that causes the the program - to exit with signal SIGRC. - - SIM_RUNNING, SIM_POLLING: The return of one of these values - indicates a problem internal to the simulator. */ - -enum sim_stop { sim_running, sim_polling, sim_exited, sim_stopped, sim_signalled }; - -void sim_stop_reason PARAMS ((SIM_DESC sd, enum sim_stop *reason, int *sigrc)); - - -/* Passthru for other commands that the simulator might support. - Simulators should be prepared to deal with any combination of NULL - or empty CMD. */ - -void sim_do_command PARAMS ((SIM_DESC sd, char *cmd)); - -/* Call these functions to set and clear breakpoints at ADDR. */ - -SIM_RC sim_set_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr)); -SIM_RC sim_clear_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr)); -SIM_RC sim_clear_all_breakpoints PARAMS ((SIM_DESC sd)); - -/* These functions are used to enable and disable breakpoints. */ - -SIM_RC sim_enable_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr)); -SIM_RC sim_disable_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr)); -SIM_RC sim_enable_all_breakpoints PARAMS ((SIM_DESC sd)); -SIM_RC sim_disable_all_breakpoints PARAMS ((SIM_DESC sd)); - - -/* Provide simulator with a default (global) host_callback_struct. - THIS PROCEDURE IS DEPRECIATED. - GDB and NRUN do not use this interface. - This procedure does not take a SIM_DESC argument as it is - used before sim_open. */ - -void sim_set_callbacks PARAMS ((struct host_callback_struct *)); - - -/* Set the size of the simulator memory array. - THIS PROCEDURE IS DEPRECIATED. - GDB and NRUN do not use this interface. - This procedure does not take a SIM_DESC argument as it is - used before sim_open. */ - -void sim_size PARAMS ((int i)); - - -/* Single-step simulator with tracing enabled. - THIS PROCEDURE IS DEPRECIATED. - THIS PROCEDURE IS EVEN MORE DEPRECATED THAN SIM_SET_TRACE - GDB and NRUN do not use this interface. - This procedure returns: ``0'' indicating that the simulator should - be continued using sim_trace() calls; ``1'' indicating that the - simulation has finished. */ - -int sim_trace PARAMS ((SIM_DESC sd)); - - -/* Enable tracing. - THIS PROCEDURE IS DEPRECIATED. - GDB and NRUN do not use this interface. - This procedure returns: ``0'' indicating that the simulator should - be continued using sim_trace() calls; ``1'' indicating that the - simulation has finished. */ - -void sim_set_trace PARAMS ((void)); - - -/* Configure the size of the profile buffer. - THIS PROCEDURE IS DEPRECIATED. - GDB and NRUN do not use this interface. - This procedure does not take a SIM_DESC argument as it is - used before sim_open. */ - -void sim_set_profile_size PARAMS ((int n)); - - -/* Kill the running program. - THIS PROCEDURE IS DEPRECIATED. - GDB and NRUN do not use this interface. - This procedure will be replaced as part of the introduction of - multi-cpu simulators. */ - -void sim_kill PARAMS ((SIM_DESC sd)); - -#ifdef __cplusplus -} -#endif - -#endif /* !defined (REMOTE_SIM_H) */ diff -uprN binutils-2.12.90.0.11/ld/ChangeLog binutils-2.12.90.0.12/ld/ChangeLog --- binutils-2.12.90.0.11/ld/ChangeLog Sat Jun 8 20:44:53 2002 +++ binutils-2.12.90.0.12/ld/ChangeLog Tue Jun 18 21:41:59 2002 @@ -1,3 +1,36 @@ +2002-06-18 Chris Demetriou + + * emultempl/mipself.em (mips_elf${ELFSIZE}_check_sections): Fix + format specifier used to print BFD name. + +2002-06-18 Dave Brolley + + From Catherine Moore, Michael Meissner, Jim Blandy: + * emulparams/elf32frv.sh: New file. + * configure.tgt: Support frv-*-*. + * Makefile.am (ALL_EMULATIONS): Add eelf32frv.o. + (eelf32frv.c): New target. + +2002-06-17 Tom Rix + + * emultempl/elf32.em: gld*_get_script: Check for + GENERATE_COMBRELOC_SCRIPT. + * scripttempl/elfd10v.sc : Fix STACK and INSN. + * emulparams/d10velf.sh : Fix TEXT_START_ADDR. + +Thu Jun 13 20:18:38 2002 J"orn Rennecke + + * configure.tgt: Add support for sh[1234]*le*-*-elf, sh[1234]*-*-elf. + +2002-06-12 H.J. Lu + + * emultempl/elf32.em (gld${EMULATION_NAME}_try_needed): Return + false if xvec doesn't match. + +2002-06-10 Richard Sandiford + + * ldlang.c (lang_size_sections_1): Skip removed output sections. + 2002-06-08 Alan Modra * ldexp.c: Replace CONST with const. diff -uprN binutils-2.12.90.0.11/ld/Makefile.am binutils-2.12.90.0.12/ld/Makefile.am --- binutils-2.12.90.0.11/ld/Makefile.am Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/ld/Makefile.am Tue Jun 18 21:41:59 2002 @@ -159,6 +159,7 @@ ALL_EMULATIONS = \ eelf32ebmip.o \ eelf32elmip.o \ eelf32fr30.o \ + eelf32frv.o \ eelf32i370.o \ eelf32l4300.o \ eelf32lmip.o \ @@ -526,6 +527,9 @@ eelf32vax.c: $(srcdir)/emulparams/elf32v eelf32fr30.c: $(srcdir)/emulparams/elf32fr30.sh \ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32fr30 "$(tdir_fr30)" +eelf32frv.c: $(srcdir)/emulparams/elf32frv.sh \ + $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ${GENSCRIPTS} elf32frv "$(tdir_frv)" eelf32mcore.c: $(srcdir)/emulparams/elf32mcore.sh \ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32mcore "$(tdir_mcore)" diff -uprN binutils-2.12.90.0.11/ld/Makefile.in binutils-2.12.90.0.12/ld/Makefile.in --- binutils-2.12.90.0.11/ld/Makefile.in Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/ld/Makefile.in Tue Jun 18 21:41:59 2002 @@ -186,7 +186,7 @@ INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) BFDLIB = ../bfd/libbfd.la LIBIBERTY = ../libiberty/libiberty.a -ALL_EMULATIONS = ea29k.o eaixppc.o eaixrs6.o ealpha.o earcelf.o earm_epoc_pe.o earmaoutb.o earmaoutl.o earmcoff.o earmelf.o earmelf_fbsd.o earmelf_linux.o earmelf_nbsd.o earmelfb_nbsd.o earmelf_oabi.o earmnbsd.o earmpe.o eavr1200.o eavr23xx.o eavr4433.o eavr44x4.o eavr85xx.o eavrmega103.o eavrmega161.o eavrmega603.o eavr1.o eavr2.o eavr3.o eavr4.o eavr5.o ecoff_sparc.o ecrisaout.o ecriself.o ecrislinux.o ed10velf.o ed30v_e.o ed30v_o.o ed30velf.o edelta68.o eelf32_dlx.o eebmon29k.o eelf32_i960.o eelf32_i860.o eelf32_sparc.o eelf32b4300.o eelf32bmip.o eelf32bmipn32.o eelf32btsmip.o eelf32ltsmip.o eelf32ebmip.o eelf32elmip.o eelf32fr30.o eelf32i370.o eelf32l4300.o eelf32lmip.o eelf32lppc.o eelf32lppcsim.o eelf32mcore.o eelf32openrisc.o eelf32ppc.o eelf32ppc_fbsd.o eelf32ppclinux.o eelf32ppcsim.o eelf32ppcwindiss.o eelf32vax.o eelf32xstormy16.o eelf_i386.o eelf_i386_be.o eelf_i386_chaos.o eelf_i386_fbsd.o eelf_i386_ldso.o eelf_s390.o egld960.o egld960coff.o eh8300.o eh8300h.o eh8300s.o eh8300elf.o eh8300helf.o eh8300self.o eh8500.o eh8500b.o eh8500c.o eh8500m.o eh8500s.o ehp300bsd.o ehp3hpux.o ehppaelf.o ehppalinux.o ehppanbsd.o ei386aout.o ei386beos.o ei386bsd.o ei386coff.o ei386go32.o ei386linux.o ei386lynx.o ei386mach.o ei386moss.o ei386msdos.o ei386nbsd.o ei386nto.o ei386nw.o ei386pe.o ei386pe_posix.o elnk960.o em68hc11elf.o em68hc11elfb.o em68hc12elf.o em68hc12elfb.o em68k4knbsd.o em68kaout.o em68kaux.o em68kcoff.o em68kelf.o em68kelfnbsd.o em68klinux.o em68klynx.o em68knbsd.o em68kpsos.o em88kbcs.o emcorepe.o emipsbig.o emipsbsd.o emipsidt.o emipsidtl.o emipslit.o emipslnews.o emipspe.o enews.o ens32knbsd.o eor32.o eor32elf.o epc532macha.o epdp11.o epjelf.o epjlelf.o eppcmacos.o eppcnw.o eppcpe.o eriscix.o esa29200.o esh.o eshelf32.o eshlelf32.o eshelf32_nbsd.o eshlelf32_nbsd.o eshelf.o eshelf_linux.o eshlelf_linux.o eshelf_nbsd.o eshlelf_nbsd.o eshl.o eshlelf.o eshpe.o esparcaout.o esparclinux.o esparclynx.o esparcnbsd.o est2000.o esun3.o esun4.o etic30aout.o etic30coff.o etic54xcoff.o etic80coff.o evanilla.o evax.o evaxnbsd.o evsta.o ew65.o ez8001.o ez8002.o +ALL_EMULATIONS = ea29k.o eaixppc.o eaixrs6.o ealpha.o earcelf.o earm_epoc_pe.o earmaoutb.o earmaoutl.o earmcoff.o earmelf.o earmelf_fbsd.o earmelf_linux.o earmelf_nbsd.o earmelfb_nbsd.o earmelf_oabi.o earmnbsd.o earmpe.o eavr1200.o eavr23xx.o eavr4433.o eavr44x4.o eavr85xx.o eavrmega103.o eavrmega161.o eavrmega603.o eavr1.o eavr2.o eavr3.o eavr4.o eavr5.o ecoff_sparc.o ecrisaout.o ecriself.o ecrislinux.o ed10velf.o ed30v_e.o ed30v_o.o ed30velf.o edelta68.o eelf32_dlx.o eebmon29k.o eelf32_i960.o eelf32_i860.o eelf32_sparc.o eelf32b4300.o eelf32bmip.o eelf32bmipn32.o eelf32btsmip.o eelf32ltsmip.o eelf32ebmip.o eelf32elmip.o eelf32fr30.o eelf32frv.o eelf32i370.o eelf32l4300.o eelf32lmip.o eelf32lppc.o eelf32lppcsim.o eelf32mcore.o eelf32openrisc.o eelf32ppc.o eelf32ppc_fbsd.o eelf32ppclinux.o eelf32ppcsim.o eelf32ppcwindiss.o eelf32vax.o eelf32xstormy16.o eelf_i386.o eelf_i386_be.o eelf_i386_chaos.o eelf_i386_fbsd.o eelf_i386_ldso.o eelf_s390.o egld960.o egld960coff.o eh8300.o eh8300h.o eh8300s.o eh8300elf.o eh8300helf.o eh8300self.o eh8500.o eh8500b.o eh8500c.o eh8500m.o eh8500s.o ehp300bsd.o ehp3hpux.o ehppaelf.o ehppalinux.o ehppanbsd.o ei386aout.o ei386beos.o ei386bsd.o ei386coff.o ei386go32.o ei386linux.o ei386lynx.o ei386mach.o ei386moss.o ei386msdos.o ei386nbsd.o ei386nto.o ei386nw.o ei386pe.o ei386pe_posix.o elnk960.o em68hc11elf.o em68hc11elfb.o em68hc12elf.o em68hc12elfb.o em68k4knbsd.o em68kaout.o em68kaux.o em68kcoff.o em68kelf.o em68kelfnbsd.o em68klinux.o em68klynx.o em68knbsd.o em68kpsos.o em88kbcs.o emcorepe.o emipsbig.o emipsbsd.o emipsidt.o emipsidtl.o emipslit.o emipslnews.o emipspe.o enews.o ens32knbsd.o eor32.o eor32elf.o epc532macha.o epdp11.o epjelf.o epjlelf.o eppcmacos.o eppcnw.o eppcpe.o eriscix.o esa29200.o esh.o eshelf32.o eshlelf32.o eshelf32_nbsd.o eshlelf32_nbsd.o eshelf.o eshelf_linux.o eshlelf_linux.o eshelf_nbsd.o eshlelf_nbsd.o eshl.o eshlelf.o eshpe.o esparcaout.o esparclinux.o esparclynx.o esparcnbsd.o est2000.o esun3.o esun4.o etic30aout.o etic30coff.o etic54xcoff.o etic80coff.o evanilla.o evax.o evaxnbsd.o evsta.o ew65.o ez8001.o ez8002.o ALL_64_EMULATIONS = eelf64_aix.o eelf64_ia64.o eelf64_ia64_fbsd.o eshelf64.o eshlelf64.o eshelf64_nbsd.o eshlelf64_nbsd.o eelf_x86_64.o eelf_x86_64_fbsd.o eelf64_s390.o eelf64_sparc.o eelf64_sparc_fbsd.o eelf64alpha.o eelf64alpha_fbsd.o eelf64alpha_nbsd.o eelf64bmip.o eelf64btsmip.o eelf64ltsmip.o eelf64hppa.o eelf64mmix.o emmo.o eelf64ppc.o eelf64lppc.o ehppa64linux.o @@ -1011,6 +1011,9 @@ eelf32vax.c: $(srcdir)/emulparams/elf32v eelf32fr30.c: $(srcdir)/emulparams/elf32fr30.sh \ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32fr30 "$(tdir_fr30)" +eelf32frv.c: $(srcdir)/emulparams/elf32frv.sh \ + $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ${GENSCRIPTS} elf32frv "$(tdir_frv)" eelf32mcore.c: $(srcdir)/emulparams/elf32mcore.sh \ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32mcore "$(tdir_mcore)" diff -uprN binutils-2.12.90.0.11/ld/NEWS binutils-2.12.90.0.12/ld/NEWS --- binutils-2.12.90.0.11/ld/NEWS Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/ld/NEWS Tue Jun 18 21:41:59 2002 @@ -1,4 +1,7 @@ -*- text -*- +Support for the Fujitsu FRV architecture added by Red Hat. Models for FR400 and +FR500 included. + Changes in version 2.13: * DEC VAX ELF support, by Matt Thomas. diff -uprN binutils-2.12.90.0.11/ld/configure.tgt binutils-2.12.90.0.12/ld/configure.tgt --- binutils-2.12.90.0.11/ld/configure.tgt Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/ld/configure.tgt Tue Jun 18 21:41:59 2002 @@ -294,11 +294,11 @@ sh*-*-netbsdelf*) targ_emul=shelf_nbsd targ_extra_emuls=shlelf_nbsd ;; -shle*-*-elf*) +shle*-*-elf* | sh[1234]*le*-*-elf) targ_emul=shlelf targ_extra_emuls="shelf shl sh" ;; -sh-*-elf* | sh-*-rtemself*) +sh-*-elf* | sh[1234]*-*-elf | sh-*-rtemself*) targ_emul=shelf targ_extra_emuls="shlelf sh shl" ;; @@ -481,6 +481,7 @@ tic80-*-*) targ_emul=tic80coff ;; v850-*-*) targ_emul=v850 ;; v850e-*-*) targ_emul=v850 ;; v850ea-*-*) targ_emul=v850 ;; +frv-*-*) targ_emul=elf32frv ;; w65-*-*) targ_emul=w65 ;; xstormy16-*-*) targ_emul=elf32xstormy16 ;; fr30-*-*) targ_emul=elf32fr30 ;; diff -uprN binutils-2.12.90.0.11/ld/emulparams/d10velf.sh binutils-2.12.90.0.12/ld/emulparams/d10velf.sh --- binutils-2.12.90.0.11/ld/emulparams/d10velf.sh Fri Sep 10 13:02:40 1999 +++ binutils-2.12.90.0.12/ld/emulparams/d10velf.sh Tue Jun 18 21:41:59 2002 @@ -1,7 +1,7 @@ MACHINE= SCRIPT_NAME=elfd10v OUTPUT_FORMAT="elf32-d10v" -TEXT_START_ADDR=0x01000000 +TEXT_START_ADDR=0x01014000 READONLY_START_ADDR=0x02000004 ARCH=d10v MAXPAGESIZE=32 diff -uprN binutils-2.12.90.0.11/ld/emulparams/elf32frv.sh binutils-2.12.90.0.12/ld/emulparams/elf32frv.sh --- binutils-2.12.90.0.11/ld/emulparams/elf32frv.sh Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/emulparams/elf32frv.sh Tue Jun 18 21:41:59 2002 @@ -0,0 +1,20 @@ +MACHINE= +SCRIPT_NAME=elf +OUTPUT_FORMAT="elf32-frv" +TEXT_START_ADDR=0x10000 +ARCH=frv +MAXPAGESIZE=256 +ENTRY=_start +EMBEDDED=yes +OTHER_EXCLUDE_FILES='*frvend.o' +OTHER_BSS_END_SYMBOLS='__end = .;' +DATA_START_SYMBOLS='__data_start = . ;' +OTHER_RELOCATING_SECTIONS=' + PROVIDE (_stack = 0x200000); + PROVIDE (__stack = 0x200000);' +OTHER_GOT_SYMBOLS=' + . = ALIGN(8); _gp = . + 2048; + PROVIDE (gp = _gp);' +OTHER_READONLY_SECTIONS=' + .rofixup : { *(.rofixup) } +' diff -uprN binutils-2.12.90.0.11/ld/emultempl/elf32.em binutils-2.12.90.0.12/ld/emultempl/elf32.em --- binutils-2.12.90.0.11/ld/emultempl/elf32.em Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/ld/emultempl/elf32.em Tue Jun 18 21:41:59 2002 @@ -281,6 +281,13 @@ gld${EMULATION_NAME}_try_needed (name, f return false; } + /* For DT_NEEDED, they have to match. */ + if (abfd->xvec != output_bfd->xvec) + { + bfd_close (abfd); + return false; + } + /* Check whether this object would include any conflicting library versions. If FORCE is set, then we skip this check; we use this the second time around, if we couldn't find any compatible @@ -1394,13 +1401,17 @@ echo ' ; else if (!config.magic_demand_ sed $sc ldscripts/${EMULATION_NAME}.xn >> e${EMULATION_NAME}.c fi if test -n "$GENERATE_SHLIB_SCRIPT" ; then +if test -n "$GENERATE_COMBRELOC_SCRIPT" ; then echo ' ; else if (link_info.shared && link_info.combreloc) return' >> e${EMULATION_NAME}.c sed $sc ldscripts/${EMULATION_NAME}.xsc >> e${EMULATION_NAME}.c +fi echo ' ; else if (link_info.shared) return' >> e${EMULATION_NAME}.c sed $sc ldscripts/${EMULATION_NAME}.xs >> e${EMULATION_NAME}.c fi +if test -n "$GENERATE_COMBRELOC_SCRIPT" ; then echo ' ; else if (link_info.combreloc) return' >> e${EMULATION_NAME}.c sed $sc ldscripts/${EMULATION_NAME}.xc >> e${EMULATION_NAME}.c +fi echo ' ; else return' >> e${EMULATION_NAME}.c sed $sc ldscripts/${EMULATION_NAME}.x >> e${EMULATION_NAME}.c echo '; }' >> e${EMULATION_NAME}.c diff -uprN binutils-2.12.90.0.11/ld/emultempl/mipself.em binutils-2.12.90.0.12/ld/emultempl/mipself.em --- binutils-2.12.90.0.11/ld/emultempl/mipself.em Sun Feb 3 11:22:32 2002 +++ binutils-2.12.90.0.12/ld/emultempl/mipself.em Tue Jun 18 21:41:59 2002 @@ -124,7 +124,7 @@ mips_elf${ELFSIZE}_check_sections (abfd, if ((bfd_get_section_flags (abfd, sec) & SEC_CODE) == 0 && sec != (asection *) sdatasec && sec->reloc_count != 0) - einfo ("%F%X: section %s has relocs; cannot use --embedded-relocs\n", + einfo ("%B%X: section %s has relocs; cannot use --embedded-relocs\n", abfd, bfd_get_section_name (abfd, sec)); } #endif /* SUPPORT_EMBEDDED_RELOCS */ diff -uprN binutils-2.12.90.0.11/ld/ldlang.c binutils-2.12.90.0.12/ld/ldlang.c --- binutils-2.12.90.0.11/ld/ldlang.c Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/ld/ldlang.c Tue Jun 18 21:41:59 2002 @@ -2907,6 +2907,14 @@ lang_size_sections_1 (s, output_section_ /* This section was never actually created. */ break; + /* The section might have been removed after its statement was + added. For example, ldemul_before_allocation can remove + dynamic sections if they turn out not to be needed. */ + if (!link_info.relocateable + && (bfd_get_section_flags (output_bfd, os->bfd_section) + & SEC_EXCLUDE) != 0) + break; + /* If this is a COFF shared library section, use the size and address from the input section. FIXME: This is COFF specific; it would be cleaner if there were some other way diff -uprN binutils-2.12.90.0.11/ld/scripttempl/elfd10v.sc binutils-2.12.90.0.12/ld/scripttempl/elfd10v.sc --- binutils-2.12.90.0.11/ld/scripttempl/elfd10v.sc Fri Mar 9 11:18:25 2001 +++ binutils-2.12.90.0.12/ld/scripttempl/elfd10v.sc Tue Jun 18 21:41:59 2002 @@ -66,14 +66,14 @@ ${RELOCATING+${EXECUTABLE_SYMBOLS}} MEMORY { UNIFIED : org = 0, len = 0x1000000 - INSN : org = 0x1000000, len = 0x40000 + INSN : org = 0x1014000, len = 0x40000 DATA : org = 0x2000004, len = 0x7FFC - STACK : org = 0x2007FFE, len = 4 + STACK : org = 0x200BFFE, len = 4 } SECTIONS { - .text : + .text ${RELOCATING+${TEXT_START_ADDR}} : { ${RELOCATING+${TEXT_START_SYMBOLS}} KEEP (*(.init)) diff -uprN binutils-2.12.90.0.11/ld/testsuite/ChangeLog binutils-2.12.90.0.12/ld/testsuite/ChangeLog --- binutils-2.12.90.0.11/ld/testsuite/ChangeLog Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/ld/testsuite/ChangeLog Tue Jun 18 21:41:59 2002 @@ -1,3 +1,33 @@ +2002-06-18 Chris Demetriou + + * ld-mips-elf/empic2-ref.s: Add a missing .end, apparently + turned up by recent assembler changes. + +2002-06-17 Tom Rix + + * ld-d10v/d10v.exp: New driver for d10v. + * ld-d10v/default_layout.d : New test. + * ld-d10v/regression-001.lt: New test for a linker regression. + * ld-d10v/linktest-002.lt: New test for run_link_test. + * ld-d10v/reloc-001.d - reloc-016.d: New tests. + +2002-06-11 John David Anglin + + * ld-scripts/cross1.t: Add .hash, .dynstr and .dynsym sections to + script. + +2002-06-11 Andreas Jaeger + + * ld-undefined/undefined.exp: Add s390x to dwarf2 xfails. + +2002-06-10 Richard Sandiford + + * ld-mips-elf/region1a.s, + * ld-mips-elf/region1b.s, + * ld-mips-elf/region1.t, + * ld-mips-elf/region1.d: New test. + * ld-mips-elf/mips-elf.exp: Run it. + 2002-06-07 Nick Clifton * ld-scripts/phdrs2.s: Use .p2align instead of .align. diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/d10v.exp binutils-2.12.90.0.12/ld/testsuite/ld-d10v/d10v.exp --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/d10v.exp Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/d10v.exp Tue Jun 18 21:41:59 2002 @@ -0,0 +1,250 @@ +# Expect script for ld-d10v tests +# Copyright 2002 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# Written by Tom Rix, trix@redhat.com +# + +# Test d10v + +if ![istarget d10v-*-*] { + return +} + +# run_link_test FILE +# Copied from run_dump_test, with the dumping part removed. +# +# Assemble a .s file, then run some utility on it and check the output. +# +# There should be an assembly language file named FILE.s in the test +# suite directory. `run_link_test' will assemble and link FILE.s +# +# The FILE.lt file begins with zero or more option lines, which specify +# flags to pass to the assembler, the program to run to dump the +# assembler's output, and the options it wants. The option lines have +# the syntax: +# +# # OPTION: VALUE +# +# OPTION is the name of some option, like "name" or "ld", and +# VALUE is OPTION's value. The valid options are described below. +# Whitespace is ignored everywhere, except within VALUE. The option +# list ends with the first line that doesn't match the above syntax +# (hmm, not great for error detection). +# +# The interesting options are: +# +# name: TEST-NAME +# The name of this test, passed to DejaGNU's `pass' and `fail' +# commands. If omitted, this defaults to FILE, the root of the +# .s and .d files' names. +# +# as: FLAGS +# When assembling, pass FLAGS to the assembler. +# If assembling several files, you can pass different assembler +# options in the "source" directives. See below. +# +# ld: FLAGS +# Link assembled files using FLAGS, in the order of the "source" +# directives, when using multiple files. +# +# source: SOURCE [FLAGS] +# Assemble the file SOURCE.s using the flags in the "as" directive +# and the (optional) FLAGS. If omitted, the source defaults to +# FILE.s. +# This is useful if several .x files want to share a .s file. +# More than one "source" directive can be given, which is useful +# when testing linking. +# +# xfail: TARGET +# The test is expected to fail on TARGET. This may occur more than +# once. +# +# target: TARGET +# Only run the test for TARGET. This may occur more than once; the +# target being tested must match at least one. +# +# notarget: TARGET +# Do not run the test for TARGET. This may occur more than once; +# the target being tested must not match any of them. +# +# Each option may occur at most once unless otherwise mentioned. +# + +proc run_link_test { name } { + global subdir srcdir + global AS LD + global ASFLAGS LDFLAGS + global host_triplet runtests + + if [string match "*/*" $name] { + set file $name + set name [file tail $name] + } else { + set file "$srcdir/$subdir/$name" + } + + if ![runtest_file_p $runtests $name] then { + return + } + + set opt_array [slurp_options "${file}.lt"] + if { $opt_array == -1 } { + perror "error reading options from $file.lt" + unresolved $subdir/$name + return + } + set dumpfile tmpdir/dump.out + set run_ld 0 + set opts(as) {} + set opts(ld) {} + set opts(xfail) {} + set opts(target) {} + set opts(notarget) {} + set opts(name) {} + set opts(source) {} + set asflags(${file}.s) {} + + foreach i $opt_array { + set opt_name [lindex $i 0] + set opt_val [lindex $i 1] + if ![info exists opts($opt_name)] { + perror "unknown option $opt_name in file $file.lt" + unresolved $subdir/$name + return + } + + switch -- $opt_name { + xfail {} + target {} + notarget {} + source { + # Move any source-specific as-flags to a separate array to + # simplify processing. + if { [llength $opt_val] > 1 } { + set asflags([lindex $opt_val 0]) [lrange $opt_val 1 end] + set opt_val [lindex $opt_val 0] + } else { + set asflags($opt_val) {} + } + } + default { + if [string length $opts($opt_name)] { + perror "option $opt_name multiply set in $file.lt" + unresolved $subdir/$name + return + } + } + } + set opts($opt_name) [concat $opts($opt_name) $opt_val] + } + + # Decide early whether we should run the test for this target. + if { [llength $opts(target)] > 0 } { + set targmatch 0 + foreach targ $opts(target) { + if [istarget $targ] { + set targmatch 1 + break + } + } + if { $targmatch == 0 } { + return + } + } + foreach targ $opts(notarget) { + if [istarget $targ] { + return + } + } + + if { $opts(name) == "" } { + set testname "$subdir/$name" + } else { + set testname $opts(name) + } + + if { $opts(source) == "" } { + set sourcefiles [list ${file}.s] + } else { + set sourcefiles {} + foreach sf $opts(source) { + lappend sourcefiles "$srcdir/$subdir/$sf" + # Must have asflags indexed on source name. + set asflags($srcdir/$subdir/$sf) $asflags($sf) + } + } + + # Time to setup xfailures. + foreach targ $opts(xfail) { + setup_xfail $targ + } + + # Assemble each file. + set objfiles {} + for { set i 0 } { $i < [llength $sourcefiles] } { incr i } { + set sourcefile [lindex $sourcefiles $i] + + set objfile "tmpdir/dump$i.o" + lappend objfiles $objfile + set cmd "$AS $ASFLAGS $opts(as) $asflags($sourcefile) -o $objfile $sourcefile" + + send_log "$cmd\n" + set cmdret [catch "exec $cmd" comp_output] + set comp_output [prune_warnings $comp_output] + + # We accept errors at assembly stage too, unless we're supposed to + # link something. + if { $cmdret != 0 || ![string match "" $comp_output] } then { + send_log "$comp_output\n" + verbose "$comp_output" 3 + fail $testname + return + } + } + + # Link the file(s). + set objfile "tmpdir/dump" + set cmd "$LD $LDFLAGS $opts(ld) -o $objfile $objfiles" + + send_log "$cmd\n" + set cmdret [catch "exec $cmd" comp_output] + set comp_output [prune_warnings $comp_output] + + if { $cmdret != 0 || ![string match "" $comp_output] } then { + + send_log "$comp_output\n" + verbose "$comp_output" 3 + fail $testname + return + } + pass $testname +} + + +set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]] +foreach test $test_list { + # We need to strip the ".d", but can leave the dirname. + verbose [file rootname $test] + run_dump_test [file rootname $test] +} + +set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.lt]] +foreach test $test_list { + # We need to strip the ".lt", but can leave the dirname. + verbose [file rootname $test] + run_link_test [file rootname $test] +} diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/default_layout.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/default_layout.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/default_layout.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/default_layout.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,16 @@ +#source: simple.s +#ld: +#objdump: -h + +.*: file format elf32-d10v + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.text 00000004 01014000 01014000 00001000 2\*\*0 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 \.data 00000000 02000004 02000004 00001004 2\*\*0 + CONTENTS, ALLOC, LOAD, DATA + 2 \.bss 00000000 02000004 02000004 00001004 2\*\*0 + ALLOC + 3 .stack 00000000 0200bffe 0200bffe 00001004 2\*\*0 + CONTENTS diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/linktest-001.s binutils-2.12.90.0.12/ld/testsuite/ld-d10v/linktest-001.s --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/linktest-001.s Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/linktest-001.s Tue Jun 18 21:41:59 2002 @@ -0,0 +1,4 @@ + .section .data + .global bar +bar: + .space 64 diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/linktest-002.lt binutils-2.12.90.0.12/ld/testsuite/ld-d10v/linktest-002.lt --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/linktest-002.lt Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/linktest-002.lt Tue Jun 18 21:41:59 2002 @@ -0,0 +1,2 @@ +#source: linktest-001.s +#source: linktest-002.s diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/linktest-002.s binutils-2.12.90.0.12/ld/testsuite/ld-d10v/linktest-002.s --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/linktest-002.s Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/linktest-002.s Tue Jun 18 21:41:59 2002 @@ -0,0 +1,4 @@ + .section .text + .global _start +_start: + ldi r0,bar diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/regression-001.lt binutils-2.12.90.0.12/ld/testsuite/ld-d10v/regression-001.lt --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/regression-001.lt Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/regression-001.lt Tue Jun 18 21:41:59 2002 @@ -0,0 +1,3 @@ +#source: regression-001.s +#as: -W + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/regression-001.s binutils-2.12.90.0.12/ld/testsuite/ld-d10v/regression-001.s --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/regression-001.s Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/regression-001.s Tue Jun 18 21:41:59 2002 @@ -0,0 +1,14 @@ + .section .data + ;; + ;; The next line caused an earlier ld to core dump. + .global .data +foo: + .space 0x0064 + + .section .text + .global _test + .global _start +_test: + ldi r0,foo +_start: + nop diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-001.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-001.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-001.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-001.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,14 @@ +#source: reloc-001.s +#ld: -T $srcdir/$subdir/reloc-001.ld +#objdump: -D + +# Test 10 bit pc rel reloc normal case + +.*: file format elf32-d10v + +Disassembly of section .text: + +01014000 <_start>: + 1014000: 65 20 cc 1a brf0f.s 1014104 -> jmp r13 +Disassembly of section .data: + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-001.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-001.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-001.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-001.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,10 @@ +SECTIONS +{ + .text 0x01014000 : + { + *(.text) + foo = (. + 0x100); + } +} + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-001.s binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-001.s --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-001.s Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-001.s Tue Jun 18 21:41:59 2002 @@ -0,0 +1,11 @@ + ;; Test pc relative relocation + + .text + .global _start +_start: + brf0f.s foo + jmp r13 + + + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-002.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-002.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-002.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-002.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,13 @@ +#source: reloc-001.s +#ld: -T $srcdir/$subdir/reloc-002.ld +#objdump: -D + +# Test 10 bit pc rel reloc good boundary. + +.*: file format elf32-d10v + +Disassembly of section .text: + +01014000 <_start>: + 1014000: 65 3f cc 1a brf0f.s 10141fc -> jmp r13 +Disassembly of section .data: diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-002.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-002.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-002.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-002.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,10 @@ +SECTIONS +{ + .text 0x01014000 : + { + *(.text) + foo = (. + 0x1F8); + } +} + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-003.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-003.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-003.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-003.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,5 @@ +#source: reloc-001.s +#ld: -T $srcdir/$subdir/reloc-003.ld +#error: relocation truncated to fit: R_D10V_10_PCREL_L foo$ + +# Test 10 bit pc rel reloc bad boundary. \ No newline at end of file diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-003.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-003.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-003.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-003.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,10 @@ +SECTIONS +{ + .text 0x01014000 : + { + *(.text) + foo = (. + 0x1FC); + } +} + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-004.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-004.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-004.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-004.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,5 @@ +#source: reloc-001.s +#ld: -T $srcdir/$subdir/reloc-004.ld +#error: relocation truncated to fit: R_D10V_10_PCREL_L foo$ + +# Test 10 bit pc rel reloc normal bad. \ No newline at end of file diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-004.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-004.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-004.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-004.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,10 @@ +SECTIONS +{ + .text 0x01014000 : + { + foo = .; + . = (. + 0x400); + } +} + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-005.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-005.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-005.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-005.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,14 @@ +#source: reloc-005.s +#ld: -T $srcdir/$subdir/reloc-005.ld +#objdump: -D + +# Test 18 bit pc rel reloc normal case + +.*: file format elf32-d10v + +Disassembly of section .text: + +01014000 <_start>: + 1014000: e4 00 10 02 bra.l 1018008 + 1014004: 26 0d 5e 00 jmp r13 || nop +Disassembly of section .data: diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-005.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-005.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-005.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-005.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,10 @@ +SECTIONS +{ + .text 0x01014000 : + { + *(.text) + foo = (. + 0x4000); + } +} + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-005.s binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-005.s --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-005.s Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-005.s Tue Jun 18 21:41:59 2002 @@ -0,0 +1,11 @@ + ;; Test 18 bit pc rel relocation + + .text + .global _start +_start: + bra.l foo + jmp r13 + + + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-006.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-006.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-006.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-006.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,14 @@ +#source: reloc-005.s +#ld: -T $srcdir/$subdir/reloc-006.ld +#objdump: -D + +# Test 18 bit pc rel reloc good boundary + +.*: file format elf32-d10v + +Disassembly of section .text: + +01014000 <_start>: + 1014000: e4 00 7f ff bra.l 1033ffc + 1014004: 26 0d 5e 00 jmp r13 || nop +Disassembly of section .data: diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-006.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-006.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-006.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-006.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,8 @@ +SECTIONS +{ + .text 0x01014000 : + { + *(.text) + foo = (. + 0x1fff4); + } +} diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-007.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-007.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-007.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-007.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,7 @@ +#source: reloc-005.s +#ld: -T $srcdir/$subdir/reloc-007.ld +#objdump: -D +#error: relocation truncated to fit: R_D10V_18_PCREL foo$ + +# Test 18 bit pc rel reloc bad boundary + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-007.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-007.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-007.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-007.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,8 @@ +SECTIONS +{ + .text 0x01014000 : + { + *(.text) + foo = (. + 0x1fff8); + } +} diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-008.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-008.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-008.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-008.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,7 @@ +#source: reloc-005.s +#ld: -T $srcdir/$subdir/reloc-008.ld +#objdump: -D +#error: relocation truncated to fit: R_D10V_18_PCREL foo$ + +# Test 18 bit pc rel reloc normal bad + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-008.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-008.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-008.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-008.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,8 @@ +SECTIONS +{ + .text 0x01014000 : + { + *(.text) + foo = (. + 0x41fff8); + } +} diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-009.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-009.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-009.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-009.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,16 @@ +#source: reloc-009.s +#ld: -T $srcdir/$subdir/reloc-009.ld +#objdump: -D + +# Test 10 bit pc rel reloc negative normal case + +.*: file format elf32-d10v +Disassembly of section .text: + +01014000 : + ... + +01014100 <_start>: + 1014100: 6f 00 4a c0 nop -> brf0f.s 1014000 + 1014104: 26 0d 5e 00 jmp r13 || nop +Disassembly of section .data: diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-009.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-009.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-009.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-009.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,11 @@ +SECTIONS +{ + .text 0x01014000 : + { + foo = .; + . = (. + 0x100); + *(.text) + } +} + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-009.s binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-009.s --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-009.s Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-009.s Tue Jun 18 21:41:59 2002 @@ -0,0 +1,12 @@ + ;; Test pc relative relocation + + .text + .global _start +_start: + nop + brf0f.s foo + jmp r13 + + + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-010.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-010.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-010.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-010.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,17 @@ +#source: reloc-009.s +#ld: -T $srcdir/$subdir/reloc-010.ld +#objdump: -D + +# Test 10 bit pc rel reloc negative good boundary case + +.*: file format elf32-d10v + +Disassembly of section .text: + +01014000 : + ... + +01014200 <_start>: + 1014200: 6f 00 4a 80 nop -> brf0f.s 1014000 + 1014204: 26 0d 5e 00 jmp r13 || nop +Disassembly of section .data: diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-010.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-010.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-010.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-010.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,11 @@ +SECTIONS +{ + .text 0x01014000 : + { + foo = .; + . = (. + 0x200); + *(.text) + } +} + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-011.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-011.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-011.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-011.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,6 @@ +#source: reloc-009.s +#ld: -T $srcdir/$subdir/reloc-011.ld +#error: relocation truncated to fit: R_D10V_10_PCREL_R foo$ + +# Test 10 bit pc rel reloc negative bad boundary. + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-011.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-011.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-011.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-011.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,11 @@ +SECTIONS +{ + .text 0x01014000 : + { + foo = .; + . = (. + 0x204); + *(.text) + } +} + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-012.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-012.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-012.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-012.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,6 @@ +#source: reloc-009.s +#ld: -T $srcdir/$subdir/reloc-012.ld +#error: relocation truncated to fit: R_D10V_10_PCREL_R foo$ + +# Test 10 bit pc rel reloc negative normal bad. + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-012.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-012.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-012.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-012.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,11 @@ +SECTIONS +{ + .text 0x01014000 : + { + foo = .; + . = (. + 0x80004); + *(.text) + } +} + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-013.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-013.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-013.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-013.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,17 @@ +#source: reloc-005.s +#ld: -T $srcdir/$subdir/reloc-013.ld +#objdump: -D + +# Test 18 bit pc rel reloc negative normal case + +.*: file format elf32-d10v + +Disassembly of section .text: + +01014000 : + ... + +01014400 <_start>: + 1014400: e4 00 ff 00 bra.l 1014000 + 1014404: 26 0d 5e 00 jmp r13 || nop +Disassembly of section .data: diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-013.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-013.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-013.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-013.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,12 @@ +SECTIONS +{ + .text 0x01014000 : + { + foo = .; + . = (. + 0x400); + *(.text) + } +} + + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-014.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-014.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-014.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-014.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,17 @@ +#source: reloc-005.s +#ld: -T $srcdir/$subdir/reloc-014.ld +#objdump: -D + +# Test 18 bit pc rel reloc negative good boundary case + +.*: file format elf32-d10v + +Disassembly of section .text: + +01014000 : + ... + +01034000 <_start>: + 1034000: e4 00 80 00 bra.l 1014000 + 1034004: 26 0d 5e 00 jmp r13 || nop +Disassembly of section .data: diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-014.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-014.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-014.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-014.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,12 @@ +SECTIONS +{ + .text 0x01014000 : + { + foo = .; + . = (. + 0x20000); + *(.text) + } +} + + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-015.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-015.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-015.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-015.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,7 @@ +#source: reloc-005.s +#ld: -T $srcdir/$subdir/reloc-015.ld +#objdump: -D +#error: relocation truncated to fit: R_D10V_18_PCREL foo$ + +# Test 18 bit pc rel negative reloc bad boundary + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-015.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-015.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-015.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-015.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,12 @@ +SECTIONS +{ + .text 0x01014000 : + { + foo = .; + . = (. + 0x20004); + *(.text) + } +} + + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-016.d binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-016.d --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-016.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-016.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,7 @@ +#source: reloc-005.s +#ld: -T $srcdir/$subdir/reloc-016.ld +#objdump: -D +#error: relocation truncated to fit: R_D10V_18_PCREL foo$ + +# Test 18 bit pc rel negative reloc normal bad + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-016.ld binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-016.ld --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/reloc-016.ld Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/reloc-016.ld Tue Jun 18 21:41:59 2002 @@ -0,0 +1,12 @@ +SECTIONS +{ + .text 0x01014000 : + { + foo = .; + . = (. + 0x800004); + *(.text) + } +} + + + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-d10v/simple.s binutils-2.12.90.0.12/ld/testsuite/ld-d10v/simple.s --- binutils-2.12.90.0.11/ld/testsuite/ld-d10v/simple.s Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-d10v/simple.s Tue Jun 18 21:41:59 2002 @@ -0,0 +1,5 @@ + .text + .global _start +_start: + jmp r13 + diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-mips-elf/empic2-ref.s binutils-2.12.90.0.12/ld/testsuite/ld-mips-elf/empic2-ref.s --- binutils-2.12.90.0.11/ld/testsuite/ld-mips-elf/empic2-ref.s Sun Feb 3 11:22:33 2002 +++ binutils-2.12.90.0.12/ld/testsuite/ld-mips-elf/empic2-ref.s Tue Jun 18 21:41:59 2002 @@ -2,5 +2,6 @@ .ent foo foo: la $2,bar-foo + .end foo .p2align 4 diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-mips-elf/mips-elf.exp binutils-2.12.90.0.12/ld/testsuite/ld-mips-elf/mips-elf.exp --- binutils-2.12.90.0.11/ld/testsuite/ld-mips-elf/mips-elf.exp Sun Feb 3 11:22:33 2002 +++ binutils-2.12.90.0.12/ld/testsuite/ld-mips-elf/mips-elf.exp Tue Jun 18 21:41:59 2002 @@ -38,5 +38,7 @@ if { [istarget mips*-*-*] } then { # Check generation of embedded relocs section. run_dump_test "emrelocs-eb" run_dump_test "emrelocs-el" + + run_dump_test "region1" } } diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-mips-elf/region1.d binutils-2.12.90.0.12/ld/testsuite/ld-mips-elf/region1.d --- binutils-2.12.90.0.11/ld/testsuite/ld-mips-elf/region1.d Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-mips-elf/region1.d Tue Jun 18 21:41:59 2002 @@ -0,0 +1,11 @@ +# as: -mabi=eabi -mips1 -G0 +# source: region1a.s +# source: region1b.s +# ld: -T region1.t +# name: MIPS region1 +# objdump: --headers +#... + 0 \.text +0+004 +0+10000 .* +#... + 1 \.data +0+004 +0+20000 .* +#pass diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-mips-elf/region1.t binutils-2.12.90.0.12/ld/testsuite/ld-mips-elf/region1.t --- binutils-2.12.90.0.11/ld/testsuite/ld-mips-elf/region1.t Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-mips-elf/region1.t Tue Jun 18 21:41:59 2002 @@ -0,0 +1,12 @@ +MEMORY +{ + TEXTMEM : ORIGIN = 0x10000, LENGTH = 32K + DATAMEM : ORIGIN = 0x20000, LENGTH = 32K +} + +SECTIONS +{ + .text : { *(.text) } > TEXTMEM + .data : { *(.data) } > DATAMEM + .bss : { *(.bss) } > DATAMEM +} diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-mips-elf/region1a.s binutils-2.12.90.0.12/ld/testsuite/ld-mips-elf/region1a.s --- binutils-2.12.90.0.11/ld/testsuite/ld-mips-elf/region1a.s Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-mips-elf/region1a.s Tue Jun 18 21:41:59 2002 @@ -0,0 +1,3 @@ + .text + .global foo +foo: .4byte 1 diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-mips-elf/region1b.s binutils-2.12.90.0.12/ld/testsuite/ld-mips-elf/region1b.s --- binutils-2.12.90.0.11/ld/testsuite/ld-mips-elf/region1b.s Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/ld/testsuite/ld-mips-elf/region1b.s Tue Jun 18 21:41:59 2002 @@ -0,0 +1,2 @@ + .data + .4byte foo diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-scripts/cross1.t binutils-2.12.90.0.12/ld/testsuite/ld-scripts/cross1.t --- binutils-2.12.90.0.11/ld/testsuite/ld-scripts/cross1.t Sun Feb 3 11:22:33 2002 +++ binutils-2.12.90.0.12/ld/testsuite/ld-scripts/cross1.t Tue Jun 18 21:41:59 2002 @@ -1,6 +1,9 @@ NOCROSSREFS ( .text .data ) SECTIONS { + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .hash : { *(.hash) } .toc : { *(.toc) } .opd : { *(.opd) } .text : { tmpdir/cross1.o } diff -uprN binutils-2.12.90.0.11/ld/testsuite/ld-undefined/undefined.exp binutils-2.12.90.0.12/ld/testsuite/ld-undefined/undefined.exp --- binutils-2.12.90.0.11/ld/testsuite/ld-undefined/undefined.exp Sun Apr 21 01:09:26 2002 +++ binutils-2.12.90.0.12/ld/testsuite/ld-undefined/undefined.exp Tue Jun 18 21:41:59 2002 @@ -142,6 +142,8 @@ setup_xfail "sh64-*-*" # the function. Therefore the line number in the error message is 8 instead # of 9. On 64 bit s/390 this works because of the new brasl instruction that # doesn't need a literal pool entry. +# With gcc 3.1 s/390 uses dwarf-2 and the test will fail on 64 bit as well. setup_xfail s390-*-* +setup_xfail s390x-*-* checkund $ml $testline diff -uprN binutils-2.12.90.0.11/libiberty/ChangeLog binutils-2.12.90.0.12/libiberty/ChangeLog --- binutils-2.12.90.0.11/libiberty/ChangeLog Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/libiberty/ChangeLog Tue Jun 18 21:41:59 2002 @@ -1,3 +1,8 @@ +2002-06-17 Douglas Rupp + + * lbasename.c: Add 2002 to copyright. + (IS_DIR_SEPARATOR): Remove VMS junk. + 2002-06-05 Geoffrey Keating * hashtab.c (htab_create): New stub function for backward diff -uprN binutils-2.12.90.0.11/libiberty/lbasename.c binutils-2.12.90.0.12/libiberty/lbasename.c --- binutils-2.12.90.0.11/libiberty/lbasename.c Mon Oct 15 21:27:23 2001 +++ binutils-2.12.90.0.12/libiberty/lbasename.c Tue Jun 18 21:41:59 2002 @@ -1,6 +1,6 @@ /* Libiberty basename. Like basename, but is not overridden by the system C library. - Copyright (C) 2001 Free Software Foundation, Inc. + Copyright (C) 2001, 2002 Free Software Foundation, Inc. This file is part of the libiberty library. Libiberty is free software; you can redistribute it and/or @@ -53,19 +53,11 @@ and a path ending in @code{/} returns th # endif #endif -/* Define IS_DIR_SEPARATOR. VMS uses '::', ':', '[...]' and '<...>' to - separate the different components of a file specification. It's a - bit of a stretch to call ':', ']' and '>' directory separators, so - just define the test to find the file name component. */ -#ifdef VMS -# define IS_DIR_SEPARATOR(ch) ((ch) == ':' || (ch) == ']' || (ch) == '>') +#ifndef DIR_SEPARATOR_2 +# define IS_DIR_SEPARATOR(ch) ((ch) == DIR_SEPARATOR) #else -# ifndef DIR_SEPARATOR_2 -# define IS_DIR_SEPARATOR(ch) ((ch) == DIR_SEPARATOR) -# else -# define IS_DIR_SEPARATOR(ch) \ +# define IS_DIR_SEPARATOR(ch) \ (((ch) == DIR_SEPARATOR) || ((ch) == DIR_SEPARATOR_2)) -# endif #endif const char * diff -uprN binutils-2.12.90.0.11/opcodes/ChangeLog binutils-2.12.90.0.12/opcodes/ChangeLog --- binutils-2.12.90.0.11/opcodes/ChangeLog Sat Jun 8 20:44:53 2002 +++ binutils-2.12.90.0.12/opcodes/ChangeLog Tue Jun 18 21:41:59 2002 @@ -1,3 +1,27 @@ +2002-06-18 Dave Brolley + + * po/POTFILES.in: Add frv-*.[ch]. + * disassemble.c (ARCH_frv): New macro. + (disassembler): Handle bfd_arch_frv. + * configure.in: Support frv_bfd_arch. + * Makefile.am (HFILES): Add frv-*.h. + (CFILES): Add frv-*.c + (ALL_MACHINES): Add frv-*.lo. + (CLEANFILES): Add stamp-frv. + (FRV_DEPS): New variable. + (stamp-frv): New target. + (frv-asm.lo): New target. + (frv-desc.lo): New target. + (frv-dis.lo): New target. + (frv-ibld.lo): New target. + (frv-opc.lo): New target. + (frv-*.[ch]): New files. + +2002-06-18 Ben Elliston + + * Makefile.am (CGENDEPS): Remove unnecessary stamp-cgen. + * Makefile.in: Regenerate. + 2002-06-08 Alan Modra * a29k-dis.c: Replace CONST with const. diff -uprN binutils-2.12.90.0.11/opcodes/Makefile.am binutils-2.12.90.0.12/opcodes/Makefile.am --- binutils-2.12.90.0.11/opcodes/Makefile.am Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/opcodes/Makefile.am Tue Jun 18 21:41:59 2002 @@ -26,6 +26,7 @@ LIBIBERTY = ../libiberty/libiberty.a HFILES = \ arm-opc.h \ fr30-desc.h fr30-opc.h \ + frv-desc.h frv-opc.h \ h8500-opc.h \ ia64-asmtab.h \ ia64-opc.h \ @@ -66,6 +67,11 @@ CFILES = \ fr30-dis.c \ fr30-ibld.c \ fr30-opc.c \ + frv-asm.c \ + frv-desc.c \ + frv-dis.c \ + frv-ibld.c \ + frv-opc.c \ h8300-dis.c \ h8500-dis.c \ hppa-dis.c \ @@ -168,6 +174,11 @@ ALL_MACHINES = \ fr30-dis.lo \ fr30-ibld.lo \ fr30-opc.lo \ + frv-asm.lo \ + frv-desc.lo \ + frv-dis.lo \ + frv-ibld.lo \ + frv-opc.lo \ h8300-dis.lo \ h8500-dis.lo \ hppa-dis.lo \ @@ -301,7 +312,7 @@ uninstall_libopcodes: rm -f $(DESTDIR)$(bfdincludedir)/dis-asm.h CLEANFILES = \ - stamp-m32r stamp-fr30 stamp-openrisc \ + stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -311,7 +322,7 @@ CPUDIR = $(CGENDIR)/cpu CGEN = `if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi` CGENFLAGS = -v -CGENDEPS = ../cgen/stamp-cgen \ +CGENDEPS = \ $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \ $(CGENDIR)/opcodes.scm $(CGENDIR)/opc-asmdis.scm \ $(CGENDIR)/opc-ibld.scm $(CGENDIR)/opc-itab.scm \ @@ -321,11 +332,13 @@ CGENDEPS = ../cgen/stamp-cgen \ if CGEN_MAINT M32R_DEPS = stamp-m32r FR30_DEPS = stamp-fr30 +FRV_DEPS = stamp-frv OPENRISC_DEPS = stamp-openrisc XSTORMY16_DEPS = stamp-xstormy16 else M32R_DEPS = FR30_DEPS = +FRV_DEPS = OPENRISC_DEPS = XSTORMY16_DEPS = endif @@ -348,6 +361,11 @@ $(srcdir)/fr30-desc.h $(srcdir)/fr30-des stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= +$(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) + @true +stamp-frv: $(CGENDEPS) $(CPUDIR)/frv.cpu $(CPUDIR)/frv.opc + $(MAKE) run-cgen arch=frv prefix=frv options= extrafiles= + $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc @@ -495,6 +513,23 @@ fr30-ibld.lo: fr30-ibld.c sysdep.h confi fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ fr30-opc.h $(INCDIR)/libiberty.h +frv-asm.lo: frv-asm.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h +frv-desc.lo: frv-desc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h +frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h +frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h +frv-opc.lo: frv-opc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/symcat.h opintl.h diff -uprN binutils-2.12.90.0.11/opcodes/Makefile.in binutils-2.12.90.0.12/opcodes/Makefile.in --- binutils-2.12.90.0.11/opcodes/Makefile.in Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/opcodes/Makefile.in Tue Jun 18 21:41:59 2002 @@ -136,6 +136,7 @@ LIBIBERTY = ../libiberty/libiberty.a HFILES = \ arm-opc.h \ fr30-desc.h fr30-opc.h \ + frv-desc.h frv-opc.h \ h8500-opc.h \ ia64-asmtab.h \ ia64-opc.h \ @@ -177,6 +178,11 @@ CFILES = \ fr30-dis.c \ fr30-ibld.c \ fr30-opc.c \ + frv-asm.c \ + frv-desc.c \ + frv-dis.c \ + frv-ibld.c \ + frv-opc.c \ h8300-dis.c \ h8500-dis.c \ hppa-dis.c \ @@ -280,6 +286,11 @@ ALL_MACHINES = \ fr30-dis.lo \ fr30-ibld.lo \ fr30-opc.lo \ + frv-asm.lo \ + frv-desc.lo \ + frv-dis.lo \ + frv-ibld.lo \ + frv-opc.lo \ h8300-dis.lo \ h8500-dis.lo \ hppa-dis.lo \ @@ -368,7 +379,7 @@ noinst_LIBRARIES = libopcodes.a POTFILES = $(HFILES) $(CFILES) CLEANFILES = \ - stamp-m32r stamp-fr30 stamp-openrisc \ + stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -378,7 +389,7 @@ CPUDIR = $(CGENDIR)/cpu CGEN = `if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi` CGENFLAGS = -v -CGENDEPS = ../cgen/stamp-cgen \ +CGENDEPS = \ $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \ $(CGENDIR)/opcodes.scm $(CGENDIR)/opc-asmdis.scm \ $(CGENDIR)/opc-ibld.scm $(CGENDIR)/opc-itab.scm \ @@ -389,6 +400,8 @@ CGENDEPS = ../cgen/stamp-cgen \ @CGEN_MAINT_FALSE@M32R_DEPS = @CGEN_MAINT_TRUE@FR30_DEPS = @CGEN_MAINT_TRUE@stamp-fr30 @CGEN_MAINT_FALSE@FR30_DEPS = +@CGEN_MAINT_TRUE@FRV_DEPS = @CGEN_MAINT_TRUE@stamp-frv +@CGEN_MAINT_FALSE@FRV_DEPS = @CGEN_MAINT_TRUE@OPENRISC_DEPS = @CGEN_MAINT_TRUE@stamp-openrisc @CGEN_MAINT_FALSE@OPENRISC_DEPS = @CGEN_MAINT_TRUE@XSTORMY16_DEPS = @CGEN_MAINT_TRUE@stamp-xstormy16 @@ -844,6 +857,11 @@ $(srcdir)/fr30-desc.h $(srcdir)/fr30-des stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= +$(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) + @true +stamp-frv: $(CGENDEPS) $(CPUDIR)/frv.cpu $(CPUDIR)/frv.opc + $(MAKE) run-cgen arch=frv prefix=frv options= extrafiles= + $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc @@ -991,6 +1009,23 @@ fr30-ibld.lo: fr30-ibld.c sysdep.h confi fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ fr30-opc.h $(INCDIR)/libiberty.h +frv-asm.lo: frv-asm.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h +frv-desc.lo: frv-desc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h +frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h +frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h +frv-opc.lo: frv-opc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/symcat.h opintl.h diff -uprN binutils-2.12.90.0.11/opcodes/configure binutils-2.12.90.0.12/opcodes/configure --- binutils-2.12.90.0.11/opcodes/configure Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/opcodes/configure Tue Jun 18 21:41:59 2002 @@ -4644,6 +4644,7 @@ if test x${all_targets} = xfalse ; then bfd_we32k_arch) ;; bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; + bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; "") ;; *) { echo "configure: error: *** unknown target architecture $arch" 1>&2; exit 1; } ;; diff -uprN binutils-2.12.90.0.11/opcodes/configure.in binutils-2.12.90.0.12/opcodes/configure.in --- binutils-2.12.90.0.11/opcodes/configure.in Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/opcodes/configure.in Tue Jun 18 21:41:59 2002 @@ -238,6 +238,7 @@ if test x${all_targets} = xfalse ; then bfd_we32k_arch) ;; bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; + bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; "") ;; *) AC_MSG_ERROR(*** unknown target architecture $arch) ;; diff -uprN binutils-2.12.90.0.11/opcodes/disassemble.c binutils-2.12.90.0.12/opcodes/disassemble.c --- binutils-2.12.90.0.11/opcodes/disassemble.c Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/opcodes/disassemble.c Tue Jun 18 21:41:59 2002 @@ -66,6 +66,7 @@ Foundation, Inc., 59 Temple Place - Suit #define ARCH_w65 #define ARCH_xstormy16 #define ARCH_z8k +#define ARCH_frv #define INCLUDE_SHMEDIA #endif @@ -336,6 +337,11 @@ disassembler (abfd) disassemble = print_insn_vax; break; #endif +#ifdef ARCH_frv + case bfd_arch_frv: + disassemble = print_insn_frv; + break; +#endif default: return 0; } diff -uprN binutils-2.12.90.0.11/opcodes/frv-asm.c binutils-2.12.90.0.12/opcodes/frv-asm.c --- binutils-2.12.90.0.11/opcodes/frv-asm.c Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/opcodes/frv-asm.c Tue Jun 18 21:41:59 2002 @@ -0,0 +1,1023 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-asm.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +static const char * parse_ulo16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_uslo16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_uhi16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static long parse_register_number + PARAMS ((const char **)); +static const char * parse_spr + PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); +static const char * parse_d12 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_s12 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_u12 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); + +static const char * +parse_ulo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "lo(", 3) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + if (strncasecmp (*strp + 1, "gprello(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELLO, + &result_type, &value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value >>= 16; + *valuep = value; + return errmsg; + } + } + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_uslo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "lo(", 3) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gprello(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELLO, + &result_type, &value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + } + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_uhi16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "hi(", 3) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_HI16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value >>= 16; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gprelhi(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELHI, + &result_type, &value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value >>= 16; + *valuep = value; + return errmsg; + } + } + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +static long +parse_register_number (strp) + const char **strp; +{ + int regno; + if (**strp < '0' || **strp > '9') + return -1; /* error */ + + regno = **strp - '0'; + for (++*strp; **strp >= '0' && **strp <= '9'; ++*strp) + regno = regno * 10 + (**strp - '0'); + + return regno; +} + +static const char * +parse_spr (cd, strp, table, valuep) + CGEN_CPU_DESC cd; + const char **strp; + CGEN_KEYWORD * table; + long *valuep; +{ + const char *save_strp; + long regno; + + /* Check for spr index notation. */ + if (strncasecmp (*strp, "spr[", 4) == 0) + { + *strp += 4; + regno = parse_register_number (strp); + if (**strp != ']') + return "missing `]'"; + ++*strp; + if (! spr_valid (regno)) + return "Special purpose register number is out of range"; + *valuep = regno; + return NULL; + } + + save_strp = *strp; + regno = parse_register_number (strp); + if (regno != -1) + { + if (! spr_valid (regno)) + return "Special purpose register number is out of range"; + *valuep = regno; + return NULL; + } + + *strp = save_strp; + return cgen_parse_keyword (cd, strp, table, valuep); +} + +static const char * +parse_d12 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Check for small data reference. */ + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "gprel12(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPREL12, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + } + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_s12 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Check for small data reference. */ + if ((**strp == '#' || **strp == '%') + && strncasecmp (*strp + 1, "gprel12(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPREL12, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + else + { + if (**strp == '#') + ++*strp; + return cgen_parse_signed_integer (cd, strp, opindex, valuep); + } +} + +static const char * +parse_u12 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Check for small data reference. */ + if ((**strp == '#' || **strp == '%') + && strncasecmp (*strp + 1, "gprel12(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELU12, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + else + { + if (**strp == '#') + ++*strp; + return cgen_parse_signed_integer (cd, strp, opindex, valuep); + } +} + +/* -- */ + +const char * frv_cgen_parse_operand + PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +frv_cgen_parse_operand (cd, opindex, strp, fields) + CGEN_CPU_DESC cd; + int opindex; + const char ** strp; + CGEN_FIELDS * fields; +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case FRV_OPERAND_A : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_A, &fields->f_A); + break; + case FRV_OPERAND_ACC40SI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Si); + break; + case FRV_OPERAND_ACC40SK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Sk); + break; + case FRV_OPERAND_ACC40UI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Ui); + break; + case FRV_OPERAND_ACC40UK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Uk); + break; + case FRV_OPERAND_ACCGI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_accg_names, & fields->f_ACCGi); + break; + case FRV_OPERAND_ACCGK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_accg_names, & fields->f_ACCGk); + break; + case FRV_OPERAND_CCI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CCi); + break; + case FRV_OPERAND_CPRDOUBLEK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRk); + break; + case FRV_OPERAND_CPRI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRi); + break; + case FRV_OPERAND_CPRJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRj); + break; + case FRV_OPERAND_CPRK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRk); + break; + case FRV_OPERAND_CRI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRi); + break; + case FRV_OPERAND_CRJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRj); + break; + case FRV_OPERAND_CRJ_FLOAT : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRj_float); + break; + case FRV_OPERAND_CRJ_INT : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRj_int); + break; + case FRV_OPERAND_CRK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRk); + break; + case FRV_OPERAND_FCCI_1 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCi_1); + break; + case FRV_OPERAND_FCCI_2 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCi_2); + break; + case FRV_OPERAND_FCCI_3 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCi_3); + break; + case FRV_OPERAND_FCCK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCk); + break; + case FRV_OPERAND_FRDOUBLEI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); + break; + case FRV_OPERAND_FRDOUBLEJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); + break; + case FRV_OPERAND_FRDOUBLEK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_FRI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); + break; + case FRV_OPERAND_FRINTK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_FRJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); + break; + case FRV_OPERAND_FRK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_FRKHI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_FRKLO : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_GRDOUBLEK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk); + break; + case FRV_OPERAND_GRI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRi); + break; + case FRV_OPERAND_GRJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRj); + break; + case FRV_OPERAND_GRK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk); + break; + case FRV_OPERAND_GRKHI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk); + break; + case FRV_OPERAND_GRKLO : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk); + break; + case FRV_OPERAND_ICCI_1 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_iccr_names, & fields->f_ICCi_1); + break; + case FRV_OPERAND_ICCI_2 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_iccr_names, & fields->f_ICCi_2); + break; + case FRV_OPERAND_ICCI_3 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_iccr_names, & fields->f_ICCi_3); + break; + case FRV_OPERAND_LI : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LI, &fields->f_LI); + break; + case FRV_OPERAND_AE : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_AE, &fields->f_ae); + break; + case FRV_OPERAND_CCOND : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_CCOND, &fields->f_ccond); + break; + case FRV_OPERAND_COND : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_COND, &fields->f_cond); + break; + case FRV_OPERAND_D12 : + errmsg = parse_d12 (cd, strp, FRV_OPERAND_D12, &fields->f_d12); + break; + case FRV_OPERAND_DEBUG : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_DEBUG, &fields->f_debug); + break; + case FRV_OPERAND_EIR : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_EIR, &fields->f_eir); + break; + case FRV_OPERAND_HINT : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_HINT, &fields->f_hint); + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_h_hint_not_taken, & fields->f_hint); + break; + case FRV_OPERAND_HINT_TAKEN : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_h_hint_taken, & fields->f_hint); + break; + case FRV_OPERAND_LABEL16 : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, FRV_OPERAND_LABEL16, 0, NULL, & value); + fields->f_label16 = value; + } + break; + case FRV_OPERAND_LABEL24 : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, FRV_OPERAND_LABEL24, 0, NULL, & value); + fields->f_label24 = value; + } + break; + case FRV_OPERAND_LOCK : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LOCK, &fields->f_lock); + break; + case FRV_OPERAND_PACK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_h_pack, & fields->f_pack); + break; + case FRV_OPERAND_S10 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S10, &fields->f_s10); + break; + case FRV_OPERAND_S12 : + errmsg = parse_s12 (cd, strp, FRV_OPERAND_S12, &fields->f_d12); + break; + case FRV_OPERAND_S16 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S16, &fields->f_s16); + break; + case FRV_OPERAND_S5 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S5, &fields->f_s5); + break; + case FRV_OPERAND_S6 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S6, &fields->f_s6); + break; + case FRV_OPERAND_S6_1 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S6_1, &fields->f_s6_1); + break; + case FRV_OPERAND_SLO16 : + errmsg = parse_uslo16 (cd, strp, FRV_OPERAND_SLO16, &fields->f_s16); + break; + case FRV_OPERAND_SPR : + errmsg = parse_spr (cd, strp, & frv_cgen_opval_spr_names, & fields->f_spr); + break; + case FRV_OPERAND_U12 : + errmsg = parse_u12 (cd, strp, FRV_OPERAND_U12, &fields->f_u12); + break; + case FRV_OPERAND_U16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_U16, &fields->f_u16); + break; + case FRV_OPERAND_U6 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_U6, &fields->f_u6); + break; + case FRV_OPERAND_UHI16 : + errmsg = parse_uhi16 (cd, strp, FRV_OPERAND_UHI16, &fields->f_u16); + break; + case FRV_OPERAND_ULO16 : + errmsg = parse_ulo16 (cd, strp, FRV_OPERAND_ULO16, &fields->f_u16); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const frv_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +frv_cgen_init_asm (cd) + CGEN_CPU_DESC cd; +{ + frv_cgen_init_opcode_table (cd); + frv_cgen_init_ibld_table (cd); + cd->parse_handlers = & frv_cgen_parse_handlers[0]; + cd->parse_operand = frv_cgen_parse_operand; +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by frv_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +frv_cgen_build_insn_regex (insn) + CGEN_INSN *insn; +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (cd, insn, strp, fields) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + const char **strp; + CGEN_FIELDS *fields; +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +frv_cgen_assemble_insn (cd, str, fields, buf, errmsg) + CGEN_CPU_DESC cd; + const char *str; + CGEN_FIELDS *fields; + CGEN_INSN_BYTES_PTR buf; + char **errmsg; +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! frv_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAX attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} + +#if 0 /* This calls back to GAS which we can't do without care. */ + +/* Record each member of OPVALS in the assembler's symbol table. + This lets GAS parse registers for us. + ??? Interesting idea but not currently used. */ + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +frv_cgen_asm_hash_keywords (cd, opvals) + CGEN_CPU_DESC cd; + CGEN_KEYWORD *opvals; +{ + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY * ke; + + while ((ke = cgen_keyword_search_next (& search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! frv_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (cd, ke->name, ke->value); + } +} + +#endif /* 0 */ diff -uprN binutils-2.12.90.0.11/opcodes/frv-desc.c binutils-2.12.90.0.12/opcodes/frv-desc.c --- binutils-2.12.90.0.11/opcodes/frv-desc.c Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/opcodes/frv-desc.c Tue Jun 18 21:41:59 2002 @@ -0,0 +1,6311 @@ +/* CPU data for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "opintl.h" +#include "libiberty.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] = +{ + { "base", MACH_BASE }, + { "frv", MACH_FRV }, + { "fr500", MACH_FR500 }, + { "fr400", MACH_FR400 }, + { "tomcat", MACH_TOMCAT }, + { "simple", MACH_SIMPLE }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] = +{ + { "frv", ISA_FRV }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY UNIT_attr[] = +{ + { "NIL", UNIT_NIL }, + { "I0", UNIT_I0 }, + { "I1", UNIT_I1 }, + { "I01", UNIT_I01 }, + { "FM0", UNIT_FM0 }, + { "FM1", UNIT_FM1 }, + { "FM01", UNIT_FM01 }, + { "B0", UNIT_B0 }, + { "B1", UNIT_B1 }, + { "B01", UNIT_B01 }, + { "C", UNIT_C }, + { "MULT_DIV", UNIT_MULT_DIV }, + { "LOAD", UNIT_LOAD }, + { "NUM_UNITS", UNIT_NUM_UNITS }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY FR400_MAJOR_attr[] = +{ + { "NONE", FR400_MAJOR_NONE }, + { "I_1", FR400_MAJOR_I_1 }, + { "I_2", FR400_MAJOR_I_2 }, + { "I_3", FR400_MAJOR_I_3 }, + { "I_4", FR400_MAJOR_I_4 }, + { "I_5", FR400_MAJOR_I_5 }, + { "B_1", FR400_MAJOR_B_1 }, + { "B_2", FR400_MAJOR_B_2 }, + { "B_3", FR400_MAJOR_B_3 }, + { "B_4", FR400_MAJOR_B_4 }, + { "B_5", FR400_MAJOR_B_5 }, + { "B_6", FR400_MAJOR_B_6 }, + { "C_1", FR400_MAJOR_C_1 }, + { "C_2", FR400_MAJOR_C_2 }, + { "M_1", FR400_MAJOR_M_1 }, + { "M_2", FR400_MAJOR_M_2 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] = +{ + { "NONE", FR500_MAJOR_NONE }, + { "I_1", FR500_MAJOR_I_1 }, + { "I_2", FR500_MAJOR_I_2 }, + { "I_3", FR500_MAJOR_I_3 }, + { "I_4", FR500_MAJOR_I_4 }, + { "I_5", FR500_MAJOR_I_5 }, + { "I_6", FR500_MAJOR_I_6 }, + { "B_1", FR500_MAJOR_B_1 }, + { "B_2", FR500_MAJOR_B_2 }, + { "B_3", FR500_MAJOR_B_3 }, + { "B_4", FR500_MAJOR_B_4 }, + { "B_5", FR500_MAJOR_B_5 }, + { "B_6", FR500_MAJOR_B_6 }, + { "C_1", FR500_MAJOR_C_1 }, + { "C_2", FR500_MAJOR_C_2 }, + { "F_1", FR500_MAJOR_F_1 }, + { "F_2", FR500_MAJOR_F_2 }, + { "F_3", FR500_MAJOR_F_3 }, + { "F_4", FR500_MAJOR_F_4 }, + { "F_5", FR500_MAJOR_F_5 }, + { "F_6", FR500_MAJOR_F_6 }, + { "F_7", FR500_MAJOR_F_7 }, + { "F_8", FR500_MAJOR_F_8 }, + { "M_1", FR500_MAJOR_M_1 }, + { "M_2", FR500_MAJOR_M_2 }, + { "M_3", FR500_MAJOR_M_3 }, + { "M_4", FR500_MAJOR_M_4 }, + { "M_5", FR500_MAJOR_M_5 }, + { "M_6", FR500_MAJOR_M_6 }, + { "M_7", FR500_MAJOR_M_7 }, + { "M_8", FR500_MAJOR_M_8 }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "UNIT", & UNIT_attr[0], & UNIT_attr[0] }, + { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] }, + { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "PRIVILEGED", &bool_attr[0], &bool_attr[0] }, + { "NON-EXCEPTING", &bool_attr[0], &bool_attr[0] }, + { "CONDITIONAL", &bool_attr[0], &bool_attr[0] }, + { "FR-ACCESS", &bool_attr[0], &bool_attr[0] }, + { "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA frv_cgen_isa_table[] = { + { "frv", 32, 32, 32, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH frv_cgen_mach_table[] = { + { "frv", "frv", MACH_FRV, 0 }, + { "fr500", "fr500", MACH_FR500, 0 }, + { "tomcat", "tomcat", MACH_TOMCAT, 0 }, + { "fr400", "fr400", MACH_FR400, 0 }, + { "simple", "simple", MACH_SIMPLE, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] = +{ + { "sp", 1, {0, {0}}, 0, 0 }, + { "fp", 2, {0, {0}}, 0, 0 }, + { "gr0", 0, {0, {0}}, 0, 0 }, + { "gr1", 1, {0, {0}}, 0, 0 }, + { "gr2", 2, {0, {0}}, 0, 0 }, + { "gr3", 3, {0, {0}}, 0, 0 }, + { "gr4", 4, {0, {0}}, 0, 0 }, + { "gr5", 5, {0, {0}}, 0, 0 }, + { "gr6", 6, {0, {0}}, 0, 0 }, + { "gr7", 7, {0, {0}}, 0, 0 }, + { "gr8", 8, {0, {0}}, 0, 0 }, + { "gr9", 9, {0, {0}}, 0, 0 }, + { "gr10", 10, {0, {0}}, 0, 0 }, + { "gr11", 11, {0, {0}}, 0, 0 }, + { "gr12", 12, {0, {0}}, 0, 0 }, + { "gr13", 13, {0, {0}}, 0, 0 }, + { "gr14", 14, {0, {0}}, 0, 0 }, + { "gr15", 15, {0, {0}}, 0, 0 }, + { "gr16", 16, {0, {0}}, 0, 0 }, + { "gr17", 17, {0, {0}}, 0, 0 }, + { "gr18", 18, {0, {0}}, 0, 0 }, + { "gr19", 19, {0, {0}}, 0, 0 }, + { "gr20", 20, {0, {0}}, 0, 0 }, + { "gr21", 21, {0, {0}}, 0, 0 }, + { "gr22", 22, {0, {0}}, 0, 0 }, + { "gr23", 23, {0, {0}}, 0, 0 }, + { "gr24", 24, {0, {0}}, 0, 0 }, + { "gr25", 25, {0, {0}}, 0, 0 }, + { "gr26", 26, {0, {0}}, 0, 0 }, + { "gr27", 27, {0, {0}}, 0, 0 }, + { "gr28", 28, {0, {0}}, 0, 0 }, + { "gr29", 29, {0, {0}}, 0, 0 }, + { "gr30", 30, {0, {0}}, 0, 0 }, + { "gr31", 31, {0, {0}}, 0, 0 }, + { "gr32", 32, {0, {0}}, 0, 0 }, + { "gr33", 33, {0, {0}}, 0, 0 }, + { "gr34", 34, {0, {0}}, 0, 0 }, + { "gr35", 35, {0, {0}}, 0, 0 }, + { "gr36", 36, {0, {0}}, 0, 0 }, + { "gr37", 37, {0, {0}}, 0, 0 }, + { "gr38", 38, {0, {0}}, 0, 0 }, + { "gr39", 39, {0, {0}}, 0, 0 }, + { "gr40", 40, {0, {0}}, 0, 0 }, + { "gr41", 41, {0, {0}}, 0, 0 }, + { "gr42", 42, {0, {0}}, 0, 0 }, + { "gr43", 43, {0, {0}}, 0, 0 }, + { "gr44", 44, {0, {0}}, 0, 0 }, + { "gr45", 45, {0, {0}}, 0, 0 }, + { "gr46", 46, {0, {0}}, 0, 0 }, + { "gr47", 47, {0, {0}}, 0, 0 }, + { "gr48", 48, {0, {0}}, 0, 0 }, + { "gr49", 49, {0, {0}}, 0, 0 }, + { "gr50", 50, {0, {0}}, 0, 0 }, + { "gr51", 51, {0, {0}}, 0, 0 }, + { "gr52", 52, {0, {0}}, 0, 0 }, + { "gr53", 53, {0, {0}}, 0, 0 }, + { "gr54", 54, {0, {0}}, 0, 0 }, + { "gr55", 55, {0, {0}}, 0, 0 }, + { "gr56", 56, {0, {0}}, 0, 0 }, + { "gr57", 57, {0, {0}}, 0, 0 }, + { "gr58", 58, {0, {0}}, 0, 0 }, + { "gr59", 59, {0, {0}}, 0, 0 }, + { "gr60", 60, {0, {0}}, 0, 0 }, + { "gr61", 61, {0, {0}}, 0, 0 }, + { "gr62", 62, {0, {0}}, 0, 0 }, + { "gr63", 63, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_gr_names = +{ + & frv_cgen_opval_gr_names_entries[0], + 66, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_fr_names_entries[] = +{ + { "fr0", 0, {0, {0}}, 0, 0 }, + { "fr1", 1, {0, {0}}, 0, 0 }, + { "fr2", 2, {0, {0}}, 0, 0 }, + { "fr3", 3, {0, {0}}, 0, 0 }, + { "fr4", 4, {0, {0}}, 0, 0 }, + { "fr5", 5, {0, {0}}, 0, 0 }, + { "fr6", 6, {0, {0}}, 0, 0 }, + { "fr7", 7, {0, {0}}, 0, 0 }, + { "fr8", 8, {0, {0}}, 0, 0 }, + { "fr9", 9, {0, {0}}, 0, 0 }, + { "fr10", 10, {0, {0}}, 0, 0 }, + { "fr11", 11, {0, {0}}, 0, 0 }, + { "fr12", 12, {0, {0}}, 0, 0 }, + { "fr13", 13, {0, {0}}, 0, 0 }, + { "fr14", 14, {0, {0}}, 0, 0 }, + { "fr15", 15, {0, {0}}, 0, 0 }, + { "fr16", 16, {0, {0}}, 0, 0 }, + { "fr17", 17, {0, {0}}, 0, 0 }, + { "fr18", 18, {0, {0}}, 0, 0 }, + { "fr19", 19, {0, {0}}, 0, 0 }, + { "fr20", 20, {0, {0}}, 0, 0 }, + { "fr21", 21, {0, {0}}, 0, 0 }, + { "fr22", 22, {0, {0}}, 0, 0 }, + { "fr23", 23, {0, {0}}, 0, 0 }, + { "fr24", 24, {0, {0}}, 0, 0 }, + { "fr25", 25, {0, {0}}, 0, 0 }, + { "fr26", 26, {0, {0}}, 0, 0 }, + { "fr27", 27, {0, {0}}, 0, 0 }, + { "fr28", 28, {0, {0}}, 0, 0 }, + { "fr29", 29, {0, {0}}, 0, 0 }, + { "fr30", 30, {0, {0}}, 0, 0 }, + { "fr31", 31, {0, {0}}, 0, 0 }, + { "fr32", 32, {0, {0}}, 0, 0 }, + { "fr33", 33, {0, {0}}, 0, 0 }, + { "fr34", 34, {0, {0}}, 0, 0 }, + { "fr35", 35, {0, {0}}, 0, 0 }, + { "fr36", 36, {0, {0}}, 0, 0 }, + { "fr37", 37, {0, {0}}, 0, 0 }, + { "fr38", 38, {0, {0}}, 0, 0 }, + { "fr39", 39, {0, {0}}, 0, 0 }, + { "fr40", 40, {0, {0}}, 0, 0 }, + { "fr41", 41, {0, {0}}, 0, 0 }, + { "fr42", 42, {0, {0}}, 0, 0 }, + { "fr43", 43, {0, {0}}, 0, 0 }, + { "fr44", 44, {0, {0}}, 0, 0 }, + { "fr45", 45, {0, {0}}, 0, 0 }, + { "fr46", 46, {0, {0}}, 0, 0 }, + { "fr47", 47, {0, {0}}, 0, 0 }, + { "fr48", 48, {0, {0}}, 0, 0 }, + { "fr49", 49, {0, {0}}, 0, 0 }, + { "fr50", 50, {0, {0}}, 0, 0 }, + { "fr51", 51, {0, {0}}, 0, 0 }, + { "fr52", 52, {0, {0}}, 0, 0 }, + { "fr53", 53, {0, {0}}, 0, 0 }, + { "fr54", 54, {0, {0}}, 0, 0 }, + { "fr55", 55, {0, {0}}, 0, 0 }, + { "fr56", 56, {0, {0}}, 0, 0 }, + { "fr57", 57, {0, {0}}, 0, 0 }, + { "fr58", 58, {0, {0}}, 0, 0 }, + { "fr59", 59, {0, {0}}, 0, 0 }, + { "fr60", 60, {0, {0}}, 0, 0 }, + { "fr61", 61, {0, {0}}, 0, 0 }, + { "fr62", 62, {0, {0}}, 0, 0 }, + { "fr63", 63, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_fr_names = +{ + & frv_cgen_opval_fr_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_cpr_names_entries[] = +{ + { "cpr0", 0, {0, {0}}, 0, 0 }, + { "cpr1", 1, {0, {0}}, 0, 0 }, + { "cpr2", 2, {0, {0}}, 0, 0 }, + { "cpr3", 3, {0, {0}}, 0, 0 }, + { "cpr4", 4, {0, {0}}, 0, 0 }, + { "cpr5", 5, {0, {0}}, 0, 0 }, + { "cpr6", 6, {0, {0}}, 0, 0 }, + { "cpr7", 7, {0, {0}}, 0, 0 }, + { "cpr8", 8, {0, {0}}, 0, 0 }, + { "cpr9", 9, {0, {0}}, 0, 0 }, + { "cpr10", 10, {0, {0}}, 0, 0 }, + { "cpr11", 11, {0, {0}}, 0, 0 }, + { "cpr12", 12, {0, {0}}, 0, 0 }, + { "cpr13", 13, {0, {0}}, 0, 0 }, + { "cpr14", 14, {0, {0}}, 0, 0 }, + { "cpr15", 15, {0, {0}}, 0, 0 }, + { "cpr16", 16, {0, {0}}, 0, 0 }, + { "cpr17", 17, {0, {0}}, 0, 0 }, + { "cpr18", 18, {0, {0}}, 0, 0 }, + { "cpr19", 19, {0, {0}}, 0, 0 }, + { "cpr20", 20, {0, {0}}, 0, 0 }, + { "cpr21", 21, {0, {0}}, 0, 0 }, + { "cpr22", 22, {0, {0}}, 0, 0 }, + { "cpr23", 23, {0, {0}}, 0, 0 }, + { "cpr24", 24, {0, {0}}, 0, 0 }, + { "cpr25", 25, {0, {0}}, 0, 0 }, + { "cpr26", 26, {0, {0}}, 0, 0 }, + { "cpr27", 27, {0, {0}}, 0, 0 }, + { "cpr28", 28, {0, {0}}, 0, 0 }, + { "cpr29", 29, {0, {0}}, 0, 0 }, + { "cpr30", 30, {0, {0}}, 0, 0 }, + { "cpr31", 31, {0, {0}}, 0, 0 }, + { "cpr32", 32, {0, {0}}, 0, 0 }, + { "cpr33", 33, {0, {0}}, 0, 0 }, + { "cpr34", 34, {0, {0}}, 0, 0 }, + { "cpr35", 35, {0, {0}}, 0, 0 }, + { "cpr36", 36, {0, {0}}, 0, 0 }, + { "cpr37", 37, {0, {0}}, 0, 0 }, + { "cpr38", 38, {0, {0}}, 0, 0 }, + { "cpr39", 39, {0, {0}}, 0, 0 }, + { "cpr40", 40, {0, {0}}, 0, 0 }, + { "cpr41", 41, {0, {0}}, 0, 0 }, + { "cpr42", 42, {0, {0}}, 0, 0 }, + { "cpr43", 43, {0, {0}}, 0, 0 }, + { "cpr44", 44, {0, {0}}, 0, 0 }, + { "cpr45", 45, {0, {0}}, 0, 0 }, + { "cpr46", 46, {0, {0}}, 0, 0 }, + { "cpr47", 47, {0, {0}}, 0, 0 }, + { "cpr48", 48, {0, {0}}, 0, 0 }, + { "cpr49", 49, {0, {0}}, 0, 0 }, + { "cpr50", 50, {0, {0}}, 0, 0 }, + { "cpr51", 51, {0, {0}}, 0, 0 }, + { "cpr52", 52, {0, {0}}, 0, 0 }, + { "cpr53", 53, {0, {0}}, 0, 0 }, + { "cpr54", 54, {0, {0}}, 0, 0 }, + { "cpr55", 55, {0, {0}}, 0, 0 }, + { "cpr56", 56, {0, {0}}, 0, 0 }, + { "cpr57", 57, {0, {0}}, 0, 0 }, + { "cpr58", 58, {0, {0}}, 0, 0 }, + { "cpr59", 59, {0, {0}}, 0, 0 }, + { "cpr60", 60, {0, {0}}, 0, 0 }, + { "cpr61", 61, {0, {0}}, 0, 0 }, + { "cpr62", 62, {0, {0}}, 0, 0 }, + { "cpr63", 63, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_cpr_names = +{ + & frv_cgen_opval_cpr_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] = +{ + { "psr", 0, {0, {0}}, 0, 0 }, + { "pcsr", 1, {0, {0}}, 0, 0 }, + { "bpcsr", 2, {0, {0}}, 0, 0 }, + { "tbr", 3, {0, {0}}, 0, 0 }, + { "bpsr", 4, {0, {0}}, 0, 0 }, + { "hsr0", 16, {0, {0}}, 0, 0 }, + { "hsr1", 17, {0, {0}}, 0, 0 }, + { "hsr2", 18, {0, {0}}, 0, 0 }, + { "hsr3", 19, {0, {0}}, 0, 0 }, + { "hsr4", 20, {0, {0}}, 0, 0 }, + { "hsr5", 21, {0, {0}}, 0, 0 }, + { "hsr6", 22, {0, {0}}, 0, 0 }, + { "hsr7", 23, {0, {0}}, 0, 0 }, + { "hsr8", 24, {0, {0}}, 0, 0 }, + { "hsr9", 25, {0, {0}}, 0, 0 }, + { "hsr10", 26, {0, {0}}, 0, 0 }, + { "hsr11", 27, {0, {0}}, 0, 0 }, + { "hsr12", 28, {0, {0}}, 0, 0 }, + { "hsr13", 29, {0, {0}}, 0, 0 }, + { "hsr14", 30, {0, {0}}, 0, 0 }, + { "hsr15", 31, {0, {0}}, 0, 0 }, + { "hsr16", 32, {0, {0}}, 0, 0 }, + { "hsr17", 33, {0, {0}}, 0, 0 }, + { "hsr18", 34, {0, {0}}, 0, 0 }, + { "hsr19", 35, {0, {0}}, 0, 0 }, + { "hsr20", 36, {0, {0}}, 0, 0 }, + { "hsr21", 37, {0, {0}}, 0, 0 }, + { "hsr22", 38, {0, {0}}, 0, 0 }, + { "hsr23", 39, {0, {0}}, 0, 0 }, + { "hsr24", 40, {0, {0}}, 0, 0 }, + { "hsr25", 41, {0, {0}}, 0, 0 }, + { "hsr26", 42, {0, {0}}, 0, 0 }, + { "hsr27", 43, {0, {0}}, 0, 0 }, + { "hsr28", 44, {0, {0}}, 0, 0 }, + { "hsr29", 45, {0, {0}}, 0, 0 }, + { "hsr30", 46, {0, {0}}, 0, 0 }, + { "hsr31", 47, {0, {0}}, 0, 0 }, + { "hsr32", 48, {0, {0}}, 0, 0 }, + { "hsr33", 49, {0, {0}}, 0, 0 }, + { "hsr34", 50, {0, {0}}, 0, 0 }, + { "hsr35", 51, {0, {0}}, 0, 0 }, + { "hsr36", 52, {0, {0}}, 0, 0 }, + { "hsr37", 53, {0, {0}}, 0, 0 }, + { "hsr38", 54, {0, {0}}, 0, 0 }, + { "hsr39", 55, {0, {0}}, 0, 0 }, + { "hsr40", 56, {0, {0}}, 0, 0 }, + { "hsr41", 57, {0, {0}}, 0, 0 }, + { "hsr42", 58, {0, {0}}, 0, 0 }, + { "hsr43", 59, {0, {0}}, 0, 0 }, + { "hsr44", 60, {0, {0}}, 0, 0 }, + { "hsr45", 61, {0, {0}}, 0, 0 }, + { "hsr46", 62, {0, {0}}, 0, 0 }, + { "hsr47", 63, {0, {0}}, 0, 0 }, + { "hsr48", 64, {0, {0}}, 0, 0 }, + { "hsr49", 65, {0, {0}}, 0, 0 }, + { "hsr50", 66, {0, {0}}, 0, 0 }, + { "hsr51", 67, {0, {0}}, 0, 0 }, + { "hsr52", 68, {0, {0}}, 0, 0 }, + { "hsr53", 69, {0, {0}}, 0, 0 }, + { "hsr54", 70, {0, {0}}, 0, 0 }, + { "hsr55", 71, {0, {0}}, 0, 0 }, + { "hsr56", 72, {0, {0}}, 0, 0 }, + { "hsr57", 73, {0, {0}}, 0, 0 }, + { "hsr58", 74, {0, {0}}, 0, 0 }, + { "hsr59", 75, {0, {0}}, 0, 0 }, + { "hsr60", 76, {0, {0}}, 0, 0 }, + { "hsr61", 77, {0, {0}}, 0, 0 }, + { "hsr62", 78, {0, {0}}, 0, 0 }, + { "hsr63", 79, {0, {0}}, 0, 0 }, + { "ccr", 256, {0, {0}}, 0, 0 }, + { "cccr", 263, {0, {0}}, 0, 0 }, + { "lr", 272, {0, {0}}, 0, 0 }, + { "lcr", 273, {0, {0}}, 0, 0 }, + { "isr", 288, {0, {0}}, 0, 0 }, + { "neear0", 352, {0, {0}}, 0, 0 }, + { "neear1", 353, {0, {0}}, 0, 0 }, + { "neear2", 354, {0, {0}}, 0, 0 }, + { "neear3", 355, {0, {0}}, 0, 0 }, + { "neear4", 356, {0, {0}}, 0, 0 }, + { "neear5", 357, {0, {0}}, 0, 0 }, + { "neear6", 358, {0, {0}}, 0, 0 }, + { "neear7", 359, {0, {0}}, 0, 0 }, + { "neear8", 360, {0, {0}}, 0, 0 }, + { "neear9", 361, {0, {0}}, 0, 0 }, + { "neear10", 362, {0, {0}}, 0, 0 }, + { "neear11", 363, {0, {0}}, 0, 0 }, + { "neear12", 364, {0, {0}}, 0, 0 }, + { "neear13", 365, {0, {0}}, 0, 0 }, + { "neear14", 366, {0, {0}}, 0, 0 }, + { "neear15", 367, {0, {0}}, 0, 0 }, + { "neear16", 368, {0, {0}}, 0, 0 }, + { "neear17", 369, {0, {0}}, 0, 0 }, + { "neear18", 370, {0, {0}}, 0, 0 }, + { "neear19", 371, {0, {0}}, 0, 0 }, + { "neear20", 372, {0, {0}}, 0, 0 }, + { "neear21", 373, {0, {0}}, 0, 0 }, + { "neear22", 374, {0, {0}}, 0, 0 }, + { "neear23", 375, {0, {0}}, 0, 0 }, + { "neear24", 376, {0, {0}}, 0, 0 }, + { "neear25", 377, {0, {0}}, 0, 0 }, + { "neear26", 378, {0, {0}}, 0, 0 }, + { "neear27", 379, {0, {0}}, 0, 0 }, + { "neear28", 380, {0, {0}}, 0, 0 }, + { "neear29", 381, {0, {0}}, 0, 0 }, + { "neear30", 382, {0, {0}}, 0, 0 }, + { "neear31", 383, {0, {0}}, 0, 0 }, + { "nesr0", 384, {0, {0}}, 0, 0 }, + { "nesr1", 385, {0, {0}}, 0, 0 }, + { "nesr2", 386, {0, {0}}, 0, 0 }, + { "nesr3", 387, {0, {0}}, 0, 0 }, + { "nesr4", 388, {0, {0}}, 0, 0 }, + { "nesr5", 389, {0, {0}}, 0, 0 }, + { "nesr6", 390, {0, {0}}, 0, 0 }, + { "nesr7", 391, {0, {0}}, 0, 0 }, + { "nesr8", 392, {0, {0}}, 0, 0 }, + { "nesr9", 393, {0, {0}}, 0, 0 }, + { "nesr10", 394, {0, {0}}, 0, 0 }, + { "nesr11", 395, {0, {0}}, 0, 0 }, + { "nesr12", 396, {0, {0}}, 0, 0 }, + { "nesr13", 397, {0, {0}}, 0, 0 }, + { "nesr14", 398, {0, {0}}, 0, 0 }, + { "nesr15", 399, {0, {0}}, 0, 0 }, + { "nesr16", 400, {0, {0}}, 0, 0 }, + { "nesr17", 401, {0, {0}}, 0, 0 }, + { "nesr18", 402, {0, {0}}, 0, 0 }, + { "nesr19", 403, {0, {0}}, 0, 0 }, + { "nesr20", 404, {0, {0}}, 0, 0 }, + { "nesr21", 405, {0, {0}}, 0, 0 }, + { "nesr22", 406, {0, {0}}, 0, 0 }, + { "nesr23", 407, {0, {0}}, 0, 0 }, + { "nesr24", 408, {0, {0}}, 0, 0 }, + { "nesr25", 409, {0, {0}}, 0, 0 }, + { "nesr26", 410, {0, {0}}, 0, 0 }, + { "nesr27", 411, {0, {0}}, 0, 0 }, + { "nesr28", 412, {0, {0}}, 0, 0 }, + { "nesr29", 413, {0, {0}}, 0, 0 }, + { "nesr30", 414, {0, {0}}, 0, 0 }, + { "nesr31", 415, {0, {0}}, 0, 0 }, + { "necr", 416, {0, {0}}, 0, 0 }, + { "gner0", 432, {0, {0}}, 0, 0 }, + { "gner1", 433, {0, {0}}, 0, 0 }, + { "fner0", 434, {0, {0}}, 0, 0 }, + { "fner1", 435, {0, {0}}, 0, 0 }, + { "epcr0", 512, {0, {0}}, 0, 0 }, + { "epcr1", 513, {0, {0}}, 0, 0 }, + { "epcr2", 514, {0, {0}}, 0, 0 }, + { "epcr3", 515, {0, {0}}, 0, 0 }, + { "epcr4", 516, {0, {0}}, 0, 0 }, + { "epcr5", 517, {0, {0}}, 0, 0 }, + { "epcr6", 518, {0, {0}}, 0, 0 }, + { "epcr7", 519, {0, {0}}, 0, 0 }, + { "epcr8", 520, {0, {0}}, 0, 0 }, + { "epcr9", 521, {0, {0}}, 0, 0 }, + { "epcr10", 522, {0, {0}}, 0, 0 }, + { "epcr11", 523, {0, {0}}, 0, 0 }, + { "epcr12", 524, {0, {0}}, 0, 0 }, + { "epcr13", 525, {0, {0}}, 0, 0 }, + { "epcr14", 526, {0, {0}}, 0, 0 }, + { "epcr15", 527, {0, {0}}, 0, 0 }, + { "epcr16", 528, {0, {0}}, 0, 0 }, + { "epcr17", 529, {0, {0}}, 0, 0 }, + { "epcr18", 530, {0, {0}}, 0, 0 }, + { "epcr19", 531, {0, {0}}, 0, 0 }, + { "epcr20", 532, {0, {0}}, 0, 0 }, + { "epcr21", 533, {0, {0}}, 0, 0 }, + { "epcr22", 534, {0, {0}}, 0, 0 }, + { "epcr23", 535, {0, {0}}, 0, 0 }, + { "epcr24", 536, {0, {0}}, 0, 0 }, + { "epcr25", 537, {0, {0}}, 0, 0 }, + { "epcr26", 538, {0, {0}}, 0, 0 }, + { "epcr27", 539, {0, {0}}, 0, 0 }, + { "epcr28", 540, {0, {0}}, 0, 0 }, + { "epcr29", 541, {0, {0}}, 0, 0 }, + { "epcr30", 542, {0, {0}}, 0, 0 }, + { "epcr31", 543, {0, {0}}, 0, 0 }, + { "epcr32", 544, {0, {0}}, 0, 0 }, + { "epcr33", 545, {0, {0}}, 0, 0 }, + { "epcr34", 546, {0, {0}}, 0, 0 }, + { "epcr35", 547, {0, {0}}, 0, 0 }, + { "epcr36", 548, {0, {0}}, 0, 0 }, + { "epcr37", 549, {0, {0}}, 0, 0 }, + { "epcr38", 550, {0, {0}}, 0, 0 }, + { "epcr39", 551, {0, {0}}, 0, 0 }, + { "epcr40", 552, {0, {0}}, 0, 0 }, + { "epcr41", 553, {0, {0}}, 0, 0 }, + { "epcr42", 554, {0, {0}}, 0, 0 }, + { "epcr43", 555, {0, {0}}, 0, 0 }, + { "epcr44", 556, {0, {0}}, 0, 0 }, + { "epcr45", 557, {0, {0}}, 0, 0 }, + { "epcr46", 558, {0, {0}}, 0, 0 }, + { "epcr47", 559, {0, {0}}, 0, 0 }, + { "epcr48", 560, {0, {0}}, 0, 0 }, + { "epcr49", 561, {0, {0}}, 0, 0 }, + { "epcr50", 562, {0, {0}}, 0, 0 }, + { "epcr51", 563, {0, {0}}, 0, 0 }, + { "epcr52", 564, {0, {0}}, 0, 0 }, + { "epcr53", 565, {0, {0}}, 0, 0 }, + { "epcr54", 566, {0, {0}}, 0, 0 }, + { "epcr55", 567, {0, {0}}, 0, 0 }, + { "epcr56", 568, {0, {0}}, 0, 0 }, + { "epcr57", 569, {0, {0}}, 0, 0 }, + { "epcr58", 570, {0, {0}}, 0, 0 }, + { "epcr59", 571, {0, {0}}, 0, 0 }, + { "epcr60", 572, {0, {0}}, 0, 0 }, + { "epcr61", 573, {0, {0}}, 0, 0 }, + { "epcr62", 574, {0, {0}}, 0, 0 }, + { "epcr63", 575, {0, {0}}, 0, 0 }, + { "esr0", 576, {0, {0}}, 0, 0 }, + { "esr1", 577, {0, {0}}, 0, 0 }, + { "esr2", 578, {0, {0}}, 0, 0 }, + { "esr3", 579, {0, {0}}, 0, 0 }, + { "esr4", 580, {0, {0}}, 0, 0 }, + { "esr5", 581, {0, {0}}, 0, 0 }, + { "esr6", 582, {0, {0}}, 0, 0 }, + { "esr7", 583, {0, {0}}, 0, 0 }, + { "esr8", 584, {0, {0}}, 0, 0 }, + { "esr9", 585, {0, {0}}, 0, 0 }, + { "esr10", 586, {0, {0}}, 0, 0 }, + { "esr11", 587, {0, {0}}, 0, 0 }, + { "esr12", 588, {0, {0}}, 0, 0 }, + { "esr13", 589, {0, {0}}, 0, 0 }, + { "esr14", 590, {0, {0}}, 0, 0 }, + { "esr15", 591, {0, {0}}, 0, 0 }, + { "esr16", 592, {0, {0}}, 0, 0 }, + { "esr17", 593, {0, {0}}, 0, 0 }, + { "esr18", 594, {0, {0}}, 0, 0 }, + { "esr19", 595, {0, {0}}, 0, 0 }, + { "esr20", 596, {0, {0}}, 0, 0 }, + { "esr21", 597, {0, {0}}, 0, 0 }, + { "esr22", 598, {0, {0}}, 0, 0 }, + { "esr23", 599, {0, {0}}, 0, 0 }, + { "esr24", 600, {0, {0}}, 0, 0 }, + { "esr25", 601, {0, {0}}, 0, 0 }, + { "esr26", 602, {0, {0}}, 0, 0 }, + { "esr27", 603, {0, {0}}, 0, 0 }, + { "esr28", 604, {0, {0}}, 0, 0 }, + { "esr29", 605, {0, {0}}, 0, 0 }, + { "esr30", 606, {0, {0}}, 0, 0 }, + { "esr31", 607, {0, {0}}, 0, 0 }, + { "esr32", 608, {0, {0}}, 0, 0 }, + { "esr33", 609, {0, {0}}, 0, 0 }, + { "esr34", 610, {0, {0}}, 0, 0 }, + { "esr35", 611, {0, {0}}, 0, 0 }, + { "esr36", 612, {0, {0}}, 0, 0 }, + { "esr37", 613, {0, {0}}, 0, 0 }, + { "esr38", 614, {0, {0}}, 0, 0 }, + { "esr39", 615, {0, {0}}, 0, 0 }, + { "esr40", 616, {0, {0}}, 0, 0 }, + { "esr41", 617, {0, {0}}, 0, 0 }, + { "esr42", 618, {0, {0}}, 0, 0 }, + { "esr43", 619, {0, {0}}, 0, 0 }, + { "esr44", 620, {0, {0}}, 0, 0 }, + { "esr45", 621, {0, {0}}, 0, 0 }, + { "esr46", 622, {0, {0}}, 0, 0 }, + { "esr47", 623, {0, {0}}, 0, 0 }, + { "esr48", 624, {0, {0}}, 0, 0 }, + { "esr49", 625, {0, {0}}, 0, 0 }, + { "esr50", 626, {0, {0}}, 0, 0 }, + { "esr51", 627, {0, {0}}, 0, 0 }, + { "esr52", 628, {0, {0}}, 0, 0 }, + { "esr53", 629, {0, {0}}, 0, 0 }, + { "esr54", 630, {0, {0}}, 0, 0 }, + { "esr55", 631, {0, {0}}, 0, 0 }, + { "esr56", 632, {0, {0}}, 0, 0 }, + { "esr57", 633, {0, {0}}, 0, 0 }, + { "esr58", 634, {0, {0}}, 0, 0 }, + { "esr59", 635, {0, {0}}, 0, 0 }, + { "esr60", 636, {0, {0}}, 0, 0 }, + { "esr61", 637, {0, {0}}, 0, 0 }, + { "esr62", 638, {0, {0}}, 0, 0 }, + { "esr63", 639, {0, {0}}, 0, 0 }, + { "eir0", 640, {0, {0}}, 0, 0 }, + { "eir1", 641, {0, {0}}, 0, 0 }, + { "eir2", 642, {0, {0}}, 0, 0 }, + { "eir3", 643, {0, {0}}, 0, 0 }, + { "eir4", 644, {0, {0}}, 0, 0 }, + { "eir5", 645, {0, {0}}, 0, 0 }, + { "eir6", 646, {0, {0}}, 0, 0 }, + { "eir7", 647, {0, {0}}, 0, 0 }, + { "eir8", 648, {0, {0}}, 0, 0 }, + { "eir9", 649, {0, {0}}, 0, 0 }, + { "eir10", 650, {0, {0}}, 0, 0 }, + { "eir11", 651, {0, {0}}, 0, 0 }, + { "eir12", 652, {0, {0}}, 0, 0 }, + { "eir13", 653, {0, {0}}, 0, 0 }, + { "eir14", 654, {0, {0}}, 0, 0 }, + { "eir15", 655, {0, {0}}, 0, 0 }, + { "eir16", 656, {0, {0}}, 0, 0 }, + { "eir17", 657, {0, {0}}, 0, 0 }, + { "eir18", 658, {0, {0}}, 0, 0 }, + { "eir19", 659, {0, {0}}, 0, 0 }, + { "eir20", 660, {0, {0}}, 0, 0 }, + { "eir21", 661, {0, {0}}, 0, 0 }, + { "eir22", 662, {0, {0}}, 0, 0 }, + { "eir23", 663, {0, {0}}, 0, 0 }, + { "eir24", 664, {0, {0}}, 0, 0 }, + { "eir25", 665, {0, {0}}, 0, 0 }, + { "eir26", 666, {0, {0}}, 0, 0 }, + { "eir27", 667, {0, {0}}, 0, 0 }, + { "eir28", 668, {0, {0}}, 0, 0 }, + { "eir29", 669, {0, {0}}, 0, 0 }, + { "eir30", 670, {0, {0}}, 0, 0 }, + { "eir31", 671, {0, {0}}, 0, 0 }, + { "esfr0", 672, {0, {0}}, 0, 0 }, + { "esfr1", 673, {0, {0}}, 0, 0 }, + { "sr0", 768, {0, {0}}, 0, 0 }, + { "sr1", 769, {0, {0}}, 0, 0 }, + { "sr2", 770, {0, {0}}, 0, 0 }, + { "sr3", 771, {0, {0}}, 0, 0 }, + { "fsr0", 1024, {0, {0}}, 0, 0 }, + { "fsr1", 1025, {0, {0}}, 0, 0 }, + { "fsr2", 1026, {0, {0}}, 0, 0 }, + { "fsr3", 1027, {0, {0}}, 0, 0 }, + { "fsr4", 1028, {0, {0}}, 0, 0 }, + { "fsr5", 1029, {0, {0}}, 0, 0 }, + { "fsr6", 1030, {0, {0}}, 0, 0 }, + { "fsr7", 1031, {0, {0}}, 0, 0 }, + { "fsr8", 1032, {0, {0}}, 0, 0 }, + { "fsr9", 1033, {0, {0}}, 0, 0 }, + { "fsr10", 1034, {0, {0}}, 0, 0 }, + { "fsr11", 1035, {0, {0}}, 0, 0 }, + { "fsr12", 1036, {0, {0}}, 0, 0 }, + { "fsr13", 1037, {0, {0}}, 0, 0 }, + { "fsr14", 1038, {0, {0}}, 0, 0 }, + { "fsr15", 1039, {0, {0}}, 0, 0 }, + { "fsr16", 1040, {0, {0}}, 0, 0 }, + { "fsr17", 1041, {0, {0}}, 0, 0 }, + { "fsr18", 1042, {0, {0}}, 0, 0 }, + { "fsr19", 1043, {0, {0}}, 0, 0 }, + { "fsr20", 1044, {0, {0}}, 0, 0 }, + { "fsr21", 1045, {0, {0}}, 0, 0 }, + { "fsr22", 1046, {0, {0}}, 0, 0 }, + { "fsr23", 1047, {0, {0}}, 0, 0 }, + { "fsr24", 1048, {0, {0}}, 0, 0 }, + { "fsr25", 1049, {0, {0}}, 0, 0 }, + { "fsr26", 1050, {0, {0}}, 0, 0 }, + { "fsr27", 1051, {0, {0}}, 0, 0 }, + { "fsr28", 1052, {0, {0}}, 0, 0 }, + { "fsr29", 1053, {0, {0}}, 0, 0 }, + { "fsr30", 1054, {0, {0}}, 0, 0 }, + { "fsr31", 1055, {0, {0}}, 0, 0 }, + { "fsr32", 1056, {0, {0}}, 0, 0 }, + { "fsr33", 1057, {0, {0}}, 0, 0 }, + { "fsr34", 1058, {0, {0}}, 0, 0 }, + { "fsr35", 1059, {0, {0}}, 0, 0 }, + { "fsr36", 1060, {0, {0}}, 0, 0 }, + { "fsr37", 1061, {0, {0}}, 0, 0 }, + { "fsr38", 1062, {0, {0}}, 0, 0 }, + { "fsr39", 1063, {0, {0}}, 0, 0 }, + { "fsr40", 1064, {0, {0}}, 0, 0 }, + { "fsr41", 1065, {0, {0}}, 0, 0 }, + { "fsr42", 1066, {0, {0}}, 0, 0 }, + { "fsr43", 1067, {0, {0}}, 0, 0 }, + { "fsr44", 1068, {0, {0}}, 0, 0 }, + { "fsr45", 1069, {0, {0}}, 0, 0 }, + { "fsr46", 1070, {0, {0}}, 0, 0 }, + { "fsr47", 1071, {0, {0}}, 0, 0 }, + { "fsr48", 1072, {0, {0}}, 0, 0 }, + { "fsr49", 1073, {0, {0}}, 0, 0 }, + { "fsr50", 1074, {0, {0}}, 0, 0 }, + { "fsr51", 1075, {0, {0}}, 0, 0 }, + { "fsr52", 1076, {0, {0}}, 0, 0 }, + { "fsr53", 1077, {0, {0}}, 0, 0 }, + { "fsr54", 1078, {0, {0}}, 0, 0 }, + { "fsr55", 1079, {0, {0}}, 0, 0 }, + { "fsr56", 1080, {0, {0}}, 0, 0 }, + { "fsr57", 1081, {0, {0}}, 0, 0 }, + { "fsr58", 1082, {0, {0}}, 0, 0 }, + { "fsr59", 1083, {0, {0}}, 0, 0 }, + { "fsr60", 1084, {0, {0}}, 0, 0 }, + { "fsr61", 1085, {0, {0}}, 0, 0 }, + { "fsr62", 1086, {0, {0}}, 0, 0 }, + { "fsr63", 1087, {0, {0}}, 0, 0 }, + { "fqop0", 1088, {0, {0}}, 0, 0 }, + { "fqop1", 1090, {0, {0}}, 0, 0 }, + { "fqop2", 1092, {0, {0}}, 0, 0 }, + { "fqop3", 1094, {0, {0}}, 0, 0 }, + { "fqop4", 1096, {0, {0}}, 0, 0 }, + { "fqop5", 1098, {0, {0}}, 0, 0 }, + { "fqop6", 1100, {0, {0}}, 0, 0 }, + { "fqop7", 1102, {0, {0}}, 0, 0 }, + { "fqop8", 1104, {0, {0}}, 0, 0 }, + { "fqop9", 1106, {0, {0}}, 0, 0 }, + { "fqop10", 1108, {0, {0}}, 0, 0 }, + { "fqop11", 1110, {0, {0}}, 0, 0 }, + { "fqop12", 1112, {0, {0}}, 0, 0 }, + { "fqop13", 1114, {0, {0}}, 0, 0 }, + { "fqop14", 1116, {0, {0}}, 0, 0 }, + { "fqop15", 1118, {0, {0}}, 0, 0 }, + { "fqop16", 1120, {0, {0}}, 0, 0 }, + { "fqop17", 1122, {0, {0}}, 0, 0 }, + { "fqop18", 1124, {0, {0}}, 0, 0 }, + { "fqop19", 1126, {0, {0}}, 0, 0 }, + { "fqop20", 1128, {0, {0}}, 0, 0 }, + { "fqop21", 1130, {0, {0}}, 0, 0 }, + { "fqop22", 1132, {0, {0}}, 0, 0 }, + { "fqop23", 1134, {0, {0}}, 0, 0 }, + { "fqop24", 1136, {0, {0}}, 0, 0 }, + { "fqop25", 1138, {0, {0}}, 0, 0 }, + { "fqop26", 1140, {0, {0}}, 0, 0 }, + { "fqop27", 1142, {0, {0}}, 0, 0 }, + { "fqop28", 1144, {0, {0}}, 0, 0 }, + { "fqop29", 1146, {0, {0}}, 0, 0 }, + { "fqop30", 1148, {0, {0}}, 0, 0 }, + { "fqop31", 1150, {0, {0}}, 0, 0 }, + { "fqst0", 1089, {0, {0}}, 0, 0 }, + { "fqst1", 1091, {0, {0}}, 0, 0 }, + { "fqst2", 1093, {0, {0}}, 0, 0 }, + { "fqst3", 1095, {0, {0}}, 0, 0 }, + { "fqst4", 1097, {0, {0}}, 0, 0 }, + { "fqst5", 1099, {0, {0}}, 0, 0 }, + { "fqst6", 1101, {0, {0}}, 0, 0 }, + { "fqst7", 1103, {0, {0}}, 0, 0 }, + { "fqst8", 1105, {0, {0}}, 0, 0 }, + { "fqst9", 1107, {0, {0}}, 0, 0 }, + { "fqst10", 1109, {0, {0}}, 0, 0 }, + { "fqst11", 1111, {0, {0}}, 0, 0 }, + { "fqst12", 1113, {0, {0}}, 0, 0 }, + { "fqst13", 1115, {0, {0}}, 0, 0 }, + { "fqst14", 1117, {0, {0}}, 0, 0 }, + { "fqst15", 1119, {0, {0}}, 0, 0 }, + { "fqst16", 1121, {0, {0}}, 0, 0 }, + { "fqst17", 1123, {0, {0}}, 0, 0 }, + { "fqst18", 1125, {0, {0}}, 0, 0 }, + { "fqst19", 1127, {0, {0}}, 0, 0 }, + { "fqst20", 1129, {0, {0}}, 0, 0 }, + { "fqst21", 1131, {0, {0}}, 0, 0 }, + { "fqst22", 1133, {0, {0}}, 0, 0 }, + { "fqst23", 1135, {0, {0}}, 0, 0 }, + { "fqst24", 1137, {0, {0}}, 0, 0 }, + { "fqst25", 1139, {0, {0}}, 0, 0 }, + { "fqst26", 1141, {0, {0}}, 0, 0 }, + { "fqst27", 1143, {0, {0}}, 0, 0 }, + { "fqst28", 1145, {0, {0}}, 0, 0 }, + { "fqst29", 1147, {0, {0}}, 0, 0 }, + { "fqst30", 1149, {0, {0}}, 0, 0 }, + { "fqst31", 1151, {0, {0}}, 0, 0 }, + { "mcilr0", 1272, {0, {0}}, 0, 0 }, + { "mcilr1", 1273, {0, {0}}, 0, 0 }, + { "msr0", 1280, {0, {0}}, 0, 0 }, + { "msr1", 1281, {0, {0}}, 0, 0 }, + { "msr2", 1282, {0, {0}}, 0, 0 }, + { "msr3", 1283, {0, {0}}, 0, 0 }, + { "msr4", 1284, {0, {0}}, 0, 0 }, + { "msr5", 1285, {0, {0}}, 0, 0 }, + { "msr6", 1286, {0, {0}}, 0, 0 }, + { "msr7", 1287, {0, {0}}, 0, 0 }, + { "msr8", 1288, {0, {0}}, 0, 0 }, + { "msr9", 1289, {0, {0}}, 0, 0 }, + { "msr10", 1290, {0, {0}}, 0, 0 }, + { "msr11", 1291, {0, {0}}, 0, 0 }, + { "msr12", 1292, {0, {0}}, 0, 0 }, + { "msr13", 1293, {0, {0}}, 0, 0 }, + { "msr14", 1294, {0, {0}}, 0, 0 }, + { "msr15", 1295, {0, {0}}, 0, 0 }, + { "msr16", 1296, {0, {0}}, 0, 0 }, + { "msr17", 1297, {0, {0}}, 0, 0 }, + { "msr18", 1298, {0, {0}}, 0, 0 }, + { "msr19", 1299, {0, {0}}, 0, 0 }, + { "msr20", 1300, {0, {0}}, 0, 0 }, + { "msr21", 1301, {0, {0}}, 0, 0 }, + { "msr22", 1302, {0, {0}}, 0, 0 }, + { "msr23", 1303, {0, {0}}, 0, 0 }, + { "msr24", 1304, {0, {0}}, 0, 0 }, + { "msr25", 1305, {0, {0}}, 0, 0 }, + { "msr26", 1306, {0, {0}}, 0, 0 }, + { "msr27", 1307, {0, {0}}, 0, 0 }, + { "msr28", 1308, {0, {0}}, 0, 0 }, + { "msr29", 1309, {0, {0}}, 0, 0 }, + { "msr30", 1310, {0, {0}}, 0, 0 }, + { "msr31", 1311, {0, {0}}, 0, 0 }, + { "msr32", 1312, {0, {0}}, 0, 0 }, + { "msr33", 1313, {0, {0}}, 0, 0 }, + { "msr34", 1314, {0, {0}}, 0, 0 }, + { "msr35", 1315, {0, {0}}, 0, 0 }, + { "msr36", 1316, {0, {0}}, 0, 0 }, + { "msr37", 1317, {0, {0}}, 0, 0 }, + { "msr38", 1318, {0, {0}}, 0, 0 }, + { "msr39", 1319, {0, {0}}, 0, 0 }, + { "msr40", 1320, {0, {0}}, 0, 0 }, + { "msr41", 1321, {0, {0}}, 0, 0 }, + { "msr42", 1322, {0, {0}}, 0, 0 }, + { "msr43", 1323, {0, {0}}, 0, 0 }, + { "msr44", 1324, {0, {0}}, 0, 0 }, + { "msr45", 1325, {0, {0}}, 0, 0 }, + { "msr46", 1326, {0, {0}}, 0, 0 }, + { "msr47", 1327, {0, {0}}, 0, 0 }, + { "msr48", 1328, {0, {0}}, 0, 0 }, + { "msr49", 1329, {0, {0}}, 0, 0 }, + { "msr50", 1330, {0, {0}}, 0, 0 }, + { "msr51", 1331, {0, {0}}, 0, 0 }, + { "msr52", 1332, {0, {0}}, 0, 0 }, + { "msr53", 1333, {0, {0}}, 0, 0 }, + { "msr54", 1334, {0, {0}}, 0, 0 }, + { "msr55", 1335, {0, {0}}, 0, 0 }, + { "msr56", 1336, {0, {0}}, 0, 0 }, + { "msr57", 1337, {0, {0}}, 0, 0 }, + { "msr58", 1338, {0, {0}}, 0, 0 }, + { "msr59", 1339, {0, {0}}, 0, 0 }, + { "msr60", 1340, {0, {0}}, 0, 0 }, + { "msr61", 1341, {0, {0}}, 0, 0 }, + { "msr62", 1342, {0, {0}}, 0, 0 }, + { "msr63", 1343, {0, {0}}, 0, 0 }, + { "mqop0", 1344, {0, {0}}, 0, 0 }, + { "mqop1", 1346, {0, {0}}, 0, 0 }, + { "mqop2", 1348, {0, {0}}, 0, 0 }, + { "mqop3", 1350, {0, {0}}, 0, 0 }, + { "mqop4", 1352, {0, {0}}, 0, 0 }, + { "mqop5", 1354, {0, {0}}, 0, 0 }, + { "mqop6", 1356, {0, {0}}, 0, 0 }, + { "mqop7", 1358, {0, {0}}, 0, 0 }, + { "mqop8", 1360, {0, {0}}, 0, 0 }, + { "mqop9", 1362, {0, {0}}, 0, 0 }, + { "mqop10", 1364, {0, {0}}, 0, 0 }, + { "mqop11", 1366, {0, {0}}, 0, 0 }, + { "mqop12", 1368, {0, {0}}, 0, 0 }, + { "mqop13", 1370, {0, {0}}, 0, 0 }, + { "mqop14", 1372, {0, {0}}, 0, 0 }, + { "mqop15", 1374, {0, {0}}, 0, 0 }, + { "mqop16", 1376, {0, {0}}, 0, 0 }, + { "mqop17", 1378, {0, {0}}, 0, 0 }, + { "mqop18", 1380, {0, {0}}, 0, 0 }, + { "mqop19", 1382, {0, {0}}, 0, 0 }, + { "mqop20", 1384, {0, {0}}, 0, 0 }, + { "mqop21", 1386, {0, {0}}, 0, 0 }, + { "mqop22", 1388, {0, {0}}, 0, 0 }, + { "mqop23", 1390, {0, {0}}, 0, 0 }, + { "mqop24", 1392, {0, {0}}, 0, 0 }, + { "mqop25", 1394, {0, {0}}, 0, 0 }, + { "mqop26", 1396, {0, {0}}, 0, 0 }, + { "mqop27", 1398, {0, {0}}, 0, 0 }, + { "mqop28", 1400, {0, {0}}, 0, 0 }, + { "mqop29", 1402, {0, {0}}, 0, 0 }, + { "mqop30", 1404, {0, {0}}, 0, 0 }, + { "mqop31", 1406, {0, {0}}, 0, 0 }, + { "mqst0", 1345, {0, {0}}, 0, 0 }, + { "mqst1", 1347, {0, {0}}, 0, 0 }, + { "mqst2", 1349, {0, {0}}, 0, 0 }, + { "mqst3", 1351, {0, {0}}, 0, 0 }, + { "mqst4", 1353, {0, {0}}, 0, 0 }, + { "mqst5", 1355, {0, {0}}, 0, 0 }, + { "mqst6", 1357, {0, {0}}, 0, 0 }, + { "mqst7", 1359, {0, {0}}, 0, 0 }, + { "mqst8", 1361, {0, {0}}, 0, 0 }, + { "mqst9", 1363, {0, {0}}, 0, 0 }, + { "mqst10", 1365, {0, {0}}, 0, 0 }, + { "mqst11", 1367, {0, {0}}, 0, 0 }, + { "mqst12", 1369, {0, {0}}, 0, 0 }, + { "mqst13", 1371, {0, {0}}, 0, 0 }, + { "mqst14", 1373, {0, {0}}, 0, 0 }, + { "mqst15", 1375, {0, {0}}, 0, 0 }, + { "mqst16", 1377, {0, {0}}, 0, 0 }, + { "mqst17", 1379, {0, {0}}, 0, 0 }, + { "mqst18", 1381, {0, {0}}, 0, 0 }, + { "mqst19", 1383, {0, {0}}, 0, 0 }, + { "mqst20", 1385, {0, {0}}, 0, 0 }, + { "mqst21", 1387, {0, {0}}, 0, 0 }, + { "mqst22", 1389, {0, {0}}, 0, 0 }, + { "mqst23", 1391, {0, {0}}, 0, 0 }, + { "mqst24", 1393, {0, {0}}, 0, 0 }, + { "mqst25", 1395, {0, {0}}, 0, 0 }, + { "mqst26", 1397, {0, {0}}, 0, 0 }, + { "mqst27", 1399, {0, {0}}, 0, 0 }, + { "mqst28", 1401, {0, {0}}, 0, 0 }, + { "mqst29", 1403, {0, {0}}, 0, 0 }, + { "mqst30", 1405, {0, {0}}, 0, 0 }, + { "mqst31", 1407, {0, {0}}, 0, 0 }, + { "ear0", 1536, {0, {0}}, 0, 0 }, + { "ear1", 1537, {0, {0}}, 0, 0 }, + { "ear2", 1538, {0, {0}}, 0, 0 }, + { "ear3", 1539, {0, {0}}, 0, 0 }, + { "ear4", 1540, {0, {0}}, 0, 0 }, + { "ear5", 1541, {0, {0}}, 0, 0 }, + { "ear6", 1542, {0, {0}}, 0, 0 }, + { "ear7", 1543, {0, {0}}, 0, 0 }, + { "ear8", 1544, {0, {0}}, 0, 0 }, + { "ear9", 1545, {0, {0}}, 0, 0 }, + { "ear10", 1546, {0, {0}}, 0, 0 }, + { "ear11", 1547, {0, {0}}, 0, 0 }, + { "ear12", 1548, {0, {0}}, 0, 0 }, + { "ear13", 1549, {0, {0}}, 0, 0 }, + { "ear14", 1550, {0, {0}}, 0, 0 }, + { "ear15", 1551, {0, {0}}, 0, 0 }, + { "ear16", 1552, {0, {0}}, 0, 0 }, + { "ear17", 1553, {0, {0}}, 0, 0 }, + { "ear18", 1554, {0, {0}}, 0, 0 }, + { "ear19", 1555, {0, {0}}, 0, 0 }, + { "ear20", 1556, {0, {0}}, 0, 0 }, + { "ear21", 1557, {0, {0}}, 0, 0 }, + { "ear22", 1558, {0, {0}}, 0, 0 }, + { "ear23", 1559, {0, {0}}, 0, 0 }, + { "ear24", 1560, {0, {0}}, 0, 0 }, + { "ear25", 1561, {0, {0}}, 0, 0 }, + { "ear26", 1562, {0, {0}}, 0, 0 }, + { "ear27", 1563, {0, {0}}, 0, 0 }, + { "ear28", 1564, {0, {0}}, 0, 0 }, + { "ear29", 1565, {0, {0}}, 0, 0 }, + { "ear30", 1566, {0, {0}}, 0, 0 }, + { "ear31", 1567, {0, {0}}, 0, 0 }, + { "ear32", 1568, {0, {0}}, 0, 0 }, + { "ear33", 1569, {0, {0}}, 0, 0 }, + { "ear34", 1570, {0, {0}}, 0, 0 }, + { "ear35", 1571, {0, {0}}, 0, 0 }, + { "ear36", 1572, {0, {0}}, 0, 0 }, + { "ear37", 1573, {0, {0}}, 0, 0 }, + { "ear38", 1574, {0, {0}}, 0, 0 }, + { "ear39", 1575, {0, {0}}, 0, 0 }, + { "ear40", 1576, {0, {0}}, 0, 0 }, + { "ear41", 1577, {0, {0}}, 0, 0 }, + { "ear42", 1578, {0, {0}}, 0, 0 }, + { "ear43", 1579, {0, {0}}, 0, 0 }, + { "ear44", 1580, {0, {0}}, 0, 0 }, + { "ear45", 1581, {0, {0}}, 0, 0 }, + { "ear46", 1582, {0, {0}}, 0, 0 }, + { "ear47", 1583, {0, {0}}, 0, 0 }, + { "ear48", 1584, {0, {0}}, 0, 0 }, + { "ear49", 1585, {0, {0}}, 0, 0 }, + { "ear50", 1586, {0, {0}}, 0, 0 }, + { "ear51", 1587, {0, {0}}, 0, 0 }, + { "ear52", 1588, {0, {0}}, 0, 0 }, + { "ear53", 1589, {0, {0}}, 0, 0 }, + { "ear54", 1590, {0, {0}}, 0, 0 }, + { "ear55", 1591, {0, {0}}, 0, 0 }, + { "ear56", 1592, {0, {0}}, 0, 0 }, + { "ear57", 1593, {0, {0}}, 0, 0 }, + { "ear58", 1594, {0, {0}}, 0, 0 }, + { "ear59", 1595, {0, {0}}, 0, 0 }, + { "ear60", 1596, {0, {0}}, 0, 0 }, + { "ear61", 1597, {0, {0}}, 0, 0 }, + { "ear62", 1598, {0, {0}}, 0, 0 }, + { "ear63", 1599, {0, {0}}, 0, 0 }, + { "edr0", 1600, {0, {0}}, 0, 0 }, + { "edr1", 1601, {0, {0}}, 0, 0 }, + { "edr2", 1602, {0, {0}}, 0, 0 }, + { "edr3", 1603, {0, {0}}, 0, 0 }, + { "edr4", 1604, {0, {0}}, 0, 0 }, + { "edr5", 1605, {0, {0}}, 0, 0 }, + { "edr6", 1606, {0, {0}}, 0, 0 }, + { "edr7", 1607, {0, {0}}, 0, 0 }, + { "edr8", 1608, {0, {0}}, 0, 0 }, + { "edr9", 1609, {0, {0}}, 0, 0 }, + { "edr10", 1610, {0, {0}}, 0, 0 }, + { "edr11", 1611, {0, {0}}, 0, 0 }, + { "edr12", 1612, {0, {0}}, 0, 0 }, + { "edr13", 1613, {0, {0}}, 0, 0 }, + { "edr14", 1614, {0, {0}}, 0, 0 }, + { "edr15", 1615, {0, {0}}, 0, 0 }, + { "edr16", 1616, {0, {0}}, 0, 0 }, + { "edr17", 1617, {0, {0}}, 0, 0 }, + { "edr18", 1618, {0, {0}}, 0, 0 }, + { "edr19", 1619, {0, {0}}, 0, 0 }, + { "edr20", 1620, {0, {0}}, 0, 0 }, + { "edr21", 1621, {0, {0}}, 0, 0 }, + { "edr22", 1622, {0, {0}}, 0, 0 }, + { "edr23", 1623, {0, {0}}, 0, 0 }, + { "edr24", 1624, {0, {0}}, 0, 0 }, + { "edr25", 1625, {0, {0}}, 0, 0 }, + { "edr26", 1626, {0, {0}}, 0, 0 }, + { "edr27", 1627, {0, {0}}, 0, 0 }, + { "edr28", 1628, {0, {0}}, 0, 0 }, + { "edr29", 1629, {0, {0}}, 0, 0 }, + { "edr30", 1630, {0, {0}}, 0, 0 }, + { "edr31", 1631, {0, {0}}, 0, 0 }, + { "edr32", 1632, {0, {0}}, 0, 0 }, + { "edr33", 1636, {0, {0}}, 0, 0 }, + { "edr34", 1634, {0, {0}}, 0, 0 }, + { "edr35", 1635, {0, {0}}, 0, 0 }, + { "edr36", 1636, {0, {0}}, 0, 0 }, + { "edr37", 1637, {0, {0}}, 0, 0 }, + { "edr38", 1638, {0, {0}}, 0, 0 }, + { "edr39", 1639, {0, {0}}, 0, 0 }, + { "edr40", 1640, {0, {0}}, 0, 0 }, + { "edr41", 1641, {0, {0}}, 0, 0 }, + { "edr42", 1642, {0, {0}}, 0, 0 }, + { "edr43", 1643, {0, {0}}, 0, 0 }, + { "edr44", 1644, {0, {0}}, 0, 0 }, + { "edr45", 1645, {0, {0}}, 0, 0 }, + { "edr46", 1646, {0, {0}}, 0, 0 }, + { "edr47", 1647, {0, {0}}, 0, 0 }, + { "edr48", 1648, {0, {0}}, 0, 0 }, + { "edr49", 1649, {0, {0}}, 0, 0 }, + { "edr50", 1650, {0, {0}}, 0, 0 }, + { "edr51", 1651, {0, {0}}, 0, 0 }, + { "edr52", 1652, {0, {0}}, 0, 0 }, + { "edr53", 1653, {0, {0}}, 0, 0 }, + { "edr54", 1654, {0, {0}}, 0, 0 }, + { "edr55", 1655, {0, {0}}, 0, 0 }, + { "edr56", 1656, {0, {0}}, 0, 0 }, + { "edr57", 1657, {0, {0}}, 0, 0 }, + { "edr58", 1658, {0, {0}}, 0, 0 }, + { "edr59", 1659, {0, {0}}, 0, 0 }, + { "edr60", 1660, {0, {0}}, 0, 0 }, + { "edr61", 1661, {0, {0}}, 0, 0 }, + { "edr62", 1662, {0, {0}}, 0, 0 }, + { "edr63", 1663, {0, {0}}, 0, 0 }, + { "iamlr0", 1664, {0, {0}}, 0, 0 }, + { "iamlr1", 1665, {0, {0}}, 0, 0 }, + { "iamlr2", 1666, {0, {0}}, 0, 0 }, + { "iamlr3", 1667, {0, {0}}, 0, 0 }, + { "iamlr4", 1668, {0, {0}}, 0, 0 }, + { "iamlr5", 1669, {0, {0}}, 0, 0 }, + { "iamlr6", 1670, {0, {0}}, 0, 0 }, + { "iamlr7", 1671, {0, {0}}, 0, 0 }, + { "iamlr8", 1672, {0, {0}}, 0, 0 }, + { "iamlr9", 1673, {0, {0}}, 0, 0 }, + { "iamlr10", 1674, {0, {0}}, 0, 0 }, + { "iamlr11", 1675, {0, {0}}, 0, 0 }, + { "iamlr12", 1676, {0, {0}}, 0, 0 }, + { "iamlr13", 1677, {0, {0}}, 0, 0 }, + { "iamlr14", 1678, {0, {0}}, 0, 0 }, + { "iamlr15", 1679, {0, {0}}, 0, 0 }, + { "iamlr16", 1680, {0, {0}}, 0, 0 }, + { "iamlr17", 1681, {0, {0}}, 0, 0 }, + { "iamlr18", 1682, {0, {0}}, 0, 0 }, + { "iamlr19", 1683, {0, {0}}, 0, 0 }, + { "iamlr20", 1684, {0, {0}}, 0, 0 }, + { "iamlr21", 1685, {0, {0}}, 0, 0 }, + { "iamlr22", 1686, {0, {0}}, 0, 0 }, + { "iamlr23", 1687, {0, {0}}, 0, 0 }, + { "iamlr24", 1688, {0, {0}}, 0, 0 }, + { "iamlr25", 1689, {0, {0}}, 0, 0 }, + { "iamlr26", 1690, {0, {0}}, 0, 0 }, + { "iamlr27", 1691, {0, {0}}, 0, 0 }, + { "iamlr28", 1692, {0, {0}}, 0, 0 }, + { "iamlr29", 1693, {0, {0}}, 0, 0 }, + { "iamlr30", 1694, {0, {0}}, 0, 0 }, + { "iamlr31", 1695, {0, {0}}, 0, 0 }, + { "iamlr32", 1696, {0, {0}}, 0, 0 }, + { "iamlr33", 1697, {0, {0}}, 0, 0 }, + { "iamlr34", 1698, {0, {0}}, 0, 0 }, + { "iamlr35", 1699, {0, {0}}, 0, 0 }, + { "iamlr36", 1700, {0, {0}}, 0, 0 }, + { "iamlr37", 1701, {0, {0}}, 0, 0 }, + { "iamlr38", 1702, {0, {0}}, 0, 0 }, + { "iamlr39", 1703, {0, {0}}, 0, 0 }, + { "iamlr40", 1704, {0, {0}}, 0, 0 }, + { "iamlr41", 1705, {0, {0}}, 0, 0 }, + { "iamlr42", 1706, {0, {0}}, 0, 0 }, + { "iamlr43", 1707, {0, {0}}, 0, 0 }, + { "iamlr44", 1708, {0, {0}}, 0, 0 }, + { "iamlr45", 1709, {0, {0}}, 0, 0 }, + { "iamlr46", 1710, {0, {0}}, 0, 0 }, + { "iamlr47", 1711, {0, {0}}, 0, 0 }, + { "iamlr48", 1712, {0, {0}}, 0, 0 }, + { "iamlr49", 1713, {0, {0}}, 0, 0 }, + { "iamlr50", 1714, {0, {0}}, 0, 0 }, + { "iamlr51", 1715, {0, {0}}, 0, 0 }, + { "iamlr52", 1716, {0, {0}}, 0, 0 }, + { "iamlr53", 1717, {0, {0}}, 0, 0 }, + { "iamlr54", 1718, {0, {0}}, 0, 0 }, + { "iamlr55", 1719, {0, {0}}, 0, 0 }, + { "iamlr56", 1720, {0, {0}}, 0, 0 }, + { "iamlr57", 1721, {0, {0}}, 0, 0 }, + { "iamlr58", 1722, {0, {0}}, 0, 0 }, + { "iamlr59", 1723, {0, {0}}, 0, 0 }, + { "iamlr60", 1724, {0, {0}}, 0, 0 }, + { "iamlr61", 1725, {0, {0}}, 0, 0 }, + { "iamlr62", 1726, {0, {0}}, 0, 0 }, + { "iamlr63", 1727, {0, {0}}, 0, 0 }, + { "iampr0", 1728, {0, {0}}, 0, 0 }, + { "iampr1", 1729, {0, {0}}, 0, 0 }, + { "iampr2", 1730, {0, {0}}, 0, 0 }, + { "iampr3", 1731, {0, {0}}, 0, 0 }, + { "iampr4", 1732, {0, {0}}, 0, 0 }, + { "iampr5", 1733, {0, {0}}, 0, 0 }, + { "iampr6", 1734, {0, {0}}, 0, 0 }, + { "iampr7", 1735, {0, {0}}, 0, 0 }, + { "iampr8", 1736, {0, {0}}, 0, 0 }, + { "iampr9", 1737, {0, {0}}, 0, 0 }, + { "iampr10", 1738, {0, {0}}, 0, 0 }, + { "iampr11", 1739, {0, {0}}, 0, 0 }, + { "iampr12", 1740, {0, {0}}, 0, 0 }, + { "iampr13", 1741, {0, {0}}, 0, 0 }, + { "iampr14", 1742, {0, {0}}, 0, 0 }, + { "iampr15", 1743, {0, {0}}, 0, 0 }, + { "iampr16", 1744, {0, {0}}, 0, 0 }, + { "iampr17", 1745, {0, {0}}, 0, 0 }, + { "iampr18", 1746, {0, {0}}, 0, 0 }, + { "iampr19", 1747, {0, {0}}, 0, 0 }, + { "iampr20", 1748, {0, {0}}, 0, 0 }, + { "iampr21", 1749, {0, {0}}, 0, 0 }, + { "iampr22", 1750, {0, {0}}, 0, 0 }, + { "iampr23", 1751, {0, {0}}, 0, 0 }, + { "iampr24", 1752, {0, {0}}, 0, 0 }, + { "iampr25", 1753, {0, {0}}, 0, 0 }, + { "iampr26", 1754, {0, {0}}, 0, 0 }, + { "iampr27", 1755, {0, {0}}, 0, 0 }, + { "iampr28", 1756, {0, {0}}, 0, 0 }, + { "iampr29", 1757, {0, {0}}, 0, 0 }, + { "iampr30", 1758, {0, {0}}, 0, 0 }, + { "iampr31", 1759, {0, {0}}, 0, 0 }, + { "iampr32", 1760, {0, {0}}, 0, 0 }, + { "iampr33", 1761, {0, {0}}, 0, 0 }, + { "iampr34", 1762, {0, {0}}, 0, 0 }, + { "iampr35", 1763, {0, {0}}, 0, 0 }, + { "iampr36", 1764, {0, {0}}, 0, 0 }, + { "iampr37", 1765, {0, {0}}, 0, 0 }, + { "iampr38", 1766, {0, {0}}, 0, 0 }, + { "iampr39", 1767, {0, {0}}, 0, 0 }, + { "iampr40", 1768, {0, {0}}, 0, 0 }, + { "iampr41", 1769, {0, {0}}, 0, 0 }, + { "iampr42", 1770, {0, {0}}, 0, 0 }, + { "iampr43", 1771, {0, {0}}, 0, 0 }, + { "iampr44", 1772, {0, {0}}, 0, 0 }, + { "iampr45", 1773, {0, {0}}, 0, 0 }, + { "iampr46", 1774, {0, {0}}, 0, 0 }, + { "iampr47", 1775, {0, {0}}, 0, 0 }, + { "iampr48", 1776, {0, {0}}, 0, 0 }, + { "iampr49", 1777, {0, {0}}, 0, 0 }, + { "iampr50", 1778, {0, {0}}, 0, 0 }, + { "iampr51", 1779, {0, {0}}, 0, 0 }, + { "iampr52", 1780, {0, {0}}, 0, 0 }, + { "iampr53", 1781, {0, {0}}, 0, 0 }, + { "iampr54", 1782, {0, {0}}, 0, 0 }, + { "iampr55", 1783, {0, {0}}, 0, 0 }, + { "iampr56", 1784, {0, {0}}, 0, 0 }, + { "iampr57", 1785, {0, {0}}, 0, 0 }, + { "iampr58", 1786, {0, {0}}, 0, 0 }, + { "iampr59", 1787, {0, {0}}, 0, 0 }, + { "iampr60", 1788, {0, {0}}, 0, 0 }, + { "iampr61", 1789, {0, {0}}, 0, 0 }, + { "iampr62", 1790, {0, {0}}, 0, 0 }, + { "iampr63", 1791, {0, {0}}, 0, 0 }, + { "damlr0", 1792, {0, {0}}, 0, 0 }, + { "damlr1", 1793, {0, {0}}, 0, 0 }, + { "damlr2", 1794, {0, {0}}, 0, 0 }, + { "damlr3", 1795, {0, {0}}, 0, 0 }, + { "damlr4", 1796, {0, {0}}, 0, 0 }, + { "damlr5", 1797, {0, {0}}, 0, 0 }, + { "damlr6", 1798, {0, {0}}, 0, 0 }, + { "damlr7", 1799, {0, {0}}, 0, 0 }, + { "damlr8", 1800, {0, {0}}, 0, 0 }, + { "damlr9", 1801, {0, {0}}, 0, 0 }, + { "damlr10", 1802, {0, {0}}, 0, 0 }, + { "damlr11", 1803, {0, {0}}, 0, 0 }, + { "damlr12", 1804, {0, {0}}, 0, 0 }, + { "damlr13", 1805, {0, {0}}, 0, 0 }, + { "damlr14", 1806, {0, {0}}, 0, 0 }, + { "damlr15", 1807, {0, {0}}, 0, 0 }, + { "damlr16", 1808, {0, {0}}, 0, 0 }, + { "damlr17", 1809, {0, {0}}, 0, 0 }, + { "damlr18", 1810, {0, {0}}, 0, 0 }, + { "damlr19", 1811, {0, {0}}, 0, 0 }, + { "damlr20", 1812, {0, {0}}, 0, 0 }, + { "damlr21", 1813, {0, {0}}, 0, 0 }, + { "damlr22", 1814, {0, {0}}, 0, 0 }, + { "damlr23", 1815, {0, {0}}, 0, 0 }, + { "damlr24", 1816, {0, {0}}, 0, 0 }, + { "damlr25", 1817, {0, {0}}, 0, 0 }, + { "damlr26", 1818, {0, {0}}, 0, 0 }, + { "damlr27", 1819, {0, {0}}, 0, 0 }, + { "damlr28", 1820, {0, {0}}, 0, 0 }, + { "damlr29", 1821, {0, {0}}, 0, 0 }, + { "damlr30", 1822, {0, {0}}, 0, 0 }, + { "damlr31", 1823, {0, {0}}, 0, 0 }, + { "damlr32", 1824, {0, {0}}, 0, 0 }, + { "damlr33", 1825, {0, {0}}, 0, 0 }, + { "damlr34", 1826, {0, {0}}, 0, 0 }, + { "damlr35", 1827, {0, {0}}, 0, 0 }, + { "damlr36", 1828, {0, {0}}, 0, 0 }, + { "damlr37", 1829, {0, {0}}, 0, 0 }, + { "damlr38", 1830, {0, {0}}, 0, 0 }, + { "damlr39", 1831, {0, {0}}, 0, 0 }, + { "damlr40", 1832, {0, {0}}, 0, 0 }, + { "damlr41", 1833, {0, {0}}, 0, 0 }, + { "damlr42", 1834, {0, {0}}, 0, 0 }, + { "damlr43", 1835, {0, {0}}, 0, 0 }, + { "damlr44", 1836, {0, {0}}, 0, 0 }, + { "damlr45", 1837, {0, {0}}, 0, 0 }, + { "damlr46", 1838, {0, {0}}, 0, 0 }, + { "damlr47", 1839, {0, {0}}, 0, 0 }, + { "damlr48", 1840, {0, {0}}, 0, 0 }, + { "damlr49", 1841, {0, {0}}, 0, 0 }, + { "damlr50", 1842, {0, {0}}, 0, 0 }, + { "damlr51", 1843, {0, {0}}, 0, 0 }, + { "damlr52", 1844, {0, {0}}, 0, 0 }, + { "damlr53", 1845, {0, {0}}, 0, 0 }, + { "damlr54", 1846, {0, {0}}, 0, 0 }, + { "damlr55", 1847, {0, {0}}, 0, 0 }, + { "damlr56", 1848, {0, {0}}, 0, 0 }, + { "damlr57", 1849, {0, {0}}, 0, 0 }, + { "damlr58", 1850, {0, {0}}, 0, 0 }, + { "damlr59", 1851, {0, {0}}, 0, 0 }, + { "damlr60", 1852, {0, {0}}, 0, 0 }, + { "damlr61", 1853, {0, {0}}, 0, 0 }, + { "damlr62", 1854, {0, {0}}, 0, 0 }, + { "damlr63", 1855, {0, {0}}, 0, 0 }, + { "dampr0", 1856, {0, {0}}, 0, 0 }, + { "dampr1", 1857, {0, {0}}, 0, 0 }, + { "dampr2", 1858, {0, {0}}, 0, 0 }, + { "dampr3", 1859, {0, {0}}, 0, 0 }, + { "dampr4", 1860, {0, {0}}, 0, 0 }, + { "dampr5", 1861, {0, {0}}, 0, 0 }, + { "dampr6", 1862, {0, {0}}, 0, 0 }, + { "dampr7", 1863, {0, {0}}, 0, 0 }, + { "dampr8", 1864, {0, {0}}, 0, 0 }, + { "dampr9", 1865, {0, {0}}, 0, 0 }, + { "dampr10", 1866, {0, {0}}, 0, 0 }, + { "dampr11", 1867, {0, {0}}, 0, 0 }, + { "dampr12", 1868, {0, {0}}, 0, 0 }, + { "dampr13", 1869, {0, {0}}, 0, 0 }, + { "dampr14", 1870, {0, {0}}, 0, 0 }, + { "dampr15", 1871, {0, {0}}, 0, 0 }, + { "dampr16", 1872, {0, {0}}, 0, 0 }, + { "dampr17", 1873, {0, {0}}, 0, 0 }, + { "dampr18", 1874, {0, {0}}, 0, 0 }, + { "dampr19", 1875, {0, {0}}, 0, 0 }, + { "dampr20", 1876, {0, {0}}, 0, 0 }, + { "dampr21", 1877, {0, {0}}, 0, 0 }, + { "dampr22", 1878, {0, {0}}, 0, 0 }, + { "dampr23", 1879, {0, {0}}, 0, 0 }, + { "dampr24", 1880, {0, {0}}, 0, 0 }, + { "dampr25", 1881, {0, {0}}, 0, 0 }, + { "dampr26", 1882, {0, {0}}, 0, 0 }, + { "dampr27", 1883, {0, {0}}, 0, 0 }, + { "dampr28", 1884, {0, {0}}, 0, 0 }, + { "dampr29", 1885, {0, {0}}, 0, 0 }, + { "dampr30", 1886, {0, {0}}, 0, 0 }, + { "dampr31", 1887, {0, {0}}, 0, 0 }, + { "dampr32", 1888, {0, {0}}, 0, 0 }, + { "dampr33", 1889, {0, {0}}, 0, 0 }, + { "dampr34", 1890, {0, {0}}, 0, 0 }, + { "dampr35", 1891, {0, {0}}, 0, 0 }, + { "dampr36", 1892, {0, {0}}, 0, 0 }, + { "dampr37", 1893, {0, {0}}, 0, 0 }, + { "dampr38", 1894, {0, {0}}, 0, 0 }, + { "dampr39", 1895, {0, {0}}, 0, 0 }, + { "dampr40", 1896, {0, {0}}, 0, 0 }, + { "dampr41", 1897, {0, {0}}, 0, 0 }, + { "dampr42", 1898, {0, {0}}, 0, 0 }, + { "dampr43", 1899, {0, {0}}, 0, 0 }, + { "dampr44", 1900, {0, {0}}, 0, 0 }, + { "dampr45", 1901, {0, {0}}, 0, 0 }, + { "dampr46", 1902, {0, {0}}, 0, 0 }, + { "dampr47", 1903, {0, {0}}, 0, 0 }, + { "dampr48", 1904, {0, {0}}, 0, 0 }, + { "dampr49", 1905, {0, {0}}, 0, 0 }, + { "dampr50", 1906, {0, {0}}, 0, 0 }, + { "dampr51", 1907, {0, {0}}, 0, 0 }, + { "dampr52", 1908, {0, {0}}, 0, 0 }, + { "dampr53", 1909, {0, {0}}, 0, 0 }, + { "dampr54", 1910, {0, {0}}, 0, 0 }, + { "dampr55", 1911, {0, {0}}, 0, 0 }, + { "dampr56", 1912, {0, {0}}, 0, 0 }, + { "dampr57", 1913, {0, {0}}, 0, 0 }, + { "dampr58", 1914, {0, {0}}, 0, 0 }, + { "dampr59", 1915, {0, {0}}, 0, 0 }, + { "dampr60", 1916, {0, {0}}, 0, 0 }, + { "dampr61", 1917, {0, {0}}, 0, 0 }, + { "dampr62", 1918, {0, {0}}, 0, 0 }, + { "dampr63", 1919, {0, {0}}, 0, 0 }, + { "amcr", 1920, {0, {0}}, 0, 0 }, + { "stbar", 1921, {0, {0}}, 0, 0 }, + { "mmcr", 1922, {0, {0}}, 0, 0 }, + { "dcr", 2048, {0, {0}}, 0, 0 }, + { "brr", 2049, {0, {0}}, 0, 0 }, + { "nmar", 2050, {0, {0}}, 0, 0 }, + { "ibar0", 2052, {0, {0}}, 0, 0 }, + { "ibar1", 2053, {0, {0}}, 0, 0 }, + { "ibar2", 2054, {0, {0}}, 0, 0 }, + { "ibar3", 2055, {0, {0}}, 0, 0 }, + { "dbar0", 2056, {0, {0}}, 0, 0 }, + { "dbar1", 2057, {0, {0}}, 0, 0 }, + { "dbar2", 2058, {0, {0}}, 0, 0 }, + { "dbar3", 2059, {0, {0}}, 0, 0 }, + { "dbdr00", 2060, {0, {0}}, 0, 0 }, + { "dbdr01", 2061, {0, {0}}, 0, 0 }, + { "dbdr02", 2062, {0, {0}}, 0, 0 }, + { "dbdr03", 2063, {0, {0}}, 0, 0 }, + { "dbdr10", 2064, {0, {0}}, 0, 0 }, + { "dbdr11", 2065, {0, {0}}, 0, 0 }, + { "dbdr12", 2066, {0, {0}}, 0, 0 }, + { "dbdr13", 2067, {0, {0}}, 0, 0 }, + { "dbdr20", 2068, {0, {0}}, 0, 0 }, + { "dbdr21", 2069, {0, {0}}, 0, 0 }, + { "dbdr22", 2070, {0, {0}}, 0, 0 }, + { "dbdr23", 2071, {0, {0}}, 0, 0 }, + { "dbdr30", 2072, {0, {0}}, 0, 0 }, + { "dbdr31", 2073, {0, {0}}, 0, 0 }, + { "dbdr32", 2074, {0, {0}}, 0, 0 }, + { "dbdr33", 2075, {0, {0}}, 0, 0 }, + { "dbmr00", 2076, {0, {0}}, 0, 0 }, + { "dbmr01", 2077, {0, {0}}, 0, 0 }, + { "dbmr02", 2078, {0, {0}}, 0, 0 }, + { "dbmr03", 2079, {0, {0}}, 0, 0 }, + { "dbmr10", 2080, {0, {0}}, 0, 0 }, + { "dbmr11", 2081, {0, {0}}, 0, 0 }, + { "dbmr12", 2082, {0, {0}}, 0, 0 }, + { "dbmr13", 2083, {0, {0}}, 0, 0 }, + { "dbmr20", 2084, {0, {0}}, 0, 0 }, + { "dbmr21", 2085, {0, {0}}, 0, 0 }, + { "dbmr22", 2086, {0, {0}}, 0, 0 }, + { "dbmr23", 2087, {0, {0}}, 0, 0 }, + { "dbmr30", 2088, {0, {0}}, 0, 0 }, + { "dbmr31", 2089, {0, {0}}, 0, 0 }, + { "dbmr32", 2090, {0, {0}}, 0, 0 }, + { "dbmr33", 2091, {0, {0}}, 0, 0 }, + { "cpcfr", 2092, {0, {0}}, 0, 0 }, + { "cpcr", 2093, {0, {0}}, 0, 0 }, + { "cpsr", 2094, {0, {0}}, 0, 0 }, + { "cpesr0", 2096, {0, {0}}, 0, 0 }, + { "cpesr1", 2097, {0, {0}}, 0, 0 }, + { "cpemr0", 2098, {0, {0}}, 0, 0 }, + { "cpemr1", 2099, {0, {0}}, 0, 0 }, + { "ihsr8", 3848, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_spr_names = +{ + & frv_cgen_opval_spr_names_entries[0], + 1005, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_accg_names_entries[] = +{ + { "accg0", 0, {0, {0}}, 0, 0 }, + { "accg1", 1, {0, {0}}, 0, 0 }, + { "accg2", 2, {0, {0}}, 0, 0 }, + { "accg3", 3, {0, {0}}, 0, 0 }, + { "accg4", 4, {0, {0}}, 0, 0 }, + { "accg5", 5, {0, {0}}, 0, 0 }, + { "accg6", 6, {0, {0}}, 0, 0 }, + { "accg7", 7, {0, {0}}, 0, 0 }, + { "accg8", 8, {0, {0}}, 0, 0 }, + { "accg9", 9, {0, {0}}, 0, 0 }, + { "accg10", 10, {0, {0}}, 0, 0 }, + { "accg11", 11, {0, {0}}, 0, 0 }, + { "accg12", 12, {0, {0}}, 0, 0 }, + { "accg13", 13, {0, {0}}, 0, 0 }, + { "accg14", 14, {0, {0}}, 0, 0 }, + { "accg15", 15, {0, {0}}, 0, 0 }, + { "accg16", 16, {0, {0}}, 0, 0 }, + { "accg17", 17, {0, {0}}, 0, 0 }, + { "accg18", 18, {0, {0}}, 0, 0 }, + { "accg19", 19, {0, {0}}, 0, 0 }, + { "accg20", 20, {0, {0}}, 0, 0 }, + { "accg21", 21, {0, {0}}, 0, 0 }, + { "accg22", 22, {0, {0}}, 0, 0 }, + { "accg23", 23, {0, {0}}, 0, 0 }, + { "accg24", 24, {0, {0}}, 0, 0 }, + { "accg25", 25, {0, {0}}, 0, 0 }, + { "accg26", 26, {0, {0}}, 0, 0 }, + { "accg27", 27, {0, {0}}, 0, 0 }, + { "accg28", 28, {0, {0}}, 0, 0 }, + { "accg29", 29, {0, {0}}, 0, 0 }, + { "accg30", 30, {0, {0}}, 0, 0 }, + { "accg31", 31, {0, {0}}, 0, 0 }, + { "accg32", 32, {0, {0}}, 0, 0 }, + { "accg33", 33, {0, {0}}, 0, 0 }, + { "accg34", 34, {0, {0}}, 0, 0 }, + { "accg35", 35, {0, {0}}, 0, 0 }, + { "accg36", 36, {0, {0}}, 0, 0 }, + { "accg37", 37, {0, {0}}, 0, 0 }, + { "accg38", 38, {0, {0}}, 0, 0 }, + { "accg39", 39, {0, {0}}, 0, 0 }, + { "accg40", 40, {0, {0}}, 0, 0 }, + { "accg41", 41, {0, {0}}, 0, 0 }, + { "accg42", 42, {0, {0}}, 0, 0 }, + { "accg43", 43, {0, {0}}, 0, 0 }, + { "accg44", 44, {0, {0}}, 0, 0 }, + { "accg45", 45, {0, {0}}, 0, 0 }, + { "accg46", 46, {0, {0}}, 0, 0 }, + { "accg47", 47, {0, {0}}, 0, 0 }, + { "accg48", 48, {0, {0}}, 0, 0 }, + { "accg49", 49, {0, {0}}, 0, 0 }, + { "accg50", 50, {0, {0}}, 0, 0 }, + { "accg51", 51, {0, {0}}, 0, 0 }, + { "accg52", 52, {0, {0}}, 0, 0 }, + { "accg53", 53, {0, {0}}, 0, 0 }, + { "accg54", 54, {0, {0}}, 0, 0 }, + { "accg55", 55, {0, {0}}, 0, 0 }, + { "accg56", 56, {0, {0}}, 0, 0 }, + { "accg57", 57, {0, {0}}, 0, 0 }, + { "accg58", 58, {0, {0}}, 0, 0 }, + { "accg59", 59, {0, {0}}, 0, 0 }, + { "accg60", 60, {0, {0}}, 0, 0 }, + { "accg61", 61, {0, {0}}, 0, 0 }, + { "accg62", 62, {0, {0}}, 0, 0 }, + { "accg63", 63, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_accg_names = +{ + & frv_cgen_opval_accg_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_acc_names_entries[] = +{ + { "acc0", 0, {0, {0}}, 0, 0 }, + { "acc1", 1, {0, {0}}, 0, 0 }, + { "acc2", 2, {0, {0}}, 0, 0 }, + { "acc3", 3, {0, {0}}, 0, 0 }, + { "acc4", 4, {0, {0}}, 0, 0 }, + { "acc5", 5, {0, {0}}, 0, 0 }, + { "acc6", 6, {0, {0}}, 0, 0 }, + { "acc7", 7, {0, {0}}, 0, 0 }, + { "acc8", 8, {0, {0}}, 0, 0 }, + { "acc9", 9, {0, {0}}, 0, 0 }, + { "acc10", 10, {0, {0}}, 0, 0 }, + { "acc11", 11, {0, {0}}, 0, 0 }, + { "acc12", 12, {0, {0}}, 0, 0 }, + { "acc13", 13, {0, {0}}, 0, 0 }, + { "acc14", 14, {0, {0}}, 0, 0 }, + { "acc15", 15, {0, {0}}, 0, 0 }, + { "acc16", 16, {0, {0}}, 0, 0 }, + { "acc17", 17, {0, {0}}, 0, 0 }, + { "acc18", 18, {0, {0}}, 0, 0 }, + { "acc19", 19, {0, {0}}, 0, 0 }, + { "acc20", 20, {0, {0}}, 0, 0 }, + { "acc21", 21, {0, {0}}, 0, 0 }, + { "acc22", 22, {0, {0}}, 0, 0 }, + { "acc23", 23, {0, {0}}, 0, 0 }, + { "acc24", 24, {0, {0}}, 0, 0 }, + { "acc25", 25, {0, {0}}, 0, 0 }, + { "acc26", 26, {0, {0}}, 0, 0 }, + { "acc27", 27, {0, {0}}, 0, 0 }, + { "acc28", 28, {0, {0}}, 0, 0 }, + { "acc29", 29, {0, {0}}, 0, 0 }, + { "acc30", 30, {0, {0}}, 0, 0 }, + { "acc31", 31, {0, {0}}, 0, 0 }, + { "acc32", 32, {0, {0}}, 0, 0 }, + { "acc33", 33, {0, {0}}, 0, 0 }, + { "acc34", 34, {0, {0}}, 0, 0 }, + { "acc35", 35, {0, {0}}, 0, 0 }, + { "acc36", 36, {0, {0}}, 0, 0 }, + { "acc37", 37, {0, {0}}, 0, 0 }, + { "acc38", 38, {0, {0}}, 0, 0 }, + { "acc39", 39, {0, {0}}, 0, 0 }, + { "acc40", 40, {0, {0}}, 0, 0 }, + { "acc41", 41, {0, {0}}, 0, 0 }, + { "acc42", 42, {0, {0}}, 0, 0 }, + { "acc43", 43, {0, {0}}, 0, 0 }, + { "acc44", 44, {0, {0}}, 0, 0 }, + { "acc45", 45, {0, {0}}, 0, 0 }, + { "acc46", 46, {0, {0}}, 0, 0 }, + { "acc47", 47, {0, {0}}, 0, 0 }, + { "acc48", 48, {0, {0}}, 0, 0 }, + { "acc49", 49, {0, {0}}, 0, 0 }, + { "acc50", 50, {0, {0}}, 0, 0 }, + { "acc51", 51, {0, {0}}, 0, 0 }, + { "acc52", 52, {0, {0}}, 0, 0 }, + { "acc53", 53, {0, {0}}, 0, 0 }, + { "acc54", 54, {0, {0}}, 0, 0 }, + { "acc55", 55, {0, {0}}, 0, 0 }, + { "acc56", 56, {0, {0}}, 0, 0 }, + { "acc57", 57, {0, {0}}, 0, 0 }, + { "acc58", 58, {0, {0}}, 0, 0 }, + { "acc59", 59, {0, {0}}, 0, 0 }, + { "acc60", 60, {0, {0}}, 0, 0 }, + { "acc61", 61, {0, {0}}, 0, 0 }, + { "acc62", 62, {0, {0}}, 0, 0 }, + { "acc63", 63, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_acc_names = +{ + & frv_cgen_opval_acc_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] = +{ + { "icc0", 0, {0, {0}}, 0, 0 }, + { "icc1", 1, {0, {0}}, 0, 0 }, + { "icc2", 2, {0, {0}}, 0, 0 }, + { "icc3", 3, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_iccr_names = +{ + & frv_cgen_opval_iccr_names_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_fccr_names_entries[] = +{ + { "fcc0", 0, {0, {0}}, 0, 0 }, + { "fcc1", 1, {0, {0}}, 0, 0 }, + { "fcc2", 2, {0, {0}}, 0, 0 }, + { "fcc3", 3, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_fccr_names = +{ + & frv_cgen_opval_fccr_names_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_cccr_names_entries[] = +{ + { "cc0", 0, {0, {0}}, 0, 0 }, + { "cc1", 1, {0, {0}}, 0, 0 }, + { "cc2", 2, {0, {0}}, 0, 0 }, + { "cc3", 3, {0, {0}}, 0, 0 }, + { "cc4", 4, {0, {0}}, 0, 0 }, + { "cc5", 5, {0, {0}}, 0, 0 }, + { "cc6", 6, {0, {0}}, 0, 0 }, + { "cc7", 7, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_cccr_names = +{ + & frv_cgen_opval_cccr_names_entries[0], + 8, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_pack_entries[] = +{ + { "", 1, {0, {0}}, 0, 0 }, + { ".p", 0, {0, {0}}, 0, 0 }, + { ".P", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_h_pack = +{ + & frv_cgen_opval_h_pack_entries[0], + 3, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_taken_entries[] = +{ + { "", 2, {0, {0}}, 0, 0 }, + { "", 0, {0, {0}}, 0, 0 }, + { "", 1, {0, {0}}, 0, 0 }, + { "", 3, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_h_hint_taken = +{ + & frv_cgen_opval_h_hint_taken_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_not_taken_entries[] = +{ + { "", 0, {0, {0}}, 0, 0 }, + { "", 1, {0, {0}}, 0, 0 }, + { "", 2, {0, {0}}, 0, 0 }, + { "", 3, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken = +{ + & frv_cgen_opval_h_hint_not_taken_entries[0], + 4, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_HW_##a) +#else +#define A(a) (1 << CGEN_HW_/**/a) +#endif + +const CGEN_HW_ENTRY frv_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of frv_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & frv_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of frv_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (cd) + CGEN_CPU_TABLE *cd; +{ + cd->ifld_table = & frv_cgen_ifld_table[0]; +} + +/* Subroutine of frv_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & frv_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = + (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of frv_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + const CGEN_IBASE *ib = & frv_cgen_insn_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of frv_cgen_cpu_open to rebuild the tables. */ + +static void +frv_cgen_rebuild_tables (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + unsigned int isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (((1 << i) & isas) != 0) + { + const CGEN_ISA *isa = & frv_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* this is ok */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* this is ok */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & frv_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "frv_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +CGEN_CPU_DESC +frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + unsigned int isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (frv_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "frv_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* mach unspecified means "all" */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* base mach is always selected */ + machs |= 1; + /* isa unspecified means "all" */ + if (isas == 0) + isas = (1 << MAX_ISAS) - 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "frv_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = isas; + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = frv_cgen_rebuild_tables; + frv_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to frv_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +frv_cgen_cpu_open_1 (mach_name, endian) + const char *mach_name; + enum cgen_endian endian; +{ + return frv_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +frv_cgen_cpu_close (cd) + CGEN_CPU_DESC cd; +{ + unsigned int i; + CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX ((insns))) + regfree(CGEN_INSN_RX (insns)); + } + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX (insns)) + regfree(CGEN_INSN_RX (insns)); + } + } + + + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff -uprN binutils-2.12.90.0.11/opcodes/frv-desc.h binutils-2.12.90.0.12/opcodes/frv-desc.h --- binutils-2.12.90.0.11/opcodes/frv-desc.h Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/opcodes/frv-desc.h Tue Jun 18 21:41:59 2002 @@ -0,0 +1,748 @@ +/* CPU data header for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef FRV_CPU_H +#define FRV_CPU_H + +#define CGEN_ARCH frv + +/* Given symbol S, return frv_cgen_. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CGEN_SYM(s) frv##_cgen_##s +#else +#define CGEN_SYM(s) frv/**/_cgen_/**/s +#endif + + +/* Selected cpu families. */ +#define HAVE_CPU_FRVBF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 4 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10 + +/* Enums. */ + +/* Enum declaration for insn op enums. */ +typedef enum insn_op { + OP_00, OP_01, OP_02, OP_03 + , OP_04, OP_05, OP_06, OP_07 + , OP_08, OP_09, OP_0A, OP_0B + , OP_0C, OP_0D, OP_0E, OP_0F + , OP_10, OP_11, OP_12, OP_13 + , OP_14, OP_15, OP_16, OP_17 + , OP_18, OP_19, OP_1A, OP_1B + , OP_1C, OP_1D, OP_1E, OP_1F + , OP_20, OP_21, OP_22, OP_23 + , OP_24, OP_25, OP_26, OP_27 + , OP_28, OP_29, OP_2A, OP_2B + , OP_2C, OP_2D, OP_2E, OP_2F + , OP_30, OP_31, OP_32, OP_33 + , OP_34, OP_35, OP_36, OP_37 + , OP_38, OP_39, OP_3A, OP_3B + , OP_3C, OP_3D, OP_3E, OP_3F + , OP_40, OP_41, OP_42, OP_43 + , OP_44, OP_45, OP_46, OP_47 + , OP_48, OP_49, OP_4A, OP_4B + , OP_4C, OP_4D, OP_4E, OP_4F + , OP_50, OP_51, OP_52, OP_53 + , OP_54, OP_55, OP_56, OP_57 + , OP_58, OP_59, OP_5A, OP_5B + , OP_5C, OP_5D, OP_5E, OP_5F + , OP_60, OP_61, OP_62, OP_63 + , OP_64, OP_65, OP_66, OP_67 + , OP_68, OP_69, OP_6A, OP_6B + , OP_6C, OP_6D, OP_6E, OP_6F + , OP_70, OP_71, OP_72, OP_73 + , OP_74, OP_75, OP_76, OP_77 + , OP_78, OP_79, OP_7A, OP_7B + , OP_7C, OP_7D, OP_7E, OP_7F +} INSN_OP; + +/* Enum declaration for insn ope enums. */ +typedef enum insn_ope1 { + OPE1_00, OPE1_01, OPE1_02, OPE1_03 + , OPE1_04, OPE1_05, OPE1_06, OPE1_07 + , OPE1_08, OPE1_09, OPE1_0A, OPE1_0B + , OPE1_0C, OPE1_0D, OPE1_0E, OPE1_0F + , OPE1_10, OPE1_11, OPE1_12, OPE1_13 + , OPE1_14, OPE1_15, OPE1_16, OPE1_17 + , OPE1_18, OPE1_19, OPE1_1A, OPE1_1B + , OPE1_1C, OPE1_1D, OPE1_1E, OPE1_1F + , OPE1_20, OPE1_21, OPE1_22, OPE1_23 + , OPE1_24, OPE1_25, OPE1_26, OPE1_27 + , OPE1_28, OPE1_29, OPE1_2A, OPE1_2B + , OPE1_2C, OPE1_2D, OPE1_2E, OPE1_2F + , OPE1_30, OPE1_31, OPE1_32, OPE1_33 + , OPE1_34, OPE1_35, OPE1_36, OPE1_37 + , OPE1_38, OPE1_39, OPE1_3A, OPE1_3B + , OPE1_3C, OPE1_3D, OPE1_3E, OPE1_3F +} INSN_OPE1; + +/* Enum declaration for insn ope enums. */ +typedef enum insn_ope2 { + OPE2_00, OPE2_01, OPE2_02, OPE2_03 + , OPE2_04, OPE2_05, OPE2_06, OPE2_07 + , OPE2_08, OPE2_09, OPE2_0A, OPE2_0B + , OPE2_0C, OPE2_0D, OPE2_0E, OPE2_0F +} INSN_OPE2; + +/* Enum declaration for insn ope enums. */ +typedef enum insn_ope3 { + OPE3_00, OPE3_01, OPE3_02, OPE3_03 + , OPE3_04, OPE3_05, OPE3_06, OPE3_07 +} INSN_OPE3; + +/* Enum declaration for insn ope enums. */ +typedef enum insn_ope4 { + OPE4_0, OPE4_1, OPE4_2, OPE4_3 +} INSN_OPE4; + +/* Enum declaration for integer branch cond enums. */ +typedef enum int_cc { + ICC_NEV, ICC_C, ICC_V, ICC_LT + , ICC_EQ, ICC_LS, ICC_N, ICC_LE + , ICC_RA, ICC_NC, ICC_NV, ICC_GE + , ICC_NE, ICC_HI, ICC_P, ICC_GT +} INT_CC; + +/* Enum declaration for float branch cond enums. */ +typedef enum flt_cc { + FCC_NEV, FCC_U, FCC_GT, FCC_UG + , FCC_LT, FCC_UL, FCC_LG, FCC_NE + , FCC_EQ, FCC_UE, FCC_GE, FCC_UGE + , FCC_LE, FCC_ULE, FCC_O, FCC_RA +} FLT_CC; + +/* Enum declaration for . */ +typedef enum gr_names { + H_GR_SP = 1, H_GR_FP = 2, H_GR_GR0 = 0, H_GR_GR1 = 1 + , H_GR_GR2 = 2, H_GR_GR3 = 3, H_GR_GR4 = 4, H_GR_GR5 = 5 + , H_GR_GR6 = 6, H_GR_GR7 = 7, H_GR_GR8 = 8, H_GR_GR9 = 9 + , H_GR_GR10 = 10, H_GR_GR11 = 11, H_GR_GR12 = 12, H_GR_GR13 = 13 + , H_GR_GR14 = 14, H_GR_GR15 = 15, H_GR_GR16 = 16, H_GR_GR17 = 17 + , H_GR_GR18 = 18, H_GR_GR19 = 19, H_GR_GR20 = 20, H_GR_GR21 = 21 + , H_GR_GR22 = 22, H_GR_GR23 = 23, H_GR_GR24 = 24, H_GR_GR25 = 25 + , H_GR_GR26 = 26, H_GR_GR27 = 27, H_GR_GR28 = 28, H_GR_GR29 = 29 + , H_GR_GR30 = 30, H_GR_GR31 = 31, H_GR_GR32 = 32, H_GR_GR33 = 33 + , H_GR_GR34 = 34, H_GR_GR35 = 35, H_GR_GR36 = 36, H_GR_GR37 = 37 + , H_GR_GR38 = 38, H_GR_GR39 = 39, H_GR_GR40 = 40, H_GR_GR41 = 41 + , H_GR_GR42 = 42, H_GR_GR43 = 43, H_GR_GR44 = 44, H_GR_GR45 = 45 + , H_GR_GR46 = 46, H_GR_GR47 = 47, H_GR_GR48 = 48, H_GR_GR49 = 49 + , H_GR_GR50 = 50, H_GR_GR51 = 51, H_GR_GR52 = 52, H_GR_GR53 = 53 + , H_GR_GR54 = 54, H_GR_GR55 = 55, H_GR_GR56 = 56, H_GR_GR57 = 57 + , H_GR_GR58 = 58, H_GR_GR59 = 59, H_GR_GR60 = 60, H_GR_GR61 = 61 + , H_GR_GR62 = 62, H_GR_GR63 = 63 +} GR_NAMES; + +/* Enum declaration for . */ +typedef enum fr_names { + H_FR_FR0, H_FR_FR1, H_FR_FR2, H_FR_FR3 + , H_FR_FR4, H_FR_FR5, H_FR_FR6, H_FR_FR7 + , H_FR_FR8, H_FR_FR9, H_FR_FR10, H_FR_FR11 + , H_FR_FR12, H_FR_FR13, H_FR_FR14, H_FR_FR15 + , H_FR_FR16, H_FR_FR17, H_FR_FR18, H_FR_FR19 + , H_FR_FR20, H_FR_FR21, H_FR_FR22, H_FR_FR23 + , H_FR_FR24, H_FR_FR25, H_FR_FR26, H_FR_FR27 + , H_FR_FR28, H_FR_FR29, H_FR_FR30, H_FR_FR31 + , H_FR_FR32, H_FR_FR33, H_FR_FR34, H_FR_FR35 + , H_FR_FR36, H_FR_FR37, H_FR_FR38, H_FR_FR39 + , H_FR_FR40, H_FR_FR41, H_FR_FR42, H_FR_FR43 + , H_FR_FR44, H_FR_FR45, H_FR_FR46, H_FR_FR47 + , H_FR_FR48, H_FR_FR49, H_FR_FR50, H_FR_FR51 + , H_FR_FR52, H_FR_FR53, H_FR_FR54, H_FR_FR55 + , H_FR_FR56, H_FR_FR57, H_FR_FR58, H_FR_FR59 + , H_FR_FR60, H_FR_FR61, H_FR_FR62, H_FR_FR63 +} FR_NAMES; + +/* Enum declaration for . */ +typedef enum cpr_names { + H_CPR_CPR0, H_CPR_CPR1, H_CPR_CPR2, H_CPR_CPR3 + , H_CPR_CPR4, H_CPR_CPR5, H_CPR_CPR6, H_CPR_CPR7 + , H_CPR_CPR8, H_CPR_CPR9, H_CPR_CPR10, H_CPR_CPR11 + , H_CPR_CPR12, H_CPR_CPR13, H_CPR_CPR14, H_CPR_CPR15 + , H_CPR_CPR16, H_CPR_CPR17, H_CPR_CPR18, H_CPR_CPR19 + , H_CPR_CPR20, H_CPR_CPR21, H_CPR_CPR22, H_CPR_CPR23 + , H_CPR_CPR24, H_CPR_CPR25, H_CPR_CPR26, H_CPR_CPR27 + , H_CPR_CPR28, H_CPR_CPR29, H_CPR_CPR30, H_CPR_CPR31 + , H_CPR_CPR32, H_CPR_CPR33, H_CPR_CPR34, H_CPR_CPR35 + , H_CPR_CPR36, H_CPR_CPR37, H_CPR_CPR38, H_CPR_CPR39 + , H_CPR_CPR40, H_CPR_CPR41, H_CPR_CPR42, H_CPR_CPR43 + , H_CPR_CPR44, H_CPR_CPR45, H_CPR_CPR46, H_CPR_CPR47 + , H_CPR_CPR48, H_CPR_CPR49, H_CPR_CPR50, H_CPR_CPR51 + , H_CPR_CPR52, H_CPR_CPR53, H_CPR_CPR54, H_CPR_CPR55 + , H_CPR_CPR56, H_CPR_CPR57, H_CPR_CPR58, H_CPR_CPR59 + , H_CPR_CPR60, H_CPR_CPR61, H_CPR_CPR62, H_CPR_CPR63 +} CPR_NAMES; + +/* Enum declaration for . */ +typedef enum spr_names { + H_SPR_PSR = 0, H_SPR_PCSR = 1, H_SPR_BPCSR = 2, H_SPR_TBR = 3 + , H_SPR_BPSR = 4, H_SPR_HSR0 = 16, H_SPR_HSR1 = 17, H_SPR_HSR2 = 18 + , H_SPR_HSR3 = 19, H_SPR_HSR4 = 20, H_SPR_HSR5 = 21, H_SPR_HSR6 = 22 + , H_SPR_HSR7 = 23, H_SPR_HSR8 = 24, H_SPR_HSR9 = 25, H_SPR_HSR10 = 26 + , H_SPR_HSR11 = 27, H_SPR_HSR12 = 28, H_SPR_HSR13 = 29, H_SPR_HSR14 = 30 + , H_SPR_HSR15 = 31, H_SPR_HSR16 = 32, H_SPR_HSR17 = 33, H_SPR_HSR18 = 34 + , H_SPR_HSR19 = 35, H_SPR_HSR20 = 36, H_SPR_HSR21 = 37, H_SPR_HSR22 = 38 + , H_SPR_HSR23 = 39, H_SPR_HSR24 = 40, H_SPR_HSR25 = 41, H_SPR_HSR26 = 42 + , H_SPR_HSR27 = 43, H_SPR_HSR28 = 44, H_SPR_HSR29 = 45, H_SPR_HSR30 = 46 + , H_SPR_HSR31 = 47, H_SPR_HSR32 = 48, H_SPR_HSR33 = 49, H_SPR_HSR34 = 50 + , H_SPR_HSR35 = 51, H_SPR_HSR36 = 52, H_SPR_HSR37 = 53, H_SPR_HSR38 = 54 + , H_SPR_HSR39 = 55, H_SPR_HSR40 = 56, H_SPR_HSR41 = 57, H_SPR_HSR42 = 58 + , H_SPR_HSR43 = 59, H_SPR_HSR44 = 60, H_SPR_HSR45 = 61, H_SPR_HSR46 = 62 + , H_SPR_HSR47 = 63, H_SPR_HSR48 = 64, H_SPR_HSR49 = 65, H_SPR_HSR50 = 66 + , H_SPR_HSR51 = 67, H_SPR_HSR52 = 68, H_SPR_HSR53 = 69, H_SPR_HSR54 = 70 + , H_SPR_HSR55 = 71, H_SPR_HSR56 = 72, H_SPR_HSR57 = 73, H_SPR_HSR58 = 74 + , H_SPR_HSR59 = 75, H_SPR_HSR60 = 76, H_SPR_HSR61 = 77, H_SPR_HSR62 = 78 + , H_SPR_HSR63 = 79, H_SPR_CCR = 256, H_SPR_CCCR = 263, H_SPR_LR = 272 + , H_SPR_LCR = 273, H_SPR_ISR = 288, H_SPR_NEEAR0 = 352, H_SPR_NEEAR1 = 353 + , H_SPR_NEEAR2 = 354, H_SPR_NEEAR3 = 355, H_SPR_NEEAR4 = 356, H_SPR_NEEAR5 = 357 + , H_SPR_NEEAR6 = 358, H_SPR_NEEAR7 = 359, H_SPR_NEEAR8 = 360, H_SPR_NEEAR9 = 361 + , H_SPR_NEEAR10 = 362, H_SPR_NEEAR11 = 363, H_SPR_NEEAR12 = 364, H_SPR_NEEAR13 = 365 + , H_SPR_NEEAR14 = 366, H_SPR_NEEAR15 = 367, H_SPR_NEEAR16 = 368, H_SPR_NEEAR17 = 369 + , H_SPR_NEEAR18 = 370, H_SPR_NEEAR19 = 371, H_SPR_NEEAR20 = 372, H_SPR_NEEAR21 = 373 + , H_SPR_NEEAR22 = 374, H_SPR_NEEAR23 = 375, H_SPR_NEEAR24 = 376, H_SPR_NEEAR25 = 377 + , H_SPR_NEEAR26 = 378, H_SPR_NEEAR27 = 379, H_SPR_NEEAR28 = 380, H_SPR_NEEAR29 = 381 + , H_SPR_NEEAR30 = 382, H_SPR_NEEAR31 = 383, H_SPR_NESR0 = 384, H_SPR_NESR1 = 385 + , H_SPR_NESR2 = 386, H_SPR_NESR3 = 387, H_SPR_NESR4 = 388, H_SPR_NESR5 = 389 + , H_SPR_NESR6 = 390, H_SPR_NESR7 = 391, H_SPR_NESR8 = 392, H_SPR_NESR9 = 393 + , H_SPR_NESR10 = 394, H_SPR_NESR11 = 395, H_SPR_NESR12 = 396, H_SPR_NESR13 = 397 + , H_SPR_NESR14 = 398, H_SPR_NESR15 = 399, H_SPR_NESR16 = 400, H_SPR_NESR17 = 401 + , H_SPR_NESR18 = 402, H_SPR_NESR19 = 403, H_SPR_NESR20 = 404, H_SPR_NESR21 = 405 + , H_SPR_NESR22 = 406, H_SPR_NESR23 = 407, H_SPR_NESR24 = 408, H_SPR_NESR25 = 409 + , H_SPR_NESR26 = 410, H_SPR_NESR27 = 411, H_SPR_NESR28 = 412, H_SPR_NESR29 = 413 + , H_SPR_NESR30 = 414, H_SPR_NESR31 = 415, H_SPR_NECR = 416, H_SPR_GNER0 = 432 + , H_SPR_GNER1 = 433, H_SPR_FNER0 = 434, H_SPR_FNER1 = 435, H_SPR_EPCR0 = 512 + , H_SPR_EPCR1 = 513, H_SPR_EPCR2 = 514, H_SPR_EPCR3 = 515, H_SPR_EPCR4 = 516 + , H_SPR_EPCR5 = 517, H_SPR_EPCR6 = 518, H_SPR_EPCR7 = 519, H_SPR_EPCR8 = 520 + , H_SPR_EPCR9 = 521, H_SPR_EPCR10 = 522, H_SPR_EPCR11 = 523, H_SPR_EPCR12 = 524 + , H_SPR_EPCR13 = 525, H_SPR_EPCR14 = 526, H_SPR_EPCR15 = 527, H_SPR_EPCR16 = 528 + , H_SPR_EPCR17 = 529, H_SPR_EPCR18 = 530, H_SPR_EPCR19 = 531, H_SPR_EPCR20 = 532 + , H_SPR_EPCR21 = 533, H_SPR_EPCR22 = 534, H_SPR_EPCR23 = 535, H_SPR_EPCR24 = 536 + , H_SPR_EPCR25 = 537, H_SPR_EPCR26 = 538, H_SPR_EPCR27 = 539, H_SPR_EPCR28 = 540 + , H_SPR_EPCR29 = 541, H_SPR_EPCR30 = 542, H_SPR_EPCR31 = 543, H_SPR_EPCR32 = 544 + , H_SPR_EPCR33 = 545, H_SPR_EPCR34 = 546, H_SPR_EPCR35 = 547, H_SPR_EPCR36 = 548 + , H_SPR_EPCR37 = 549, H_SPR_EPCR38 = 550, H_SPR_EPCR39 = 551, H_SPR_EPCR40 = 552 + , H_SPR_EPCR41 = 553, H_SPR_EPCR42 = 554, H_SPR_EPCR43 = 555, H_SPR_EPCR44 = 556 + , H_SPR_EPCR45 = 557, H_SPR_EPCR46 = 558, H_SPR_EPCR47 = 559, H_SPR_EPCR48 = 560 + , H_SPR_EPCR49 = 561, H_SPR_EPCR50 = 562, H_SPR_EPCR51 = 563, H_SPR_EPCR52 = 564 + , H_SPR_EPCR53 = 565, H_SPR_EPCR54 = 566, H_SPR_EPCR55 = 567, H_SPR_EPCR56 = 568 + , H_SPR_EPCR57 = 569, H_SPR_EPCR58 = 570, H_SPR_EPCR59 = 571, H_SPR_EPCR60 = 572 + , H_SPR_EPCR61 = 573, H_SPR_EPCR62 = 574, H_SPR_EPCR63 = 575, H_SPR_ESR0 = 576 + , H_SPR_ESR1 = 577, H_SPR_ESR2 = 578, H_SPR_ESR3 = 579, H_SPR_ESR4 = 580 + , H_SPR_ESR5 = 581, H_SPR_ESR6 = 582, H_SPR_ESR7 = 583, H_SPR_ESR8 = 584 + , H_SPR_ESR9 = 585, H_SPR_ESR10 = 586, H_SPR_ESR11 = 587, H_SPR_ESR12 = 588 + , H_SPR_ESR13 = 589, H_SPR_ESR14 = 590, H_SPR_ESR15 = 591, H_SPR_ESR16 = 592 + , H_SPR_ESR17 = 593, H_SPR_ESR18 = 594, H_SPR_ESR19 = 595, H_SPR_ESR20 = 596 + , H_SPR_ESR21 = 597, H_SPR_ESR22 = 598, H_SPR_ESR23 = 599, H_SPR_ESR24 = 600 + , H_SPR_ESR25 = 601, H_SPR_ESR26 = 602, H_SPR_ESR27 = 603, H_SPR_ESR28 = 604 + , H_SPR_ESR29 = 605, H_SPR_ESR30 = 606, H_SPR_ESR31 = 607, H_SPR_ESR32 = 608 + , H_SPR_ESR33 = 609, H_SPR_ESR34 = 610, H_SPR_ESR35 = 611, H_SPR_ESR36 = 612 + , H_SPR_ESR37 = 613, H_SPR_ESR38 = 614, H_SPR_ESR39 = 615, H_SPR_ESR40 = 616 + , H_SPR_ESR41 = 617, H_SPR_ESR42 = 618, H_SPR_ESR43 = 619, H_SPR_ESR44 = 620 + , H_SPR_ESR45 = 621, H_SPR_ESR46 = 622, H_SPR_ESR47 = 623, H_SPR_ESR48 = 624 + , H_SPR_ESR49 = 625, H_SPR_ESR50 = 626, H_SPR_ESR51 = 627, H_SPR_ESR52 = 628 + , H_SPR_ESR53 = 629, H_SPR_ESR54 = 630, H_SPR_ESR55 = 631, H_SPR_ESR56 = 632 + , H_SPR_ESR57 = 633, H_SPR_ESR58 = 634, H_SPR_ESR59 = 635, H_SPR_ESR60 = 636 + , H_SPR_ESR61 = 637, H_SPR_ESR62 = 638, H_SPR_ESR63 = 639, H_SPR_EIR0 = 640 + , H_SPR_EIR1 = 641, H_SPR_EIR2 = 642, H_SPR_EIR3 = 643, H_SPR_EIR4 = 644 + , H_SPR_EIR5 = 645, H_SPR_EIR6 = 646, H_SPR_EIR7 = 647, H_SPR_EIR8 = 648 + , H_SPR_EIR9 = 649, H_SPR_EIR10 = 650, H_SPR_EIR11 = 651, H_SPR_EIR12 = 652 + , H_SPR_EIR13 = 653, H_SPR_EIR14 = 654, H_SPR_EIR15 = 655, H_SPR_EIR16 = 656 + , H_SPR_EIR17 = 657, H_SPR_EIR18 = 658, H_SPR_EIR19 = 659, H_SPR_EIR20 = 660 + , H_SPR_EIR21 = 661, H_SPR_EIR22 = 662, H_SPR_EIR23 = 663, H_SPR_EIR24 = 664 + , H_SPR_EIR25 = 665, H_SPR_EIR26 = 666, H_SPR_EIR27 = 667, H_SPR_EIR28 = 668 + , H_SPR_EIR29 = 669, H_SPR_EIR30 = 670, H_SPR_EIR31 = 671, H_SPR_ESFR0 = 672 + , H_SPR_ESFR1 = 673, H_SPR_SR0 = 768, H_SPR_SR1 = 769, H_SPR_SR2 = 770 + , H_SPR_SR3 = 771, H_SPR_FSR0 = 1024, H_SPR_FSR1 = 1025, H_SPR_FSR2 = 1026 + , H_SPR_FSR3 = 1027, H_SPR_FSR4 = 1028, H_SPR_FSR5 = 1029, H_SPR_FSR6 = 1030 + , H_SPR_FSR7 = 1031, H_SPR_FSR8 = 1032, H_SPR_FSR9 = 1033, H_SPR_FSR10 = 1034 + , H_SPR_FSR11 = 1035, H_SPR_FSR12 = 1036, H_SPR_FSR13 = 1037, H_SPR_FSR14 = 1038 + , H_SPR_FSR15 = 1039, H_SPR_FSR16 = 1040, H_SPR_FSR17 = 1041, H_SPR_FSR18 = 1042 + , H_SPR_FSR19 = 1043, H_SPR_FSR20 = 1044, H_SPR_FSR21 = 1045, H_SPR_FSR22 = 1046 + , H_SPR_FSR23 = 1047, H_SPR_FSR24 = 1048, H_SPR_FSR25 = 1049, H_SPR_FSR26 = 1050 + , H_SPR_FSR27 = 1051, H_SPR_FSR28 = 1052, H_SPR_FSR29 = 1053, H_SPR_FSR30 = 1054 + , H_SPR_FSR31 = 1055, H_SPR_FSR32 = 1056, H_SPR_FSR33 = 1057, H_SPR_FSR34 = 1058 + , H_SPR_FSR35 = 1059, H_SPR_FSR36 = 1060, H_SPR_FSR37 = 1061, H_SPR_FSR38 = 1062 + , H_SPR_FSR39 = 1063, H_SPR_FSR40 = 1064, H_SPR_FSR41 = 1065, H_SPR_FSR42 = 1066 + , H_SPR_FSR43 = 1067, H_SPR_FSR44 = 1068, H_SPR_FSR45 = 1069, H_SPR_FSR46 = 1070 + , H_SPR_FSR47 = 1071, H_SPR_FSR48 = 1072, H_SPR_FSR49 = 1073, H_SPR_FSR50 = 1074 + , H_SPR_FSR51 = 1075, H_SPR_FSR52 = 1076, H_SPR_FSR53 = 1077, H_SPR_FSR54 = 1078 + , H_SPR_FSR55 = 1079, H_SPR_FSR56 = 1080, H_SPR_FSR57 = 1081, H_SPR_FSR58 = 1082 + , H_SPR_FSR59 = 1083, H_SPR_FSR60 = 1084, H_SPR_FSR61 = 1085, H_SPR_FSR62 = 1086 + , H_SPR_FSR63 = 1087, H_SPR_FQOP0 = 1088, H_SPR_FQOP1 = 1090, H_SPR_FQOP2 = 1092 + , H_SPR_FQOP3 = 1094, H_SPR_FQOP4 = 1096, H_SPR_FQOP5 = 1098, H_SPR_FQOP6 = 1100 + , H_SPR_FQOP7 = 1102, H_SPR_FQOP8 = 1104, H_SPR_FQOP9 = 1106, H_SPR_FQOP10 = 1108 + , H_SPR_FQOP11 = 1110, H_SPR_FQOP12 = 1112, H_SPR_FQOP13 = 1114, H_SPR_FQOP14 = 1116 + , H_SPR_FQOP15 = 1118, H_SPR_FQOP16 = 1120, H_SPR_FQOP17 = 1122, H_SPR_FQOP18 = 1124 + , H_SPR_FQOP19 = 1126, H_SPR_FQOP20 = 1128, H_SPR_FQOP21 = 1130, H_SPR_FQOP22 = 1132 + , H_SPR_FQOP23 = 1134, H_SPR_FQOP24 = 1136, H_SPR_FQOP25 = 1138, H_SPR_FQOP26 = 1140 + , H_SPR_FQOP27 = 1142, H_SPR_FQOP28 = 1144, H_SPR_FQOP29 = 1146, H_SPR_FQOP30 = 1148 + , H_SPR_FQOP31 = 1150, H_SPR_FQST0 = 1089, H_SPR_FQST1 = 1091, H_SPR_FQST2 = 1093 + , H_SPR_FQST3 = 1095, H_SPR_FQST4 = 1097, H_SPR_FQST5 = 1099, H_SPR_FQST6 = 1101 + , H_SPR_FQST7 = 1103, H_SPR_FQST8 = 1105, H_SPR_FQST9 = 1107, H_SPR_FQST10 = 1109 + , H_SPR_FQST11 = 1111, H_SPR_FQST12 = 1113, H_SPR_FQST13 = 1115, H_SPR_FQST14 = 1117 + , H_SPR_FQST15 = 1119, H_SPR_FQST16 = 1121, H_SPR_FQST17 = 1123, H_SPR_FQST18 = 1125 + , H_SPR_FQST19 = 1127, H_SPR_FQST20 = 1129, H_SPR_FQST21 = 1131, H_SPR_FQST22 = 1133 + , H_SPR_FQST23 = 1135, H_SPR_FQST24 = 1137, H_SPR_FQST25 = 1139, H_SPR_FQST26 = 1141 + , H_SPR_FQST27 = 1143, H_SPR_FQST28 = 1145, H_SPR_FQST29 = 1147, H_SPR_FQST30 = 1149 + , H_SPR_FQST31 = 1151, H_SPR_MCILR0 = 1272, H_SPR_MCILR1 = 1273, H_SPR_MSR0 = 1280 + , H_SPR_MSR1 = 1281, H_SPR_MSR2 = 1282, H_SPR_MSR3 = 1283, H_SPR_MSR4 = 1284 + , H_SPR_MSR5 = 1285, H_SPR_MSR6 = 1286, H_SPR_MSR7 = 1287, H_SPR_MSR8 = 1288 + , H_SPR_MSR9 = 1289, H_SPR_MSR10 = 1290, H_SPR_MSR11 = 1291, H_SPR_MSR12 = 1292 + , H_SPR_MSR13 = 1293, H_SPR_MSR14 = 1294, H_SPR_MSR15 = 1295, H_SPR_MSR16 = 1296 + , H_SPR_MSR17 = 1297, H_SPR_MSR18 = 1298, H_SPR_MSR19 = 1299, H_SPR_MSR20 = 1300 + , H_SPR_MSR21 = 1301, H_SPR_MSR22 = 1302, H_SPR_MSR23 = 1303, H_SPR_MSR24 = 1304 + , H_SPR_MSR25 = 1305, H_SPR_MSR26 = 1306, H_SPR_MSR27 = 1307, H_SPR_MSR28 = 1308 + , H_SPR_MSR29 = 1309, H_SPR_MSR30 = 1310, H_SPR_MSR31 = 1311, H_SPR_MSR32 = 1312 + , H_SPR_MSR33 = 1313, H_SPR_MSR34 = 1314, H_SPR_MSR35 = 1315, H_SPR_MSR36 = 1316 + , H_SPR_MSR37 = 1317, H_SPR_MSR38 = 1318, H_SPR_MSR39 = 1319, H_SPR_MSR40 = 1320 + , H_SPR_MSR41 = 1321, H_SPR_MSR42 = 1322, H_SPR_MSR43 = 1323, H_SPR_MSR44 = 1324 + , H_SPR_MSR45 = 1325, H_SPR_MSR46 = 1326, H_SPR_MSR47 = 1327, H_SPR_MSR48 = 1328 + , H_SPR_MSR49 = 1329, H_SPR_MSR50 = 1330, H_SPR_MSR51 = 1331, H_SPR_MSR52 = 1332 + , H_SPR_MSR53 = 1333, H_SPR_MSR54 = 1334, H_SPR_MSR55 = 1335, H_SPR_MSR56 = 1336 + , H_SPR_MSR57 = 1337, H_SPR_MSR58 = 1338, H_SPR_MSR59 = 1339, H_SPR_MSR60 = 1340 + , H_SPR_MSR61 = 1341, H_SPR_MSR62 = 1342, H_SPR_MSR63 = 1343, H_SPR_MQOP0 = 1344 + , H_SPR_MQOP1 = 1346, H_SPR_MQOP2 = 1348, H_SPR_MQOP3 = 1350, H_SPR_MQOP4 = 1352 + , H_SPR_MQOP5 = 1354, H_SPR_MQOP6 = 1356, H_SPR_MQOP7 = 1358, H_SPR_MQOP8 = 1360 + , H_SPR_MQOP9 = 1362, H_SPR_MQOP10 = 1364, H_SPR_MQOP11 = 1366, H_SPR_MQOP12 = 1368 + , H_SPR_MQOP13 = 1370, H_SPR_MQOP14 = 1372, H_SPR_MQOP15 = 1374, H_SPR_MQOP16 = 1376 + , H_SPR_MQOP17 = 1378, H_SPR_MQOP18 = 1380, H_SPR_MQOP19 = 1382, H_SPR_MQOP20 = 1384 + , H_SPR_MQOP21 = 1386, H_SPR_MQOP22 = 1388, H_SPR_MQOP23 = 1390, H_SPR_MQOP24 = 1392 + , H_SPR_MQOP25 = 1394, H_SPR_MQOP26 = 1396, H_SPR_MQOP27 = 1398, H_SPR_MQOP28 = 1400 + , H_SPR_MQOP29 = 1402, H_SPR_MQOP30 = 1404, H_SPR_MQOP31 = 1406, H_SPR_MQST0 = 1345 + , H_SPR_MQST1 = 1347, H_SPR_MQST2 = 1349, H_SPR_MQST3 = 1351, H_SPR_MQST4 = 1353 + , H_SPR_MQST5 = 1355, H_SPR_MQST6 = 1357, H_SPR_MQST7 = 1359, H_SPR_MQST8 = 1361 + , H_SPR_MQST9 = 1363, H_SPR_MQST10 = 1365, H_SPR_MQST11 = 1367, H_SPR_MQST12 = 1369 + , H_SPR_MQST13 = 1371, H_SPR_MQST14 = 1373, H_SPR_MQST15 = 1375, H_SPR_MQST16 = 1377 + , H_SPR_MQST17 = 1379, H_SPR_MQST18 = 1381, H_SPR_MQST19 = 1383, H_SPR_MQST20 = 1385 + , H_SPR_MQST21 = 1387, H_SPR_MQST22 = 1389, H_SPR_MQST23 = 1391, H_SPR_MQST24 = 1393 + , H_SPR_MQST25 = 1395, H_SPR_MQST26 = 1397, H_SPR_MQST27 = 1399, H_SPR_MQST28 = 1401 + , H_SPR_MQST29 = 1403, H_SPR_MQST30 = 1405, H_SPR_MQST31 = 1407, H_SPR_EAR0 = 1536 + , H_SPR_EAR1 = 1537, H_SPR_EAR2 = 1538, H_SPR_EAR3 = 1539, H_SPR_EAR4 = 1540 + , H_SPR_EAR5 = 1541, H_SPR_EAR6 = 1542, H_SPR_EAR7 = 1543, H_SPR_EAR8 = 1544 + , H_SPR_EAR9 = 1545, H_SPR_EAR10 = 1546, H_SPR_EAR11 = 1547, H_SPR_EAR12 = 1548 + , H_SPR_EAR13 = 1549, H_SPR_EAR14 = 1550, H_SPR_EAR15 = 1551, H_SPR_EAR16 = 1552 + , H_SPR_EAR17 = 1553, H_SPR_EAR18 = 1554, H_SPR_EAR19 = 1555, H_SPR_EAR20 = 1556 + , H_SPR_EAR21 = 1557, H_SPR_EAR22 = 1558, H_SPR_EAR23 = 1559, H_SPR_EAR24 = 1560 + , H_SPR_EAR25 = 1561, H_SPR_EAR26 = 1562, H_SPR_EAR27 = 1563, H_SPR_EAR28 = 1564 + , H_SPR_EAR29 = 1565, H_SPR_EAR30 = 1566, H_SPR_EAR31 = 1567, H_SPR_EAR32 = 1568 + , H_SPR_EAR33 = 1569, H_SPR_EAR34 = 1570, H_SPR_EAR35 = 1571, H_SPR_EAR36 = 1572 + , H_SPR_EAR37 = 1573, H_SPR_EAR38 = 1574, H_SPR_EAR39 = 1575, H_SPR_EAR40 = 1576 + , H_SPR_EAR41 = 1577, H_SPR_EAR42 = 1578, H_SPR_EAR43 = 1579, H_SPR_EAR44 = 1580 + , H_SPR_EAR45 = 1581, H_SPR_EAR46 = 1582, H_SPR_EAR47 = 1583, H_SPR_EAR48 = 1584 + , H_SPR_EAR49 = 1585, H_SPR_EAR50 = 1586, H_SPR_EAR51 = 1587, H_SPR_EAR52 = 1588 + , H_SPR_EAR53 = 1589, H_SPR_EAR54 = 1590, H_SPR_EAR55 = 1591, H_SPR_EAR56 = 1592 + , H_SPR_EAR57 = 1593, H_SPR_EAR58 = 1594, H_SPR_EAR59 = 1595, H_SPR_EAR60 = 1596 + , H_SPR_EAR61 = 1597, H_SPR_EAR62 = 1598, H_SPR_EAR63 = 1599, H_SPR_EDR0 = 1600 + , H_SPR_EDR1 = 1601, H_SPR_EDR2 = 1602, H_SPR_EDR3 = 1603, H_SPR_EDR4 = 1604 + , H_SPR_EDR5 = 1605, H_SPR_EDR6 = 1606, H_SPR_EDR7 = 1607, H_SPR_EDR8 = 1608 + , H_SPR_EDR9 = 1609, H_SPR_EDR10 = 1610, H_SPR_EDR11 = 1611, H_SPR_EDR12 = 1612 + , H_SPR_EDR13 = 1613, H_SPR_EDR14 = 1614, H_SPR_EDR15 = 1615, H_SPR_EDR16 = 1616 + , H_SPR_EDR17 = 1617, H_SPR_EDR18 = 1618, H_SPR_EDR19 = 1619, H_SPR_EDR20 = 1620 + , H_SPR_EDR21 = 1621, H_SPR_EDR22 = 1622, H_SPR_EDR23 = 1623, H_SPR_EDR24 = 1624 + , H_SPR_EDR25 = 1625, H_SPR_EDR26 = 1626, H_SPR_EDR27 = 1627, H_SPR_EDR28 = 1628 + , H_SPR_EDR29 = 1629, H_SPR_EDR30 = 1630, H_SPR_EDR31 = 1631, H_SPR_EDR32 = 1632 + , H_SPR_EDR33 = 1636, H_SPR_EDR34 = 1634, H_SPR_EDR35 = 1635, H_SPR_EDR36 = 1636 + , H_SPR_EDR37 = 1637, H_SPR_EDR38 = 1638, H_SPR_EDR39 = 1639, H_SPR_EDR40 = 1640 + , H_SPR_EDR41 = 1641, H_SPR_EDR42 = 1642, H_SPR_EDR43 = 1643, H_SPR_EDR44 = 1644 + , H_SPR_EDR45 = 1645, H_SPR_EDR46 = 1646, H_SPR_EDR47 = 1647, H_SPR_EDR48 = 1648 + , H_SPR_EDR49 = 1649, H_SPR_EDR50 = 1650, H_SPR_EDR51 = 1651, H_SPR_EDR52 = 1652 + , H_SPR_EDR53 = 1653, H_SPR_EDR54 = 1654, H_SPR_EDR55 = 1655, H_SPR_EDR56 = 1656 + , H_SPR_EDR57 = 1657, H_SPR_EDR58 = 1658, H_SPR_EDR59 = 1659, H_SPR_EDR60 = 1660 + , H_SPR_EDR61 = 1661, H_SPR_EDR62 = 1662, H_SPR_EDR63 = 1663, H_SPR_IAMLR0 = 1664 + , H_SPR_IAMLR1 = 1665, H_SPR_IAMLR2 = 1666, H_SPR_IAMLR3 = 1667, H_SPR_IAMLR4 = 1668 + , H_SPR_IAMLR5 = 1669, H_SPR_IAMLR6 = 1670, H_SPR_IAMLR7 = 1671, H_SPR_IAMLR8 = 1672 + , H_SPR_IAMLR9 = 1673, H_SPR_IAMLR10 = 1674, H_SPR_IAMLR11 = 1675, H_SPR_IAMLR12 = 1676 + , H_SPR_IAMLR13 = 1677, H_SPR_IAMLR14 = 1678, H_SPR_IAMLR15 = 1679, H_SPR_IAMLR16 = 1680 + , H_SPR_IAMLR17 = 1681, H_SPR_IAMLR18 = 1682, H_SPR_IAMLR19 = 1683, H_SPR_IAMLR20 = 1684 + , H_SPR_IAMLR21 = 1685, H_SPR_IAMLR22 = 1686, H_SPR_IAMLR23 = 1687, H_SPR_IAMLR24 = 1688 + , H_SPR_IAMLR25 = 1689, H_SPR_IAMLR26 = 1690, H_SPR_IAMLR27 = 1691, H_SPR_IAMLR28 = 1692 + , H_SPR_IAMLR29 = 1693, H_SPR_IAMLR30 = 1694, H_SPR_IAMLR31 = 1695, H_SPR_IAMLR32 = 1696 + , H_SPR_IAMLR33 = 1697, H_SPR_IAMLR34 = 1698, H_SPR_IAMLR35 = 1699, H_SPR_IAMLR36 = 1700 + , H_SPR_IAMLR37 = 1701, H_SPR_IAMLR38 = 1702, H_SPR_IAMLR39 = 1703, H_SPR_IAMLR40 = 1704 + , H_SPR_IAMLR41 = 1705, H_SPR_IAMLR42 = 1706, H_SPR_IAMLR43 = 1707, H_SPR_IAMLR44 = 1708 + , H_SPR_IAMLR45 = 1709, H_SPR_IAMLR46 = 1710, H_SPR_IAMLR47 = 1711, H_SPR_IAMLR48 = 1712 + , H_SPR_IAMLR49 = 1713, H_SPR_IAMLR50 = 1714, H_SPR_IAMLR51 = 1715, H_SPR_IAMLR52 = 1716 + , H_SPR_IAMLR53 = 1717, H_SPR_IAMLR54 = 1718, H_SPR_IAMLR55 = 1719, H_SPR_IAMLR56 = 1720 + , H_SPR_IAMLR57 = 1721, H_SPR_IAMLR58 = 1722, H_SPR_IAMLR59 = 1723, H_SPR_IAMLR60 = 1724 + , H_SPR_IAMLR61 = 1725, H_SPR_IAMLR62 = 1726, H_SPR_IAMLR63 = 1727, H_SPR_IAMPR0 = 1728 + , H_SPR_IAMPR1 = 1729, H_SPR_IAMPR2 = 1730, H_SPR_IAMPR3 = 1731, H_SPR_IAMPR4 = 1732 + , H_SPR_IAMPR5 = 1733, H_SPR_IAMPR6 = 1734, H_SPR_IAMPR7 = 1735, H_SPR_IAMPR8 = 1736 + , H_SPR_IAMPR9 = 1737, H_SPR_IAMPR10 = 1738, H_SPR_IAMPR11 = 1739, H_SPR_IAMPR12 = 1740 + , H_SPR_IAMPR13 = 1741, H_SPR_IAMPR14 = 1742, H_SPR_IAMPR15 = 1743, H_SPR_IAMPR16 = 1744 + , H_SPR_IAMPR17 = 1745, H_SPR_IAMPR18 = 1746, H_SPR_IAMPR19 = 1747, H_SPR_IAMPR20 = 1748 + , H_SPR_IAMPR21 = 1749, H_SPR_IAMPR22 = 1750, H_SPR_IAMPR23 = 1751, H_SPR_IAMPR24 = 1752 + , H_SPR_IAMPR25 = 1753, H_SPR_IAMPR26 = 1754, H_SPR_IAMPR27 = 1755, H_SPR_IAMPR28 = 1756 + , H_SPR_IAMPR29 = 1757, H_SPR_IAMPR30 = 1758, H_SPR_IAMPR31 = 1759, H_SPR_IAMPR32 = 1760 + , H_SPR_IAMPR33 = 1761, H_SPR_IAMPR34 = 1762, H_SPR_IAMPR35 = 1763, H_SPR_IAMPR36 = 1764 + , H_SPR_IAMPR37 = 1765, H_SPR_IAMPR38 = 1766, H_SPR_IAMPR39 = 1767, H_SPR_IAMPR40 = 1768 + , H_SPR_IAMPR41 = 1769, H_SPR_IAMPR42 = 1770, H_SPR_IAMPR43 = 1771, H_SPR_IAMPR44 = 1772 + , H_SPR_IAMPR45 = 1773, H_SPR_IAMPR46 = 1774, H_SPR_IAMPR47 = 1775, H_SPR_IAMPR48 = 1776 + , H_SPR_IAMPR49 = 1777, H_SPR_IAMPR50 = 1778, H_SPR_IAMPR51 = 1779, H_SPR_IAMPR52 = 1780 + , H_SPR_IAMPR53 = 1781, H_SPR_IAMPR54 = 1782, H_SPR_IAMPR55 = 1783, H_SPR_IAMPR56 = 1784 + , H_SPR_IAMPR57 = 1785, H_SPR_IAMPR58 = 1786, H_SPR_IAMPR59 = 1787, H_SPR_IAMPR60 = 1788 + , H_SPR_IAMPR61 = 1789, H_SPR_IAMPR62 = 1790, H_SPR_IAMPR63 = 1791, H_SPR_DAMLR0 = 1792 + , H_SPR_DAMLR1 = 1793, H_SPR_DAMLR2 = 1794, H_SPR_DAMLR3 = 1795, H_SPR_DAMLR4 = 1796 + , H_SPR_DAMLR5 = 1797, H_SPR_DAMLR6 = 1798, H_SPR_DAMLR7 = 1799, H_SPR_DAMLR8 = 1800 + , H_SPR_DAMLR9 = 1801, H_SPR_DAMLR10 = 1802, H_SPR_DAMLR11 = 1803, H_SPR_DAMLR12 = 1804 + , H_SPR_DAMLR13 = 1805, H_SPR_DAMLR14 = 1806, H_SPR_DAMLR15 = 1807, H_SPR_DAMLR16 = 1808 + , H_SPR_DAMLR17 = 1809, H_SPR_DAMLR18 = 1810, H_SPR_DAMLR19 = 1811, H_SPR_DAMLR20 = 1812 + , H_SPR_DAMLR21 = 1813, H_SPR_DAMLR22 = 1814, H_SPR_DAMLR23 = 1815, H_SPR_DAMLR24 = 1816 + , H_SPR_DAMLR25 = 1817, H_SPR_DAMLR26 = 1818, H_SPR_DAMLR27 = 1819, H_SPR_DAMLR28 = 1820 + , H_SPR_DAMLR29 = 1821, H_SPR_DAMLR30 = 1822, H_SPR_DAMLR31 = 1823, H_SPR_DAMLR32 = 1824 + , H_SPR_DAMLR33 = 1825, H_SPR_DAMLR34 = 1826, H_SPR_DAMLR35 = 1827, H_SPR_DAMLR36 = 1828 + , H_SPR_DAMLR37 = 1829, H_SPR_DAMLR38 = 1830, H_SPR_DAMLR39 = 1831, H_SPR_DAMLR40 = 1832 + , H_SPR_DAMLR41 = 1833, H_SPR_DAMLR42 = 1834, H_SPR_DAMLR43 = 1835, H_SPR_DAMLR44 = 1836 + , H_SPR_DAMLR45 = 1837, H_SPR_DAMLR46 = 1838, H_SPR_DAMLR47 = 1839, H_SPR_DAMLR48 = 1840 + , H_SPR_DAMLR49 = 1841, H_SPR_DAMLR50 = 1842, H_SPR_DAMLR51 = 1843, H_SPR_DAMLR52 = 1844 + , H_SPR_DAMLR53 = 1845, H_SPR_DAMLR54 = 1846, H_SPR_DAMLR55 = 1847, H_SPR_DAMLR56 = 1848 + , H_SPR_DAMLR57 = 1849, H_SPR_DAMLR58 = 1850, H_SPR_DAMLR59 = 1851, H_SPR_DAMLR60 = 1852 + , H_SPR_DAMLR61 = 1853, H_SPR_DAMLR62 = 1854, H_SPR_DAMLR63 = 1855, H_SPR_DAMPR0 = 1856 + , H_SPR_DAMPR1 = 1857, H_SPR_DAMPR2 = 1858, H_SPR_DAMPR3 = 1859, H_SPR_DAMPR4 = 1860 + , H_SPR_DAMPR5 = 1861, H_SPR_DAMPR6 = 1862, H_SPR_DAMPR7 = 1863, H_SPR_DAMPR8 = 1864 + , H_SPR_DAMPR9 = 1865, H_SPR_DAMPR10 = 1866, H_SPR_DAMPR11 = 1867, H_SPR_DAMPR12 = 1868 + , H_SPR_DAMPR13 = 1869, H_SPR_DAMPR14 = 1870, H_SPR_DAMPR15 = 1871, H_SPR_DAMPR16 = 1872 + , H_SPR_DAMPR17 = 1873, H_SPR_DAMPR18 = 1874, H_SPR_DAMPR19 = 1875, H_SPR_DAMPR20 = 1876 + , H_SPR_DAMPR21 = 1877, H_SPR_DAMPR22 = 1878, H_SPR_DAMPR23 = 1879, H_SPR_DAMPR24 = 1880 + , H_SPR_DAMPR25 = 1881, H_SPR_DAMPR26 = 1882, H_SPR_DAMPR27 = 1883, H_SPR_DAMPR28 = 1884 + , H_SPR_DAMPR29 = 1885, H_SPR_DAMPR30 = 1886, H_SPR_DAMPR31 = 1887, H_SPR_DAMPR32 = 1888 + , H_SPR_DAMPR33 = 1889, H_SPR_DAMPR34 = 1890, H_SPR_DAMPR35 = 1891, H_SPR_DAMPR36 = 1892 + , H_SPR_DAMPR37 = 1893, H_SPR_DAMPR38 = 1894, H_SPR_DAMPR39 = 1895, H_SPR_DAMPR40 = 1896 + , H_SPR_DAMPR41 = 1897, H_SPR_DAMPR42 = 1898, H_SPR_DAMPR43 = 1899, H_SPR_DAMPR44 = 1900 + , H_SPR_DAMPR45 = 1901, H_SPR_DAMPR46 = 1902, H_SPR_DAMPR47 = 1903, H_SPR_DAMPR48 = 1904 + , H_SPR_DAMPR49 = 1905, H_SPR_DAMPR50 = 1906, H_SPR_DAMPR51 = 1907, H_SPR_DAMPR52 = 1908 + , H_SPR_DAMPR53 = 1909, H_SPR_DAMPR54 = 1910, H_SPR_DAMPR55 = 1911, H_SPR_DAMPR56 = 1912 + , H_SPR_DAMPR57 = 1913, H_SPR_DAMPR58 = 1914, H_SPR_DAMPR59 = 1915, H_SPR_DAMPR60 = 1916 + , H_SPR_DAMPR61 = 1917, H_SPR_DAMPR62 = 1918, H_SPR_DAMPR63 = 1919, H_SPR_AMCR = 1920 + , H_SPR_STBAR = 1921, H_SPR_MMCR = 1922, H_SPR_DCR = 2048, H_SPR_BRR = 2049 + , H_SPR_NMAR = 2050, H_SPR_IBAR0 = 2052, H_SPR_IBAR1 = 2053, H_SPR_IBAR2 = 2054 + , H_SPR_IBAR3 = 2055, H_SPR_DBAR0 = 2056, H_SPR_DBAR1 = 2057, H_SPR_DBAR2 = 2058 + , H_SPR_DBAR3 = 2059, H_SPR_DBDR00 = 2060, H_SPR_DBDR01 = 2061, H_SPR_DBDR02 = 2062 + , H_SPR_DBDR03 = 2063, H_SPR_DBDR10 = 2064, H_SPR_DBDR11 = 2065, H_SPR_DBDR12 = 2066 + , H_SPR_DBDR13 = 2067, H_SPR_DBDR20 = 2068, H_SPR_DBDR21 = 2069, H_SPR_DBDR22 = 2070 + , H_SPR_DBDR23 = 2071, H_SPR_DBDR30 = 2072, H_SPR_DBDR31 = 2073, H_SPR_DBDR32 = 2074 + , H_SPR_DBDR33 = 2075, H_SPR_DBMR00 = 2076, H_SPR_DBMR01 = 2077, H_SPR_DBMR02 = 2078 + , H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080, H_SPR_DBMR11 = 2081, H_SPR_DBMR12 = 2082 + , H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084, H_SPR_DBMR21 = 2085, H_SPR_DBMR22 = 2086 + , H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088, H_SPR_DBMR31 = 2089, H_SPR_DBMR32 = 2090 + , H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092, H_SPR_CPCR = 2093, H_SPR_CPSR = 2094 + , H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097, H_SPR_CPEMR0 = 2098, H_SPR_CPEMR1 = 2099 + , H_SPR_IHSR8 = 3848 +} SPR_NAMES; + +/* Enum declaration for . */ +typedef enum accg_names { + H_ACCG_ACCG0, H_ACCG_ACCG1, H_ACCG_ACCG2, H_ACCG_ACCG3 + , H_ACCG_ACCG4, H_ACCG_ACCG5, H_ACCG_ACCG6, H_ACCG_ACCG7 + , H_ACCG_ACCG8, H_ACCG_ACCG9, H_ACCG_ACCG10, H_ACCG_ACCG11 + , H_ACCG_ACCG12, H_ACCG_ACCG13, H_ACCG_ACCG14, H_ACCG_ACCG15 + , H_ACCG_ACCG16, H_ACCG_ACCG17, H_ACCG_ACCG18, H_ACCG_ACCG19 + , H_ACCG_ACCG20, H_ACCG_ACCG21, H_ACCG_ACCG22, H_ACCG_ACCG23 + , H_ACCG_ACCG24, H_ACCG_ACCG25, H_ACCG_ACCG26, H_ACCG_ACCG27 + , H_ACCG_ACCG28, H_ACCG_ACCG29, H_ACCG_ACCG30, H_ACCG_ACCG31 + , H_ACCG_ACCG32, H_ACCG_ACCG33, H_ACCG_ACCG34, H_ACCG_ACCG35 + , H_ACCG_ACCG36, H_ACCG_ACCG37, H_ACCG_ACCG38, H_ACCG_ACCG39 + , H_ACCG_ACCG40, H_ACCG_ACCG41, H_ACCG_ACCG42, H_ACCG_ACCG43 + , H_ACCG_ACCG44, H_ACCG_ACCG45, H_ACCG_ACCG46, H_ACCG_ACCG47 + , H_ACCG_ACCG48, H_ACCG_ACCG49, H_ACCG_ACCG50, H_ACCG_ACCG51 + , H_ACCG_ACCG52, H_ACCG_ACCG53, H_ACCG_ACCG54, H_ACCG_ACCG55 + , H_ACCG_ACCG56, H_ACCG_ACCG57, H_ACCG_ACCG58, H_ACCG_ACCG59 + , H_ACCG_ACCG60, H_ACCG_ACCG61, H_ACCG_ACCG62, H_ACCG_ACCG63 +} ACCG_NAMES; + +/* Enum declaration for . */ +typedef enum acc_names { + H_ACC40_ACC0, H_ACC40_ACC1, H_ACC40_ACC2, H_ACC40_ACC3 + , H_ACC40_ACC4, H_ACC40_ACC5, H_ACC40_ACC6, H_ACC40_ACC7 + , H_ACC40_ACC8, H_ACC40_ACC9, H_ACC40_ACC10, H_ACC40_ACC11 + , H_ACC40_ACC12, H_ACC40_ACC13, H_ACC40_ACC14, H_ACC40_ACC15 + , H_ACC40_ACC16, H_ACC40_ACC17, H_ACC40_ACC18, H_ACC40_ACC19 + , H_ACC40_ACC20, H_ACC40_ACC21, H_ACC40_ACC22, H_ACC40_ACC23 + , H_ACC40_ACC24, H_ACC40_ACC25, H_ACC40_ACC26, H_ACC40_ACC27 + , H_ACC40_ACC28, H_ACC40_ACC29, H_ACC40_ACC30, H_ACC40_ACC31 + , H_ACC40_ACC32, H_ACC40_ACC33, H_ACC40_ACC34, H_ACC40_ACC35 + , H_ACC40_ACC36, H_ACC40_ACC37, H_ACC40_ACC38, H_ACC40_ACC39 + , H_ACC40_ACC40, H_ACC40_ACC41, H_ACC40_ACC42, H_ACC40_ACC43 + , H_ACC40_ACC44, H_ACC40_ACC45, H_ACC40_ACC46, H_ACC40_ACC47 + , H_ACC40_ACC48, H_ACC40_ACC49, H_ACC40_ACC50, H_ACC40_ACC51 + , H_ACC40_ACC52, H_ACC40_ACC53, H_ACC40_ACC54, H_ACC40_ACC55 + , H_ACC40_ACC56, H_ACC40_ACC57, H_ACC40_ACC58, H_ACC40_ACC59 + , H_ACC40_ACC60, H_ACC40_ACC61, H_ACC40_ACC62, H_ACC40_ACC63 +} ACC_NAMES; + +/* Enum declaration for . */ +typedef enum iccr_names { + H_ICCR_ICC0, H_ICCR_ICC1, H_ICCR_ICC2, H_ICCR_ICC3 +} ICCR_NAMES; + +/* Enum declaration for . */ +typedef enum fccr_names { + H_FCCR_FCC0, H_FCCR_FCC1, H_FCCR_FCC2, H_FCCR_FCC3 +} FCCR_NAMES; + +/* Enum declaration for . */ +typedef enum cccr_names { + H_CCCR_CC0, H_CCCR_CC1, H_CCCR_CC2, H_CCCR_CC3 + , H_CCCR_CC4, H_CCCR_CC5, H_CCCR_CC6, H_CCCR_CC7 +} CCCR_NAMES; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_FRV, MACH_FR500, MACH_FR400 + , MACH_TOMCAT, MACH_SIMPLE, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_FRV, ISA_MAX +} ISA_ATTR; + +/* Enum declaration for parallel execution pipeline selection. */ +typedef enum unit_attr { + UNIT_NIL, UNIT_I0, UNIT_I1, UNIT_I01 + , UNIT_FM0, UNIT_FM1, UNIT_FM01, UNIT_B0 + , UNIT_B1, UNIT_B01, UNIT_C, UNIT_MULT_DIV + , UNIT_LOAD, UNIT_NUM_UNITS +} UNIT_ATTR; + +/* Enum declaration for fr400 major insn categories. */ +typedef enum fr400_major_attr { + FR400_MAJOR_NONE, FR400_MAJOR_I_1, FR400_MAJOR_I_2, FR400_MAJOR_I_3 + , FR400_MAJOR_I_4, FR400_MAJOR_I_5, FR400_MAJOR_B_1, FR400_MAJOR_B_2 + , FR400_MAJOR_B_3, FR400_MAJOR_B_4, FR400_MAJOR_B_5, FR400_MAJOR_B_6 + , FR400_MAJOR_C_1, FR400_MAJOR_C_2, FR400_MAJOR_M_1, FR400_MAJOR_M_2 +} FR400_MAJOR_ATTR; + +/* Enum declaration for fr500 major insn categories. */ +typedef enum fr500_major_attr { + FR500_MAJOR_NONE, FR500_MAJOR_I_1, FR500_MAJOR_I_2, FR500_MAJOR_I_3 + , FR500_MAJOR_I_4, FR500_MAJOR_I_5, FR500_MAJOR_I_6, FR500_MAJOR_B_1 + , FR500_MAJOR_B_2, FR500_MAJOR_B_3, FR500_MAJOR_B_4, FR500_MAJOR_B_5 + , FR500_MAJOR_B_6, FR500_MAJOR_C_1, FR500_MAJOR_C_2, FR500_MAJOR_F_1 + , FR500_MAJOR_F_2, FR500_MAJOR_F_3, FR500_MAJOR_F_4, FR500_MAJOR_F_5 + , FR500_MAJOR_F_6, FR500_MAJOR_F_7, FR500_MAJOR_F_8, FR500_MAJOR_M_1 + , FR500_MAJOR_M_2, FR500_MAJOR_M_3, FR500_MAJOR_M_4, FR500_MAJOR_M_5 + , FR500_MAJOR_M_6, FR500_MAJOR_M_7, FR500_MAJOR_M_8 +} FR500_MAJOR_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +extern const struct cgen_ifld frv_cgen_ifld_table[]; + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* Enum declaration for frv ifield types. */ +typedef enum ifield_type { + FRV_F_NIL, FRV_F_ANYOF, FRV_F_PACK, FRV_F_OP + , FRV_F_OPE1, FRV_F_OPE2, FRV_F_OPE3, FRV_F_OPE4 + , FRV_F_GRI, FRV_F_GRJ, FRV_F_GRK, FRV_F_FRI + , FRV_F_FRJ, FRV_F_FRK, FRV_F_CPRI, FRV_F_CPRJ + , FRV_F_CPRK, FRV_F_ACCGI, FRV_F_ACCGK, FRV_F_ACC40SI + , FRV_F_ACC40UI, FRV_F_ACC40SK, FRV_F_ACC40UK, FRV_F_CRI + , FRV_F_CRJ, FRV_F_CRK, FRV_F_CCI, FRV_F_CRJ_INT + , FRV_F_CRJ_FLOAT, FRV_F_ICCI_1, FRV_F_ICCI_2, FRV_F_ICCI_3 + , FRV_F_FCCI_1, FRV_F_FCCI_2, FRV_F_FCCI_3, FRV_F_FCCK + , FRV_F_EIR, FRV_F_S10, FRV_F_S12, FRV_F_D12 + , FRV_F_U16, FRV_F_S16, FRV_F_S6, FRV_F_S6_1 + , FRV_F_U6, FRV_F_S5, FRV_F_U12_H, FRV_F_U12_L + , FRV_F_U12, FRV_F_INT_CC, FRV_F_FLT_CC, FRV_F_COND + , FRV_F_CCOND, FRV_F_HINT, FRV_F_LI, FRV_F_LOCK + , FRV_F_DEBUG, FRV_F_A, FRV_F_AE, FRV_F_SPR_H + , FRV_F_SPR_L, FRV_F_SPR, FRV_F_LABEL16, FRV_F_LABELH6 + , FRV_F_LABELL18, FRV_F_LABEL24, FRV_F_ICCI_1_NULL, FRV_F_ICCI_2_NULL + , FRV_F_ICCI_3_NULL, FRV_F_FCCI_1_NULL, FRV_F_FCCI_2_NULL, FRV_F_FCCI_3_NULL + , FRV_F_RS_NULL, FRV_F_GRI_NULL, FRV_F_GRJ_NULL, FRV_F_GRK_NULL + , FRV_F_FRI_NULL, FRV_F_FRJ_NULL, FRV_F_ACCJ_NULL, FRV_F_RD_NULL + , FRV_F_COND_NULL, FRV_F_CCOND_NULL, FRV_F_S12_NULL, FRV_F_LABEL16_NULL + , FRV_F_MISC_NULL_1, FRV_F_MISC_NULL_2, FRV_F_MISC_NULL_3, FRV_F_MISC_NULL_4 + , FRV_F_MISC_NULL_5, FRV_F_MISC_NULL_6, FRV_F_MISC_NULL_7, FRV_F_MISC_NULL_8 + , FRV_F_MISC_NULL_9, FRV_F_MISC_NULL_10, FRV_F_MISC_NULL_11, FRV_F_LI_OFF + , FRV_F_LI_ON, FRV_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) FRV_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* Enum declaration for frv hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_PSR_IMPLE, HW_H_PSR_VER + , HW_H_PSR_ICE, HW_H_PSR_NEM, HW_H_PSR_CM, HW_H_PSR_BE + , HW_H_PSR_ESR, HW_H_PSR_EF, HW_H_PSR_EM, HW_H_PSR_PIL + , HW_H_PSR_PS, HW_H_PSR_ET, HW_H_PSR_S, HW_H_TBR_TBA + , HW_H_TBR_TT, HW_H_BPSR_BS, HW_H_BPSR_BET, HW_H_GR + , HW_H_GR_DOUBLE, HW_H_GR_HI, HW_H_GR_LO, HW_H_FR + , HW_H_FR_DOUBLE, HW_H_FR_INT, HW_H_FR_HI, HW_H_FR_LO + , HW_H_FR_0, HW_H_FR_1, HW_H_FR_2, HW_H_FR_3 + , HW_H_CPR, HW_H_CPR_DOUBLE, HW_H_SPR, HW_H_ACCG + , HW_H_ACC40S, HW_H_ACC40U, HW_H_ICCR, HW_H_FCCR + , HW_H_CCCR, HW_H_PACK, HW_H_HINT_TAKEN, HW_H_HINT_NOT_TAKEN + , HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH + , CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* Enum declaration for frv operand types. */ +typedef enum cgen_operand_type { + FRV_OPERAND_PC, FRV_OPERAND_PACK, FRV_OPERAND_GRI, FRV_OPERAND_GRJ + , FRV_OPERAND_GRK, FRV_OPERAND_GRKHI, FRV_OPERAND_GRKLO, FRV_OPERAND_GRDOUBLEK + , FRV_OPERAND_ACC40SI, FRV_OPERAND_ACC40UI, FRV_OPERAND_ACC40SK, FRV_OPERAND_ACC40UK + , FRV_OPERAND_ACCGI, FRV_OPERAND_ACCGK, FRV_OPERAND_CPRI, FRV_OPERAND_CPRJ + , FRV_OPERAND_CPRK, FRV_OPERAND_CPRDOUBLEK, FRV_OPERAND_FRINTI, FRV_OPERAND_FRINTJ + , FRV_OPERAND_FRINTK, FRV_OPERAND_FRI, FRV_OPERAND_FRJ, FRV_OPERAND_FRK + , FRV_OPERAND_FRKHI, FRV_OPERAND_FRKLO, FRV_OPERAND_FRDOUBLEI, FRV_OPERAND_FRDOUBLEJ + , FRV_OPERAND_FRDOUBLEK, FRV_OPERAND_CRI, FRV_OPERAND_CRJ, FRV_OPERAND_CRJ_INT + , FRV_OPERAND_CRJ_FLOAT, FRV_OPERAND_CRK, FRV_OPERAND_CCI, FRV_OPERAND_ICCI_1 + , FRV_OPERAND_ICCI_2, FRV_OPERAND_ICCI_3, FRV_OPERAND_FCCI_1, FRV_OPERAND_FCCI_2 + , FRV_OPERAND_FCCI_3, FRV_OPERAND_FCCK, FRV_OPERAND_EIR, FRV_OPERAND_S10 + , FRV_OPERAND_U16, FRV_OPERAND_S16, FRV_OPERAND_S6, FRV_OPERAND_S6_1 + , FRV_OPERAND_U6, FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND + , FRV_OPERAND_HINT, FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI + , FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_A, FRV_OPERAND_AE + , FRV_OPERAND_LABEL16, FRV_OPERAND_LABEL24, FRV_OPERAND_D12, FRV_OPERAND_S12 + , FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16 + , FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS + , FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA + , FRV_OPERAND_TBR_TT, FRV_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 77 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_PRIVILEGED, CGEN_INSN_NON_EXCEPTING + , CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_END_BOOLS + , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT, CGEN_INSN_FR400_MAJOR + , CGEN_INSN_FR500_MAJOR, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +/* Attributes. */ +extern const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD frv_cgen_opval_gr_names; +extern CGEN_KEYWORD frv_cgen_opval_gr_names; +extern CGEN_KEYWORD frv_cgen_opval_gr_names; +extern CGEN_KEYWORD frv_cgen_opval_gr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_cpr_names; +extern CGEN_KEYWORD frv_cgen_opval_cpr_names; +extern CGEN_KEYWORD frv_cgen_opval_spr_names; +extern CGEN_KEYWORD frv_cgen_opval_accg_names; +extern CGEN_KEYWORD frv_cgen_opval_acc_names; +extern CGEN_KEYWORD frv_cgen_opval_acc_names; +extern CGEN_KEYWORD frv_cgen_opval_iccr_names; +extern CGEN_KEYWORD frv_cgen_opval_fccr_names; +extern CGEN_KEYWORD frv_cgen_opval_cccr_names; +extern CGEN_KEYWORD frv_cgen_opval_h_pack; +extern CGEN_KEYWORD frv_cgen_opval_h_hint_taken; +extern CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken; + + + + +#endif /* FRV_CPU_H */ diff -uprN binutils-2.12.90.0.11/opcodes/frv-dis.c binutils-2.12.90.0.12/opcodes/frv-dis.c --- binutils-2.12.90.0.11/opcodes/frv-dis.c Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/opcodes/frv-dis.c Tue Jun 18 21:41:59 2002 @@ -0,0 +1,789 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-dis.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); +static void print_address + PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); +static void print_keyword + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); +static void print_insn_normal + PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, + bfd_vma, int)); +static int print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); +static int default_print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); +static int read_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, + CGEN_EXTRACT_INFO *, unsigned long *)); + +/* -- disassembler routines inserted here */ + +/* -- dis.c */ +static void print_spr + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned)); +static void print_hi + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); +static void print_lo + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); + +static void +print_spr (cd, dis_info, names, regno, attrs) + CGEN_CPU_DESC cd; + PTR dis_info; + CGEN_KEYWORD *names; + long regno; + unsigned int attrs; +{ + /* Use the register index format for any unnamed registers. */ + if (cgen_keyword_lookup_value (names, regno) == NULL) + { + disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, "spr[%ld]", regno); + } + else + print_keyword (cd, dis_info, names, regno, attrs); +} + +static void +print_hi (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + if (value) + (*info->fprintf_func) (info->stream, "0x%lx", value); + else + (*info->fprintf_func) (info->stream, "hi(0x%lx)", value); +} + +static void +print_lo (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + if (value) + (*info->fprintf_func) (info->stream, "0x%lx", value); + else + (*info->fprintf_func) (info->stream, "lo(0x%lx)", value); +} + +/* -- */ + +void frv_cgen_print_operand + PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, + void const *, bfd_vma, int)); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) + CGEN_CPU_DESC cd; + int opindex; + PTR xinfo; + CGEN_FIELDS *fields; + void const *attrs ATTRIBUTE_UNUSED; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case FRV_OPERAND_A : + print_normal (cd, info, fields->f_A, 0|(1<f_ACC40Si, 0); + break; + case FRV_OPERAND_ACC40SK : + print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Sk, 0); + break; + case FRV_OPERAND_ACC40UI : + print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Ui, 0); + break; + case FRV_OPERAND_ACC40UK : + print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Uk, 0); + break; + case FRV_OPERAND_ACCGI : + print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGi, 0); + break; + case FRV_OPERAND_ACCGK : + print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGk, 0); + break; + case FRV_OPERAND_CCI : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CCi, 0); + break; + case FRV_OPERAND_CPRDOUBLEK : + print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0); + break; + case FRV_OPERAND_CPRI : + print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRi, 0); + break; + case FRV_OPERAND_CPRJ : + print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRj, 0); + break; + case FRV_OPERAND_CPRK : + print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0); + break; + case FRV_OPERAND_CRI : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRi, 0); + break; + case FRV_OPERAND_CRJ : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj, 0); + break; + case FRV_OPERAND_CRJ_FLOAT : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_float, 0); + break; + case FRV_OPERAND_CRJ_INT : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_int, 0); + break; + case FRV_OPERAND_CRK : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRk, 0); + break; + case FRV_OPERAND_FCCI_1 : + print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_1, 0); + break; + case FRV_OPERAND_FCCI_2 : + print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_2, 0); + break; + case FRV_OPERAND_FCCI_3 : + print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_3, 0); + break; + case FRV_OPERAND_FCCK : + print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCk, 0); + break; + case FRV_OPERAND_FRDOUBLEI : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); + break; + case FRV_OPERAND_FRDOUBLEJ : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); + break; + case FRV_OPERAND_FRDOUBLEK : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_FRI : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); + break; + case FRV_OPERAND_FRINTI : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); + break; + case FRV_OPERAND_FRINTJ : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); + break; + case FRV_OPERAND_FRINTK : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_FRJ : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); + break; + case FRV_OPERAND_FRK : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_FRKHI : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_FRKLO : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_GRDOUBLEK : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); + break; + case FRV_OPERAND_GRI : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRi, 0); + break; + case FRV_OPERAND_GRJ : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRj, 0); + break; + case FRV_OPERAND_GRK : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); + break; + case FRV_OPERAND_GRKHI : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); + break; + case FRV_OPERAND_GRKLO : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); + break; + case FRV_OPERAND_ICCI_1 : + print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_1, 0); + break; + case FRV_OPERAND_ICCI_2 : + print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_2, 0); + break; + case FRV_OPERAND_ICCI_3 : + print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_3, 0); + break; + case FRV_OPERAND_LI : + print_normal (cd, info, fields->f_LI, 0, pc, length); + break; + case FRV_OPERAND_AE : + print_normal (cd, info, fields->f_ae, 0|(1<f_ccond, 0|(1<f_cond, 0|(1<f_d12, 0|(1<f_debug, 0|(1<f_eir, 0, pc, length); + break; + case FRV_OPERAND_HINT : + print_normal (cd, info, fields->f_hint, 0|(1<f_hint, 0); + break; + case FRV_OPERAND_HINT_TAKEN : + print_keyword (cd, info, & frv_cgen_opval_h_hint_taken, fields->f_hint, 0); + break; + case FRV_OPERAND_LABEL16 : + print_address (cd, info, fields->f_label16, 0|(1<f_label24, 0|(1<f_lock, 0|(1<f_pack, 0); + break; + case FRV_OPERAND_S10 : + print_normal (cd, info, fields->f_s10, 0|(1<f_d12, 0|(1<f_s16, 0|(1<f_s5, 0|(1<f_s6, 0|(1<f_s6_1, 0|(1<f_s16, 0|(1<f_spr, 0|(1<f_u12, 0|(1<f_u16, 0|(1<f_u6, 0|(1<f_u16, 0, pc, length); + break; + case FRV_OPERAND_ULO16 : + print_lo (cd, info, fields->f_u16, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const frv_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +frv_cgen_init_dis (cd) + CGEN_CPU_DESC cd; +{ + frv_cgen_init_opcode_table (cd); + frv_cgen_init_ibld_table (cd); + cd->print_handlers = & frv_cgen_print_handlers[0]; + cd->print_operand = frv_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + bfd_vma value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (cd, dis_info, keyword_table, value, attrs) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + CGEN_KEYWORD *keyword_table; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `PTR' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (cd, dis_info, insn, fields, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + const CGEN_INSN *insn; + CGEN_FIELDS *fields; + bfd_vma pc; + int length; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + frv_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; + CGEN_EXTRACT_INFO *ex_info; + unsigned long *insn_value; +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (cd, pc, info, buf, buflen) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; + char *buf; + unsigned int buflen; +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! frv_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* length < 0 -> error */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (cd, pc, info) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; +{ + char buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list { + struct cpu_desc_list *next; + int isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_frv (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static int prev_isa; + static int prev_mach; + static int prev_endian; + int length; + int isa,mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_frv +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + isa = CGEN_COMPUTE_ISA (info); +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (isa != prev_isa + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cl->isa == isa && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = isa; + prev_mach = mach; + prev_endian = endian; + cd = frv_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* save this away for future reference */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + frv_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff -uprN binutils-2.12.90.0.11/opcodes/frv-ibld.c binutils-2.12.90.0.12/opcodes/frv-ibld.c --- binutils-2.12.90.0.11/opcodes/frv-ibld.c Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/opcodes/frv-ibld.c Tue Jun 18 21:41:59 2002 @@ -0,0 +1,2051 @@ +/* Instruction building/extraction support for frv. -*- C -*- + +THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. +- the resultant file is machine generated, cgen-ibld.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); +static const char * insert_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); +static int extract_normal + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *)); +static int extract_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +#if CGEN_INT_INSN_P +static void put_insn_int_value + PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (cd, value, start, length, word_length, bufp) + CGEN_CPU_DESC cd; + unsigned long value; + int start,length,word_length; + unsigned char *bufp; +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (cd, value, attrs, word_offset, start, length, word_length, + total_length, buffer) + CGEN_CPU_DESC cd; + long value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_BYTES_PTR buffer; +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (cd, insn, fields, buffer, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN * insn; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (cd, buf, length, insn_length, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_INSN_BYTES_PTR buf; + int length; + int insn_length; + CGEN_INSN_INT value; +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (cd, ex_info, offset, bytes, pc) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info; + int offset, bytes; + bfd_vma pc; +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (cd, ex_info, start, length, word_length, bufp, pc) + CGEN_CPU_DESC cd; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + int start,length,word_length; + unsigned char *bufp; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + unsigned long x; + int shift; +#if 0 + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; +#endif + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, + word_length, total_length, pc, valuep) + CGEN_CPU_DESC cd; +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info; +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; +#endif + CGEN_INSN_INT insn_value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; +#if ! CGEN_INT_INSN_P + bfd_vma pc; +#else + bfd_vma pc ATTRIBUTE_UNUSED; +#endif + long *valuep; +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS *fields; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* machine generated code added here */ + +const char * frv_cgen_insert_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +frv_cgen_insert_operand (cd, opindex, fields, buffer, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case FRV_OPERAND_A : + errmsg = insert_normal (cd, fields->f_A, 0, 0, 17, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_ACC40SI : + errmsg = insert_normal (cd, fields->f_ACC40Si, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACC40SK : + errmsg = insert_normal (cd, fields->f_ACC40Sk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACC40UI : + errmsg = insert_normal (cd, fields->f_ACC40Ui, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACC40UK : + errmsg = insert_normal (cd, fields->f_ACC40Uk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACCGI : + errmsg = insert_normal (cd, fields->f_ACCGi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACCGK : + errmsg = insert_normal (cd, fields->f_ACCGk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CCI : + errmsg = insert_normal (cd, fields->f_CCi, 0, 0, 11, 3, 32, total_length, buffer); + break; + case FRV_OPERAND_CPRDOUBLEK : + errmsg = insert_normal (cd, fields->f_CPRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CPRI : + errmsg = insert_normal (cd, fields->f_CPRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CPRJ : + errmsg = insert_normal (cd, fields->f_CPRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CPRK : + errmsg = insert_normal (cd, fields->f_CPRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CRI : + errmsg = insert_normal (cd, fields->f_CRi, 0, 0, 14, 3, 32, total_length, buffer); + break; + case FRV_OPERAND_CRJ : + errmsg = insert_normal (cd, fields->f_CRj, 0, 0, 2, 3, 32, total_length, buffer); + break; + case FRV_OPERAND_CRJ_FLOAT : + errmsg = insert_normal (cd, fields->f_CRj_float, 0, 0, 26, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_CRJ_INT : + { + long value = fields->f_CRj_int; + value = ((value) - (4)); + errmsg = insert_normal (cd, value, 0, 0, 26, 2, 32, total_length, buffer); + } + break; + case FRV_OPERAND_CRK : + errmsg = insert_normal (cd, fields->f_CRk, 0, 0, 27, 3, 32, total_length, buffer); + break; + case FRV_OPERAND_FCCI_1 : + errmsg = insert_normal (cd, fields->f_FCCi_1, 0, 0, 11, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_FCCI_2 : + errmsg = insert_normal (cd, fields->f_FCCi_2, 0, 0, 26, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_FCCI_3 : + errmsg = insert_normal (cd, fields->f_FCCi_3, 0, 0, 1, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_FCCK : + errmsg = insert_normal (cd, fields->f_FCCk, 0, 0, 26, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_FRDOUBLEI : + errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRDOUBLEJ : + errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRDOUBLEK : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRI : + errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRINTI : + errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRINTJ : + errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRINTK : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRJ : + errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRK : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRKHI : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRKLO : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRDOUBLEK : + errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRI : + errmsg = insert_normal (cd, fields->f_GRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRJ : + errmsg = insert_normal (cd, fields->f_GRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRK : + errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRKHI : + errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRKLO : + errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ICCI_1 : + errmsg = insert_normal (cd, fields->f_ICCi_1, 0, 0, 11, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_ICCI_2 : + errmsg = insert_normal (cd, fields->f_ICCi_2, 0, 0, 26, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_ICCI_3 : + errmsg = insert_normal (cd, fields->f_ICCi_3, 0, 0, 1, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_LI : + errmsg = insert_normal (cd, fields->f_LI, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_AE : + errmsg = insert_normal (cd, fields->f_ae, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_CCOND : + errmsg = insert_normal (cd, fields->f_ccond, 0, 0, 12, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_COND : + errmsg = insert_normal (cd, fields->f_cond, 0, 0, 8, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_D12 : + errmsg = insert_normal (cd, fields->f_d12, 0|(1<f_debug, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_EIR : + errmsg = insert_normal (cd, fields->f_eir, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_HINT : + errmsg = insert_normal (cd, fields->f_hint, 0, 0, 17, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + errmsg = insert_normal (cd, fields->f_hint, 0, 0, 17, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_HINT_TAKEN : + errmsg = insert_normal (cd, fields->f_hint, 0, 0, 17, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_LABEL16 : + { + long value = fields->f_label16; + value = ((int) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<> (20)); + FLD (f_labelL18) = ((((unsigned int) (((FLD (f_label24)) - (pc))) >> (2))) & (262143)); +} + errmsg = insert_normal (cd, fields->f_labelH6, 0|(1<f_labelL18, 0, 0, 17, 18, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case FRV_OPERAND_LOCK : + errmsg = insert_normal (cd, fields->f_lock, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_PACK : + errmsg = insert_normal (cd, fields->f_pack, 0, 0, 31, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_S10 : + errmsg = insert_normal (cd, fields->f_s10, 0|(1<f_d12, 0|(1<f_s16, 0|(1<f_s5, 0|(1<f_s6, 0|(1<f_s6_1, 0|(1<f_s16, 0|(1<> (6)); + FLD (f_spr_l) = ((FLD (f_spr)) & (63)); +} + errmsg = insert_normal (cd, fields->f_spr_h, 0, 0, 30, 6, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_spr_l, 0, 0, 17, 6, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case FRV_OPERAND_U12 : + { +{ + FLD (f_u12_h) = ((int) (FLD (f_u12)) >> (6)); + FLD (f_u12_l) = ((FLD (f_u12)) & (63)); +} + errmsg = insert_normal (cd, fields->f_u12_h, 0|(1<f_u12_l, 0, 0, 5, 6, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case FRV_OPERAND_U16 : + errmsg = insert_normal (cd, fields->f_u16, 0, 0, 15, 16, 32, total_length, buffer); + break; + case FRV_OPERAND_U6 : + errmsg = insert_normal (cd, fields->f_u6, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_UHI16 : + errmsg = insert_normal (cd, fields->f_u16, 0, 0, 15, 16, 32, total_length, buffer); + break; + case FRV_OPERAND_ULO16 : + errmsg = insert_normal (cd, fields->f_u16, 0, 0, 15, 16, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int frv_cgen_extract_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *, bfd_vma)); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS * fields; + bfd_vma pc; +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case FRV_OPERAND_A : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_A); + break; + case FRV_OPERAND_ACC40SI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_ACC40Si); + break; + case FRV_OPERAND_ACC40SK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_ACC40Sk); + break; + case FRV_OPERAND_ACC40UI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_ACC40Ui); + break; + case FRV_OPERAND_ACC40UK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_ACC40Uk); + break; + case FRV_OPERAND_ACCGI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_ACCGi); + break; + case FRV_OPERAND_ACCGK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_ACCGk); + break; + case FRV_OPERAND_CCI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 3, 32, total_length, pc, & fields->f_CCi); + break; + case FRV_OPERAND_CPRDOUBLEK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_CPRk); + break; + case FRV_OPERAND_CPRI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_CPRi); + break; + case FRV_OPERAND_CPRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_CPRj); + break; + case FRV_OPERAND_CPRK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_CPRk); + break; + case FRV_OPERAND_CRI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_CRi); + break; + case FRV_OPERAND_CRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 32, total_length, pc, & fields->f_CRj); + break; + case FRV_OPERAND_CRJ_FLOAT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_CRj_float); + break; + case FRV_OPERAND_CRJ_INT : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & value); + value = ((value) + (4)); + fields->f_CRj_int = value; + } + break; + case FRV_OPERAND_CRK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 3, 32, total_length, pc, & fields->f_CRk); + break; + case FRV_OPERAND_FCCI_1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 2, 32, total_length, pc, & fields->f_FCCi_1); + break; + case FRV_OPERAND_FCCI_2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_FCCi_2); + break; + case FRV_OPERAND_FCCI_3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 2, 32, total_length, pc, & fields->f_FCCi_3); + break; + case FRV_OPERAND_FCCK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_FCCk); + break; + case FRV_OPERAND_FRDOUBLEI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); + break; + case FRV_OPERAND_FRDOUBLEJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); + break; + case FRV_OPERAND_FRDOUBLEK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_FRI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); + break; + case FRV_OPERAND_FRINTK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_FRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); + break; + case FRV_OPERAND_FRK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_FRKHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_FRKLO : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_GRDOUBLEK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk); + break; + case FRV_OPERAND_GRI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_GRi); + break; + case FRV_OPERAND_GRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_GRj); + break; + case FRV_OPERAND_GRK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk); + break; + case FRV_OPERAND_GRKHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk); + break; + case FRV_OPERAND_GRKLO : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk); + break; + case FRV_OPERAND_ICCI_1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 2, 32, total_length, pc, & fields->f_ICCi_1); + break; + case FRV_OPERAND_ICCI_2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_ICCi_2); + break; + case FRV_OPERAND_ICCI_3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 2, 32, total_length, pc, & fields->f_ICCi_3); + break; + case FRV_OPERAND_LI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_LI); + break; + case FRV_OPERAND_AE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_ae); + break; + case FRV_OPERAND_CCOND : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 1, 32, total_length, pc, & fields->f_ccond); + break; + case FRV_OPERAND_COND : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_cond); + break; + case FRV_OPERAND_D12 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_d12); + break; + case FRV_OPERAND_DEBUG : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_debug); + break; + case FRV_OPERAND_EIR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_eir); + break; + case FRV_OPERAND_HINT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 2, 32, total_length, pc, & fields->f_hint); + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 2, 32, total_length, pc, & fields->f_hint); + break; + case FRV_OPERAND_HINT_TAKEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 2, 32, total_length, pc, & fields->f_hint); + break; + case FRV_OPERAND_LABEL16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_label16 = value; + } + break; + case FRV_OPERAND_LABEL24 : + { + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_labelH6); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 18, 32, total_length, pc, & fields->f_labelL18); + if (length <= 0) break; +{ + FLD (f_label24) = ((((((((FLD (f_labelH6)) << (18))) | (FLD (f_labelL18)))) << (2))) + (pc)); +} + } + break; + case FRV_OPERAND_LOCK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_lock); + break; + case FRV_OPERAND_PACK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 1, 32, total_length, pc, & fields->f_pack); + break; + case FRV_OPERAND_S10 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s10); + break; + case FRV_OPERAND_S12 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_d12); + break; + case FRV_OPERAND_S16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s16); + break; + case FRV_OPERAND_S5 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s5); + break; + case FRV_OPERAND_S6 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s6); + break; + case FRV_OPERAND_S6_1 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s6_1); + break; + case FRV_OPERAND_SLO16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s16); + break; + case FRV_OPERAND_SPR : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_spr_h); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_spr_l); + if (length <= 0) break; +{ + FLD (f_spr) = ((((FLD (f_spr_h)) << (6))) | (FLD (f_spr_l))); +} + } + break; + case FRV_OPERAND_U12 : + { + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_u12_h); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_u12_l); + if (length <= 0) break; +{ + FLD (f_u12) = ((((FLD (f_u12_h)) << (6))) | (FLD (f_u12_l))); +} + } + break; + case FRV_OPERAND_U16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_u16); + break; + case FRV_OPERAND_U6 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_u6); + break; + case FRV_OPERAND_UHI16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_u16); + break; + case FRV_OPERAND_ULO16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_u16); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const frv_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const frv_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int frv_cgen_get_int_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +bfd_vma frv_cgen_get_vma_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +frv_cgen_get_int_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + int value; + + switch (opindex) + { + case FRV_OPERAND_A : + value = fields->f_A; + break; + case FRV_OPERAND_ACC40SI : + value = fields->f_ACC40Si; + break; + case FRV_OPERAND_ACC40SK : + value = fields->f_ACC40Sk; + break; + case FRV_OPERAND_ACC40UI : + value = fields->f_ACC40Ui; + break; + case FRV_OPERAND_ACC40UK : + value = fields->f_ACC40Uk; + break; + case FRV_OPERAND_ACCGI : + value = fields->f_ACCGi; + break; + case FRV_OPERAND_ACCGK : + value = fields->f_ACCGk; + break; + case FRV_OPERAND_CCI : + value = fields->f_CCi; + break; + case FRV_OPERAND_CPRDOUBLEK : + value = fields->f_CPRk; + break; + case FRV_OPERAND_CPRI : + value = fields->f_CPRi; + break; + case FRV_OPERAND_CPRJ : + value = fields->f_CPRj; + break; + case FRV_OPERAND_CPRK : + value = fields->f_CPRk; + break; + case FRV_OPERAND_CRI : + value = fields->f_CRi; + break; + case FRV_OPERAND_CRJ : + value = fields->f_CRj; + break; + case FRV_OPERAND_CRJ_FLOAT : + value = fields->f_CRj_float; + break; + case FRV_OPERAND_CRJ_INT : + value = fields->f_CRj_int; + break; + case FRV_OPERAND_CRK : + value = fields->f_CRk; + break; + case FRV_OPERAND_FCCI_1 : + value = fields->f_FCCi_1; + break; + case FRV_OPERAND_FCCI_2 : + value = fields->f_FCCi_2; + break; + case FRV_OPERAND_FCCI_3 : + value = fields->f_FCCi_3; + break; + case FRV_OPERAND_FCCK : + value = fields->f_FCCk; + break; + case FRV_OPERAND_FRDOUBLEI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRDOUBLEJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRDOUBLEK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRINTK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRKHI : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRKLO : + value = fields->f_FRk; + break; + case FRV_OPERAND_GRDOUBLEK : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRI : + value = fields->f_GRi; + break; + case FRV_OPERAND_GRJ : + value = fields->f_GRj; + break; + case FRV_OPERAND_GRK : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRKHI : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRKLO : + value = fields->f_GRk; + break; + case FRV_OPERAND_ICCI_1 : + value = fields->f_ICCi_1; + break; + case FRV_OPERAND_ICCI_2 : + value = fields->f_ICCi_2; + break; + case FRV_OPERAND_ICCI_3 : + value = fields->f_ICCi_3; + break; + case FRV_OPERAND_LI : + value = fields->f_LI; + break; + case FRV_OPERAND_AE : + value = fields->f_ae; + break; + case FRV_OPERAND_CCOND : + value = fields->f_ccond; + break; + case FRV_OPERAND_COND : + value = fields->f_cond; + break; + case FRV_OPERAND_D12 : + value = fields->f_d12; + break; + case FRV_OPERAND_DEBUG : + value = fields->f_debug; + break; + case FRV_OPERAND_EIR : + value = fields->f_eir; + break; + case FRV_OPERAND_HINT : + value = fields->f_hint; + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + value = fields->f_hint; + break; + case FRV_OPERAND_HINT_TAKEN : + value = fields->f_hint; + break; + case FRV_OPERAND_LABEL16 : + value = fields->f_label16; + break; + case FRV_OPERAND_LABEL24 : + value = fields->f_label24; + break; + case FRV_OPERAND_LOCK : + value = fields->f_lock; + break; + case FRV_OPERAND_PACK : + value = fields->f_pack; + break; + case FRV_OPERAND_S10 : + value = fields->f_s10; + break; + case FRV_OPERAND_S12 : + value = fields->f_d12; + break; + case FRV_OPERAND_S16 : + value = fields->f_s16; + break; + case FRV_OPERAND_S5 : + value = fields->f_s5; + break; + case FRV_OPERAND_S6 : + value = fields->f_s6; + break; + case FRV_OPERAND_S6_1 : + value = fields->f_s6_1; + break; + case FRV_OPERAND_SLO16 : + value = fields->f_s16; + break; + case FRV_OPERAND_SPR : + value = fields->f_spr; + break; + case FRV_OPERAND_U12 : + value = fields->f_u12; + break; + case FRV_OPERAND_U16 : + value = fields->f_u16; + break; + case FRV_OPERAND_U6 : + value = fields->f_u6; + break; + case FRV_OPERAND_UHI16 : + value = fields->f_u16; + break; + case FRV_OPERAND_ULO16 : + value = fields->f_u16; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +frv_cgen_get_vma_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + bfd_vma value; + + switch (opindex) + { + case FRV_OPERAND_A : + value = fields->f_A; + break; + case FRV_OPERAND_ACC40SI : + value = fields->f_ACC40Si; + break; + case FRV_OPERAND_ACC40SK : + value = fields->f_ACC40Sk; + break; + case FRV_OPERAND_ACC40UI : + value = fields->f_ACC40Ui; + break; + case FRV_OPERAND_ACC40UK : + value = fields->f_ACC40Uk; + break; + case FRV_OPERAND_ACCGI : + value = fields->f_ACCGi; + break; + case FRV_OPERAND_ACCGK : + value = fields->f_ACCGk; + break; + case FRV_OPERAND_CCI : + value = fields->f_CCi; + break; + case FRV_OPERAND_CPRDOUBLEK : + value = fields->f_CPRk; + break; + case FRV_OPERAND_CPRI : + value = fields->f_CPRi; + break; + case FRV_OPERAND_CPRJ : + value = fields->f_CPRj; + break; + case FRV_OPERAND_CPRK : + value = fields->f_CPRk; + break; + case FRV_OPERAND_CRI : + value = fields->f_CRi; + break; + case FRV_OPERAND_CRJ : + value = fields->f_CRj; + break; + case FRV_OPERAND_CRJ_FLOAT : + value = fields->f_CRj_float; + break; + case FRV_OPERAND_CRJ_INT : + value = fields->f_CRj_int; + break; + case FRV_OPERAND_CRK : + value = fields->f_CRk; + break; + case FRV_OPERAND_FCCI_1 : + value = fields->f_FCCi_1; + break; + case FRV_OPERAND_FCCI_2 : + value = fields->f_FCCi_2; + break; + case FRV_OPERAND_FCCI_3 : + value = fields->f_FCCi_3; + break; + case FRV_OPERAND_FCCK : + value = fields->f_FCCk; + break; + case FRV_OPERAND_FRDOUBLEI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRDOUBLEJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRDOUBLEK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRINTK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRKHI : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRKLO : + value = fields->f_FRk; + break; + case FRV_OPERAND_GRDOUBLEK : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRI : + value = fields->f_GRi; + break; + case FRV_OPERAND_GRJ : + value = fields->f_GRj; + break; + case FRV_OPERAND_GRK : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRKHI : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRKLO : + value = fields->f_GRk; + break; + case FRV_OPERAND_ICCI_1 : + value = fields->f_ICCi_1; + break; + case FRV_OPERAND_ICCI_2 : + value = fields->f_ICCi_2; + break; + case FRV_OPERAND_ICCI_3 : + value = fields->f_ICCi_3; + break; + case FRV_OPERAND_LI : + value = fields->f_LI; + break; + case FRV_OPERAND_AE : + value = fields->f_ae; + break; + case FRV_OPERAND_CCOND : + value = fields->f_ccond; + break; + case FRV_OPERAND_COND : + value = fields->f_cond; + break; + case FRV_OPERAND_D12 : + value = fields->f_d12; + break; + case FRV_OPERAND_DEBUG : + value = fields->f_debug; + break; + case FRV_OPERAND_EIR : + value = fields->f_eir; + break; + case FRV_OPERAND_HINT : + value = fields->f_hint; + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + value = fields->f_hint; + break; + case FRV_OPERAND_HINT_TAKEN : + value = fields->f_hint; + break; + case FRV_OPERAND_LABEL16 : + value = fields->f_label16; + break; + case FRV_OPERAND_LABEL24 : + value = fields->f_label24; + break; + case FRV_OPERAND_LOCK : + value = fields->f_lock; + break; + case FRV_OPERAND_PACK : + value = fields->f_pack; + break; + case FRV_OPERAND_S10 : + value = fields->f_s10; + break; + case FRV_OPERAND_S12 : + value = fields->f_d12; + break; + case FRV_OPERAND_S16 : + value = fields->f_s16; + break; + case FRV_OPERAND_S5 : + value = fields->f_s5; + break; + case FRV_OPERAND_S6 : + value = fields->f_s6; + break; + case FRV_OPERAND_S6_1 : + value = fields->f_s6_1; + break; + case FRV_OPERAND_SLO16 : + value = fields->f_s16; + break; + case FRV_OPERAND_SPR : + value = fields->f_spr; + break; + case FRV_OPERAND_U12 : + value = fields->f_u12; + break; + case FRV_OPERAND_U16 : + value = fields->f_u16; + break; + case FRV_OPERAND_U6 : + value = fields->f_u6; + break; + case FRV_OPERAND_UHI16 : + value = fields->f_u16; + break; + case FRV_OPERAND_ULO16 : + value = fields->f_u16; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void frv_cgen_set_int_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); +void frv_cgen_set_vma_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +frv_cgen_set_int_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + int value; +{ + switch (opindex) + { + case FRV_OPERAND_A : + fields->f_A = value; + break; + case FRV_OPERAND_ACC40SI : + fields->f_ACC40Si = value; + break; + case FRV_OPERAND_ACC40SK : + fields->f_ACC40Sk = value; + break; + case FRV_OPERAND_ACC40UI : + fields->f_ACC40Ui = value; + break; + case FRV_OPERAND_ACC40UK : + fields->f_ACC40Uk = value; + break; + case FRV_OPERAND_ACCGI : + fields->f_ACCGi = value; + break; + case FRV_OPERAND_ACCGK : + fields->f_ACCGk = value; + break; + case FRV_OPERAND_CCI : + fields->f_CCi = value; + break; + case FRV_OPERAND_CPRDOUBLEK : + fields->f_CPRk = value; + break; + case FRV_OPERAND_CPRI : + fields->f_CPRi = value; + break; + case FRV_OPERAND_CPRJ : + fields->f_CPRj = value; + break; + case FRV_OPERAND_CPRK : + fields->f_CPRk = value; + break; + case FRV_OPERAND_CRI : + fields->f_CRi = value; + break; + case FRV_OPERAND_CRJ : + fields->f_CRj = value; + break; + case FRV_OPERAND_CRJ_FLOAT : + fields->f_CRj_float = value; + break; + case FRV_OPERAND_CRJ_INT : + fields->f_CRj_int = value; + break; + case FRV_OPERAND_CRK : + fields->f_CRk = value; + break; + case FRV_OPERAND_FCCI_1 : + fields->f_FCCi_1 = value; + break; + case FRV_OPERAND_FCCI_2 : + fields->f_FCCi_2 = value; + break; + case FRV_OPERAND_FCCI_3 : + fields->f_FCCi_3 = value; + break; + case FRV_OPERAND_FCCK : + fields->f_FCCk = value; + break; + case FRV_OPERAND_FRDOUBLEI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRDOUBLEJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRDOUBLEK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRINTK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRKHI : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRKLO : + fields->f_FRk = value; + break; + case FRV_OPERAND_GRDOUBLEK : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRI : + fields->f_GRi = value; + break; + case FRV_OPERAND_GRJ : + fields->f_GRj = value; + break; + case FRV_OPERAND_GRK : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRKHI : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRKLO : + fields->f_GRk = value; + break; + case FRV_OPERAND_ICCI_1 : + fields->f_ICCi_1 = value; + break; + case FRV_OPERAND_ICCI_2 : + fields->f_ICCi_2 = value; + break; + case FRV_OPERAND_ICCI_3 : + fields->f_ICCi_3 = value; + break; + case FRV_OPERAND_LI : + fields->f_LI = value; + break; + case FRV_OPERAND_AE : + fields->f_ae = value; + break; + case FRV_OPERAND_CCOND : + fields->f_ccond = value; + break; + case FRV_OPERAND_COND : + fields->f_cond = value; + break; + case FRV_OPERAND_D12 : + fields->f_d12 = value; + break; + case FRV_OPERAND_DEBUG : + fields->f_debug = value; + break; + case FRV_OPERAND_EIR : + fields->f_eir = value; + break; + case FRV_OPERAND_HINT : + fields->f_hint = value; + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + fields->f_hint = value; + break; + case FRV_OPERAND_HINT_TAKEN : + fields->f_hint = value; + break; + case FRV_OPERAND_LABEL16 : + fields->f_label16 = value; + break; + case FRV_OPERAND_LABEL24 : + fields->f_label24 = value; + break; + case FRV_OPERAND_LOCK : + fields->f_lock = value; + break; + case FRV_OPERAND_PACK : + fields->f_pack = value; + break; + case FRV_OPERAND_S10 : + fields->f_s10 = value; + break; + case FRV_OPERAND_S12 : + fields->f_d12 = value; + break; + case FRV_OPERAND_S16 : + fields->f_s16 = value; + break; + case FRV_OPERAND_S5 : + fields->f_s5 = value; + break; + case FRV_OPERAND_S6 : + fields->f_s6 = value; + break; + case FRV_OPERAND_S6_1 : + fields->f_s6_1 = value; + break; + case FRV_OPERAND_SLO16 : + fields->f_s16 = value; + break; + case FRV_OPERAND_SPR : + fields->f_spr = value; + break; + case FRV_OPERAND_U12 : + fields->f_u12 = value; + break; + case FRV_OPERAND_U16 : + fields->f_u16 = value; + break; + case FRV_OPERAND_U6 : + fields->f_u6 = value; + break; + case FRV_OPERAND_UHI16 : + fields->f_u16 = value; + break; + case FRV_OPERAND_ULO16 : + fields->f_u16 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +frv_cgen_set_vma_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + bfd_vma value; +{ + switch (opindex) + { + case FRV_OPERAND_A : + fields->f_A = value; + break; + case FRV_OPERAND_ACC40SI : + fields->f_ACC40Si = value; + break; + case FRV_OPERAND_ACC40SK : + fields->f_ACC40Sk = value; + break; + case FRV_OPERAND_ACC40UI : + fields->f_ACC40Ui = value; + break; + case FRV_OPERAND_ACC40UK : + fields->f_ACC40Uk = value; + break; + case FRV_OPERAND_ACCGI : + fields->f_ACCGi = value; + break; + case FRV_OPERAND_ACCGK : + fields->f_ACCGk = value; + break; + case FRV_OPERAND_CCI : + fields->f_CCi = value; + break; + case FRV_OPERAND_CPRDOUBLEK : + fields->f_CPRk = value; + break; + case FRV_OPERAND_CPRI : + fields->f_CPRi = value; + break; + case FRV_OPERAND_CPRJ : + fields->f_CPRj = value; + break; + case FRV_OPERAND_CPRK : + fields->f_CPRk = value; + break; + case FRV_OPERAND_CRI : + fields->f_CRi = value; + break; + case FRV_OPERAND_CRJ : + fields->f_CRj = value; + break; + case FRV_OPERAND_CRJ_FLOAT : + fields->f_CRj_float = value; + break; + case FRV_OPERAND_CRJ_INT : + fields->f_CRj_int = value; + break; + case FRV_OPERAND_CRK : + fields->f_CRk = value; + break; + case FRV_OPERAND_FCCI_1 : + fields->f_FCCi_1 = value; + break; + case FRV_OPERAND_FCCI_2 : + fields->f_FCCi_2 = value; + break; + case FRV_OPERAND_FCCI_3 : + fields->f_FCCi_3 = value; + break; + case FRV_OPERAND_FCCK : + fields->f_FCCk = value; + break; + case FRV_OPERAND_FRDOUBLEI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRDOUBLEJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRDOUBLEK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRINTK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRKHI : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRKLO : + fields->f_FRk = value; + break; + case FRV_OPERAND_GRDOUBLEK : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRI : + fields->f_GRi = value; + break; + case FRV_OPERAND_GRJ : + fields->f_GRj = value; + break; + case FRV_OPERAND_GRK : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRKHI : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRKLO : + fields->f_GRk = value; + break; + case FRV_OPERAND_ICCI_1 : + fields->f_ICCi_1 = value; + break; + case FRV_OPERAND_ICCI_2 : + fields->f_ICCi_2 = value; + break; + case FRV_OPERAND_ICCI_3 : + fields->f_ICCi_3 = value; + break; + case FRV_OPERAND_LI : + fields->f_LI = value; + break; + case FRV_OPERAND_AE : + fields->f_ae = value; + break; + case FRV_OPERAND_CCOND : + fields->f_ccond = value; + break; + case FRV_OPERAND_COND : + fields->f_cond = value; + break; + case FRV_OPERAND_D12 : + fields->f_d12 = value; + break; + case FRV_OPERAND_DEBUG : + fields->f_debug = value; + break; + case FRV_OPERAND_EIR : + fields->f_eir = value; + break; + case FRV_OPERAND_HINT : + fields->f_hint = value; + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + fields->f_hint = value; + break; + case FRV_OPERAND_HINT_TAKEN : + fields->f_hint = value; + break; + case FRV_OPERAND_LABEL16 : + fields->f_label16 = value; + break; + case FRV_OPERAND_LABEL24 : + fields->f_label24 = value; + break; + case FRV_OPERAND_LOCK : + fields->f_lock = value; + break; + case FRV_OPERAND_PACK : + fields->f_pack = value; + break; + case FRV_OPERAND_S10 : + fields->f_s10 = value; + break; + case FRV_OPERAND_S12 : + fields->f_d12 = value; + break; + case FRV_OPERAND_S16 : + fields->f_s16 = value; + break; + case FRV_OPERAND_S5 : + fields->f_s5 = value; + break; + case FRV_OPERAND_S6 : + fields->f_s6 = value; + break; + case FRV_OPERAND_S6_1 : + fields->f_s6_1 = value; + break; + case FRV_OPERAND_SLO16 : + fields->f_s16 = value; + break; + case FRV_OPERAND_SPR : + fields->f_spr = value; + break; + case FRV_OPERAND_U12 : + fields->f_u12 = value; + break; + case FRV_OPERAND_U16 : + fields->f_u16 = value; + break; + case FRV_OPERAND_U6 : + fields->f_u6 = value; + break; + case FRV_OPERAND_UHI16 : + fields->f_u16 = value; + break; + case FRV_OPERAND_ULO16 : + fields->f_u16 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +frv_cgen_init_ibld_table (cd) + CGEN_CPU_DESC cd; +{ + cd->insert_handlers = & frv_cgen_insert_handlers[0]; + cd->extract_handlers = & frv_cgen_extract_handlers[0]; + + cd->insert_operand = frv_cgen_insert_operand; + cd->extract_operand = frv_cgen_extract_operand; + + cd->get_int_operand = frv_cgen_get_int_operand; + cd->set_int_operand = frv_cgen_set_int_operand; + cd->get_vma_operand = frv_cgen_get_vma_operand; + cd->set_vma_operand = frv_cgen_set_vma_operand; +} diff -uprN binutils-2.12.90.0.11/opcodes/frv-opc.c binutils-2.12.90.0.12/opcodes/frv-opc.c --- binutils-2.12.90.0.11/opcodes/frv-opc.c Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/opcodes/frv-opc.c Tue Jun 18 21:41:59 2002 @@ -0,0 +1,5842 @@ +/* Instruction opcode table for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "libiberty.h" + +/* -- opc.c */ +#include "elf/frv.h" + +static int match_unit + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, CGEN_ATTR_VALUE_TYPE)); +static int match_vliw + PARAMS ((VLIW_COMBO *, VLIW_COMBO *, int)); +static VLIW_COMBO * add_next_to_vliw + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int find_major_in_vliw + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int fr400_check_insn_major_constraints + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int fr500_check_insn_major_constraints + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int check_insn_major_constraints + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); + +int +frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +{ + switch (mach) + { + case bfd_mach_fr400: + if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6) + return 1; /* is a branch */ + break; + default: + if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6) + return 1; /* is a branch */ + break; + } + + return 0; /* not a branch */ +} + +int +frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +{ + switch (mach) + { + case bfd_mach_fr400: + return 0; /* No float insns */ + default: + if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8) + return 1; /* is a float insn */ + break; + } + + return 0; /* not a branch */ +} + +int +frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +{ + switch (mach) + { + case bfd_mach_fr400: + if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2) + return 1; /* is a media insn */ + break; + default: + if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8) + return 1; /* is a media insn */ + break; + } + + return 0; /* not a branch */ +} + +int +frv_is_branch_insn (const CGEN_INSN *insn) +{ + if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), + bfd_mach_fr400)) + return 1; + if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), + bfd_mach_fr500)) + return 1; + + return 0; +} + +int +frv_is_float_insn (const CGEN_INSN *insn) +{ + if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), + bfd_mach_fr400)) + return 1; + if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), + bfd_mach_fr500)) + return 1; + + return 0; +} + +int +frv_is_media_insn (const CGEN_INSN *insn) +{ + if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), + bfd_mach_fr400)) + return 1; + if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), + bfd_mach_fr500)) + return 1; + + return 0; +} + +/* This table represents the allowable packing for vliw insns for the fr400. + The fr400 has only 2 vliw slots. Represent this by not allowing any insns + in slots 2 and 3. + Subsets of any given row are also allowed. */ +static VLIW_COMBO fr400_allowed_vliw[] = +{ + /* slot0 slot1 slot2 slot3 */ + { UNIT_I0, UNIT_I1, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_B0, UNIT_NIL, UNIT_NIL }, + { UNIT_FM0, UNIT_FM1, UNIT_NIL, UNIT_NIL }, + { UNIT_FM0, UNIT_B0, UNIT_NIL, UNIT_NIL }, + { UNIT_B0, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_C, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL } +}; + +/* This table represents the allowable packing for vliw insns for the fr500. + Subsets of any given row are also allowed. */ +static VLIW_COMBO fr500_allowed_vliw[] = +{ + /* slot0 slot1 slot2 slot3 */ + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_B0 }, + { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_B0 }, + { UNIT_I0, UNIT_FM0, UNIT_B0, UNIT_B1 }, + { UNIT_I0, UNIT_I1, UNIT_B0, UNIT_B1 }, + { UNIT_I0, UNIT_B0, UNIT_B1, UNIT_NIL }, + { UNIT_FM0, UNIT_FM1, UNIT_B0, UNIT_B1 }, + { UNIT_FM0, UNIT_B0, UNIT_B1, UNIT_NIL }, + { UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, + { UNIT_C, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL } +}; + +/* Some insns are assigned specialized implementation units which map to + different actual implementation units on different machines. These + tables perform that mapping. */ +static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] = +{ +/* unit in insn actual unit */ +/* NIL */ UNIT_NIL, +/* I0 */ UNIT_I0, +/* I1 */ UNIT_I1, +/* I01 */ UNIT_I01, +/* FM0 */ UNIT_FM0, +/* FM1 */ UNIT_FM1, +/* FM01 */ UNIT_FM01, +/* B0 */ UNIT_B0, /* branches only in B0 unit. */ +/* B1 */ UNIT_B0, +/* B01 */ UNIT_B0, +/* C */ UNIT_C, +/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */ +/* LOAD */ UNIT_I0 /* load only in I0 unit. */ +}; + +static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = +{ +/* unit in insn actual unit */ +/* NIL */ UNIT_NIL, +/* I0 */ UNIT_I0, +/* I1 */ UNIT_I1, +/* I01 */ UNIT_I01, +/* FM0 */ UNIT_FM0, +/* FM1 */ UNIT_FM1, +/* FM01 */ UNIT_FM01, +/* B0 */ UNIT_B0, +/* B1 */ UNIT_B1, +/* B01 */ UNIT_B01, +/* C */ UNIT_C, +/* MULT-DIV */ UNIT_I01, /* multiply and divide in I0 or I1 unit. */ +/* LOAD */ UNIT_I01 /* load in I0 or I1 unit. */ +}; + +void +frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags) +{ + vliw->next_slot = 0; + vliw->constraint_violation = 0; + vliw->mach = mach; + vliw->elf_flags = elf_flags; + + switch (mach) + { + case bfd_mach_fr400: + vliw->current_vliw = fr400_allowed_vliw; + vliw->unit_mapping = fr400_unit_mapping; + break; + default: + vliw->current_vliw = fr500_allowed_vliw; + vliw->unit_mapping = fr500_unit_mapping; + break; + } +} + +/* Return 1 if unit1 is a match for unit2. + Unit1 comes from the insn's UNIT attribute. unit2 comes from one of the + *_allowed_vliw tables above. */ +static int +match_unit (FRV_VLIW *vliw, + CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2) +{ + /* Map any specialized implementation units to actual ones. */ + unit1 = vliw->unit_mapping[unit1]; + + if (unit1 == unit2) + return 1; + if (unit1 < unit2) + return 0; + + switch (unit1) + { + case UNIT_I01: + case UNIT_FM01: + case UNIT_B01: + /* The 01 versions of these units are within 2 enums of the 0 or 1 + versions. */ + if (unit1 - unit2 <= 2) + return 1; + break; + default: + break; + } + + return 0; +} + +/* Return 1 if the vliws match, 0 otherwise. */ + +static int +match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size) +{ + int i; + + for (i = 0; i < vliw_size; ++i) + { + if ((*vliw1)[i] != (*vliw2)[i]) + return 0; + } + + return 1; +} + +/* Find the next vliw vliw in the table that can accomodate the new insn. + If one is found then return it. Otherwise return NULL. */ + +static VLIW_COMBO * +add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) +{ + int next = vliw->next_slot; + VLIW_COMBO *current = vliw->current_vliw; + VLIW_COMBO *potential; + + if (next <= 0) + abort (); /* Should never happen */ + + /* The table is sorted by units allowed within slots, so vliws with + identical starting sequences are together. */ + potential = current; + do + { + if (match_unit (vliw, unit, (*potential)[next])) + return potential; + ++potential; + } + while (match_vliw (potential, current, next)); + + return NULL; +} + +/* Look for the given major insn type in the given vliw. Return 1 if found, + return 0 otherwise. */ + +static int +find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +{ + int i; + + for (i = 0; i < vliw->next_slot; ++i) + if (vliw->major[i] == major) + return 1; + + return 0; +} + +/* Check for constraints between the insns in the vliw due to major insn + types. */ + +static int +fr400_check_insn_major_constraints ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major +) +{ + /* In the cpu file, all media insns are represented as being allowed in + both media units. This makes it easier since this is the case for fr500. + Catch the invalid combinations here. Insns of major class FR400_MAJOR_M_2 + cannot coexist with any other media insn in a vliw. */ + switch (major) + { + case FR400_MAJOR_M_2: + return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1) + && ! find_major_in_vliw (vliw, FR400_MAJOR_M_2); + default: + break; + } + return 1; +} + +static int +fr500_check_insn_major_constraints ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major +) +{ + /* TODO: A table might be faster for some of the more complex instances + here. */ + switch (major) + { + case FR500_MAJOR_I_1: + case FR500_MAJOR_I_4: + case FR500_MAJOR_I_5: + case FR500_MAJOR_I_6: + case FR500_MAJOR_B_1: + case FR500_MAJOR_B_2: + case FR500_MAJOR_B_3: + case FR500_MAJOR_B_4: + case FR500_MAJOR_B_5: + case FR500_MAJOR_B_6: + case FR500_MAJOR_F_4: + case FR500_MAJOR_F_8: + case FR500_MAJOR_M_8: + return 1; /* OK */ + case FR500_MAJOR_I_2: + /* Cannot coexist with I-3 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_I_3); + case FR500_MAJOR_I_3: + /* Cannot coexist with I-2 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_I_2); + case FR500_MAJOR_F_1: + case FR500_MAJOR_F_2: + /* Cannot coexist with F-5, F-6, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_3: + /* Cannot coexist with F-7, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_5: + /* Cannot coexist with F-1, F-2, F-6, F-7, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_6: + /* Cannot coexist with F-1, F-2, F-5, F-6, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_7: + /* Cannot coexist with F-3, F-5, F-7, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_1: + /* Cannot coexist with M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_2: + case FR500_MAJOR_M_3: + /* Cannot coexist with M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_4: + /* Cannot coexist with M-6 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_6); + case FR500_MAJOR_M_5: + /* Cannot coexist with M-2, M-3, M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_6: + /* Cannot coexist with M-2, M-3, M-4, M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_4) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_7: + /* Cannot coexist with M-1, M-2, M-3, M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7); + default: + abort (); + break; + } + return 1; +} + +static int +check_insn_major_constraints ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major +) +{ + int rc; + switch (vliw->mach) + { + case bfd_mach_fr400: + rc = fr400_check_insn_major_constraints (vliw, major); + break; + default: + rc = fr500_check_insn_major_constraints (vliw, major); + break; + } + return rc; +} + +/* Add in insn to the VLIW vliw if possible. Return 0 if successful, + non-zero otherwise. */ +int +frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) +{ + int index; + CGEN_ATTR_VALUE_TYPE major; + CGEN_ATTR_VALUE_TYPE unit; + VLIW_COMBO *new_vliw; + + if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn)) + return 1; + + index = vliw->next_slot; + if (index >= FRV_VLIW_SIZE) + return 1; + + unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT); + if (unit == UNIT_NIL) + abort (); /* no UNIT specified for this insn in frv.cpu */ + + if (vliw->mach == bfd_mach_fr400) + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR); + else + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR); + + if (index <= 0) + { + /* Any insn can be added to slot 0. */ + while (! match_unit (vliw, unit, (*vliw->current_vliw)[0])) + ++vliw->current_vliw; + vliw->major[0] = major; + vliw->next_slot = 1; + return 0; + } + + /* If there are already insns in the vliw(s) check to see that + this one can be added. Do this by finding an allowable vliw + combination that can accept the new insn. */ + if (! (vliw->elf_flags & EF_FRV_NOPACK)) + { + new_vliw = add_next_to_vliw (vliw, unit); + if (new_vliw && check_insn_major_constraints (vliw, major)) + { + vliw->current_vliw = new_vliw; + vliw->major[index] = major; + vliw->next_slot++; + return 0; + } + + /* The frv machine supports all packing conbinations. If we fail, + to add the insn, then it could not be handled as if it was the fr500. + Just return as if it was handled ok. */ + if (vliw->mach == bfd_mach_frv) + return 0; + } + + vliw->constraint_violation = 1; + return 1; +} + +int +spr_valid (regno) + long regno; +{ + if (regno < 0) return 0; + if (regno <= 4095) return 1; + return 0; +} +/* -- */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); + +/* Instruction formats. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & frv_cgen_ifld_table[FRV_##f] +#else +#define F(f) & frv_cgen_ifld_table[FRV_/**/f] +#endif +static const CGEN_IFMT ifmt_empty = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_add = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1_NULL) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_not = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_ICCI_1_NULL) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smul = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1_NULL) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cadd = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cnot = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_csmul = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addcc = { + 32, 32, 0x1fc03c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smulcc = { + 32, 32, 0x1fc03c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smuli = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addicc = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_S10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smulicc = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_S10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmpb = { + 32, 32, 0x7ffc03c0, { { F (F_PACK) }, { F (F_GRK_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_setlo = { + 32, 32, 0x1ff0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_MISC_NULL_4) }, { F (F_U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sethi = { + 32, 32, 0x1ff0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_MISC_NULL_4) }, { F (F_U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_setlos = { + 32, 32, 0x1ff0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_MISC_NULL_4) }, { F (F_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldsb = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldbf = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldc = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldd = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lddf = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lddc = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldsbi = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldbfi = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lddi = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lddfi = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stdf = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cldbf = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clddf = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cstdf = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stdfi = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgf = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmovgf = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgs = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_OP) }, { F (F_SPR) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bra = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bno = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beq = { + 32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbra = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbno = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbne = { + 32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bctrlr = { + 32, 32, 0x7ffcefff, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bralr = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bnolr = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beqlr = { + 32, 32, 0x79fcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbralr = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbnolr = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbeqlr = { + 32, 32, 0x79fcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bcralr = { + 32, 32, 0x7ffcefff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bceqlr = { + 32, 32, 0x79fcefff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcbralr = { + 32, 32, 0x7ffcefff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcbeqlr = { + 32, 32, 0x79fcefff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpl = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_OFF) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_calll = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_ON) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpil = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_OFF) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_callil = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_ON) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_call = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_OP) }, { F (F_LABEL24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rett = { + 32, 32, 0x7dffffff, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_DEBUG) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rei = { + 32, 32, 0x7ffc0fff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_EIR) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tra = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tno = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_teq = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftra = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftno = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftne = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tira = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tino = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tieq = { + 32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftira = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftino = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftine = { + 32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_break = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_andcr = { + 32, 32, 0x71ff8ff8, { { F (F_PACK) }, { F (F_MISC_NULL_6) }, { F (F_CRK) }, { F (F_OP) }, { F (F_MISC_NULL_7) }, { F (F_CRI) }, { F (F_OPE1) }, { F (F_MISC_NULL_8) }, { F (F_CRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_notcr = { + 32, 32, 0x71fffff8, { { F (F_PACK) }, { F (F_MISC_NULL_6) }, { F (F_CRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_8) }, { F (F_CRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ckra = { + 32, 32, 0x79ffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_MISC_NULL_5) }, { F (F_ICCI_3_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ckeq = { + 32, 32, 0x79fffffc, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_MISC_NULL_5) }, { F (F_ICCI_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fckra = { + 32, 32, 0x79fffffc, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_CRJ_FLOAT) }, { F (F_OP) }, { F (F_MISC_NULL_5) }, { F (F_FCCI_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cckra = { + 32, 32, 0x79fff0ff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_ICCI_3_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cckeq = { + 32, 32, 0x79fff0fc, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_ICCI_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfckra = { + 32, 32, 0x79fff0ff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_CRJ_FLOAT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_FCCI_3_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfckne = { + 32, 32, 0x79fff0fc, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_CRJ_FLOAT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_FCCI_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cjmpl = { + 32, 32, 0x7ffc00c0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_OFF) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ccalll = { + 32, 32, 0x7ffc00c0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_ON) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ici = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_icei = { + 32, 32, 0x7dfc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_AE) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_icpl = { + 32, 32, 0x7dfc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LOCK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_icul = { + 32, 32, 0x7ffc0fff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bar = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cop1 = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_CPRI) }, { F (F_S6_1) }, { F (F_CPRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clrgr = { + 32, 32, 0x1ffffff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clrfr = { + 32, 32, 0x1ffffff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fitos = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fstoi = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fitod = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fdtoi = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfitos = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfstoi = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fmovs = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fmovd = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfmovs = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fadds = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_faddd = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfadds = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcmps = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcmpd = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfcmps = { + 32, 32, 0x79fc00c0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhsetlos = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_OPE1) }, { F (F_U12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhsethis = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_OPE1) }, { F (F_U12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhdsets = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_OPE1) }, { F (F_U12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhsetloh = { + 32, 32, 0x1ffffe0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_11) }, { F (F_S5) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhsethih = { + 32, 32, 0x1ffffe0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_11) }, { F (F_S5) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhdseth = { + 32, 32, 0x1ffffe0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_11) }, { F (F_S5) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mand = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmand = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mnot = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmnot = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrotli = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_U6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mcut = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mcuti = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mcmpsh = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mabshs = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_maddaccs = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_ACCJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mmulhs = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmmulhs = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mmachu = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmmachu = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmexpdhw = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_U6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_munpackh = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmbtoh = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mclracc = { + 32, 32, 0x1fdffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrdacc = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrdaccg = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACCGI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mwtacc = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mwtaccg = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACCGK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fnop = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +#undef F + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) FRV_OPERAND_##op +#else +#define OPERAND(op) FRV_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x0 } + }, +/* sub$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x100 } + }, +/* and$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40000 } + }, +/* or$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40080 } + }, +/* xor$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40100 } + }, +/* not$pack $GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_not, { 0x40180 } + }, +/* sdiv$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x380 } + }, +/* nsdiv$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40380 } + }, +/* udiv$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x3c0 } + }, +/* nudiv$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x403c0 } + }, +/* smul$pack $GRi,$GRj,$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), 0 } }, + & ifmt_smul, { 0x200 } + }, +/* umul$pack $GRi,$GRj,$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), 0 } }, + & ifmt_smul, { 0x280 } + }, +/* sll$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40200 } + }, +/* srl$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40280 } + }, +/* sra$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40300 } + }, +/* scan$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x2c0000 } + }, +/* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1600000 } + }, +/* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1600040 } + }, +/* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1680000 } + }, +/* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1680040 } + }, +/* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1680080 } + }, +/* cnot$pack $GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cnot, { 0x16800c0 } + }, +/* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x1600080 } + }, +/* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16000c0 } + }, +/* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16400c0 } + }, +/* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1700000 } + }, +/* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1700040 } + }, +/* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1700080 } + }, +/* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19400c0 } + }, +/* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40 } + }, +/* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x140 } + }, +/* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40040 } + }, +/* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x400c0 } + }, +/* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40140 } + }, +/* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40240 } + }, +/* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x402c0 } + }, +/* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40340 } + }, +/* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } }, + & ifmt_smulcc, { 0x240 } + }, +/* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } }, + & ifmt_smulcc, { 0x2c0 } + }, +/* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1640000 } + }, +/* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1640040 } + }, +/* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x1640080 } + }, +/* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16c0000 } + }, +/* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16c0040 } + }, +/* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16c0080 } + }, +/* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1740000 } + }, +/* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1740040 } + }, +/* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1740080 } + }, +/* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x80 } + }, +/* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x180 } + }, +/* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0xc0 } + }, +/* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x1c0 } + }, +/* addi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x400000 } + }, +/* subi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x500000 } + }, +/* andi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x800000 } + }, +/* ori$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x880000 } + }, +/* xori$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x900000 } + }, +/* sdivi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x780000 } + }, +/* nsdivi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xb80000 } + }, +/* udivi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x7c0000 } + }, +/* nudivi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xbc0000 } + }, +/* smuli$pack $GRi,$s12,$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRDOUBLEK), 0 } }, + & ifmt_smuli, { 0x600000 } + }, +/* umuli$pack $GRi,$s12,$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRDOUBLEK), 0 } }, + & ifmt_smuli, { 0x680000 } + }, +/* slli$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xa00000 } + }, +/* srli$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xa80000 } + }, +/* srai$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xb00000 } + }, +/* scani$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x11c0000 } + }, +/* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x440000 } + }, +/* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x540000 } + }, +/* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x840000 } + }, +/* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x8c0000 } + }, +/* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x940000 } + }, +/* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } }, + & ifmt_smulicc, { 0x640000 } + }, +/* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } }, + & ifmt_smulicc, { 0x6c0000 } + }, +/* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0xa40000 } + }, +/* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0xac0000 } + }, +/* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0xb40000 } + }, +/* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x480000 } + }, +/* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x580000 } + }, +/* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x4c0000 } + }, +/* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x5c0000 } + }, +/* cmpb$pack $GRi,$GRj,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (ICCI_1), 0 } }, + & ifmt_cmpb, { 0x300 } + }, +/* cmpba$pack $GRi,$GRj,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (ICCI_1), 0 } }, + & ifmt_cmpb, { 0x340 } + }, +/* setlo$pack $ulo16,$GRklo */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ULO16), ',', OP (GRKLO), 0 } }, + & ifmt_setlo, { 0xf40000 } + }, +/* sethi$pack $uhi16,$GRkhi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (UHI16), ',', OP (GRKHI), 0 } }, + & ifmt_sethi, { 0xf80000 } + }, +/* setlos$pack $slo16,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (SLO16), ',', OP (GRK), 0 } }, + & ifmt_setlos, { 0xfc0000 } + }, +/* ldsb$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80000 } + }, +/* ldub$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80040 } + }, +/* ldsh$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80080 } + }, +/* lduh$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x800c0 } + }, +/* ld$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80100 } + }, +/* ldbf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80200 } + }, +/* ldhf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80240 } + }, +/* ldf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80280 } + }, +/* ldc$pack @($GRi,$GRj),$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } }, + & ifmt_ldc, { 0x80340 } + }, +/* nldsb$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80800 } + }, +/* nldub$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80840 } + }, +/* nldsh$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80880 } + }, +/* nlduh$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x808c0 } + }, +/* nld$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80900 } + }, +/* nldbf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80a00 } + }, +/* nldhf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80a40 } + }, +/* nldf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80a80 } + }, +/* ldd$pack @($GRi,$GRj),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_ldd, { 0x80140 } + }, +/* lddf$pack @($GRi,$GRj),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddf, { 0x802c0 } + }, +/* lddc$pack @($GRi,$GRj),$CPRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRDOUBLEK), 0 } }, + & ifmt_lddc, { 0x80380 } + }, +/* nldd$pack @($GRi,$GRj),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_ldd, { 0x80940 } + }, +/* nlddf$pack @($GRi,$GRj),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddf, { 0x80ac0 } + }, +/* ldq$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80180 } + }, +/* ldqf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80300 } + }, +/* ldqc$pack @($GRi,$GRj),$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } }, + & ifmt_ldc, { 0x803c0 } + }, +/* nldq$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80980 } + }, +/* nldqf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80b00 } + }, +/* ldsbu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80400 } + }, +/* ldubu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80440 } + }, +/* ldshu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80480 } + }, +/* lduhu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x804c0 } + }, +/* ldu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80500 } + }, +/* nldsbu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80c00 } + }, +/* nldubu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80c40 } + }, +/* nldshu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80c80 } + }, +/* nlduhu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80cc0 } + }, +/* nldu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80d00 } + }, +/* ldbfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80600 } + }, +/* ldhfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80640 } + }, +/* ldfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80680 } + }, +/* ldcu$pack @($GRi,$GRj),$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } }, + & ifmt_ldc, { 0x80740 } + }, +/* nldbfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80e00 } + }, +/* nldhfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80e40 } + }, +/* nldfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80e80 } + }, +/* lddu$pack @($GRi,$GRj),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_ldd, { 0x80540 } + }, +/* nlddu$pack @($GRi,$GRj),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_ldd, { 0x80d40 } + }, +/* lddfu$pack @($GRi,$GRj),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddf, { 0x806c0 } + }, +/* lddcu$pack @($GRi,$GRj),$CPRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRDOUBLEK), 0 } }, + & ifmt_lddc, { 0x80780 } + }, +/* nlddfu$pack @($GRi,$GRj),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddf, { 0x80ec0 } + }, +/* ldqu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80580 } + }, +/* nldqu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80d80 } + }, +/* ldqfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80700 } + }, +/* ldqcu$pack @($GRi,$GRj),$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } }, + & ifmt_ldc, { 0x807c0 } + }, +/* nldqfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80f00 } + }, +/* ldsbi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xc00000 } + }, +/* ldshi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xc40000 } + }, +/* ldi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xc80000 } + }, +/* ldubi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xd40000 } + }, +/* lduhi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xd80000 } + }, +/* ldbfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0xe00000 } + }, +/* ldhfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0xe40000 } + }, +/* ldfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0xe80000 } + }, +/* nldsbi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1000000 } + }, +/* nldubi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1040000 } + }, +/* nldshi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1080000 } + }, +/* nlduhi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x10c0000 } + }, +/* nldi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1100000 } + }, +/* nldbfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0x1200000 } + }, +/* nldhfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0x1240000 } + }, +/* nldfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0x1280000 } + }, +/* lddi$pack @($GRi,$d12),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_lddi, { 0xcc0000 } + }, +/* lddfi$pack @($GRi,$d12),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddfi, { 0xec0000 } + }, +/* nlddi$pack @($GRi,$d12),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_lddi, { 0x1140000 } + }, +/* nlddfi$pack @($GRi,$d12),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddfi, { 0x12c0000 } + }, +/* ldqi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xd00000 } + }, +/* ldqfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0xf00000 } + }, +/* nldqi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1180000 } + }, +/* nldqfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0x1300000 } + }, +/* stb$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0000 } + }, +/* sth$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0040 } + }, +/* st$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0080 } + }, +/* stbf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0200 } + }, +/* sthf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0240 } + }, +/* stf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0280 } + }, +/* stc$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc0940 } + }, +/* rstb$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0800 } + }, +/* rsth$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0840 } + }, +/* rst$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0880 } + }, +/* rstbf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0a00 } + }, +/* rsthf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0a40 } + }, +/* rstf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0a80 } + }, +/* std$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc00c0 } + }, +/* stdf$pack $FRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_stdf, { 0xc02c0 } + }, +/* stdc$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc0980 } + }, +/* rstd$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc08c0 } + }, +/* rstdf$pack $FRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_stdf, { 0xc0ac0 } + }, +/* stq$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0100 } + }, +/* stqf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0300 } + }, +/* stqc$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc09c0 } + }, +/* rstq$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0900 } + }, +/* rstqf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0b00 } + }, +/* stbu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0400 } + }, +/* sthu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0440 } + }, +/* stu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0480 } + }, +/* stbfu$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0600 } + }, +/* sthfu$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0640 } + }, +/* stfu$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0680 } + }, +/* stcu$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc0b40 } + }, +/* stdu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc04c0 } + }, +/* stdfu$pack $FRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_stdf, { 0xc06c0 } + }, +/* stdcu$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc0b80 } + }, +/* stqu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0500 } + }, +/* stqfu$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0700 } + }, +/* stqcu$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc0bc0 } + }, +/* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1780000 } + }, +/* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1780040 } + }, +/* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1780080 } + }, +/* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x17800c0 } + }, +/* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x17c0000 } + }, +/* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1800000 } + }, +/* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1800040 } + }, +/* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1800080 } + }, +/* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x17c0040 } + }, +/* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_clddf, { 0x18000c0 } + }, +/* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x17c0080 } + }, +/* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1840000 } + }, +/* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1840040 } + }, +/* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1840080 } + }, +/* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x18400c0 } + }, +/* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1880000 } + }, +/* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x18c0000 } + }, +/* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x18c0040 } + }, +/* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x18c0080 } + }, +/* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x1880040 } + }, +/* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_clddf, { 0x18c00c0 } + }, +/* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1880080 } + }, +/* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1900000 } + }, +/* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1900040 } + }, +/* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1900080 } + }, +/* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1980000 } + }, +/* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1980040 } + }, +/* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1980080 } + }, +/* cstd$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19000c0 } + }, +/* cstdf$pack $FRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cstdf, { 0x19800c0 } + }, +/* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1940000 } + }, +/* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19c0000 } + }, +/* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19c0040 } + }, +/* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19c0080 } + }, +/* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1a00000 } + }, +/* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1a00040 } + }, +/* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1a00080 } + }, +/* cstdu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19c00c0 } + }, +/* cstdfu$pack $FRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cstdf, { 0x1a000c0 } + }, +/* stbi$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x1400000 } + }, +/* sthi$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x1440000 } + }, +/* sti$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x1480000 } + }, +/* stbfi$pack $FRintk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldbfi, { 0x1380000 } + }, +/* sthfi$pack $FRintk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldbfi, { 0x13c0000 } + }, +/* stfi$pack $FRintk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldbfi, { 0x1540000 } + }, +/* stdi$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x14c0000 } + }, +/* stdfi$pack $FRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_stdfi, { 0x1580000 } + }, +/* stqi$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x1500000 } + }, +/* stqfi$pack $FRintk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldbfi, { 0x15c0000 } + }, +/* swap$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0xc0140 } + }, +/* swapi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1340000 } + }, +/* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1940080 } + }, +/* movgf$pack $GRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), 0 } }, + & ifmt_movgf, { 0xc0540 } + }, +/* movfg$pack $FRintk,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), 0 } }, + & ifmt_movgf, { 0xc0340 } + }, +/* movgfd$pack $GRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), 0 } }, + & ifmt_movgf, { 0xc0580 } + }, +/* movfgd$pack $FRintk,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), 0 } }, + & ifmt_movgf, { 0xc0380 } + }, +/* movgfq$pack $GRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), 0 } }, + & ifmt_movgf, { 0xc05c0 } + }, +/* movfgq$pack $FRintk,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), 0 } }, + & ifmt_movgf, { 0xc03c0 } + }, +/* cmovgf$pack $GRj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmovgf, { 0x1a40000 } + }, +/* cmovfg$pack $FRintk,$GRj,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmovgf, { 0x1a40080 } + }, +/* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmovgf, { 0x1a40040 } + }, +/* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmovgf, { 0x1a400c0 } + }, +/* movgs$pack $GRj,$spr */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (SPR), 0 } }, + & ifmt_movgs, { 0xc0180 } + }, +/* movsg$pack $spr,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (SPR), ',', OP (GRJ), 0 } }, + & ifmt_movgs, { 0xc01c0 } + }, +/* bra$pack $hint_taken$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (HINT_TAKEN), OP (LABEL16), 0 } }, + & ifmt_bra, { 0x40180000 } + }, +/* bno$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_bno, { 0x180000 } + }, +/* beq$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x20180000 } + }, +/* bne$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x60180000 } + }, +/* ble$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x38180000 } + }, +/* bgt$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x78180000 } + }, +/* blt$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x18180000 } + }, +/* bge$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x58180000 } + }, +/* bls$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x28180000 } + }, +/* bhi$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x68180000 } + }, +/* bc$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x8180000 } + }, +/* bnc$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x48180000 } + }, +/* bn$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x30180000 } + }, +/* bp$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x70180000 } + }, +/* bv$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x10180000 } + }, +/* bnv$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x50180000 } + }, +/* fbra$pack $hint_taken$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (HINT_TAKEN), OP (LABEL16), 0 } }, + & ifmt_fbra, { 0x781c0000 } + }, +/* fbno$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_fbno, { 0x1c0000 } + }, +/* fbne$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x381c0000 } + }, +/* fbeq$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x401c0000 } + }, +/* fblg$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x301c0000 } + }, +/* fbue$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x481c0000 } + }, +/* fbul$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x281c0000 } + }, +/* fbge$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x501c0000 } + }, +/* fblt$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x201c0000 } + }, +/* fbuge$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x581c0000 } + }, +/* fbug$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x181c0000 } + }, +/* fble$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x601c0000 } + }, +/* fbgt$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x101c0000 } + }, +/* fbule$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x681c0000 } + }, +/* fbu$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x81c0000 } + }, +/* fbo$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x701c0000 } + }, +/* bctrlr$pack $ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bctrlr, { 0x382000 } + }, +/* bralr$pack$hint_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_TAKEN), 0 } }, + & ifmt_bralr, { 0x40384000 } + }, +/* bnolr$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_bnolr, { 0x384000 } + }, +/* beqlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x20384000 } + }, +/* bnelr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x60384000 } + }, +/* blelr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x38384000 } + }, +/* bgtlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x78384000 } + }, +/* bltlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x18384000 } + }, +/* bgelr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x58384000 } + }, +/* blslr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x28384000 } + }, +/* bhilr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x68384000 } + }, +/* bclr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x8384000 } + }, +/* bnclr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x48384000 } + }, +/* bnlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x30384000 } + }, +/* bplr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x70384000 } + }, +/* bvlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x10384000 } + }, +/* bnvlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x50384000 } + }, +/* fbralr$pack$hint_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_TAKEN), 0 } }, + & ifmt_fbralr, { 0x7838c000 } + }, +/* fbnolr$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_fbnolr, { 0x38c000 } + }, +/* fbeqlr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x4038c000 } + }, +/* fbnelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x3838c000 } + }, +/* fblglr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x3038c000 } + }, +/* fbuelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x4838c000 } + }, +/* fbullr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x2838c000 } + }, +/* fbgelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x5038c000 } + }, +/* fbltlr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x2038c000 } + }, +/* fbugelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x5838c000 } + }, +/* fbuglr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x1838c000 } + }, +/* fblelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x6038c000 } + }, +/* fbgtlr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x1038c000 } + }, +/* fbulelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x6838c000 } + }, +/* fbulr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x838c000 } + }, +/* fbolr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x7038c000 } + }, +/* bcralr$pack $ccond$hint_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CCOND), OP (HINT_TAKEN), 0 } }, + & ifmt_bcralr, { 0x40386000 } + }, +/* bcnolr$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_bnolr, { 0x386000 } + }, +/* bceqlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x20386000 } + }, +/* bcnelr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x60386000 } + }, +/* bclelr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x38386000 } + }, +/* bcgtlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x78386000 } + }, +/* bcltlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x18386000 } + }, +/* bcgelr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x58386000 } + }, +/* bclslr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x28386000 } + }, +/* bchilr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x68386000 } + }, +/* bcclr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x8386000 } + }, +/* bcnclr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x48386000 } + }, +/* bcnlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x30386000 } + }, +/* bcplr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x70386000 } + }, +/* bcvlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x10386000 } + }, +/* bcnvlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x50386000 } + }, +/* fcbralr$pack $ccond$hint_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CCOND), OP (HINT_TAKEN), 0 } }, + & ifmt_fcbralr, { 0x7838e000 } + }, +/* fcbnolr$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_fbnolr, { 0x38e000 } + }, +/* fcbeqlr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x4038e000 } + }, +/* fcbnelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x3838e000 } + }, +/* fcblglr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x3038e000 } + }, +/* fcbuelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x4838e000 } + }, +/* fcbullr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x2838e000 } + }, +/* fcbgelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x5038e000 } + }, +/* fcbltlr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x2038e000 } + }, +/* fcbugelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x5838e000 } + }, +/* fcbuglr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x1838e000 } + }, +/* fcblelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x6038e000 } + }, +/* fcbgtlr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x1038e000 } + }, +/* fcbulelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x6838e000 } + }, +/* fcbulr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x838e000 } + }, +/* fcbolr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x7038e000 } + }, +/* jmpl$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_jmpl, { 0x300000 } + }, +/* calll$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_calll, { 0x2300000 } + }, +/* jmpil$pack @($GRi,$s12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (S12), ')', 0 } }, + & ifmt_jmpil, { 0x340000 } + }, +/* callil$pack @($GRi,$s12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (S12), ')', 0 } }, + & ifmt_callil, { 0x2340000 } + }, +/* call$pack $label24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (LABEL24), 0 } }, + & ifmt_call, { 0x3c0000 } + }, +/* rett$pack $debug */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (DEBUG), 0 } }, + & ifmt_rett, { 0x140000 } + }, +/* rei$pack $eir */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (EIR), 0 } }, + & ifmt_rei, { 0xdc0000 } + }, +/* tra$pack $GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_tra, { 0x40100000 } + }, +/* tno$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_tno, { 0x100000 } + }, +/* teq$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x20100000 } + }, +/* tne$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x60100000 } + }, +/* tle$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x38100000 } + }, +/* tgt$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x78100000 } + }, +/* tlt$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x18100000 } + }, +/* tge$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x58100000 } + }, +/* tls$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x28100000 } + }, +/* thi$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x68100000 } + }, +/* tc$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x8100000 } + }, +/* tnc$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x48100000 } + }, +/* tn$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x30100000 } + }, +/* tp$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x70100000 } + }, +/* tv$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x10100000 } + }, +/* tnv$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x50100000 } + }, +/* ftra$pack $GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftra, { 0x78100040 } + }, +/* ftno$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_ftno, { 0x100040 } + }, +/* ftne$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x38100040 } + }, +/* fteq$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x40100040 } + }, +/* ftlg$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x30100040 } + }, +/* ftue$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x48100040 } + }, +/* ftul$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x28100040 } + }, +/* ftge$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x50100040 } + }, +/* ftlt$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x20100040 } + }, +/* ftuge$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x58100040 } + }, +/* ftug$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x18100040 } + }, +/* ftle$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x60100040 } + }, +/* ftgt$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x10100040 } + }, +/* ftule$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x68100040 } + }, +/* ftu$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x8100040 } + }, +/* fto$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x70100040 } + }, +/* tira$pack $GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tira, { 0x40700000 } + }, +/* tino$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_tino, { 0x700000 } + }, +/* tieq$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x20700000 } + }, +/* tine$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x60700000 } + }, +/* tile$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x38700000 } + }, +/* tigt$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x78700000 } + }, +/* tilt$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x18700000 } + }, +/* tige$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x58700000 } + }, +/* tils$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x28700000 } + }, +/* tihi$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x68700000 } + }, +/* tic$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x8700000 } + }, +/* tinc$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x48700000 } + }, +/* tin$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x30700000 } + }, +/* tip$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x70700000 } + }, +/* tiv$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x10700000 } + }, +/* tinv$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x50700000 } + }, +/* ftira$pack $GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftira, { 0x78740000 } + }, +/* ftino$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_ftino, { 0x740000 } + }, +/* ftine$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x38740000 } + }, +/* ftieq$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x40740000 } + }, +/* ftilg$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x30740000 } + }, +/* ftiue$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x48740000 } + }, +/* ftiul$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x28740000 } + }, +/* ftige$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x50740000 } + }, +/* ftilt$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x20740000 } + }, +/* ftiuge$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x58740000 } + }, +/* ftiug$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x18740000 } + }, +/* ftile$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x60740000 } + }, +/* ftigt$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x10740000 } + }, +/* ftiule$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x68740000 } + }, +/* ftiu$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x8740000 } + }, +/* ftio$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x70740000 } + }, +/* break$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_break, { 0x1000c0 } + }, +/* mtrap$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_break, { 0x100080 } + }, +/* andcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280200 } + }, +/* orcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280240 } + }, +/* xorcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280280 } + }, +/* nandcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280300 } + }, +/* norcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280340 } + }, +/* andncr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280400 } + }, +/* orncr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280440 } + }, +/* nandncr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280500 } + }, +/* norncr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280540 } + }, +/* notcr$pack $CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_notcr, { 0x2802c0 } + }, +/* ckra$pack $CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_INT), 0 } }, + & ifmt_ckra, { 0x40200000 } + }, +/* ckno$pack $CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_INT), 0 } }, + & ifmt_ckra, { 0x200000 } + }, +/* ckeq$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x20200000 } + }, +/* ckne$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x60200000 } + }, +/* ckle$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x38200000 } + }, +/* ckgt$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x78200000 } + }, +/* cklt$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x18200000 } + }, +/* ckge$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x58200000 } + }, +/* ckls$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x28200000 } + }, +/* ckhi$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x68200000 } + }, +/* ckc$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x8200000 } + }, +/* cknc$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x48200000 } + }, +/* ckn$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x30200000 } + }, +/* ckp$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x70200000 } + }, +/* ckv$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x10200000 } + }, +/* cknv$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x50200000 } + }, +/* fckra$pack $CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x78240000 } + }, +/* fckno$pack $CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x240000 } + }, +/* fckne$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x38240000 } + }, +/* fckeq$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x40240000 } + }, +/* fcklg$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x30240000 } + }, +/* fckue$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x48240000 } + }, +/* fckul$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x28240000 } + }, +/* fckge$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x50240000 } + }, +/* fcklt$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x20240000 } + }, +/* fckuge$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x58240000 } + }, +/* fckug$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x18240000 } + }, +/* fckle$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x60240000 } + }, +/* fckgt$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x10240000 } + }, +/* fckule$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x68240000 } + }, +/* fcku$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x8240000 } + }, +/* fcko$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x70240000 } + }, +/* cckra$pack $CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckra, { 0x41a80000 } + }, +/* cckno$pack $CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckra, { 0x1a80000 } + }, +/* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x21a80000 } + }, +/* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x61a80000 } + }, +/* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x39a80000 } + }, +/* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x79a80000 } + }, +/* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x19a80000 } + }, +/* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x59a80000 } + }, +/* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x29a80000 } + }, +/* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x69a80000 } + }, +/* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x9a80000 } + }, +/* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x49a80000 } + }, +/* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x31a80000 } + }, +/* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x71a80000 } + }, +/* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x11a80000 } + }, +/* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x51a80000 } + }, +/* cfckra$pack $CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckra, { 0x79a80040 } + }, +/* cfckno$pack $CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckra, { 0x1a80040 } + }, +/* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x39a80040 } + }, +/* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x41a80040 } + }, +/* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x31a80040 } + }, +/* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x49a80040 } + }, +/* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x29a80040 } + }, +/* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x51a80040 } + }, +/* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x21a80040 } + }, +/* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x59a80040 } + }, +/* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x19a80040 } + }, +/* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x61a80040 } + }, +/* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x11a80040 } + }, +/* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x69a80040 } + }, +/* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x9a80040 } + }, +/* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x71a80040 } + }, +/* cjmpl$pack @($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cjmpl, { 0x1a80080 } + }, +/* ccalll$pack @($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_ccalll, { 0x3a80080 } + }, +/* ici$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ici, { 0xc0e00 } + }, +/* dci$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ici, { 0xc0f00 } + }, +/* icei$pack @($GRi,$GRj),$ae */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (AE), 0 } }, + & ifmt_icei, { 0xc0e40 } + }, +/* dcei$pack @($GRi,$GRj),$ae */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (AE), 0 } }, + & ifmt_icei, { 0xc0e80 } + }, +/* dcf$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ici, { 0xc0f40 } + }, +/* dcef$pack @($GRi,$GRj),$ae */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (AE), 0 } }, + & ifmt_icei, { 0xc0ec0 } + }, +/* witlb$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0c80 } + }, +/* wdtlb$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0d80 } + }, +/* itlbi$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ici, { 0xc0cc0 } + }, +/* dtlbi$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ici, { 0xc0dc0 } + }, +/* icpl$pack $GRi,$GRj,$lock */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (LOCK), 0 } }, + & ifmt_icpl, { 0xc0c00 } + }, +/* dcpl$pack $GRi,$GRj,$lock */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (LOCK), 0 } }, + & ifmt_icpl, { 0xc0d00 } + }, +/* icul$pack $GRi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), 0 } }, + & ifmt_icul, { 0xc0c40 } + }, +/* dcul$pack $GRi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), 0 } }, + & ifmt_icul, { 0xc0d40 } + }, +/* bar$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0xc0f80 } + }, +/* membar$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0xc0fc0 } + }, +/* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S6_1), ',', OP (CPRI), ',', OP (CPRJ), ',', OP (CPRK), 0 } }, + & ifmt_cop1, { 0x1f80000 } + }, +/* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S6_1), ',', OP (CPRI), ',', OP (CPRJ), ',', OP (CPRK), 0 } }, + & ifmt_cop1, { 0x1fc0000 } + }, +/* clrgr$pack $GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), 0 } }, + & ifmt_clrgr, { 0x280000 } + }, +/* clrfr$pack $FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), 0 } }, + & ifmt_clrfr, { 0x280080 } + }, +/* clrga$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0x280040 } + }, +/* clrfa$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0x2800c0 } + }, +/* commitgr$pack $GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), 0 } }, + & ifmt_clrgr, { 0x280100 } + }, +/* commitfr$pack $FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), 0 } }, + & ifmt_clrfr, { 0x280180 } + }, +/* commitga$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0x280140 } + }, +/* commitfa$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0x2801c0 } + }, +/* fitos$pack $FRintj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), 0 } }, + & ifmt_fitos, { 0x1e40000 } + }, +/* fstoi$pack $FRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), 0 } }, + & ifmt_fstoi, { 0x1e40040 } + }, +/* fitod$pack $FRintj,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fitod, { 0x1e80000 } + }, +/* fdtoi$pack $FRdoublej,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRINTK), 0 } }, + & ifmt_fdtoi, { 0x1e80040 } + }, +/* fditos$pack $FRintj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), 0 } }, + & ifmt_fitos, { 0x1e40400 } + }, +/* fdstoi$pack $FRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), 0 } }, + & ifmt_fstoi, { 0x1e40440 } + }, +/* nfditos$pack $FRintj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), 0 } }, + & ifmt_fitos, { 0x1e40c00 } + }, +/* nfdstoi$pack $FRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), 0 } }, + & ifmt_fstoi, { 0x1e40c40 } + }, +/* cfitos$pack $FRintj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfitos, { 0x1ac0000 } + }, +/* cfstoi$pack $FRj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfstoi, { 0x1ac0040 } + }, +/* nfitos$pack $FRintj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), 0 } }, + & ifmt_fitos, { 0x1e40800 } + }, +/* nfstoi$pack $FRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), 0 } }, + & ifmt_fstoi, { 0x1e40840 } + }, +/* fmovs$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40080 } + }, +/* fmovd$pack $FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fmovd, { 0x1e80080 } + }, +/* fdmovs$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40480 } + }, +/* cfmovs$pack $FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfmovs, { 0x1b00000 } + }, +/* fnegs$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e400c0 } + }, +/* fnegd$pack $FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fmovd, { 0x1e800c0 } + }, +/* fdnegs$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e404c0 } + }, +/* cfnegs$pack $FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfmovs, { 0x1b00040 } + }, +/* fabss$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40100 } + }, +/* fabsd$pack $FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fmovd, { 0x1e80100 } + }, +/* fdabss$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40500 } + }, +/* cfabss$pack $FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfmovs, { 0x1b00080 } + }, +/* fsqrts$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40140 } + }, +/* fdsqrts$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40540 } + }, +/* nfdsqrts$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40d40 } + }, +/* fsqrtd$pack $FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fmovd, { 0x1e80140 } + }, +/* cfsqrts$pack $FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfmovs, { 0x1b80080 } + }, +/* nfsqrts$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40940 } + }, +/* fadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40180 } + }, +/* fsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e401c0 } + }, +/* fmuls$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40200 } + }, +/* fdivs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40240 } + }, +/* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e80180 } + }, +/* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e801c0 } + }, +/* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e80200 } + }, +/* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e80240 } + }, +/* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1b40000 } + }, +/* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1b40040 } + }, +/* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1b80000 } + }, +/* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1b80040 } + }, +/* nfadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40980 } + }, +/* nfsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e409c0 } + }, +/* nfmuls$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40a00 } + }, +/* nfdivs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40a40 } + }, +/* fcmps$pack $FRi,$FRj,$FCCi_2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FCCI_2), 0 } }, + & ifmt_fcmps, { 0x1e40280 } + }, +/* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FCCI_2), 0 } }, + & ifmt_fcmpd, { 0x1e80280 } + }, +/* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FCCI_2), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfcmps, { 0x1b40080 } + }, +/* fdcmps$pack $FRi,$FRj,$FCCi_2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FCCI_2), 0 } }, + & ifmt_fcmps, { 0x1e40680 } + }, +/* fmadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e402c0 } + }, +/* fmsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40300 } + }, +/* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e802c0 } + }, +/* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e80300 } + }, +/* fdmadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e406c0 } + }, +/* nfdmadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40ec0 } + }, +/* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1bc0000 } + }, +/* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1bc0040 } + }, +/* nfmadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40ac0 } + }, +/* nfmsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40b00 } + }, +/* fmas$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40380 } + }, +/* fmss$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e403c0 } + }, +/* fdmas$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40700 } + }, +/* fdmss$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40740 } + }, +/* nfdmas$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40f00 } + }, +/* nfdmss$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40f40 } + }, +/* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1bc0080 } + }, +/* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1bc00c0 } + }, +/* fmad$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e80380 } + }, +/* fmsd$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e803c0 } + }, +/* nfmas$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40b80 } + }, +/* nfmss$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40bc0 } + }, +/* fdadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40580 } + }, +/* fdsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e405c0 } + }, +/* fdmuls$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40600 } + }, +/* fddivs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40640 } + }, +/* fdsads$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40780 } + }, +/* fdmulcs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e407c0 } + }, +/* nfdmulcs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40fc0 } + }, +/* nfdadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40d80 } + }, +/* nfdsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40dc0 } + }, +/* nfdmuls$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40e00 } + }, +/* nfddivs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40e40 } + }, +/* nfdsads$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40f80 } + }, +/* nfdcmps$pack $FRi,$FRj,$FCCi_2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FCCI_2), 0 } }, + & ifmt_fcmps, { 0x1e40e80 } + }, +/* mhsetlos$pack $u12,$FRklo */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (U12), ',', OP (FRKLO), 0 } }, + & ifmt_mhsetlos, { 0x1e00800 } + }, +/* mhsethis$pack $u12,$FRkhi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (U12), ',', OP (FRKHI), 0 } }, + & ifmt_mhsethis, { 0x1e00880 } + }, +/* mhdsets$pack $u12,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (U12), ',', OP (FRINTK), 0 } }, + & ifmt_mhdsets, { 0x1e00900 } + }, +/* mhsetloh$pack $s5,$FRklo */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S5), ',', OP (FRKLO), 0 } }, + & ifmt_mhsetloh, { 0x1e00840 } + }, +/* mhsethih$pack $s5,$FRkhi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S5), ',', OP (FRKHI), 0 } }, + & ifmt_mhsethih, { 0x1e008c0 } + }, +/* mhdseth$pack $s5,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S5), ',', OP (FRINTK), 0 } }, + & ifmt_mhdseth, { 0x1e00940 } + }, +/* mand$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0000 } + }, +/* mor$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0040 } + }, +/* mxor$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0080 } + }, +/* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c00000 } + }, +/* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c00040 } + }, +/* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c00080 } + }, +/* mnot$pack $FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mnot, { 0x1ec00c0 } + }, +/* cmnot$pack $FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmnot, { 0x1c000c0 } + }, +/* mrotli$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0100 } + }, +/* mrotri$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0140 } + }, +/* mwcut$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0180 } + }, +/* mwcuti$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec01c0 } + }, +/* mcut$pack $ACC40Si,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mcut, { 0x1ec0b00 } + }, +/* mcuti$pack $ACC40Si,$s6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } }, + & ifmt_mcuti, { 0x1ec0b80 } + }, +/* mcutss$pack $ACC40Si,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mcut, { 0x1ec0b40 } + }, +/* mcutssi$pack $ACC40Si,$s6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } }, + & ifmt_mcuti, { 0x1ec0bc0 } + }, +/* mdcutssi$pack $ACC40Si,$s6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } }, + & ifmt_mcuti, { 0x1e00380 } + }, +/* maveh$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0200 } + }, +/* msllhi$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0240 } + }, +/* msrlhi$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0280 } + }, +/* msrahi$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec02c0 } + }, +/* mdrotli$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1e002c0 } + }, +/* mcplhi$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1e00300 } + }, +/* mcpli$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1e00340 } + }, +/* msaths$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0300 } + }, +/* mqsaths$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1e003c0 } + }, +/* msathu$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0340 } + }, +/* mcmpsh$pack $FRinti,$FRintj,$FCCk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FCCK), 0 } }, + & ifmt_mcmpsh, { 0x1ec0380 } + }, +/* mcmpuh$pack $FRinti,$FRintj,$FCCk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FCCK), 0 } }, + & ifmt_mcmpsh, { 0x1ec03c0 } + }, +/* mabshs$pack $FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mabshs, { 0x1e00280 } + }, +/* maddhss$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0400 } + }, +/* maddhus$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0440 } + }, +/* msubhss$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0480 } + }, +/* msubhus$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec04c0 } + }, +/* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c40000 } + }, +/* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c40040 } + }, +/* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c40080 } + }, +/* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c400c0 } + }, +/* mqaddhss$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0600 } + }, +/* mqaddhus$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0640 } + }, +/* mqsubhss$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0680 } + }, +/* mqsubhus$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec06c0 } + }, +/* cmqaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1cc0000 } + }, +/* cmqaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1cc0040 } + }, +/* cmqsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1cc0080 } + }, +/* cmqsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1cc00c0 } + }, +/* maddaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00100 } + }, +/* msubaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00140 } + }, +/* mdaddaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00180 } + }, +/* mdsubaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e001c0 } + }, +/* masaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00200 } + }, +/* mdasaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00240 } + }, +/* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0500 } + }, +/* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0540 } + }, +/* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0a00 } + }, +/* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0a40 } + }, +/* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1c80000 } + }, +/* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1c80040 } + }, +/* mqmulhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0700 } + }, +/* mqmulhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0740 } + }, +/* mqmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0a80 } + }, +/* mqmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0ac0 } + }, +/* cmqmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d00000 } + }, +/* cmqmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d00040 } + }, +/* mmachs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0580 } + }, +/* mmachu$pack $FRinti,$FRintj,$ACC40Uk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), 0 } }, + & ifmt_mmachu, { 0x1ec05c0 } + }, +/* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0c00 } + }, +/* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), 0 } }, + & ifmt_mmachu, { 0x1ec0c40 } + }, +/* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1c80080 } + }, +/* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmachu, { 0x1c800c0 } + }, +/* mqmachs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0780 } + }, +/* mqmachu$pack $FRinti,$FRintj,$ACC40Uk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), 0 } }, + & ifmt_mmachu, { 0x1ec07c0 } + }, +/* cmqmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d00080 } + }, +/* cmqmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmachu, { 0x1d000c0 } + }, +/* mqxmachs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1e00000 } + }, +/* mqxmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1e00040 } + }, +/* mqmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1e00080 } + }, +/* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0800 } + }, +/* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0840 } + }, +/* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0880 } + }, +/* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec08c0 } + }, +/* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d40000 } + }, +/* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d40040 } + }, +/* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d40080 } + }, +/* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d400c0 } + }, +/* mqcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0900 } + }, +/* mqcpxru$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0940 } + }, +/* mqcpxis$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0980 } + }, +/* mqcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec09c0 } + }, +/* mexpdhw$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0c80 } + }, +/* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmexpdhw, { 0x1d80080 } + }, +/* mexpdhd$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0cc0 } + }, +/* cmexpdhd$pack $FRinti,$u6,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmexpdhw, { 0x1d800c0 } + }, +/* mpackh$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0d00 } + }, +/* mdpackh$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0d80 } + }, +/* munpackh$pack $FRinti,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTK), 0 } }, + & ifmt_munpackh, { 0x1ec0d40 } + }, +/* mdunpackh$pack $FRinti,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTK), 0 } }, + & ifmt_munpackh, { 0x1ec0dc0 } + }, +/* mbtoh$pack $FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mabshs, { 0x1ec0e00 } + }, +/* cmbtoh$pack $FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmbtoh, { 0x1dc0000 } + }, +/* mhtob$pack $FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mabshs, { 0x1ec0e40 } + }, +/* cmhtob$pack $FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmbtoh, { 0x1dc0040 } + }, +/* mbtohe$pack $FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mabshs, { 0x1ec0e80 } + }, +/* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmbtoh, { 0x1dc0080 } + }, +/* mclracc$pack $ACC40Sk,$A */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A), 0 } }, + & ifmt_mclracc, { 0x1ec0ec0 } + }, +/* mrdacc$pack $ACC40Si,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (FRINTK), 0 } }, + & ifmt_mrdacc, { 0x1ec0f00 } + }, +/* mrdaccg$pack $ACCGi,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACCGI), ',', OP (FRINTK), 0 } }, + & ifmt_mrdaccg, { 0x1ec0f80 } + }, +/* mwtacc$pack $FRinti,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (ACC40SK), 0 } }, + & ifmt_mwtacc, { 0x1ec0f40 } + }, +/* mwtaccg$pack $FRinti,$ACCGk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (ACCGK), 0 } }, + & ifmt_mwtaccg, { 0x1ec0fc0 } + }, +/* mcop1$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1f00000 } + }, +/* mcop2$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1f40000 } + }, +/* fnop$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_fnop, { 0x1e40340 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & frv_cgen_ifld_table[FRV_##f] +#else +#define F(f) & frv_cgen_ifld_table[FRV_/**/f] +#endif +static const CGEN_IFMT ifmt_nop = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mnop = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ret = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp = { + 32, 32, 0x7ffc03c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmpi = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_S10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ccmp = { + 32, 32, 0x7ffc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov = { + 32, 32, 0x1fc00ff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) FRV_OPERAND_##op +#else +#define OPERAND(op) FRV_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE frv_cgen_macro_insn_table[] = +{ +/* nop$pack */ + { + -1, "nop", "nop", 32, + { 0|A(ALIAS), { (1<macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & frv_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + frv_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff -uprN binutils-2.12.90.0.11/opcodes/frv-opc.h binutils-2.12.90.0.12/opcodes/frv-opc.h --- binutils-2.12.90.0.11/opcodes/frv-opc.h Wed Dec 31 16:00:00 1969 +++ binutils-2.12.90.0.12/opcodes/frv-opc.h Tue Jun 18 21:41:59 2002 @@ -0,0 +1,372 @@ +/* Instruction opcode header for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef FRV_OPC_H +#define FRV_OPC_H + +/* -- opc.h */ + +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 128 +#undef CGEN_DIS_HASH +#define CGEN_DIS_HASH(buffer, value) (((value) >> 18) & 127) + +/* Vliw support. */ +#define FRV_VLIW_SIZE 4 /* fr500 has largest vliw size of 4. */ +typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE]; + +typedef struct +{ + int next_slot; + int constraint_violation; + unsigned long mach; + unsigned long elf_flags; + CGEN_ATTR_VALUE_TYPE *unit_mapping; + VLIW_COMBO *current_vliw; + CGEN_ATTR_VALUE_TYPE major[FRV_VLIW_SIZE]; +} FRV_VLIW; + +int frv_is_branch_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); +int frv_is_float_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); +int frv_is_media_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); +int frv_is_branch_insn PARAMS ((const CGEN_INSN *)); +int frv_is_float_insn PARAMS ((const CGEN_INSN *)); +int frv_is_media_insn PARAMS ((const CGEN_INSN *)); +void frv_vliw_reset PARAMS ((FRV_VLIW *, unsigned long mach, unsigned long elf_flags)); +int frv_vliw_add_insn PARAMS ((FRV_VLIW *, const CGEN_INSN *)); +int spr_valid PARAMS ((long)); +/* -- */ +/* Enum declaration for frv instruction types. */ +typedef enum cgen_insn_type { + FRV_INSN_INVALID, FRV_INSN_ADD, FRV_INSN_SUB, FRV_INSN_AND + , FRV_INSN_OR, FRV_INSN_XOR, FRV_INSN_NOT, FRV_INSN_SDIV + , FRV_INSN_NSDIV, FRV_INSN_UDIV, FRV_INSN_NUDIV, FRV_INSN_SMUL + , FRV_INSN_UMUL, FRV_INSN_SLL, FRV_INSN_SRL, FRV_INSN_SRA + , FRV_INSN_SCAN, FRV_INSN_CADD, FRV_INSN_CSUB, FRV_INSN_CAND + , FRV_INSN_COR, FRV_INSN_CXOR, FRV_INSN_CNOT, FRV_INSN_CSMUL + , FRV_INSN_CSDIV, FRV_INSN_CUDIV, FRV_INSN_CSLL, FRV_INSN_CSRL + , FRV_INSN_CSRA, FRV_INSN_CSCAN, FRV_INSN_ADDCC, FRV_INSN_SUBCC + , FRV_INSN_ANDCC, FRV_INSN_ORCC, FRV_INSN_XORCC, FRV_INSN_SLLCC + , FRV_INSN_SRLCC, FRV_INSN_SRACC, FRV_INSN_SMULCC, FRV_INSN_UMULCC + , FRV_INSN_CADDCC, FRV_INSN_CSUBCC, FRV_INSN_CSMULCC, FRV_INSN_CANDCC + , FRV_INSN_CORCC, FRV_INSN_CXORCC, FRV_INSN_CSLLCC, FRV_INSN_CSRLCC + , FRV_INSN_CSRACC, FRV_INSN_ADDX, FRV_INSN_SUBX, FRV_INSN_ADDXCC + , FRV_INSN_SUBXCC, FRV_INSN_ADDI, FRV_INSN_SUBI, FRV_INSN_ANDI + , FRV_INSN_ORI, FRV_INSN_XORI, FRV_INSN_SDIVI, FRV_INSN_NSDIVI + , FRV_INSN_UDIVI, FRV_INSN_NUDIVI, FRV_INSN_SMULI, FRV_INSN_UMULI + , FRV_INSN_SLLI, FRV_INSN_SRLI, FRV_INSN_SRAI, FRV_INSN_SCANI + , FRV_INSN_ADDICC, FRV_INSN_SUBICC, FRV_INSN_ANDICC, FRV_INSN_ORICC + , FRV_INSN_XORICC, FRV_INSN_SMULICC, FRV_INSN_UMULICC, FRV_INSN_SLLICC + , FRV_INSN_SRLICC, FRV_INSN_SRAICC, FRV_INSN_ADDXI, FRV_INSN_SUBXI + , FRV_INSN_ADDXICC, FRV_INSN_SUBXICC, FRV_INSN_CMPB, FRV_INSN_CMPBA + , FRV_INSN_SETLO, FRV_INSN_SETHI, FRV_INSN_SETLOS, FRV_INSN_LDSB + , FRV_INSN_LDUB, FRV_INSN_LDSH, FRV_INSN_LDUH, FRV_INSN_LD + , FRV_INSN_LDBF, FRV_INSN_LDHF, FRV_INSN_LDF, FRV_INSN_LDC + , FRV_INSN_NLDSB, FRV_INSN_NLDUB, FRV_INSN_NLDSH, FRV_INSN_NLDUH + , FRV_INSN_NLD, FRV_INSN_NLDBF, FRV_INSN_NLDHF, FRV_INSN_NLDF + , FRV_INSN_LDD, FRV_INSN_LDDF, FRV_INSN_LDDC, FRV_INSN_NLDD + , FRV_INSN_NLDDF, FRV_INSN_LDQ, FRV_INSN_LDQF, FRV_INSN_LDQC + , FRV_INSN_NLDQ, FRV_INSN_NLDQF, FRV_INSN_LDSBU, FRV_INSN_LDUBU + , FRV_INSN_LDSHU, FRV_INSN_LDUHU, FRV_INSN_LDU, FRV_INSN_NLDSBU + , FRV_INSN_NLDUBU, FRV_INSN_NLDSHU, FRV_INSN_NLDUHU, FRV_INSN_NLDU + , FRV_INSN_LDBFU, FRV_INSN_LDHFU, FRV_INSN_LDFU, FRV_INSN_LDCU + , FRV_INSN_NLDBFU, FRV_INSN_NLDHFU, FRV_INSN_NLDFU, FRV_INSN_LDDU + , FRV_INSN_NLDDU, FRV_INSN_LDDFU, FRV_INSN_LDDCU, FRV_INSN_NLDDFU + , FRV_INSN_LDQU, FRV_INSN_NLDQU, FRV_INSN_LDQFU, FRV_INSN_LDQCU + , FRV_INSN_NLDQFU, FRV_INSN_LDSBI, FRV_INSN_LDSHI, FRV_INSN_LDI + , FRV_INSN_LDUBI, FRV_INSN_LDUHI, FRV_INSN_LDBFI, FRV_INSN_LDHFI + , FRV_INSN_LDFI, FRV_INSN_NLDSBI, FRV_INSN_NLDUBI, FRV_INSN_NLDSHI + , FRV_INSN_NLDUHI, FRV_INSN_NLDI, FRV_INSN_NLDBFI, FRV_INSN_NLDHFI + , FRV_INSN_NLDFI, FRV_INSN_LDDI, FRV_INSN_LDDFI, FRV_INSN_NLDDI + , FRV_INSN_NLDDFI, FRV_INSN_LDQI, FRV_INSN_LDQFI, FRV_INSN_NLDQI + , FRV_INSN_NLDQFI, FRV_INSN_STB, FRV_INSN_STH, FRV_INSN_ST + , FRV_INSN_STBF, FRV_INSN_STHF, FRV_INSN_STF, FRV_INSN_STC + , FRV_INSN_RSTB, FRV_INSN_RSTH, FRV_INSN_RST, FRV_INSN_RSTBF + , FRV_INSN_RSTHF, FRV_INSN_RSTF, FRV_INSN_STD, FRV_INSN_STDF + , FRV_INSN_STDC, FRV_INSN_RSTD, FRV_INSN_RSTDF, FRV_INSN_STQ + , FRV_INSN_STQF, FRV_INSN_STQC, FRV_INSN_RSTQ, FRV_INSN_RSTQF + , FRV_INSN_STBU, FRV_INSN_STHU, FRV_INSN_STU, FRV_INSN_STBFU + , FRV_INSN_STHFU, FRV_INSN_STFU, FRV_INSN_STCU, FRV_INSN_STDU + , FRV_INSN_STDFU, FRV_INSN_STDCU, FRV_INSN_STQU, FRV_INSN_STQFU + , FRV_INSN_STQCU, FRV_INSN_CLDSB, FRV_INSN_CLDUB, FRV_INSN_CLDSH + , FRV_INSN_CLDUH, FRV_INSN_CLD, FRV_INSN_CLDBF, FRV_INSN_CLDHF + , FRV_INSN_CLDF, FRV_INSN_CLDD, FRV_INSN_CLDDF, FRV_INSN_CLDQ + , FRV_INSN_CLDSBU, FRV_INSN_CLDUBU, FRV_INSN_CLDSHU, FRV_INSN_CLDUHU + , FRV_INSN_CLDU, FRV_INSN_CLDBFU, FRV_INSN_CLDHFU, FRV_INSN_CLDFU + , FRV_INSN_CLDDU, FRV_INSN_CLDDFU, FRV_INSN_CLDQU, FRV_INSN_CSTB + , FRV_INSN_CSTH, FRV_INSN_CST, FRV_INSN_CSTBF, FRV_INSN_CSTHF + , FRV_INSN_CSTF, FRV_INSN_CSTD, FRV_INSN_CSTDF, FRV_INSN_CSTQ + , FRV_INSN_CSTBU, FRV_INSN_CSTHU, FRV_INSN_CSTU, FRV_INSN_CSTBFU + , FRV_INSN_CSTHFU, FRV_INSN_CSTFU, FRV_INSN_CSTDU, FRV_INSN_CSTDFU + , FRV_INSN_STBI, FRV_INSN_STHI, FRV_INSN_STI, FRV_INSN_STBFI + , FRV_INSN_STHFI, FRV_INSN_STFI, FRV_INSN_STDI, FRV_INSN_STDFI + , FRV_INSN_STQI, FRV_INSN_STQFI, FRV_INSN_SWAP, FRV_INSN_SWAPI + , FRV_INSN_CSWAP, FRV_INSN_MOVGF, FRV_INSN_MOVFG, FRV_INSN_MOVGFD + , FRV_INSN_MOVFGD, FRV_INSN_MOVGFQ, FRV_INSN_MOVFGQ, FRV_INSN_CMOVGF + , FRV_INSN_CMOVFG, FRV_INSN_CMOVGFD, FRV_INSN_CMOVFGD, FRV_INSN_MOVGS + , FRV_INSN_MOVSG, FRV_INSN_BRA, FRV_INSN_BNO, FRV_INSN_BEQ + , FRV_INSN_BNE, FRV_INSN_BLE, FRV_INSN_BGT, FRV_INSN_BLT + , FRV_INSN_BGE, FRV_INSN_BLS, FRV_INSN_BHI, FRV_INSN_BC + , FRV_INSN_BNC, FRV_INSN_BN, FRV_INSN_BP, FRV_INSN_BV + , FRV_INSN_BNV, FRV_INSN_FBRA, FRV_INSN_FBNO, FRV_INSN_FBNE + , FRV_INSN_FBEQ, FRV_INSN_FBLG, FRV_INSN_FBUE, FRV_INSN_FBUL + , FRV_INSN_FBGE, FRV_INSN_FBLT, FRV_INSN_FBUGE, FRV_INSN_FBUG + , FRV_INSN_FBLE, FRV_INSN_FBGT, FRV_INSN_FBULE, FRV_INSN_FBU + , FRV_INSN_FBO, FRV_INSN_BCTRLR, FRV_INSN_BRALR, FRV_INSN_BNOLR + , FRV_INSN_BEQLR, FRV_INSN_BNELR, FRV_INSN_BLELR, FRV_INSN_BGTLR + , FRV_INSN_BLTLR, FRV_INSN_BGELR, FRV_INSN_BLSLR, FRV_INSN_BHILR + , FRV_INSN_BCLR, FRV_INSN_BNCLR, FRV_INSN_BNLR, FRV_INSN_BPLR + , FRV_INSN_BVLR, FRV_INSN_BNVLR, FRV_INSN_FBRALR, FRV_INSN_FBNOLR + , FRV_INSN_FBEQLR, FRV_INSN_FBNELR, FRV_INSN_FBLGLR, FRV_INSN_FBUELR + , FRV_INSN_FBULLR, FRV_INSN_FBGELR, FRV_INSN_FBLTLR, FRV_INSN_FBUGELR + , FRV_INSN_FBUGLR, FRV_INSN_FBLELR, FRV_INSN_FBGTLR, FRV_INSN_FBULELR + , FRV_INSN_FBULR, FRV_INSN_FBOLR, FRV_INSN_BCRALR, FRV_INSN_BCNOLR + , FRV_INSN_BCEQLR, FRV_INSN_BCNELR, FRV_INSN_BCLELR, FRV_INSN_BCGTLR + , FRV_INSN_BCLTLR, FRV_INSN_BCGELR, FRV_INSN_BCLSLR, FRV_INSN_BCHILR + , FRV_INSN_BCCLR, FRV_INSN_BCNCLR, FRV_INSN_BCNLR, FRV_INSN_BCPLR + , FRV_INSN_BCVLR, FRV_INSN_BCNVLR, FRV_INSN_FCBRALR, FRV_INSN_FCBNOLR + , FRV_INSN_FCBEQLR, FRV_INSN_FCBNELR, FRV_INSN_FCBLGLR, FRV_INSN_FCBUELR + , FRV_INSN_FCBULLR, FRV_INSN_FCBGELR, FRV_INSN_FCBLTLR, FRV_INSN_FCBUGELR + , FRV_INSN_FCBUGLR, FRV_INSN_FCBLELR, FRV_INSN_FCBGTLR, FRV_INSN_FCBULELR + , FRV_INSN_FCBULR, FRV_INSN_FCBOLR, FRV_INSN_JMPL, FRV_INSN_CALLL + , FRV_INSN_JMPIL, FRV_INSN_CALLIL, FRV_INSN_CALL, FRV_INSN_RETT + , FRV_INSN_REI, FRV_INSN_TRA, FRV_INSN_TNO, FRV_INSN_TEQ + , FRV_INSN_TNE, FRV_INSN_TLE, FRV_INSN_TGT, FRV_INSN_TLT + , FRV_INSN_TGE, FRV_INSN_TLS, FRV_INSN_THI, FRV_INSN_TC + , FRV_INSN_TNC, FRV_INSN_TN, FRV_INSN_TP, FRV_INSN_TV + , FRV_INSN_TNV, FRV_INSN_FTRA, FRV_INSN_FTNO, FRV_INSN_FTNE + , FRV_INSN_FTEQ, FRV_INSN_FTLG, FRV_INSN_FTUE, FRV_INSN_FTUL + , FRV_INSN_FTGE, FRV_INSN_FTLT, FRV_INSN_FTUGE, FRV_INSN_FTUG + , FRV_INSN_FTLE, FRV_INSN_FTGT, FRV_INSN_FTULE, FRV_INSN_FTU + , FRV_INSN_FTO, FRV_INSN_TIRA, FRV_INSN_TINO, FRV_INSN_TIEQ + , FRV_INSN_TINE, FRV_INSN_TILE, FRV_INSN_TIGT, FRV_INSN_TILT + , FRV_INSN_TIGE, FRV_INSN_TILS, FRV_INSN_TIHI, FRV_INSN_TIC + , FRV_INSN_TINC, FRV_INSN_TIN, FRV_INSN_TIP, FRV_INSN_TIV + , FRV_INSN_TINV, FRV_INSN_FTIRA, FRV_INSN_FTINO, FRV_INSN_FTINE + , FRV_INSN_FTIEQ, FRV_INSN_FTILG, FRV_INSN_FTIUE, FRV_INSN_FTIUL + , FRV_INSN_FTIGE, FRV_INSN_FTILT, FRV_INSN_FTIUGE, FRV_INSN_FTIUG + , FRV_INSN_FTILE, FRV_INSN_FTIGT, FRV_INSN_FTIULE, FRV_INSN_FTIU + , FRV_INSN_FTIO, FRV_INSN_BREAK, FRV_INSN_MTRAP, FRV_INSN_ANDCR + , FRV_INSN_ORCR, FRV_INSN_XORCR, FRV_INSN_NANDCR, FRV_INSN_NORCR + , FRV_INSN_ANDNCR, FRV_INSN_ORNCR, FRV_INSN_NANDNCR, FRV_INSN_NORNCR + , FRV_INSN_NOTCR, FRV_INSN_CKRA, FRV_INSN_CKNO, FRV_INSN_CKEQ + , FRV_INSN_CKNE, FRV_INSN_CKLE, FRV_INSN_CKGT, FRV_INSN_CKLT + , FRV_INSN_CKGE, FRV_INSN_CKLS, FRV_INSN_CKHI, FRV_INSN_CKC + , FRV_INSN_CKNC, FRV_INSN_CKN, FRV_INSN_CKP, FRV_INSN_CKV + , FRV_INSN_CKNV, FRV_INSN_FCKRA, FRV_INSN_FCKNO, FRV_INSN_FCKNE + , FRV_INSN_FCKEQ, FRV_INSN_FCKLG, FRV_INSN_FCKUE, FRV_INSN_FCKUL + , FRV_INSN_FCKGE, FRV_INSN_FCKLT, FRV_INSN_FCKUGE, FRV_INSN_FCKUG + , FRV_INSN_FCKLE, FRV_INSN_FCKGT, FRV_INSN_FCKULE, FRV_INSN_FCKU + , FRV_INSN_FCKO, FRV_INSN_CCKRA, FRV_INSN_CCKNO, FRV_INSN_CCKEQ + , FRV_INSN_CCKNE, FRV_INSN_CCKLE, FRV_INSN_CCKGT, FRV_INSN_CCKLT + , FRV_INSN_CCKGE, FRV_INSN_CCKLS, FRV_INSN_CCKHI, FRV_INSN_CCKC + , FRV_INSN_CCKNC, FRV_INSN_CCKN, FRV_INSN_CCKP, FRV_INSN_CCKV + , FRV_INSN_CCKNV, FRV_INSN_CFCKRA, FRV_INSN_CFCKNO, FRV_INSN_CFCKNE + , FRV_INSN_CFCKEQ, FRV_INSN_CFCKLG, FRV_INSN_CFCKUE, FRV_INSN_CFCKUL + , FRV_INSN_CFCKGE, FRV_INSN_CFCKLT, FRV_INSN_CFCKUGE, FRV_INSN_CFCKUG + , FRV_INSN_CFCKLE, FRV_INSN_CFCKGT, FRV_INSN_CFCKULE, FRV_INSN_CFCKU + , FRV_INSN_CFCKO, FRV_INSN_CJMPL, FRV_INSN_CCALLL, FRV_INSN_ICI + , FRV_INSN_DCI, FRV_INSN_ICEI, FRV_INSN_DCEI, FRV_INSN_DCF + , FRV_INSN_DCEF, FRV_INSN_WITLB, FRV_INSN_WDTLB, FRV_INSN_ITLBI + , FRV_INSN_DTLBI, FRV_INSN_ICPL, FRV_INSN_DCPL, FRV_INSN_ICUL + , FRV_INSN_DCUL, FRV_INSN_BAR, FRV_INSN_MEMBAR, FRV_INSN_COP1 + , FRV_INSN_COP2, FRV_INSN_CLRGR, FRV_INSN_CLRFR, FRV_INSN_CLRGA + , FRV_INSN_CLRFA, FRV_INSN_COMMITGR, FRV_INSN_COMMITFR, FRV_INSN_COMMITGA + , FRV_INSN_COMMITFA, FRV_INSN_FITOS, FRV_INSN_FSTOI, FRV_INSN_FITOD + , FRV_INSN_FDTOI, FRV_INSN_FDITOS, FRV_INSN_FDSTOI, FRV_INSN_NFDITOS + , FRV_INSN_NFDSTOI, FRV_INSN_CFITOS, FRV_INSN_CFSTOI, FRV_INSN_NFITOS + , FRV_INSN_NFSTOI, FRV_INSN_FMOVS, FRV_INSN_FMOVD, FRV_INSN_FDMOVS + , FRV_INSN_CFMOVS, FRV_INSN_FNEGS, FRV_INSN_FNEGD, FRV_INSN_FDNEGS + , FRV_INSN_CFNEGS, FRV_INSN_FABSS, FRV_INSN_FABSD, FRV_INSN_FDABSS + , FRV_INSN_CFABSS, FRV_INSN_FSQRTS, FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS + , FRV_INSN_FSQRTD, FRV_INSN_CFSQRTS, FRV_INSN_NFSQRTS, FRV_INSN_FADDS + , FRV_INSN_FSUBS, FRV_INSN_FMULS, FRV_INSN_FDIVS, FRV_INSN_FADDD + , FRV_INSN_FSUBD, FRV_INSN_FMULD, FRV_INSN_FDIVD, FRV_INSN_CFADDS + , FRV_INSN_CFSUBS, FRV_INSN_CFMULS, FRV_INSN_CFDIVS, FRV_INSN_NFADDS + , FRV_INSN_NFSUBS, FRV_INSN_NFMULS, FRV_INSN_NFDIVS, FRV_INSN_FCMPS + , FRV_INSN_FCMPD, FRV_INSN_CFCMPS, FRV_INSN_FDCMPS, FRV_INSN_FMADDS + , FRV_INSN_FMSUBS, FRV_INSN_FMADDD, FRV_INSN_FMSUBD, FRV_INSN_FDMADDS + , FRV_INSN_NFDMADDS, FRV_INSN_CFMADDS, FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS + , FRV_INSN_NFMSUBS, FRV_INSN_FMAS, FRV_INSN_FMSS, FRV_INSN_FDMAS + , FRV_INSN_FDMSS, FRV_INSN_NFDMAS, FRV_INSN_NFDMSS, FRV_INSN_CFMAS + , FRV_INSN_CFMSS, FRV_INSN_FMAD, FRV_INSN_FMSD, FRV_INSN_NFMAS + , FRV_INSN_NFMSS, FRV_INSN_FDADDS, FRV_INSN_FDSUBS, FRV_INSN_FDMULS + , FRV_INSN_FDDIVS, FRV_INSN_FDSADS, FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS + , FRV_INSN_NFDADDS, FRV_INSN_NFDSUBS, FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS + , FRV_INSN_NFDSADS, FRV_INSN_NFDCMPS, FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS + , FRV_INSN_MHDSETS, FRV_INSN_MHSETLOH, FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH + , FRV_INSN_MAND, FRV_INSN_MOR, FRV_INSN_MXOR, FRV_INSN_CMAND + , FRV_INSN_CMOR, FRV_INSN_CMXOR, FRV_INSN_MNOT, FRV_INSN_CMNOT + , FRV_INSN_MROTLI, FRV_INSN_MROTRI, FRV_INSN_MWCUT, FRV_INSN_MWCUTI + , FRV_INSN_MCUT, FRV_INSN_MCUTI, FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI + , FRV_INSN_MDCUTSSI, FRV_INSN_MAVEH, FRV_INSN_MSLLHI, FRV_INSN_MSRLHI + , FRV_INSN_MSRAHI, FRV_INSN_MDROTLI, FRV_INSN_MCPLHI, FRV_INSN_MCPLI + , FRV_INSN_MSATHS, FRV_INSN_MQSATHS, FRV_INSN_MSATHU, FRV_INSN_MCMPSH + , FRV_INSN_MCMPUH, FRV_INSN_MABSHS, FRV_INSN_MADDHSS, FRV_INSN_MADDHUS + , FRV_INSN_MSUBHSS, FRV_INSN_MSUBHUS, FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS + , FRV_INSN_CMSUBHSS, FRV_INSN_CMSUBHUS, FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS + , FRV_INSN_MQSUBHSS, FRV_INSN_MQSUBHUS, FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS + , FRV_INSN_CMQSUBHSS, FRV_INSN_CMQSUBHUS, FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS + , FRV_INSN_MDADDACCS, FRV_INSN_MDSUBACCS, FRV_INSN_MASACCS, FRV_INSN_MDASACCS + , FRV_INSN_MMULHS, FRV_INSN_MMULHU, FRV_INSN_MMULXHS, FRV_INSN_MMULXHU + , FRV_INSN_CMMULHS, FRV_INSN_CMMULHU, FRV_INSN_MQMULHS, FRV_INSN_MQMULHU + , FRV_INSN_MQMULXHS, FRV_INSN_MQMULXHU, FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU + , FRV_INSN_MMACHS, FRV_INSN_MMACHU, FRV_INSN_MMRDHS, FRV_INSN_MMRDHU + , FRV_INSN_CMMACHS, FRV_INSN_CMMACHU, FRV_INSN_MQMACHS, FRV_INSN_MQMACHU + , FRV_INSN_CMQMACHS, FRV_INSN_CMQMACHU, FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS + , FRV_INSN_MQMACXHS, FRV_INSN_MCPXRS, FRV_INSN_MCPXRU, FRV_INSN_MCPXIS + , FRV_INSN_MCPXIU, FRV_INSN_CMCPXRS, FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS + , FRV_INSN_CMCPXIU, FRV_INSN_MQCPXRS, FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS + , FRV_INSN_MQCPXIU, FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD + , FRV_INSN_CMEXPDHD, FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH + , FRV_INSN_MDUNPACKH, FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB + , FRV_INSN_CMHTOB, FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MCLRACC + , FRV_INSN_MRDACC, FRV_INSN_MRDACCG, FRV_INSN_MWTACC, FRV_INSN_MWTACCG + , FRV_INSN_MCOP1, FRV_INSN_MCOP2, FRV_INSN_FNOP +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID FRV_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) FRV_INSN_FNOP + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_pack; + long f_op; + long f_ope1; + long f_ope2; + long f_ope3; + long f_ope4; + long f_GRi; + long f_GRj; + long f_GRk; + long f_FRi; + long f_FRj; + long f_FRk; + long f_CPRi; + long f_CPRj; + long f_CPRk; + long f_ACCGi; + long f_ACCGk; + long f_ACC40Si; + long f_ACC40Ui; + long f_ACC40Sk; + long f_ACC40Uk; + long f_CRi; + long f_CRj; + long f_CRk; + long f_CCi; + long f_CRj_int; + long f_CRj_float; + long f_ICCi_1; + long f_ICCi_2; + long f_ICCi_3; + long f_FCCi_1; + long f_FCCi_2; + long f_FCCi_3; + long f_FCCk; + long f_eir; + long f_s10; + long f_s12; + long f_d12; + long f_u16; + long f_s16; + long f_s6; + long f_s6_1; + long f_u6; + long f_s5; + long f_u12_h; + long f_u12_l; + long f_u12; + long f_int_cc; + long f_flt_cc; + long f_cond; + long f_ccond; + long f_hint; + long f_LI; + long f_lock; + long f_debug; + long f_A; + long f_ae; + long f_spr_h; + long f_spr_l; + long f_spr; + long f_label16; + long f_labelH6; + long f_labelL18; + long f_label24; + long f_ICCi_1_null; + long f_ICCi_2_null; + long f_ICCi_3_null; + long f_FCCi_1_null; + long f_FCCi_2_null; + long f_FCCi_3_null; + long f_rs_null; + long f_GRi_null; + long f_GRj_null; + long f_GRk_null; + long f_FRi_null; + long f_FRj_null; + long f_ACCj_null; + long f_rd_null; + long f_cond_null; + long f_ccond_null; + long f_s12_null; + long f_label16_null; + long f_misc_null_1; + long f_misc_null_2; + long f_misc_null_3; + long f_misc_null_4; + long f_misc_null_5; + long f_misc_null_6; + long f_misc_null_7; + long f_misc_null_8; + long f_misc_null_9; + long f_misc_null_10; + long f_misc_null_11; + long f_LI_off; + long f_LI_on; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* FRV_OPC_H */ diff -uprN binutils-2.12.90.0.11/opcodes/po/POTFILES.in binutils-2.12.90.0.12/opcodes/po/POTFILES.in --- binutils-2.12.90.0.11/opcodes/po/POTFILES.in Fri Jun 7 19:22:17 2002 +++ binutils-2.12.90.0.12/opcodes/po/POTFILES.in Tue Jun 18 21:41:59 2002 @@ -26,6 +26,13 @@ fr30-dis.c fr30-ibld.c fr30-opc.c fr30-opc.h +frv-asm.c +frv-desc.c +frv-desc.h +frv-dis.c +frv-ibld.c +frv-opc.c +frv-opc.h h8300-dis.c h8500-dis.c h8500-opc.h